1/* 2 * HND SiliconBackplane MIPS core software interface. 3 * 4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: hndmips.h,v 13.17 2008/03/28 19:07:35 Exp $ 19 */ 20 21#ifndef _hndmips_h_ 22#define _hndmips_h_ 23 24extern void si_mips_init(si_t *sih, uint shirq_map_base); 25extern bool si_mips_setclock(si_t *sih, uint32 mipsclock, uint32 sbclock, uint32 pciclock); 26extern void enable_pfc(uint32 mode); 27extern uint32 si_memc_get_ncdl(si_t *sih); 28 29#if defined(BCMPERFSTATS) 30/* enable counting - exclusive version. Only one set of counters allowed at a time */ 31extern void hndmips_perf_cyclecount_enable(void); 32extern void hndmips_perf_instrcount_enable(void); 33extern void hndmips_perf_icachecount_enable(void); 34extern void hndmips_perf_dcachecount_enable(void); 35/* start and stop counting */ 36#define hndmips_perf_start01() \ 37 MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000) 38#define hndmips_perf_stop01() \ 39 MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000) 40/* retrieve coutners - counters *decrement* */ 41#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0)) 42#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1)) 43#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2)) 44/* enable counting - modular version. Each counters can be enabled separately. */ 45extern void hndmips_perf_icache_hit_enable(void); 46extern void hndmips_perf_icache_miss_enable(void); 47extern uint32 hndmips_perf_read_instrcount(void); 48extern uint32 hndmips_perf_read_cache_miss(void); 49extern uint32 hndmips_perf_read_cache_hit(void); 50#endif 51 52#endif /* _hndmips_h_ */ 53