1/* 2 * drivers/mtd/devices/ubi32-m25p80.c 3 * NOR flash driver, Ubicom processor internal SPI flash interface. 4 * 5 * This code instantiates the serial flash that contains the 6 * original bootcode. The serial flash start at address 0x60000000 7 * in both Ubicom32V3 and Ubicom32V4 ISAs. 8 * 9 * This piece of flash is made to appear as a Memory Technology 10 * Device (MTD) with this driver to allow Read/Write/Erase operations. 11 * 12 * (C) Copyright 2009, Ubicom, Inc. 13 * 14 * This file is part of the Ubicom32 Linux Kernel Port. 15 * 16 * The Ubicom32 Linux Kernel Port is free software: you can redistribute 17 * it and/or modify it under the terms of the GNU General Public License 18 * as published by the Free Software Foundation, either version 2 of the 19 * License, or (at your option) any later version. 20 * 21 * The Ubicom32 Linux Kernel Port is distributed in the hope that it 22 * will be useful, but WITHOUT ANY WARRANTY; without even the implied 23 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 24 * the GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with the Ubicom32 Linux Kernel Port. If not, 28 * see <http://www.gnu.org/licenses/>. 29 * 30 * Ubicom32 implementation derived from (with many thanks): 31 * arch/m68knommu 32 * arch/blackfin 33 * arch/parisc 34 */ 35#include <linux/types.h> 36#include <linux/device.h> 37#include <linux/platform_device.h> 38#include <linux/mtd/mtd.h> 39#include <linux/mtd/partitions.h> 40#include <linux/mtd/physmap.h> 41#include <linux/spi/spi.h> 42#include <linux/spi/flash.h> 43 44#include <linux/init.h> 45#include <linux/module.h> 46#include <linux/interrupt.h> 47#include <linux/mutex.h> 48 49#include <asm/ip5000.h> 50#include <asm/devtree.h> 51 52#define UBICOM32_FLASH_BASE 0x60000000 53#define UBICOM32_FLASH_MAX_SIZE 0x01000000 54#define UBICOM32_FLASH_START 0x00000000 55#define UBICOM32_KERNEL_OFFSET 0x00010000 /* The kernel starts after Ubicom 56 * .protect section. */ 57 58static struct mtd_partition ubicom32_flash_partitions[] = { 59 { 60 .name = "Bootloader", /* Protected Section 61 * Partition */ 62 .size = 0x10000, 63 .offset = UBICOM32_FLASH_START, 64// .mask_flags = MTD_WRITEABLE /* Mark Read-only */ 65 }, 66 { 67 .name = "Kernel", /* Kernel Partition. */ 68 .size = 0, /* this will be set up during 69 * probe stage. At that time we 70 * will know end of linux image 71 * in flash. */ 72 .offset = MTDPART_OFS_APPEND, /* Starts right after Protected 73 * section. */ 74// .mask_flags = MTD_WRITEABLE /* Mark Read-only */ 75 }, 76 { 77 .name = "Rest", /* Rest of the flash. */ 78 .size = 0x200000, /* Use up what remains in the 79 * flash. */ 80 .offset = MTDPART_OFS_NXTBLK, /* Starts right after Protected 81 * section. */ 82 } 83}; 84 85static struct flash_platform_data ubicom32_flash_data = { 86 .name = "ubicom32_boot_flash", 87 .parts = ubicom32_flash_partitions, 88 .nr_parts = ARRAY_SIZE(ubicom32_flash_partitions), 89}; 90 91static struct resource ubicom32_flash_resource[] = { 92 { 93 .start = UBICOM32_FLASH_BASE, 94 .end = UBICOM32_FLASH_BASE + 95 UBICOM32_FLASH_MAX_SIZE - 1, 96 .flags = IORESOURCE_MEM, 97 }, 98}; 99 100static struct platform_device ubicom32_flash_device = { 101 .name = "ubicom32flashdriver", 102 .id = 0, /* Bus number */ 103 .num_resources = ARRAY_SIZE(ubicom32_flash_resource), 104 .resource = ubicom32_flash_resource, 105 .dev = { 106 .platform_data = &ubicom32_flash_data, 107 }, 108}; 109 110static struct platform_device *ubicom32_flash_devices[] = { 111 &ubicom32_flash_device, 112}; 113 114static int __init ubicom32_flash_init(void) 115{ 116 printk(KERN_INFO "%s(): registering device resources\n", 117 __FUNCTION__); 118 platform_add_devices(ubicom32_flash_devices, 119 ARRAY_SIZE(ubicom32_flash_devices)); 120 return 0; 121} 122 123arch_initcall(ubicom32_flash_init); 124 125/* 126 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips through 127 * Ubicom32 SPI controller. 128 * 129 * Author: Mike Lavender, mike@steroidmicros.com 130 * 131 * Copyright (c) 2005, Intec Automation Inc. 132 * 133 * Some parts are based on lart.c by Abraham Van Der Merwe 134 * 135 * Cleaned up and generalized based on mtd_dataflash.c 136 * 137 * This code is free software; you can redistribute it and/or modify 138 * it under the terms of the GNU General Public License version 2 as 139 * published by the Free Software Foundation. 140 * 141 */ 142 143#define FLASH_PAGESIZE 256 144 145/* Flash opcodes. */ 146#define OPCODE_WREN 0x06 /* Write enable */ 147#define OPCODE_RDSR 0x05 /* Read status register */ 148#define OPCODE_READ 0x03 /* Read data bytes (low frequency) */ 149#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ 150#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ 151#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ 152#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ 153#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ 154#define OPCODE_RDID 0x9f /* Read JEDEC ID */ 155 156/* Status Register bits. */ 157#define SR_WIP 1 /* Write in progress */ 158#define SR_WEL 2 /* Write enable latch */ 159/* meaning of other SR_* bits may differ between vendors */ 160#define SR_BP0 4 /* Block protect 0 */ 161#define SR_BP1 8 /* Block protect 1 */ 162#define SR_BP2 0x10 /* Block protect 2 */ 163#define SR_SRWD 0x80 /* SR write protect */ 164 165/* Define max times to check status register before we give up. */ 166#define MAX_READY_WAIT_COUNT 100000 167 168 169#ifdef CONFIG_MTD_PARTITIONS 170#define mtd_has_partitions() (1) 171#else 172#define mtd_has_partitions() (0) 173#endif 174 175/* 176 * Ubicom32 FLASH Command Set 177 */ 178#define FLASH_FC_INST_CMD 0x00 /* for SPI command only transaction */ 179#define FLASH_FC_INST_WR 0x01 /* for SPI write transaction */ 180#define FLASH_FC_INST_RD 0x02 /* for SPI read transaction */ 181 182#define ALIGN_DOWN(v, a) ((v) & ~((a) - 1)) 183#define ALIGN_UP(v, a) (((v) + ((a) - 1)) & ~((a) - 1)) 184 185#define FLASH_COMMAND_KICK_OFF(io) \ 186 asm volatile( \ 187 " bset "D(IO_INT_CLR)"(%0), #0, #%%bit("D(IO_XFL_INT_DONE)") \n\t" \ 188 " jmpt.t .+4 \n\t" \ 189 " bset "D(IO_INT_SET)"(%0), #0, #%%bit("D(IO_XFL_INT_START)") \n\t" \ 190 : \ 191 : "a" (io) \ 192 : "memory", "cc" \ 193 ); 194 195#define FLASH_COMMAND_WAIT_FOR_COMPLETION(io) \ 196 asm volatile( \ 197 " btst "D(IO_INT_STATUS)"(%0), #%%bit("D(IO_XFL_INT_DONE)") \n\t" \ 198 " jmpeq.f .-4 \n\t" \ 199 : \ 200 : "a" (io) \ 201 : "memory", "cc" \ 202 ); 203 204#define FLASH_COMMAND_EXEC(io) \ 205 FLASH_COMMAND_KICK_OFF(io) \ 206 FLASH_COMMAND_WAIT_FOR_COMPLETION(io) 207 208 209#define OSC1_FREQ 12000000 210#define TEN_MICRO_SECONDS (OSC1_FREQ * 10 / 1000000) 211 212/* 213 * We will have to eventually replace this null definition with the real thing. 214 */ 215#define WATCHDOG_RESET() 216 217#define EXTFLASH_WRITE_FIFO_SIZE 32 218#define EXTFLASH_WRITE_BLOCK_SIZE EXTFLASH_WRITE_FIFO_SIZE /* limit the size to 219 * FIFO capacity, so 220 * the thread can be 221 * suspended. */ 222 223#define JFFS2_FILESYSTEM_SIZE 0x100000 224 225/****************************************************************************/ 226 227struct m25p { 228 struct platform_device *plt_dev; 229 struct mutex lock; 230 struct mtd_info mtd; 231 unsigned partitioned:1; 232 u8 erase_opcode; 233 u8 command[4]; 234}; 235 236static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) 237{ 238 return container_of(mtd, struct m25p, mtd); 239} 240 241/****************************************************************************/ 242 243/* 244 * Internal helper functions 245 */ 246 247/* 248 * Read the status register, returning its value in the location 249 * Return the status register value. 250 * Returns negative if error occurred. 251 */ 252static int read_sr(struct m25p *flash) 253{ 254 struct ubicom32_io_port *io = (struct ubicom32_io_port *)RA; 255 256 io->ctl1 &= ~IO_XFL_CTL1_MASK; 257 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_RD) | 258 IO_XFL_CTL1_FC_DATA(1); 259 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_RDSR); 260 FLASH_COMMAND_EXEC(io); 261 262 return io->status1 & 0xff; 263} 264 265/* 266 * mem_flash_io_read_u32() 267 */ 268static u32 mem_flash_io_read_u32(u32 addr) 269{ 270 struct ubicom32_io_port *io = (struct ubicom32_io_port *)RA; 271 io->ctl1 &= ~IO_XFL_CTL1_MASK; 272 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_RD) | 273 IO_XFL_CTL1_FC_DATA(4) | IO_XFL_CTL1_FC_DUMMY(1) | 274 IO_XFL_CTL1_FC_ADDR; 275 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_FAST_READ) | 276 IO_XFL_CTL2_FC_ADDR(addr); 277 FLASH_COMMAND_EXEC(io); 278 return io->status1; 279} 280 281/* 282 * mem_flash_read_u8() 283 */ 284static u8 mem_flash_read_u8(u32 addr) 285{ 286 u32 tmp_addr = ALIGN_DOWN(addr, 4); 287 u32 tmp_data = mem_flash_io_read_u32(tmp_addr); 288 u8 *ptr = (u8 *)&tmp_data; 289 return ptr[addr & 0x3]; 290} 291 292/* 293 * mem_flash_read() 294 * No need to lock as read is implemented with ireads (same as normal flash 295 * execution). 296 */ 297static void mem_flash_read(u32 addr, void *dst, size_t length) 298{ 299 /* 300 * Range check 301 */ 302 /* 303 * Fix source alignment. 304 */ 305 while (addr & 0x03) { 306 if (length == 0) { 307 return; 308 } 309 *((u8 *)dst) = mem_flash_read_u8(addr++); 310 dst++; 311 length--; 312 } 313 314 while (length >= 4) { 315 u32 tmp_data = mem_flash_io_read_u32(addr); 316 addr += 4; 317 length -= 4; 318 319 /* 320 * Send the data to the destination. 321 */ 322 memcpy((void *)dst, (void *)&tmp_data, 4); 323 dst += 4; 324 } 325 326 while (length--) { 327 *((u8 *)dst) = mem_flash_read_u8(addr++); 328 dst++; 329 } 330} 331 332/* 333 * mem_flash_wait_until_complete() 334 */ 335static void mem_flash_wait_until_complete(void) 336{ 337 struct ubicom32_io_port *io = (struct ubicom32_io_port *)RA; 338 339 do { 340 /* 341 * Put a delay here to deal with flash programming problem. 342 */ 343 u32 mptval = UBICOM32_IO_TIMER->mptval + TEN_MICRO_SECONDS; 344 while (UBICOM32_IO_TIMER->mptval < mptval) 345 ; 346 347 io->ctl1 &= ~IO_XFL_CTL1_MASK; 348 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_RD) | 349 IO_XFL_CTL1_FC_DATA(1); 350 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_RDSR); 351 FLASH_COMMAND_EXEC(io); 352 } while (io->status1 & SR_WIP); 353} 354 355/* 356 * mem_flash_write_next() 357 */ 358static size_t mem_flash_write_next(u32 addr, u8 *buf, size_t length) 359{ 360 struct ubicom32_io_port *io = (struct ubicom32_io_port *)RA; 361 u32 data_start = addr; 362 u32 data_end = addr + length; 363 size_t count; 364 u32 i, j; 365 366 /* 367 * Top limit address. 368 */ 369 u32 block_start = ALIGN_DOWN(data_start, 4); 370 u32 block_end = block_start + EXTFLASH_WRITE_BLOCK_SIZE; 371 372 union { 373 u8 byte[EXTFLASH_WRITE_BLOCK_SIZE]; 374 u32 word[EXTFLASH_WRITE_BLOCK_SIZE / 4]; 375 } write_buf; 376 377 u32 *flash_addr = (u32 *)block_start; 378 379 /* 380 * The write block must be limited by FLASH internal buffer. 381 */ 382 u32 block_end_align = ALIGN_DOWN(block_end, 256); 383 bool write_needed; 384 385 block_end = (block_end_align > block_start) 386 ? block_end_align : block_end; 387 data_end = (data_end <= block_end) ? data_end : block_end; 388 block_end = ALIGN_UP(data_end, 4); 389 count = data_end - data_start; 390 391 /* 392 * Transfer data to a buffer. 393 */ 394 for (i = 0; i < (block_end - block_start) / 4; i++) { 395 /* 396 * The FLASH read can hold D-cache for a long time. 397 * Use I/O operation to read FLASH to avoid starving other 398 * threads, especially HRT. (Do this for application only) 399 */ 400 write_buf.word[i] = mem_flash_io_read_u32( 401 (u32)(&flash_addr[i])); 402 } 403 404 write_needed = false; 405 for (i = 0, j = (data_start - block_start); 406 i < (data_end - data_start); i++, j++) { 407 write_needed = write_needed || (write_buf.byte[j] != buf[i]); 408 write_buf.byte[j] &= buf[i]; 409 } 410 411 412 /* 413 * If the data in FLASH is identical to what to be written. Then skip 414 * it. 415 */ 416 if (write_needed) { 417 /* 418 * Write to flash. 419 */ 420 void *tmp __attribute__((unused)); 421 s32 extra_words; 422 423 asm volatile( 424 " move.4 %0, %2 \n\t" 425 " bset "D(IO_INT_SET)"(%1), #0, #%%bit("D(IO_PORTX_INT_FIFO_TX_RESET)") \n\t" 426 " pipe_flush 0 \n\t" 427 " .rept "D(EXTFLASH_WRITE_FIFO_SIZE / 4)" \n\t" 428 " move.4 "D(IO_TX_FIFO)"(%1), (%0)4++ \n\t" 429 " .endr \n\t" 430 : "=&a" (tmp) 431 : "a" (io), "r" (&write_buf.word[0]) 432 : "memory", "cc" 433 ); 434 435 /* Lock FLASH for write access. */ 436 io->ctl0 |= IO_XFL_CTL0_MCB_LOCK; 437 438 /* Command: WREN */ 439 io->ctl1 &= ~IO_XFL_CTL1_MASK; 440 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_CMD); 441 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_WREN); 442 FLASH_COMMAND_EXEC(io); 443 444 /* Command: BYTE PROGRAM */ 445 io->ctl1 &= ~IO_XFL_CTL1_MASK; 446 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_WR) | 447 IO_XFL_CTL1_FC_DATA(block_end - block_start) | 448 IO_XFL_CTL1_FC_ADDR; 449 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_PP) | 450 IO_XFL_CTL2_FC_ADDR(block_start); 451 FLASH_COMMAND_KICK_OFF(io); 452 453 extra_words = (s32)(block_end - block_start - 454 EXTFLASH_WRITE_FIFO_SIZE) / 4; 455 if (extra_words > 0) { 456 asm volatile( 457 " move.4 %0, %3 \n\t" 458 "1: cmpi "D(IO_FIFO_LEVEL)"(%1), #4 \n\t" 459 " jmpgt.s.t 1b \n\t" 460 " move.4 "D(IO_TX_FIFO)"(%1), (%0)4++ \n\t" 461 " add.4 %2, #-1, %2 \n\t" 462 " jmpgt.t 1b \n\t" 463 : "=&a" (tmp) 464 : "a" (io), "d" (extra_words), 465 "r" (&write_buf.word[EXTFLASH_WRITE_FIFO_SIZE / 4]) 466 : "memory", "cc" 467 ); 468 } 469 FLASH_COMMAND_WAIT_FOR_COMPLETION(io); 470 471 mem_flash_wait_until_complete(); 472 473 474 /* Unlock FLASH for cache access. */ 475 io->ctl0 &= ~IO_XFL_CTL0_MCB_LOCK; 476 } 477 478 /* 479 * Complete. 480 */ 481 return count; 482} 483 484/* 485 * mem_flash_write() 486 */ 487static void mem_flash_write(u32 addr, const void *src, size_t length) 488{ 489 /* 490 * Write data 491 */ 492 u8_t *ptr = (u8_t *)src; 493 while (length) { 494 size_t count = mem_flash_write_next(addr, ptr, length); 495 addr += count; 496 ptr += count; 497 length -= count; 498 } 499} 500 501/* 502 * Service routine to read status register until ready, or timeout occurs. 503 * Returns non-zero if error. 504 */ 505static int wait_till_ready(struct m25p *flash) 506{ 507 int count; 508 int sr; 509 510 /* one chip guarantees max 5 msec wait here after page writes, 511 * but potentially three seconds (!) after page erase. 512 */ 513 for (count = 0; count < MAX_READY_WAIT_COUNT; count++) { 514 u32 mptval; 515 sr = read_sr(flash); 516 if (sr < 0) 517 break; 518 else if (!(sr & SR_WIP)) 519 return 0; 520 521 /* 522 * Put a 10us delay here to deal with flash programming problem. 523 */ 524 mptval = UBICOM32_IO_TIMER->mptval + TEN_MICRO_SECONDS; 525 while ((s32)(mptval - UBICOM32_IO_TIMER->mptval) > 0) { 526 WATCHDOG_RESET(); 527 } 528 /* REVISIT sometimes sleeping would be best */ 529 } 530 531 return 1; 532} 533 534/* 535 * mem_flash_erase_page() 536 */ 537static void mem_flash_erase_page(u32 addr) 538{ 539 struct ubicom32_io_port *io = (struct ubicom32_io_port *)RA; 540 541 /* Lock FLASH for write access. */ 542 io->ctl0 |= IO_XFL_CTL0_MCB_LOCK; 543 544 /* Command: WREN */ 545 io->ctl1 &= ~IO_XFL_CTL1_MASK; 546 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_CMD); 547 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_WREN); 548 FLASH_COMMAND_EXEC(io); 549 550 /* Command: ERASE */ 551 io->ctl1 &= ~IO_XFL_CTL1_MASK; 552 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_CMD) | 553 IO_XFL_CTL1_FC_ADDR; 554 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_SE) | 555 IO_XFL_CTL2_FC_ADDR(addr); 556 FLASH_COMMAND_EXEC(io); 557 558 mem_flash_wait_until_complete(); 559 560 /* Unlock FLASH for cache access. */ 561 io->ctl0 &= ~IO_XFL_CTL0_MCB_LOCK; 562} 563 564/* 565 * mem_flash_erase() 566 */ 567static u32 mem_flash_erase(u32 addr, u32 length) 568{ 569 /* 570 * Calculate the endaddress to be the first address of the page 571 * just beyond this erase section of pages. 572 */ 573 u32 endaddr = addr + length; 574 575 /* 576 * Erase. 577 */ 578 while (addr < endaddr) { 579 u32 test_addr = addr; 580 mem_flash_erase_page(addr); 581 582 /* 583 * Test how much was erased as actual flash page at this address 584 * may be smaller than the expected page size. 585 */ 586 while (test_addr < endaddr) { 587 /* 588 * The FLASH read can hold D-cache for a long time. Use 589 * I/O operation to read FLASH to avoid starving other 590 * threads, especially HRT. (Do this for application 591 * only) 592 */ 593 if (mem_flash_io_read_u32(test_addr) != 0xFFFFFFFF) { 594 break; 595 } 596 test_addr += 4; 597 } 598 if (test_addr == addr) { 599 printk("erase failed at address 0x%x, skipping", 600 test_addr); 601 test_addr += 4; 602 return 1; 603 } 604 addr = test_addr; 605 } 606 return 0; 607} 608 609 610/****************************************************************************/ 611 612/* 613 * MTD implementation 614 */ 615 616/* 617 * Erase an address range on the flash chip. The address range may extend 618 * one or more erase sectors. Return an error is there is a problem erasing. 619 */ 620static int ubicom32_flash_driver_erase(struct mtd_info *mtd, 621 struct erase_info *instr) 622{ 623 struct m25p *flash = mtd_to_m25p(mtd); 624 u32 addr, len; 625 626 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %lld\n", 627 dev_name(&flash->plt_dev->dev), __FUNCTION__, "at", 628 (u32)instr->addr, instr->len); 629 630 /* sanity checks */ 631 if (instr->addr + instr->len > flash->mtd.size) 632 return -EINVAL; 633 if ((instr->addr % mtd->erasesize) != 0 634 || (instr->len % mtd->erasesize) != 0) { 635 return -EINVAL; 636 } 637 638 addr = instr->addr + UBICOM32_FLASH_BASE; 639 len = instr->len; 640 641 mutex_lock(&flash->lock); 642 643 /* REVISIT in some cases we could speed up erasing large regions 644 * by using OPCODE_SE instead of OPCODE_BE_4K 645 */ 646 647 /* now erase those sectors */ 648 if (mem_flash_erase(addr, len)) { 649 instr->state = MTD_ERASE_FAILED; 650 mutex_unlock(&flash->lock); 651 return -EIO; 652 } 653 654 mutex_unlock(&flash->lock); 655 instr->state = MTD_ERASE_DONE; 656 mtd_erase_callback(instr); 657 return 0; 658} 659 660/* 661 * Read an address range from the flash chip. The address range 662 * may be any size provided it is within the physical boundaries. 663 */ 664static int ubicom32_flash_driver_read(struct mtd_info *mtd, loff_t from, 665 size_t len, size_t *retlen, u_char *buf) 666{ 667 struct m25p *flash = mtd_to_m25p(mtd); 668 u32 base_addr = UBICOM32_FLASH_BASE + from; 669 670 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %d\n", 671 dev_name(&flash->plt_dev->dev), __FUNCTION__, "from", 672 (u32)from, len); 673 674 /* sanity checks */ 675 if (!len) 676 return 0; 677 678 if (from + len > flash->mtd.size) 679 return -EINVAL; 680 681 /* Byte count starts at zero. */ 682 if (retlen) 683 *retlen = 0; 684 685 mutex_lock(&flash->lock); 686 687 /* Wait till previous write/erase is done. */ 688 if (wait_till_ready(flash)) { 689 /* REVISIT status return?? */ 690 mutex_unlock(&flash->lock); 691 return 1; 692 } 693 694 mem_flash_read(base_addr, (void *)buf, len); 695 696 if (retlen) 697 *retlen = len; 698 699 mutex_unlock(&flash->lock); 700 701 return 0; 702} 703 704/* 705 * Write an address range to the flash chip. Data must be written in 706 * FLASH_PAGESIZE chunks. The address range may be any size provided 707 * it is within the physical boundaries. 708 */ 709static int ubicom32_flash_driver_write(struct mtd_info *mtd, loff_t to, 710 size_t len, size_t *retlen, 711 const u_char *buf) 712{ 713 struct m25p *flash = mtd_to_m25p(mtd); 714 u32 base_addr = UBICOM32_FLASH_BASE + to; 715 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %d\n", 716 dev_name(&flash->plt_dev->dev), __FUNCTION__, "to", 717 (u32)to, len); 718 719 if (retlen) 720 *retlen = 0; 721 722 /* sanity checks */ 723 if (!len) 724 return 0; 725 726 if (to + len > flash->mtd.size) 727 return -EINVAL; 728 729 mutex_lock(&flash->lock); 730 731 mem_flash_write(base_addr, (void *) buf, len); 732 733 /* Wait until finished previous write command. */ 734 if (wait_till_ready(flash)) { 735 mutex_unlock(&flash->lock); 736 return 1; 737 } 738 739 if (retlen) 740 *retlen = len; 741 742 mutex_unlock(&flash->lock); 743 return 0; 744} 745 746 747/****************************************************************************/ 748 749/* 750 * SPI device driver setup and teardown 751 */ 752 753struct flash_info { 754 char *name; 755 756 /* JEDEC id zero means "no ID" (most older chips); otherwise it has 757 * a high byte of zero plus three data bytes: the manufacturer id, 758 * then a two byte device id. 759 */ 760 u32 jedec_id; 761 762 /* The size listed here is what works with OPCODE_SE, which isn't 763 * necessarily called a "sector" by the vendor. 764 */ 765 unsigned sector_size; 766 u16 n_sectors; 767 768 u16 flags; 769#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ 770}; 771 772 773/* NOTE: double check command sets and memory organization when you add 774 * more flash chips. This current list focusses on newer chips, which 775 * have been converging on command sets which including JEDEC ID. 776 */ 777static struct flash_info __devinitdata m25p_data[] = { 778 779 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 780 { "at25fs010", 0x1f6601, 32 * 1024, 4, SECT_4K, }, 781 { "at25fs040", 0x1f6604, 64 * 1024, 8, SECT_4K, }, 782 783 { "at25df041a", 0x1f4401, 64 * 1024, 8, SECT_4K, }, 784 785 { "at26f004", 0x1f0400, 64 * 1024, 8, SECT_4K, }, 786 { "at26df081a", 0x1f4501, 64 * 1024, 16, SECT_4K, }, 787 { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K, }, 788 { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K, }, 789 790 /* Spansion -- single (large) sector size only, at least 791 * for the chips listed here (without boot sectors). 792 */ 793 { "s25sl004a", 0x010212, 64 * 1024, 8, }, 794 { "s25sl008a", 0x010213, 64 * 1024, 16, }, 795 { "s25sl016a", 0x010214, 64 * 1024, 32, }, 796 { "s25sl032a", 0x010215, 64 * 1024, 64, }, 797 { "s25sl064a", 0x010216, 64 * 1024, 128, }, 798 799 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 800 { "sst25vf040b", 0xbf258d, 64 * 1024, 8, SECT_4K, }, 801 { "sst25vf080b", 0xbf258e, 64 * 1024, 16, SECT_4K, }, 802 { "sst25vf016b", 0xbf2541, 64 * 1024, 32, SECT_4K, }, 803 { "sst25vf032b", 0xbf254a, 64 * 1024, 64, SECT_4K, }, 804 805 /* ST Microelectronics -- newer production may have feature updates */ 806 { "m25p05", 0x202010, 32 * 1024, 2, }, 807 { "m25p10", 0x202011, 32 * 1024, 4, }, 808 { "m25p20", 0x202012, 64 * 1024, 4, }, 809 { "m25p40", 0x202013, 64 * 1024, 8, }, 810 { "m25p80", 0, 64 * 1024, 16, }, 811 { "m25p16", 0x202015, 64 * 1024, 32, }, 812 { "m25p32", 0x202016, 64 * 1024, 64, }, 813 { "m25p64", 0x202017, 64 * 1024, 128, }, 814 { "m25p128", 0x202018, 256 * 1024, 64, }, 815 816 { "m45pe80", 0x204014, 64 * 1024, 16, }, 817 { "m45pe16", 0x204015, 64 * 1024, 32, }, 818 819 { "m25pe80", 0x208014, 64 * 1024, 16, }, 820 { "m25pe16", 0x208015, 64 * 1024, 32, SECT_4K, }, 821 822 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 823 { "w25x10", 0xef3011, 64 * 1024, 2, SECT_4K, }, 824 { "w25x20", 0xef3012, 64 * 1024, 4, SECT_4K, }, 825 { "w25x40", 0xef3013, 64 * 1024, 8, SECT_4K, }, 826 { "w25x80", 0xef3014, 64 * 1024, 16, SECT_4K, }, 827 { "w25x16", 0xef3015, 64 * 1024, 32, SECT_4K, }, 828 { "w25x32", 0xef3016, 64 * 1024, 64, SECT_4K, }, 829 { "w25x64", 0xef3017, 64 * 1024, 128, SECT_4K, }, 830 831 /* Macronix -- mx25lxxx */ 832 { "mx25l32", 0xc22016, 64 * 1024, 64, }, 833 { "mx25l64", 0xc22017, 64 * 1024, 128, }, 834 { "mx25l128", 0xc22018, 64 * 1024, 256, }, 835 836}; 837 838struct flash_info *__devinit jedec_probe(struct platform_device *spi) 839{ 840 int tmp; 841 u32 jedec; 842 struct flash_info *info; 843 struct ubicom32_io_port *io = (struct ubicom32_io_port *)RA; 844 845 /* 846 * Setup and run RDID command on the flash. 847 */ 848 io->ctl1 &= ~IO_XFL_CTL1_MASK; 849 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_RD) | 850 IO_XFL_CTL1_FC_DATA(3); 851 io->ctl2 = IO_XFL_CTL2_FC_CMD(OPCODE_RDID); 852 FLASH_COMMAND_EXEC(io); 853 854 jedec = io->status1 & 0x00ffffff; 855 856 for (tmp = 0, info = m25p_data; 857 tmp < ARRAY_SIZE(m25p_data); 858 tmp++, info++) { 859 if (info->jedec_id == jedec) 860 return info; 861 } 862 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); 863 return NULL; 864} 865 866 867/* 868 * board specific setup should have ensured the SPI clock used here 869 * matches what the READ command supports, at least until this driver 870 * understands FAST_READ (for clocks over 25 MHz). 871 */ 872static int __devinit ubicom32_flash_probe(struct platform_device *spi) 873{ 874 struct flash_platform_data *data; 875 struct m25p *flash; 876 struct flash_info *info; 877 unsigned i; 878 879 /* Platform data helps sort out which chip type we have, as 880 * well as how this board partitions it. If we don't have 881 * a chip ID, try the JEDEC id commands; they'll work for most 882 * newer chips, even if we don't recognize the particular chip. 883 */ 884 data = spi->dev.platform_data; 885 if (data && data->type) { 886 for (i = 0, info = m25p_data; 887 i < ARRAY_SIZE(m25p_data); 888 i++, info++) { 889 if (strcmp(data->type, info->name) == 0) 890 break; 891 } 892 893 /* unrecognized chip? */ 894 if (i == ARRAY_SIZE(m25p_data)) { 895 DEBUG(MTD_DEBUG_LEVEL0, "%s: unrecognized id %s\n", 896 dev_name(&spi->dev), data->type); 897 info = NULL; 898 899 /* recognized; is that chip really what's there? */ 900 } else if (info->jedec_id) { 901 struct flash_info *chip = jedec_probe(spi); 902 903 if (!chip || chip != info) { 904 dev_warn(&spi->dev, "found %s, expected %s\n", 905 chip ? chip->name : "UNKNOWN", 906 info->name); 907 info = NULL; 908 } 909 } 910 } else 911 info = jedec_probe(spi); 912 913 if (!info) 914 return -ENODEV; 915 916 flash = kzalloc(sizeof *flash, GFP_KERNEL); 917 if (!flash) 918 return -ENOMEM; 919 920 flash->plt_dev = spi; 921 mutex_init(&flash->lock); 922 dev_set_drvdata(&spi->dev, flash); 923 924 if (data && data->name) 925 flash->mtd.name = data->name; 926 else 927 flash->mtd.name = dev_name(&spi->dev); 928 929 flash->mtd.type = MTD_NORFLASH; 930 flash->mtd.writesize = 1; 931 flash->mtd.flags = MTD_CAP_NORFLASH; 932 flash->mtd.size = info->sector_size * info->n_sectors; 933 flash->mtd.erase = ubicom32_flash_driver_erase; 934 flash->mtd.read = ubicom32_flash_driver_read; 935 flash->mtd.write = ubicom32_flash_driver_write; 936 937 /* prefer "small sector" erase if possible */ 938 /* 939 * The Ubicom erase code does not use the opcode for smaller sectors, 940 * so disable that functionality and keep erasesize == sector_size 941 * so that the test in ubicom32_flash_driver_erase works properly. 942 * 943 * This was: `if (info->flags & SECT_4K) {' instead of `if (0) {' 944 */ 945 if (0) { 946 flash->erase_opcode = OPCODE_BE_4K; 947 flash->mtd.erasesize = 4096; 948 } else { 949 flash->erase_opcode = OPCODE_SE; 950 flash->mtd.erasesize = info->sector_size; 951 } 952 953 dev_info(&spi->dev, "%s (%lld Kbytes)\n", info->name, 954 flash->mtd.size / 1024); 955 956 DEBUG(MTD_DEBUG_LEVEL2, 957 "mtd .name = %s, .size = 0x%.8llx (%lluMiB) " 958 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 959 flash->mtd.name, 960 flash->mtd.size, flash->mtd.size / (1024*1024), 961 flash->mtd.erasesize, flash->mtd.erasesize / 1024, 962 flash->mtd.numeraseregions); 963 964 if (flash->mtd.numeraseregions) 965 for (i = 0; i < flash->mtd.numeraseregions; i++) 966 DEBUG(MTD_DEBUG_LEVEL2, 967 "mtd.eraseregions[%d] = { .offset = 0x%.8llx, " 968 ".erasesize = 0x%.8x (%uKiB), " 969 ".numblocks = %d }\n", 970 i, flash->mtd.eraseregions[i].offset, 971 flash->mtd.eraseregions[i].erasesize, 972 flash->mtd.eraseregions[i].erasesize / 1024, 973 flash->mtd.eraseregions[i].numblocks); 974 975 976 /* partitions should match sector boundaries; and it may be good to 977 * use readonly partitions for writeprotected sectors (BP2..BP0). 978 */ 979 if (mtd_has_partitions()) { 980 struct mtd_partition *parts = NULL; 981 int nr_parts = 0; 982 983#ifdef CONFIG_MTD_CMDLINE_PARTS 984 static const char *part_probes[] = { "cmdlinepart", NULL, }; 985 986 nr_parts = parse_mtd_partitions(&flash->mtd, 987 part_probes, &parts, 0); 988#endif 989 990 if (nr_parts <= 0 && data && data->parts) { 991 parts = data->parts; 992 nr_parts = data->nr_parts; 993 if (nr_parts >= 2) { 994 /* 995 * Set last partition size to be 1M. 996 */ 997 parts[1].size = flash->mtd.size - 998 parts[0].size - JFFS2_FILESYSTEM_SIZE; 999 parts[2].size = JFFS2_FILESYSTEM_SIZE; 1000 } 1001 } 1002 1003 if (nr_parts > 0) { 1004 for (i = 0; i < nr_parts; i++) { 1005 DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " 1006 "{.name = %s, .offset = 0x%.8llx, " 1007 ".size = 0x%.8llx (%lluKiB) }\n", 1008 i, parts[i].name, 1009 parts[i].offset, 1010 parts[i].size, 1011 parts[i].size / 1024); 1012 } 1013 flash->partitioned = 1; 1014 return add_mtd_partitions(&flash->mtd, parts, nr_parts); 1015 } 1016 } else if (data->nr_parts) 1017 dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", 1018 data->nr_parts, data->name); 1019 1020 return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; 1021} 1022 1023 1024static int __devexit ubicom32_flash_remove(struct spi_device *spi) 1025{ 1026 struct m25p *flash = dev_get_drvdata(&spi->dev); 1027 int status; 1028 1029 /* Clean up MTD stuff. */ 1030 if (mtd_has_partitions() && flash->partitioned) 1031 status = del_mtd_partitions(&flash->mtd); 1032 else 1033 status = del_mtd_device(&flash->mtd); 1034 if (status == 0) 1035 kfree(flash); 1036 return 0; 1037} 1038 1039static struct platform_driver ubicom32_flash_driver = { 1040 .driver = { 1041 .name = "ubicom32flashdriver", 1042 .bus = &platform_bus_type, 1043 .owner = THIS_MODULE, 1044 }, 1045 .probe = ubicom32_flash_probe, 1046 .remove = NULL, 1047}; 1048 1049static int ubicom32_flash_driver_init(void) 1050{ 1051 return platform_driver_register(&ubicom32_flash_driver); 1052} 1053 1054 1055static void ubicom32_flash_driver_exit(void) 1056{ 1057 platform_driver_unregister(&ubicom32_flash_driver); 1058} 1059 1060 1061module_init(ubicom32_flash_driver_init); 1062module_exit(ubicom32_flash_driver_exit); 1063 1064MODULE_LICENSE("GPL"); 1065MODULE_AUTHOR("Mike Lavender"); 1066MODULE_DESCRIPTION("Ubicom32 MTD SPI driver for ST M25Pxx flash chips"); 1067