1/* 2 * Copyright (c) 2006 Atheros Communications Inc. 3 * All rights reserved. 4 * 5 * $ATH_LICENSE_HOSTSDK0_C$ 6 * 7 */ 8 9#ifndef __AR6000_REGDUMP_H__ 10#define __AR6000_REGDUMP_H__ 11 12#if !defined(__ASSEMBLER__) 13/* 14 * Target CPU state at the time of failure is reflected 15 * in a register dump, which the Host can fetch through 16 * the diagnostic window. 17 */ 18 19struct MIPS_exception_frame_s { 20 A_UINT32 pc; /* Program Counter */ 21 A_UINT32 at; /* MIPS General Purpose registers */ 22 A_UINT32 v0; 23 A_UINT32 v1; 24 A_UINT32 a0; 25 A_UINT32 a1; 26 A_UINT32 a2; 27 A_UINT32 a3; 28 A_UINT32 t0; 29 A_UINT32 t1; 30 A_UINT32 t2; 31 A_UINT32 t3; 32 A_UINT32 t4; 33 A_UINT32 t5; 34 A_UINT32 t6; 35 A_UINT32 t7; 36 A_UINT32 s0; 37 A_UINT32 s1; 38 A_UINT32 s2; 39 A_UINT32 s3; 40 A_UINT32 s4; 41 A_UINT32 s5; 42 A_UINT32 s6; 43 A_UINT32 s7; 44 A_UINT32 t8; 45 A_UINT32 t9; 46 A_UINT32 k0; 47 A_UINT32 k1; 48 A_UINT32 gp; 49 A_UINT32 sp; 50 A_UINT32 s8; 51 A_UINT32 ra; 52 A_UINT32 cause; /* Selected coprocessor regs */ 53 A_UINT32 status; 54}; 55typedef struct MIPS_exception_frame_s CPU_exception_frame_t; 56 57#endif 58 59/* 60 * Offsets into MIPS_exception_frame structure, for use in assembler code 61 * MUST MATCH C STRUCTURE ABOVE 62 */ 63#define RD_pc 0 64#define RD_at 1 65#define RD_v0 2 66#define RD_v1 3 67#define RD_a0 4 68#define RD_a1 5 69#define RD_a2 6 70#define RD_a3 7 71#define RD_t0 8 72#define RD_t1 9 73#define RD_t2 10 74#define RD_t3 11 75#define RD_t4 12 76#define RD_t5 13 77#define RD_t6 14 78#define RD_t7 15 79#define RD_s0 16 80#define RD_s1 17 81#define RD_s2 18 82#define RD_s3 19 83#define RD_s4 20 84#define RD_s5 21 85#define RD_s6 22 86#define RD_s7 23 87#define RD_t8 24 88#define RD_t9 25 89#define RD_k0 26 90#define RD_k1 27 91#define RD_gp 28 92#define RD_sp 29 93#define RD_s8 30 94#define RD_ra 31 95#define RD_cause 32 96#define RD_status 33 97 98#define RD_SIZE (34*4) /* Space for this number of words */ 99 100#endif /* __AR6000_REGDUMP_H__ */ 101