1/* 2 * Copyright (C) 2007 PA Semi, Inc 3 * 4 * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and 5 * hardware register layouts. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21#ifndef PASEMI_FNU_H 22#define PASEMI_FNU_H 23 24#include <linux/spinlock.h> 25 26#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) 27#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) 28#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } 29 30/* Must be a power of two */ 31#define RX_RING_SIZE 512 32#define TX_RING_SIZE 512 33#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) 34#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) 35#define MAX_DESC_SIZE 8 36#define PASEMI_INITIAL_SESSIONS 10 37#define PASEMI_FNU_CHANNELS 8 38 39/* DMA descriptor */ 40struct pasemi_desc { 41 u64 quad[2*MAX_DESC_SIZE]; 42 int quad_cnt; 43 int size; 44 int postop; 45}; 46 47/* 48 * Holds per descriptor data 49 */ 50struct pasemi_desc_info { 51 int desc_size; 52 int desc_postop; 53#define PASEMI_CHECK_SIG 0x1 54 55 struct cryptop *cf_crp; 56}; 57 58/* 59 * Holds per channel data 60 */ 61struct pasemi_fnu_txring { 62 volatile u64 *desc; 63 volatile struct 64 pasemi_desc_info *desc_info; 65 dma_addr_t dma; 66 struct timer_list crypto_timer; 67 spinlock_t fill_lock; 68 spinlock_t clean_lock; 69 unsigned int next_to_fill; 70 unsigned int next_to_clean; 71 u16 total_pktcnt; 72 int irq; 73 int sesn; 74 char irq_name[10]; 75}; 76 77/* 78 * Holds data specific to a single pasemi device. 79 */ 80struct pasemi_softc { 81 softc_device_decl sc_cdev; 82 struct pci_dev *dma_pdev; /* device backpointer */ 83 struct pci_dev *iob_pdev; /* device backpointer */ 84 void __iomem *dma_regs; 85 void __iomem *iob_regs; 86 int base_irq; 87 int base_chan; 88 int32_t sc_cid; /* crypto tag */ 89 int sc_nsessions; 90 struct pasemi_session **sc_sessions; 91 int sc_num_channels;/* number of crypto channels */ 92 93 /* pointer to the array of txring datastructures, one txring per channel */ 94 struct pasemi_fnu_txring *tx; 95 96 /* 97 * mutual exclusion for the channel scheduler 98 */ 99 spinlock_t sc_chnlock; 100 /* last channel used, for now use round-robin to allocate channels */ 101 int sc_lastchn; 102}; 103 104struct pasemi_session { 105 u64 civ[2]; 106 u64 keysz; 107 u64 key[4]; 108 u64 ccmd; 109 u64 hkey[4]; 110 u64 hseq; 111 u64 giv[2]; 112 u64 hiv[4]; 113 114 int used; 115 dma_addr_t dma_addr; 116 int chan; 117}; 118 119/* status register layout in IOB region, at 0xfd800000 */ 120struct pasdma_status { 121 u64 rx_sta[64]; 122 u64 tx_sta[20]; 123}; 124 125#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ 126 (alg == CRYPTO_3DES_CBC) || \ 127 (alg == CRYPTO_AES_CBC) || \ 128 (alg == CRYPTO_ARC4) || \ 129 (alg == CRYPTO_NULL_CBC)) 130 131#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ 132 (alg == CRYPTO_MD5_HMAC) || \ 133 (alg == CRYPTO_SHA1) || \ 134 (alg == CRYPTO_SHA1_HMAC) || \ 135 (alg == CRYPTO_NULL_HMAC)) 136 137enum { 138 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ 139 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ 140 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ 141 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ 142 PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ 143}; 144 145/* All these registers live in the PCI configuration space for the DMA PCI 146 * device. Use the normal PCI config access functions for them. 147 */ 148 149#define PAS_DMA_COM_CFG_FWF 0x18000000 150 151#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ 152#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ 153#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ 154#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ 155 156#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ 157#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ 158#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ 159#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ 160#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ 161#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ 162#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ 163#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ 164#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) 165#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ 166#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ 167#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ 168#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) 169#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ 170#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ 171#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c 172#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 173#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ 174 PAS_DMA_TXCHAN_CFG_TATTR_M) 175#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 176#define PAS_DMA_TXCHAN_CFG_WT_S 6 177#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ 178 PAS_DMA_TXCHAN_CFG_WT_M) 179#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 180#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 181#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ 182#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ 183#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ 184#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) 185#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) 186#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 187#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 188#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ 189 PAS_DMA_TXCHAN_BASEL_BRBL_M) 190#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) 191#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff 192#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 193#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ 194 PAS_DMA_TXCHAN_BASEU_BRBH_M) 195/* # of cache lines worth of buffer ring */ 196#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 197#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ 198#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ 199 PAS_DMA_TXCHAN_BASEU_SIZ_M) 200 201#define PAS_STATUS_PCNT_M 0x000000000000ffffull 202#define PAS_STATUS_PCNT_S 0 203#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull 204#define PAS_STATUS_DCNT_S 16 205#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull 206#define PAS_STATUS_BPCNT_S 32 207#define PAS_STATUS_CAUSE_M 0xf000000000000000ull 208#define PAS_STATUS_TIMER 0x1000000000000000ull 209#define PAS_STATUS_ERROR 0x2000000000000000ull 210#define PAS_STATUS_SOFT 0x4000000000000000ull 211#define PAS_STATUS_INT 0x8000000000000000ull 212 213#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) 214#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff 215#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 216#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ 217 PAS_IOB_DMA_RXCH_CFG_CNTTH_M) 218#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) 219#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff 220#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 221#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ 222 PAS_IOB_DMA_TXCH_CFG_CNTTH_M) 223#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) 224#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 225#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff 226#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 227#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ 228 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) 229#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) 230#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 231#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff 232#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 233#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ 234 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) 235#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) 236#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 237#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 238#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ 239 PAS_IOB_DMA_RXCH_RESET_PCNT_M) 240#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 241#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 242#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 243#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 244#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 245#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 246#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) 247#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 248#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 249#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ 250 PAS_IOB_DMA_TXCH_RESET_PCNT_M) 251#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 252#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 253#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 254#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 255#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 256#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 257 258#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 259#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff 260#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 261#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ 262 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) 263 264/* Transmit descriptor fields */ 265#define XCT_MACTX_T 0x8000000000000000ull 266#define XCT_MACTX_ST 0x4000000000000000ull 267#define XCT_MACTX_NORES 0x0000000000000000ull 268#define XCT_MACTX_8BRES 0x1000000000000000ull 269#define XCT_MACTX_24BRES 0x2000000000000000ull 270#define XCT_MACTX_40BRES 0x3000000000000000ull 271#define XCT_MACTX_I 0x0800000000000000ull 272#define XCT_MACTX_O 0x0400000000000000ull 273#define XCT_MACTX_E 0x0200000000000000ull 274#define XCT_MACTX_VLAN_M 0x0180000000000000ull 275#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull 276#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull 277#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull 278#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull 279#define XCT_MACTX_CRC_M 0x0060000000000000ull 280#define XCT_MACTX_CRC_NOP 0x0000000000000000ull 281#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull 282#define XCT_MACTX_CRC_PAD 0x0040000000000000ull 283#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull 284#define XCT_MACTX_SS 0x0010000000000000ull 285#define XCT_MACTX_LLEN_M 0x00007fff00000000ull 286#define XCT_MACTX_LLEN_S 32ull 287#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ 288 XCT_MACTX_LLEN_M) 289#define XCT_MACTX_IPH_M 0x00000000f8000000ull 290#define XCT_MACTX_IPH_S 27ull 291#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ 292 XCT_MACTX_IPH_M) 293#define XCT_MACTX_IPO_M 0x0000000007c00000ull 294#define XCT_MACTX_IPO_S 22ull 295#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ 296 XCT_MACTX_IPO_M) 297#define XCT_MACTX_CSUM_M 0x0000000000000060ull 298#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull 299#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull 300#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull 301#define XCT_MACTX_V6 0x0000000000000010ull 302#define XCT_MACTX_C 0x0000000000000004ull 303#define XCT_MACTX_AL2 0x0000000000000002ull 304 305#define XCT_PTR_T 0x8000000000000000ull 306#define XCT_PTR_LEN_M 0x7ffff00000000000ull 307#define XCT_PTR_LEN_S 44 308#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ 309 XCT_PTR_LEN_M) 310#define XCT_PTR_ADDR_M 0x00000fffffffffffull 311#define XCT_PTR_ADDR_S 0 312#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ 313 XCT_PTR_ADDR_M) 314 315/* Function descriptor fields */ 316#define XCT_FUN_T 0x8000000000000000ull 317#define XCT_FUN_ST 0x4000000000000000ull 318#define XCT_FUN_NORES 0x0000000000000000ull 319#define XCT_FUN_8BRES 0x1000000000000000ull 320#define XCT_FUN_24BRES 0x2000000000000000ull 321#define XCT_FUN_40BRES 0x3000000000000000ull 322#define XCT_FUN_I 0x0800000000000000ull 323#define XCT_FUN_O 0x0400000000000000ull 324#define XCT_FUN_E 0x0200000000000000ull 325#define XCT_FUN_FUN_S 54 326#define XCT_FUN_FUN_M 0x01c0000000000000ull 327#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ 328 XCT_FUN_FUN_M) 329#define XCT_FUN_CRM_NOP 0x0000000000000000ull 330#define XCT_FUN_CRM_SIG 0x0008000000000000ull 331#define XCT_FUN_CRM_ENC 0x0010000000000000ull 332#define XCT_FUN_CRM_DEC 0x0018000000000000ull 333#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull 334#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull 335#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull 336#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull 337#define XCT_FUN_LLEN_M 0x0007ffff00000000ull 338#define XCT_FUN_LLEN_S 32ULL 339#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ 340 XCT_FUN_LLEN_M) 341#define XCT_FUN_SHL_M 0x00000000f8000000ull 342#define XCT_FUN_SHL_S 27ull 343#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ 344 XCT_FUN_SHL_M) 345#define XCT_FUN_CHL_M 0x0000000007c00000ull 346#define XCT_FUN_CHL_S 22ull 347#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ 348 XCT_FUN_CHL_M) 349#define XCT_FUN_HSZ_M 0x00000000003c0000ull 350#define XCT_FUN_HSZ_S 18ull 351#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ 352 XCT_FUN_HSZ_M) 353#define XCT_FUN_ALG_DES 0x0000000000000000ull 354#define XCT_FUN_ALG_3DES 0x0000000000008000ull 355#define XCT_FUN_ALG_AES 0x0000000000010000ull 356#define XCT_FUN_ALG_ARC 0x0000000000018000ull 357#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull 358#define XCT_FUN_BCM_ECB 0x0000000000000000ull 359#define XCT_FUN_BCM_CBC 0x0000000000001000ull 360#define XCT_FUN_BCM_CFB 0x0000000000002000ull 361#define XCT_FUN_BCM_OFB 0x0000000000003000ull 362#define XCT_FUN_BCM_CNT 0x0000000000003800ull 363#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull 364#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull 365#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull 366#define XCT_FUN_BCP_ZRO 0x0000000000000200ull 367#define XCT_FUN_BCP_PL 0x0000000000000400ull 368#define XCT_FUN_BCP_INCR 0x0000000000000600ull 369#define XCT_FUN_SIG_MD5 (0ull << 4) 370#define XCT_FUN_SIG_SHA1 (2ull << 4) 371#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) 372#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) 373#define XCT_FUN_A 0x0000000000000008ull 374#define XCT_FUN_C 0x0000000000000004ull 375#define XCT_FUN_AL2 0x0000000000000002ull 376#define XCT_FUN_SE 0x0000000000000001ull 377 378#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) 379#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ 380 0x8000000000000000ull) 381 382#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull 383#define XCT_CTRL_HDR_FUN_NUM_S 54 384#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull 385#define XCT_CTRL_HDR_LEN_S 32 386#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull 387#define XCT_CTRL_HDR_REG_S 0 388 389#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ 390 ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ 391 & XCT_CTRL_HDR_FUN_NUM_M) | \ 392 ((((long)(len)) << \ 393 XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ 394 ((((long)(reg)) << \ 395 XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) 396 397/* Function config command options */ 398#define DMA_CALGO_DES 0x00 399#define DMA_CALGO_3DES 0x01 400#define DMA_CALGO_AES 0x02 401#define DMA_CALGO_ARC 0x03 402 403#define DMA_FN_CIV0 0x02 404#define DMA_FN_CIV1 0x03 405#define DMA_FN_HKEY0 0x0a 406 407#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ 408 (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) 409 410#endif /* PASEMI_FNU_H */ 411