1/******************************************************************************* 2Copyright (C) Marvell International Ltd. and its affiliates 3 4This software file (the "File") is owned and distributed by Marvell 5International Ltd. and/or its affiliates ("Marvell") under the following 6alternative licensing terms. Once you have made an election to distribute the 7File under one of the following license alternatives, please (i) delete this 8introductory statement regarding license alternatives, (ii) delete the two 9license alternatives that you have not elected to use and (iii) preserve the 10Marvell copyright notice above. 11 12******************************************************************************** 13Marvell Commercial License Option 14 15If you received this File from Marvell and you have entered into a commercial 16license agreement (a "Commercial License") with Marvell, the File is licensed 17to you under the terms of the applicable Commercial License. 18 19******************************************************************************** 20Marvell GPL License Option 21 22If you received this File from Marvell, you may opt to use, redistribute and/or 23modify this File in accordance with the terms and conditions of the General 24Public License Version 2, June 1991 (the "GPL License"), a copy of which is 25available along with the File in the license.txt file or by writing to the Free 26Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or 27on the worldwide web at http://www.gnu.org/licenses/gpl.txt. 28 29THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED 30WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY 31DISCLAIMED. The GPL License provides additional details about this warranty 32disclaimer. 33******************************************************************************** 34Marvell BSD License Option 35 36If you received this File from Marvell, you may opt to use, redistribute and/or 37modify this File under the following licensing terms. 38Redistribution and use in source and binary forms, with or without modification, 39are permitted provided that the following conditions are met: 40 41 * Redistributions of source code must retain the above copyright notice, 42 this list of conditions and the following disclaimer. 43 44 * Redistributions in binary form must reproduce the above copyright 45 notice, this list of conditions and the following disclaimer in the 46 documentation and/or other materials provided with the distribution. 47 48 * Neither the name of Marvell nor the names of its contributors may be 49 used to endorse or promote products derived from this software without 50 specific prior written permission. 51 52THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 53ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 56ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 58LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 59ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 61SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 63*******************************************************************************/ 64 65 66#ifndef __INCmvDramIfConfigh 67#define __INCmvDramIfConfigh 68 69#ifdef __cplusplus 70extern "C" { 71#endif /* __cplusplus */ 72 73/* includes */ 74 75/* defines */ 76 77/* registers defaults values */ 78 79#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) 80 81#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ 82 (SDRAM_SRCLK_KEPT | \ 83 SDRAM_CLK1DRV_NORMAL | \ 84 (BIT28 | BIT29)) 85 86#define SDRAM_ADDR_CTRL_DV 2 87 88#define SDRAM_TIMING_CTRL_LOW_REG_DV \ 89 ((0x2 << SDRAM_TRCD_OFFS) | \ 90 (0x2 << SDRAM_TRP_OFFS) | \ 91 (0x1 << SDRAM_TWR_OFFS) | \ 92 (0x0 << SDRAM_TWTR_OFFS) | \ 93 (0x5 << SDRAM_TRAS_OFFS) | \ 94 (0x1 << SDRAM_TRRD_OFFS)) 95 96/* Note: value of 0 in register means one cycle, 1 means two and so on */ 97#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ 98 ((0x0 << SDRAM_TR2R_OFFS) | \ 99 (0x0 << SDRAM_TR2W_W2R_OFFS) | \ 100 (0x1 << SDRAM_TW2W_OFFS)) 101 102#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN 103 104/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ 105/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ 106/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ 107/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ 108/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ 109/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ 110/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ 111 112#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 113#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 114#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F 115#ifdef MV78XX0 116#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 117#else 118#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 119#endif 120 121#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C 122#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 123#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F 124#ifdef MV78XX0 125#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 126#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 127#else 128#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 129#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 130#endif 131 132/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ 133#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ 134 (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) 135 136#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ 137 (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) 138 139/* DDR SDRAM Mode Register default value */ 140#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) 141/* DDR SDRAM Timing parameter default values */ 142#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 143#define SDRAM_TRFC_DEFAULT_VALUE 0x34 144#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE 145#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) 146 147#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) 148 149#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 150#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 151#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 152 153#ifdef __cplusplus 154} 155#endif /* __cplusplus */ 156 157#endif /* __INCmvDramIfh */ 158