1/******************************************************************************* 2Copyright (C) Marvell International Ltd. and its affiliates 3 4This software file (the "File") is owned and distributed by Marvell 5International Ltd. and/or its affiliates ("Marvell") under the following 6alternative licensing terms. Once you have made an election to distribute the 7File under one of the following license alternatives, please (i) delete this 8introductory statement regarding license alternatives, (ii) delete the two 9license alternatives that you have not elected to use and (iii) preserve the 10Marvell copyright notice above. 11 12******************************************************************************** 13Marvell Commercial License Option 14 15If you received this File from Marvell and you have entered into a commercial 16license agreement (a "Commercial License") with Marvell, the File is licensed 17to you under the terms of the applicable Commercial License. 18 19******************************************************************************** 20Marvell GPL License Option 21 22If you received this File from Marvell, you may opt to use, redistribute and/or 23modify this File in accordance with the terms and conditions of the General 24Public License Version 2, June 1991 (the "GPL License"), a copy of which is 25available along with the File in the license.txt file or by writing to the Free 26Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or 27on the worldwide web at http://www.gnu.org/licenses/gpl.txt. 28 29THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED 30WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY 31DISCLAIMED. The GPL License provides additional details about this warranty 32disclaimer. 33******************************************************************************** 34Marvell BSD License Option 35 36If you received this File from Marvell, you may opt to use, redistribute and/or 37modify this File under the following licensing terms. 38Redistribution and use in source and binary forms, with or without modification, 39are permitted provided that the following conditions are met: 40 41 * Redistributions of source code must retain the above copyright notice, 42 this list of conditions and the following disclaimer. 43 44 * Redistributions in binary form must reproduce the above copyright 45 notice, this list of conditions and the following disclaimer in the 46 documentation and/or other materials provided with the distribution. 47 48 * Neither the name of Marvell nor the names of its contributors may be 49 used to endorse or promote products derived from this software without 50 specific prior written permission. 51 52THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 53ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 54WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 55DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 56ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 57(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 58LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 59ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 61SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 63*******************************************************************************/ 64 65#define MV_ASMLANGUAGE 66#include "mvSysHwConfig.h" 67#include "mvOsAsm.h" 68#include "mvBoardEnvSpec.h" 69#include "mvCpuIfRegs.h" 70#include "mvDramIfConfig.h" 71#include "mvDramIfRegs.h" 72#include "pex/mvPexRegs.h" 73#include "pci/mvPciRegs.h" 74#include "mvCtrlEnvSpec.h" 75#include "mvCtrlEnvAsm.h" 76#include "cpu/mvCpuArm.h" 77#include "mvCommon.h" 78 79/* defines */ 80 81#if !defined(MV_INC_BOARD_DDIM) 82.globl dramBoot1 83dramBoot1: 84 .word 0 85 86/****************************************************************************** 87* 88* 89* 90* 91*******************************************************************************/ 92#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) 93 94/* PEX_PCI and PRPMC boards 256 MB*/ 95#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 96#define STATIC_SDRAM_CONFIG 0x03248400 97#define STATIC_SDRAM_MODE 0x62 98#define STATIC_DUNIT_CTRL_LOW 0x4041000 99#define STATIC_SDRAM_ADDR_CTRL 0x00000020 100#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 101#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F 102#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 103#define STATIC_SDRAM_ODT_CTRL_HI 0x0 104#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 105#define STATIC_SDRAM_EXT_MODE 0x0 106 107#elif defined(DB_FPGA) 108 109/* FPGA DC boards 256 MB*/ 110#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 111#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ 112#define STATIC_SDRAM_MODE 0x22 113#define STATIC_DUNIT_CTRL_LOW 0x03041000 114#define STATIC_SDRAM_ADDR_CTRL 0x00000020 115#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 116#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D 117#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 118#define STATIC_SDRAM_ODT_CTRL_HI 0x0 119#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 120#define STATIC_SDRAM_EXT_MODE 0x1 121 122#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) 123 124/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ 125#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 126#define STATIC_SDRAM_CONFIG 0x03158400 127#define STATIC_SDRAM_MODE 0x452 128#define STATIC_DUNIT_CTRL_LOW 0x06041000 129#define STATIC_SDRAM_ADDR_CTRL 0x00000020 130#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 131#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 132#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 133#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 134#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 135#define STATIC_SDRAM_EXT_MODE 0x00000440 136 137 138#elif defined(RD_88F6183AP) 139 140/* DDR2 1 devices 512Mbit by 16 bit */ 141#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 142#define STATIC_SDRAM_CONFIG 0x1f154400 143#define STATIC_SDRAM_MODE 0x432 144#define STATIC_DUNIT_CTRL_LOW 0x04041000 145#define STATIC_SDRAM_ADDR_CTRL 0x00000020 146#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 147#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 148#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 149#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 150#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 151#define STATIC_SDRAM_EXT_MODE 0x00000440 152 153/* 6082L MARVELL DIMM */ 154#elif defined(DB_88F6082LBP) 155#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 156#define STATIC_SDRAM_CONFIG 0x7f158400 157#define STATIC_SDRAM_MODE 0x432 158#define STATIC_DUNIT_CTRL_LOW 0x04041040 159#define STATIC_SDRAM_ADDR_CTRL 0x00000020 160#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 161#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 162#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 163#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 164#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 165#define STATIC_SDRAM_EXT_MODE 0x00000440 166 167#elif defined(RD_88W8660_AP82S) 168 169/* Shark RD */ 170 171#if defined(MV_DRAM_32M) 172#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 173#define STATIC_SDRAM_ADDR_CTRL 0x00000010 174#elif defined(MV_DRAM_16M) 175 176#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 177#define STATIC_SDRAM_ADDR_CTRL 0x00000000 178 179#else 180#error "NO DDR size selected" 181#endif 182 183#define STATIC_SDRAM_CONFIG 0x03144400 184#define STATIC_SDRAM_MODE 0x62 185#define STATIC_DUNIT_CTRL_LOW 0x4041000 186 187#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 188#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b 189#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 190#define STATIC_SDRAM_ODT_CTRL_HI 0x0 191#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 192#define STATIC_SDRAM_EXT_MODE 0x0 193 194#elif defined(RD_88W8660) 195 196/* Shark RD */ 197#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 198#define STATIC_SDRAM_CONFIG 0x03144400 199#define STATIC_SDRAM_MODE 0x62 200#define STATIC_DUNIT_CTRL_LOW 0x4041000 201#define STATIC_SDRAM_ADDR_CTRL 0x00000010 202#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 203#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b 204#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 205#define STATIC_SDRAM_ODT_CTRL_HI 0x0 206#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 207#define STATIC_SDRAM_EXT_MODE 0x0 208 209#else /* NAS */ 210 211 212#if defined(RD_88F5182) 213 214#if defined(MV_88F5082) 215#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 216#define STATIC_SDRAM_ADDR_CTRL 0x20 217#else 218#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 219#define STATIC_SDRAM_ADDR_CTRL 0x20 220#endif 221 222#elif defined(RD_88F5182_3) 223 224#if defined(MV_88F5082) 225#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 226#define STATIC_SDRAM_ADDR_CTRL 0x20 227#else 228#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 229#define STATIC_SDRAM_ADDR_CTRL 0x20 230#endif 231 232#else 233 234#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 235#define STATIC_SDRAM_ADDR_CTRL 0x0 236 237#endif 238 239#if defined(MV_88F5082) 240#define STATIC_SDRAM_CONFIG 0x3144400 241#else 242#define STATIC_SDRAM_CONFIG 0x3148400 243#endif 244#define STATIC_SDRAM_MODE 0x62 245#define STATIC_DUNIT_CTRL_LOW 0x4041000 246#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 247#define STATIC_SDRAM_TIME_CTRL_HI 0x40c 248#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 249#define STATIC_SDRAM_ODT_CTRL_HI 0x0 250#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 251#define STATIC_SDRAM_EXT_MODE 0x0 252 253#endif 254 255 .globl _mvDramIfStaticInit 256_mvDramIfStaticInit: 257 258 mov r11, LR /* Save link register */ 259 mov r10, r2 260 261 /* If we boot from NAND jump to DRAM sddress */ 262 263 mov r5, #1 264 ldr r6, =dramBoot1 265 str r5, [r6] /* We started executing from DRAM */ 266 267 ldr r6, dramBoot1 268 cmp r6, #0 269 bne 1f 270 271 272 /* set all dram windows to 0 */ 273 mov r6, #0 274 MV_REG_WRITE_ASM(r6, r5, 0x1504) 275 MV_REG_WRITE_ASM(r6, r5, 0x150c) 276 MV_REG_WRITE_ASM(r6, r5, 0x1514) 277 MV_REG_WRITE_ASM(r6, r5, 0x151c) 278 279 /* set all dram configuration in temp registers */ 280 ldr r6, = STATIC_SDRAM0_BANK0_SIZE 281 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) 282 ldr r6, = STATIC_SDRAM_CONFIG 283 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) 284 ldr r6, = STATIC_SDRAM_MODE 285 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) 286 ldr r6, = STATIC_DUNIT_CTRL_LOW 287 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) 288 ldr r6, = STATIC_SDRAM_ADDR_CTRL 289 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) 290 ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW 291 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) 292 ldr r6, = STATIC_SDRAM_TIME_CTRL_HI 293 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) 294 ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW 295 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) 296 ldr r6, = STATIC_SDRAM_ODT_CTRL_HI 297 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) 298 ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL 299 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) 300 ldr r6, = STATIC_SDRAM_EXT_MODE 301 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) 302 303 mov sp, #0 304 bl _mvDramIfConfig 3051: 306 mov r2, r10 307 mov PC, r11 /* r11 is saved link register */ 308 309#else /* #if !defined(MV_INC_BOARD_DDIM) */ 310 311.globl dramBoot1 312dramBoot1: 313 .word 0 314 315/******************************************************************************* 316* mvDramIfBasicInit - Basic initialization of DRAM interface 317* 318* DESCRIPTION: 319* The function will initialize the DRAM for basic usage. The function 320* will use the TWSI assembly API to extract DIMM parameters according 321* to which DRAM interface will be initialized. 322* The function referes to the following DRAM parameters: 323* 1) DIMM is registered or not. 324* 2) DIMM width detection. 325* 3) DIMM density. 326* 327* INPUT: 328* r3 - required size for initial DRAM. 329* 330* OUTPUT: 331* None. 332* 333* RETURN: 334* None. 335* 336* Note: 337* r4 holds I2C EEPROM address 338* r5 holds SDRAM register base address 339* r7 holds returned values 340* r8 holds SDRAM various configuration registers value. 341* r11 holds return function address. 342*******************************************************************************/ 343/* Setting the offsets of the I2C registers */ 344#define NUM_OF_ROWS_OFFSET 3 345#define NUM_OF_COLS_OFFSET 4 346#define NUM_OF_RANKS 5 347#define SDRAM_WIDTH_OFFSET 13 348#define NUM_OF_BANKS_OFFSET 17 349#define SUPPORTED_CL_OFFSET 18 350#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ 351#define SDRAM_MODULES_ATTR_OFFSET 21 352 353#define DRAM_DEV_DENSITY_128M 0x080 354#define DRAM_DEV_DENSITY_256M 0x100 355#define DRAM_DEV_DENSITY_512M 0x200 356 .globl _mvDramIfBasicInit 357 .extern _i2cInit 358 359_mvDramIfBasicInit: 360 361 mov r11, LR /* Save link register */ 362 363 mov r5, #1 364 ldr r8, =dramBoot1 365 str r5, [r8] /* We started executing from DRAM */ 366 367 /* If we boot from NAND jump to DRAM sddress */ 368 ldr r8, dramBoot1 369 cmp r8, #0 370 movne pc, r11 371 372 373 374 bl _i2cInit /* Initialize TWSI master */ 375 376 /* Get default SDRAM Config values */ 377 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) 378 bic r8, r8, #SDRAM_DCFG_MASK 379 380 381 /* Read device ID */ 382 MV_CTRL_MODEL_GET_ASM(r4, r5); 383 384 /* Return if OrionN */ 385 ldr r5, =MV_5180_DEV_ID 386 cmp r4, r5 387 beq cat_through_end 388 389 /* Return if Orion1 */ 390 ldr r5, =MV_5181_DEV_ID 391 cmp r4, r5 392 beq cat_through_end 393 394 /* Return if Nas */ 395 ldr r5, =MV_5182_DEV_ID 396 cmp r4, r5 397 beq cat_through_end 398 399 /* Return if Shark */ 400 ldr r5, =MV_8660_DEV_ID 401 cmp r4, r5 402 beq cat_through_end 403 404 /* goto calcConfigReg if bigger than Orion2*/ 405 ldr r5, =MV_5281_DEV_ID 406 cmp r4, r5 407 bne cat_through 408 409cat_through: 410 /* set cat through - for better performance - in orion2 b0 and higher*/ 411 orr r8, r8, #SDRAM_CATTHR_EN 412 413cat_through_end: 414 415 416 /* Get registered/non registered info from DIMM */ 417 bl _is_Registered 418 beq nonRegistered 419 420setRegistered: 421 orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ 422 423nonRegistered: 424 /* Get SDRAM width */ 425 bl _get_width 426 427 orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ 428 cmp r7, #16 429 beq setConfigReg 430 431 orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ 432 cmp r7, #8 433 beq setConfigReg 434 435 /* This is an error. return */ 436 b exit_ddrAutoConfig 437 438setConfigReg: 439 mov r8, r6 440 ldr r6, =SDRAM_CONFIG_DV 441 orr r8, r8, r6 /* Add default settings */ 442 mov r6, r8 /* Do not swap r8 content */ 443 MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) 444 445 /* Set maximum CL supported by DIMM */ 446 bl _get_CAL 447 448 /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ 449 clz r6, r7 450 rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ 451 452 /* Check the DDR version */ 453 tst r8, #SDRAM_DTYPE_DDR2 454 bne casDdr2 455 456casDdr1: 457 ldr r7, =3 /* stBurstDel field value */ 458 ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ 459 cmp r6, #1 /* If CL = 1.5 break */ 460 beq setModeReg 461 462 ldr r7, =3 /* stBurstDel field value */ 463 ldr r8, =0x22 /* Assuming MAX CL = 2 */ 464 cmp r6, #2 /* If CL = 2 break */ 465 beq setModeReg 466 467 ldr r7, =4 /* stBurstDel field value */ 468 ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ 469 cmp r6, #3 /* If CL = 2.5 break */ 470 beq setModeReg 471 472 ldr r7, =4 /* stBurstDel field value */ 473 ldr r8, =0x32 /* Assuming MAX CL = 3 */ 474 cmp r6, #4 /* If CL = 3 break */ 475 beq setModeReg 476 477 ldr r7, =5 /* stBurstDel field value */ 478 ldr r8, =0x42 /* Assuming MAX CL = 4 */ 479 cmp r6, #6 /* If CL = 4 break */ 480 b setModeReg 481 482 b exit_ddrAutoConfig /* This is an error !! */ 483 484casDdr2: 485 ldr r7, =4 /* stBurstDel field value */ 486 ldr r8, =0x32 /* Assuming MAX CL = 3 */ 487 cmp r6, #3 /* If CL = 3 break */ 488 beq casDdr2Cont 489 490 ldr r7, =5 /* stBurstDel field value */ 491 ldr r8, =0x42 /* Assuming MAX CL = 4 */ 492 cmp r6, #4 /* If CL = 4 break */ 493 beq casDdr2Cont 494 495 /* CL 5 currently unsupported. We use CL 4 instead */ 496 ldr r7, =5 /* stBurstDel field value */ 497 ldr r8, =0x42 /* Assuming MAX CL = 5 */ 498 cmp r6, #5 /* If CL = 5 break */ 499 beq casDdr2Cont 500 501 b exit_ddrAutoConfig /* This is an error !! */ 502casDdr2Cont: 503 /* Write recovery for auto-precharge relevant only in DDR2 */ 504 orr r8, r8, #0x400 /* Default value */ 505 506setModeReg: 507 /* The CPU must not attempt to change the SDRAM Mode register setting */ 508 /* prior to DRAM controller completion of the DRAM initialization */ 509 /* sequence. To guarantee this restriction, it is recommended that */ 510 /* the CPU sets the SDRAM Operation register to NOP command, performs */ 511 /* read polling until the register is back in Normal operation value, */ 512 /* and then sets SDRAM Mode register to it's new value. */ 513 514 /* write 'nop' to SDRAM operation */ 515 mov r6, #0x5 /* 'NOP' command */ 516 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) 517 518 /* poll SDRAM operation. Make sure its back to normal operation */ 519_sdramOpPoll1: 520 ldr r6, [r5] 521 cmp r6, #0 /* '0' = Normal SDRAM Mode */ 522 bne _sdramOpPoll1 523 524 /* Now its safe to write new value to SDRAM Mode register */ 525 MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) 526 527 /* Make the Dunit write the DRAM its new mode */ 528 mov r6, #0x3 /* Mode Register Set command */ 529 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) 530 531 /* poll SDRAM operation. Make sure its back to normal operation */ 532_sdramOpPoll2: 533 ldr r6, [r5] 534 cmp r6, #0 /* '0' = Normal SDRAM Mode */ 535 bne _sdramOpPoll2 536 537 /* Set Dunit control register according to max CL detected */ 538 /* If we use registered DIMM, add 1 to stBurstDel */ 539 MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) 540 tst r6, #SDRAM_REGISTERED 541 beq setDunitReg 542 add r7, r7, #1 543 544setDunitReg: 545 ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV 546 orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS 547 MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) 548 549 550 /* DIMM density configuration*/ 551 /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ 552Density: 553 bl _getDensity 554 mov r8, r7 555 mov r8, r8, LSR #20 /* Move density 20 bits to the right */ 556 /* For example 0x10000000 --> 0x1000 */ 557 558 mov r6, #0x00 559 cmp r8, #DRAM_DEV_DENSITY_128M 560 beq densCont 561 562 mov r6, #0x10 563 cmp r8, #DRAM_DEV_DENSITY_256M 564 beq densCont 565 566 mov r6, #0x20 567 cmp r8, #DRAM_DEV_DENSITY_512M 568 beq densCont 569 570 /* This is an error. return */ 571 b exit_ddrAutoConfig 572 573densCont: 574 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) 575 576 /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ 577 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) 578 tst r8, #SDRAM_DTYPE_DDR2 579 beq _extModeODTEnd 580 581 582 /* Set DDR Extended Mode register for working with CS[0] */ 583 /* write 'nop' to SDRAM operation */ 584 mov r6, #0x5 /* 'NOP' command */ 585 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) 586 587 /* poll SDRAM operation. Make sure its back to normal operation */ 588_sdramOpPoll3: 589 ldr r6, [r5] 590 cmp r6, #0 /* '0' = Normal SDRAM Mode */ 591 bne _sdramOpPoll3 592 593 /* Now its safe to write new value to SDRAM Extended Mode register */ 594 ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV 595 MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) 596 597 /* Make the Dunit write the DRAM its new extended mode */ 598 mov r6, #0x4 /* Extended Mode Register Set command */ 599 MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) 600 601 /* poll SDRAM operation. Make sure its back to normal operation */ 602_sdramOpPoll4: 603 ldr r6, [r5] 604 cmp r6, #0 /* '0' = Normal SDRAM Mode */ 605 bne _sdramOpPoll4 606 607 /* ODT configuration is done for single bank CS[0] only */ 608 /* Config DDR2 On Die Termination (ODT) registers */ 609 ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV 610 MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) 611 612 ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV 613 MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) 614 615 ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV 616 MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) 617 618 619 /* we will check what device we are running and perform 620 Initialization according to device value */ 621 622_extModeODTEnd: 623 624 /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ 625 /* Does Not Work for Address/Control and Data Pads. */ 626 /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ 627 628 /* Read device ID */ 629 MV_CTRL_MODEL_GET_ASM(r6, r5); 630 /* Read device revision */ 631 MV_CTRL_REV_GET_ASM(r8, r5); 632 633 /* Continue if OrionN */ 634 ldr r5, =MV_5180_DEV_ID 635 cmp r6, r5 636 bne 1f 637 b glMem2End 6381: 639 640 /* Continue if Orion1 and device revision B1 */ 641 ldr r5, =MV_5181_DEV_ID 642 cmp r6, r5 643 bne 1f 644 645 cmp r8, #MV_5181_B1_REV 646 bge glMem2End 647 b glMem2Start 6481: 649 650 /* Orion NAS */ 651 ldr r5, =MV_5182_DEV_ID 652 cmp r6, r5 653 beq glMem2Start 654 655 /* Orion Shark */ 656 ldr r5, =MV_8660_DEV_ID 657 cmp r6, r5 658 beq glMem2Start 659 660 b glMem2End 661 662glMem2Start: 663 664 /* DDR SDRAM Address/Control Pads Calibration */ 665 MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) 666 667 /* Set Bit [31] to make the register writable */ 668 orr r8, r6, #SDRAM_WR_EN 669 670 MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) 671 672 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ 673 bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ 674 bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */ 675 bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */ 676 677 /* Get the final N locked value of driving strength [22:17] */ 678 mov r5, r6 679 mov r5, r5, LSL #9 680 mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */ 681 orr r5, r5, r5, LSL #6 /* r5[11:6]<DrvP> = r5[5:0]<DrvN> */ 682 683 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ 684 orr r6, r6, r5 685 686 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) 687 688 689 /* DDR SDRAM Data Pads Calibration */ 690 MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) 691 692 /* Set Bit [31] to make the register writable */ 693 orr r8, r6, #SDRAM_WR_EN 694 695 MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) 696 697 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ 698 bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ 699 bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */ 700 bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */ 701 702 /* Get the final N locked value of driving strength [22:17] */ 703 mov r5, r6 704 mov r5, r5, LSL #9 705 mov r5, r5, LSR #26 706 orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17]<LockN> */ 707 708 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ 709 orr r6, r6, r5 710 711 MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) 712 713glMem2End: 714 /* Implement Guideline (GL# MEM-3) Drive Strength Value */ 715 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ 716 717 /* Get SDRAM Config value */ 718 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) 719 720 /* Get DIMM type */ 721 tst r8, #SDRAM_DTYPE_DDR2 722 beq ddr1StrengthVal 723 724ddr2StrengthVal: 725 ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV 726 ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV 727 b setDrvStrength 728ddr1StrengthVal: 729 ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV 730 ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV 731 732setDrvStrength: 733 /* DDR SDRAM Address/Control Pads Calibration */ 734 MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) 735 736 orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ 737 738 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) 739 HTOLL(r6,r5) 740 741 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ 742 bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK 743 orr r6, r4, r6 /* Set default value for DDR */ 744 745 MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) 746 747 748 /* DDR SDRAM Data Pads Calibration */ 749 MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) 750 751 orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ 752 753 MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) 754 HTOLL(r6,r5) 755 756 bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ 757 bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK 758 orr r6, r8, r6 /* Set default value for DDR */ 759 760 MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) 761 762 763 /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ 764 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ 765 /* Get the "sample on reset" register for the DDR frequancy */ 766 767#if defined(MV_RUN_FROM_FLASH) 768 /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ 769 ldr r7, = _cpuARMDDRCLK 770 ldr r4, =_start 771 ldr r4, [r4] 772 sub r7, r7, r4 773 ldr r4, = Lrom_start_of_data 774 ldr r4, [r4] 775 add r7, r4, r7 776#else 777 /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ 778 ldr r7, = _cpuARMDDRCLK 779 ldr r4, =_start 780 sub r7, r7, r4 781 add r7, r7, #CFG_MONITOR_BASE 782#endif 783 /* Get the "sample on reset" register for the DDR frequancy */ 784 MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) 785 ldr r5, =MSAR_ARMDDRCLCK_MASK 786 and r5, r4, r5 787#if 0 /* YOTAM TO BE FIX */ 788 mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS 789#endif 790 791 /* Read device ID */ 792 MV_CTRL_MODEL_GET_ASM(r6, r8); 793 794 /* Continue if TC90 */ 795 ldr r8, =MV_1281_DEV_ID 796 cmp r6, r6 797 beq armClkMsb 798 799 /* Continue if Orion2 */ 800 ldr r8, =MV_5281_DEV_ID 801 cmp r6, r8 802#if 0 /* YOTAM TO BE FIX */ 803 bne 1f 804#endif 805 806armClkMsb: 807#if 0 /* YOTAM TO BE FIX */ 808 tst r4, #MSAR_ARMDDRCLCK_H_MASK 809 beq 1f 810 orr r5, r5, #BIT4 8111: 812 ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE 813 mul r5, r4, r5 814 add r7, r7, r5 815 add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF 816 ldr r5, [r7] 817#endif 818 819 /* Get SDRAM Config value */ 820 MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) 821 822 /* Get DIMM type */ 823 tst r8, #SDRAM_DTYPE_DDR2 824 beq ddr1FtdllVal 825 826ddr2FtdllVal: 827 ldr r4, =FTDLL_DDR2_250MHZ 828 ldr r7, =_250MHz 829 cmp r5, r7 830 beq setFtdllReg 831 ldr r4, =FTDLL_DDR2_200MHZ 832 ldr r7, =_200MHz 833 cmp r5, r7 834 beq setFtdllReg 835 ldr r4, =FTDLL_DDR2_166MHZ 836 ldr r7, =_166MHz 837 cmp r5, r7 838 beq setFtdllReg 839 ldr r4, =FTDLL_DDR2_133MHZ 840 b setFtdllReg 841 842ddr1FtdllVal: 843 ldr r4, =FTDLL_DDR1_200MHZ 844 ldr r7, =_200MHz 845 cmp r5, r7 846 beq setFtdllReg 847 ldr r4, =FTDLL_DDR1_166MHZ 848 ldr r7, =_166MHz 849 cmp r5, r7 850 beq setFtdllReg 851 ldr r4, =FTDLL_DDR1_133MHZ 852 ldr r7, =_133MHz 853 cmp r5, r7 854 beq setFtdllReg 855 ldr r4, =0 856 857setFtdllReg: 858 859#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) 860 MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) 861 orr r8, r8, r4 862 MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) 863 bic r8, r8, #1 864 MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) 865#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ 866 867 868setTimingReg: 869 /* Set default Timing parameters */ 870 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) 871 tst r8, #SDRAM_DTYPE_DDR2 872 bne ddr2TimeParam 873 874ddr1TimeParam: 875 ldr r6, =DDR1_TIMING_LOW_DV 876 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) 877 ldr r6, =DDR1_TIMING_HIGH_DV 878 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) 879 b timeParamDone 880 881ddr2TimeParam: 882 ldr r6, =DDR2_TIMING_LOW_DV 883 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) 884 ldr r6, =DDR2_TIMING_HIGH_DV 885 MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) 886 887timeParamDone: 888 /* Open CS[0] window to requested size and enable it. Disable other */ 889 /* windows */ 890 ldr r6, =SCBAR_BASE_MASK 891 sub r3, r3, #1 892 and r3, r3, r6 893 orr r3, r3, #1 /* Enable bank */ 894 MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) 895 ldr r6, =0 896 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) 897 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) 898 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) 899 900exit_ddrAutoConfig: 901 mov PC, r11 /* r11 is saved link register */ 902 903 904/***************************************************************************************/ 905/* r4 holds I2C EEPROM address 906 * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value 907 * r8 holds SDRAM various configuration registers value. 908 * r13 holds Link register 909 */ 910/**************************/ 911_getDensity: 912 mov r13, LR /* Save link register */ 913 914 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 915 mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ 916 bl _i2cRead 917 mov r8, r7 /* r8 save number of rows */ 918 919 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 920 mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ 921 bl _i2cRead 922 add r8, r8, r7 /* r8 = number of rows + number of col */ 923 924 mov r7, #0x1 925 mov r8, r7, LSL r8 /* r8 = (1 << r8) */ 926 927 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 928 mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ 929 bl _i2cRead 930 mul r8, r7, r8 931 932 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 933 mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ 934 bl _i2cRead 935 mul r7, r8, r7 936 937 mov PC, r13 938 939/**************************/ 940_get_width: 941 mov r13, LR /* Save link register */ 942 943 /* Get SDRAM width (SPD offset 13) */ 944 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 945 mov r7, #SDRAM_WIDTH_OFFSET 946 bl _i2cRead /* result in r7 */ 947 948 mov PC, r13 949 950/**************************/ 951_get_CAL: 952 mov r13, LR /* Save link register */ 953 954 /* Set maximum CL supported by DIMM */ 955 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 956 mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ 957 bl _i2cRead 958 959 mov PC, r13 960 961/**************************/ 962/* R8 - sdram configuration register. 963 * Return value in flag if no-registered then Z-flag is set 964 */ 965_is_Registered: 966 mov r13, LR /* Save link register */ 967 968 /* Get registered/non registered info from DIMM */ 969 tst r8, #SDRAM_DTYPE_DDR2 970 bne regDdr2 971 972regDdr1: 973 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 974 mov r7, #SDRAM_MODULES_ATTR_OFFSET 975 bl _i2cRead /* result in r7 */ 976 tst r7, #0x2 977 b exit 978regDdr2: 979 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ 980 mov r7, #DIMM_TYPE_INFO_OFFSET 981 bl _i2cRead /* result in r7 */ 982 tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ 983 /* or Mini-RDIMM (0x10) */ 984exit: 985 mov PC, r13 986 987 988#endif 989