1/******************************************************************************* 2Copyright (C) Marvell International Ltd. and its affiliates 3 4******************************************************************************** 5Marvell GPL License Option 6 7If you received this File from Marvell, you may opt to use, redistribute and/or 8modify this File in accordance with the terms and conditions of the General 9Public License Version 2, June 1991 (the "GPL License"), a copy of which is 10available along with the File in the license.txt file or by writing to the Free 11Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or 12on the worldwide web at http://www.gnu.org/licenses/gpl.txt. 13 14THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED 15WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY 16DISCLAIMED. The GPL License provides additional details about this warranty 17disclaimer. 18 19*******************************************************************************/ 20/******************************************************************************* 21* mvSysHwCfg.h - Marvell system HW configuration file 22* 23* DESCRIPTION: 24* None. 25* 26* DEPENDENCIES: 27* None. 28* 29*******************************************************************************/ 30 31#ifndef __INCmvSysHwConfigh 32#define __INCmvSysHwConfigh 33 34#include "../../../../include/linux/autoconf.h" 35 36#define CONFIG_MARVELL 1 37 38/* includes */ 39#define _1K 0x00000400 40#define _4K 0x00001000 41#define _8K 0x00002000 42#define _16K 0x00004000 43#define _32K 0x00008000 44#define _64K 0x00010000 45#define _128K 0x00020000 46#define _256K 0x00040000 47#define _512K 0x00080000 48 49#define _1M 0x00100000 50#define _2M 0x00200000 51#define _4M 0x00400000 52#define _8M 0x00800000 53#define _16M 0x01000000 54#define _32M 0x02000000 55#define _64M 0x04000000 56#define _128M 0x08000000 57#define _256M 0x10000000 58#define _512M 0x20000000 59 60#define _1G 0x40000000 61#define _2G 0x80000000 62 63/****************************************/ 64/* Soc supporeted Units definitions */ 65/****************************************/ 66 67#ifdef CONFIG_MV_INCLUDE_PEX 68#define MV_INCLUDE_PEX 69#endif 70#ifdef CONFIG_MV_INCLUDE_TWSI 71#define MV_INCLUDE_TWSI 72#endif 73#ifdef CONFIG_MV_INCLUDE_CESA 74#define MV_INCLUDE_CESA 75#endif 76#ifdef CONFIG_MV_INCLUDE_GIG_ETH 77#define MV_INCLUDE_GIG_ETH 78#endif 79#ifdef CONFIG_MV_INCLUDE_INTEG_SATA 80#define MV_INCLUDE_INTEG_SATA 81#define MV_INCLUDE_SATA 82#endif 83#ifdef CONFIG_MV_INCLUDE_USB 84#define MV_INCLUDE_USB 85#define MV_USB_VOLTAGE_FIX 86#endif 87#ifdef CONFIG_MV_INCLUDE_NAND 88#define MV_INCLUDE_NAND 89#endif 90#ifdef CONFIG_MV_INCLUDE_TDM 91#define MV_INCLUDE_TDM 92#endif 93#ifdef CONFIG_MV_INCLUDE_XOR 94#define MV_INCLUDE_XOR 95#endif 96#ifdef CONFIG_MV_INCLUDE_TWSI 97#define MV_INCLUDE_TWSI 98#endif 99#ifdef CONFIG_MV_INCLUDE_UART 100#define MV_INCLUDE_UART 101#endif 102#ifdef CONFIG_MV_INCLUDE_SPI 103#define MV_INCLUDE_SPI 104#endif 105#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD 106#define MV_INCLUDE_SFLASH_MTD 107#endif 108#ifdef CONFIG_MV_INCLUDE_AUDIO 109#define MV_INCLUDE_AUDIO 110#endif 111#ifdef CONFIG_MV_INCLUDE_TS 112#define MV_INCLUDE_TS 113#endif 114#ifdef CONFIG_MV_INCLUDE_SDIO 115#define MV_INCLUDE_SDIO 116#endif 117 118 119/* NAND flash stuff */ 120#ifdef CONFIG_MV_NAND_BOOT 121#define MV_NAND_BOOT 122#endif 123#ifdef CONFIG_MV_NAND 124#define MV_NAND 125#endif 126 127/* SPI flash stuff */ 128#ifdef CONFIG_MV_SPI_BOOT 129#define MV_SPI_BOOT 130#endif 131 132 133/****************************************************************/ 134/************* General configuration ********************/ 135/****************************************************************/ 136 137/* Enable Clock Power Control */ 138#define MV_INCLUDE_CLK_PWR_CNTRL 139 140/* Disable the DEVICE BAR in the PEX */ 141#define MV_DISABLE_PEX_DEVICE_BAR 142 143/* Allow the usage of early printings during initialization */ 144#define MV_INCLUDE_EARLY_PRINTK 145 146/****************************************************************/ 147/************* NFP configuration ********************************/ 148/****************************************************************/ 149#define MV_NFP_SEC_Q_SIZE 64 150#define MV_NFP_SEC_REQ_Q_SIZE 1000 151 152 153 154/****************************************************************/ 155/************* CESA configuration ********************/ 156/****************************************************************/ 157 158#ifdef MV_INCLUDE_CESA 159 160#define MV_CESA_MAX_CHAN 4 161 162/* Use 2K of SRAM */ 163#define MV_CESA_MAX_BUF_SIZE 1600 164 165#endif /* MV_INCLUDE_CESA */ 166 167#if defined(CONFIG_MV_INCLUDE_GIG_ETH) 168 169#ifdef CONFIG_MV_NFP_STATS 170#define MV_FP_STATISTICS 171#else 172#undef MV_FP_STATISTICS 173#endif 174/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ 175#define MV_ETH_SKB_REUSE_DEFAULT 1 176/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ 177#define MV_ETH_TX_EN_DEFAULT 0 178 179/* un-comment if you want to perform tx_done from within the poll function */ 180/* #define ETH_TX_DONE_ISR */ 181 182/* put descriptors in uncached memory */ 183/* #define ETH_DESCR_UNCACHED */ 184 185/* Descriptors location: DRAM/internal-SRAM */ 186#define ETH_DESCR_IN_SDRAM 187#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ 188 189#if defined(ETH_DESCR_IN_SRAM) 190#if defined(ETH_DESCR_UNCACHED) 191 #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" 192#else 193 #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" 194#endif 195#elif defined(ETH_DESCR_IN_SDRAM) 196#if defined(ETH_DESCR_UNCACHED) 197 #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" 198#else 199 #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" 200#endif 201#else 202 #error "Ethernet descriptors location undefined" 203#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ 204 205/* SW Sync-Barrier: not relevant for 88fxx81*/ 206/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ 207/* In RX the CPU theoretically might see himself as the descriptor owner, */ 208/* although the buffer hadn't been written to DRAM yet. Performance cost. */ 209/* #define INCLUDE_SYNC_BARR */ 210 211/* Buffers cache coherency method (buffers in DRAM) */ 212#ifndef MV_CACHE_COHER_SW 213/* Taken from mvCommon.h */ 214/* Memory uncached, HW or SW cache coherency is not needed */ 215#define MV_UNCACHED 0 216/* Memory cached, HW cache coherency supported in WriteThrough mode */ 217#define MV_CACHE_COHER_HW_WT 1 218/* Memory cached, HW cache coherency supported in WriteBack mode */ 219#define MV_CACHE_COHER_HW_WB 2 220/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ 221#define MV_CACHE_COHER_SW 3 222 223#endif 224 225/* DRAM cache coherency configuration */ 226#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW 227 228 229#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ 230 231#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) 232 #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" 233#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) 234 #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" 235#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) 236 #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" 237#elif (ETHER_DRAM_COHER == MV_UNCACHED) 238# define ETH_SDRAM_CONFIG_STR "DRAM uncached" 239#else 240 #error "Ethernet-DRAM undefined" 241#endif /* ETHER_DRAM_COHER */ 242 243 244/****************************************************************/ 245/************* Ethernet driver configuration ********************/ 246/****************************************************************/ 247 248/* port's default queueus */ 249#define ETH_DEF_TXQ 0 250#define ETH_DEF_RXQ 0 251 252#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM 253#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM 254 255/* interrupt coalescing setting */ 256#define ETH_TX_COAL 200 257#define ETH_RX_COAL 200 258 259/* Checksum offloading */ 260#define TX_CSUM_OFFLOAD 261#define RX_CSUM_OFFLOAD 262 263#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ 264 265/****************************************************************/ 266/*************** Telephony configuration ************************/ 267/****************************************************************/ 268#if defined(CONFIG_MV_TDM_LINEAR_MODE) 269 #define MV_TDM_LINEAR_MODE 270#elif defined(CONFIG_MV_TDM_ULAW_MODE) 271 #define MV_TDM_ULAW_MODE 272#endif 273 274#if defined(CONFIG_MV_TDM_5CHANNELS) 275 #define MV_TDM_5CHANNELS 276#endif 277 278#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) 279 #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE 280#endif 281 282/* We use the following registers to store DRAM interface pre configuration */ 283/* auto-detection results */ 284/* IMPORTANT: We are using mask register for that purpose. Before writing */ 285/* to units mask register, make sure main maks register is set to disable */ 286/* all interrupts. */ 287#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ 288#define DRAM_BUF_REG1 0x30820 /* sdram config */ 289#define DRAM_BUF_REG2 0x30830 /* sdram mode */ 290#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ 291#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ 292#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ 293#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ 294#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ 295#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ 296#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ 297#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ 298#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ 299#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ 300#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ 301#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ 302 303/* Following the pre-configuration registers default values restored after */ 304/* auto-detection is done */ 305#define DRAM_BUF_REG_DV 0 306 307/* System Mapping */ 308#define SDRAM_CS0_BASE 0x00000000 309#define SDRAM_CS0_SIZE _256M 310 311#define SDRAM_CS1_BASE 0x10000000 312#define SDRAM_CS1_SIZE _256M 313 314#define SDRAM_CS2_BASE 0x20000000 315#define SDRAM_CS2_SIZE _256M 316 317#define SDRAM_CS3_BASE 0x30000000 318#define SDRAM_CS3_SIZE _256M 319 320/* PEX */ 321#define PEX0_MEM_BASE 0xe8000000 322#define PEX0_MEM_SIZE _128M 323 324#define PEX0_IO_BASE 0xf2000000 325#define PEX0_IO_SIZE _1M 326 327/* Device Chip Selects */ 328#define NFLASH_CS_BASE 0xfa000000 329#define NFLASH_CS_SIZE _2M 330 331#define SPI_CS_BASE 0xf4000000 332#define SPI_CS_SIZE _16M 333 334#define CRYPT_ENG_BASE 0xf0000000 335#define CRYPT_ENG_SIZE _2M 336 337#define BOOTDEV_CS_BASE 0xff800000 338#define BOOTDEV_CS_SIZE _8M 339 340/* CS2 - BOOTROM */ 341#define DEVICE_CS2_BASE 0xff900000 342#define DEVICE_CS2_SIZE _1M 343 344/* PEX Work arround */ 345/* the target we will use for the workarround */ 346#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM 347/*a flag that indicates if we are going to use the 348size and base of the target we using for the workarround 349window */ 350#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 351/* if the above flag is 0 then the following values 352will be used for the workarround window base and size, 353otherwise the following defines will be ignored */ 354#define PEX_CONFIG_RW_WA_BASE 0xF3000000 355#define PEX_CONFIG_RW_WA_SIZE _16M 356 357/* Internal registers: size is defined in Controllerenvironment */ 358#define INTER_REGS_BASE 0xFEE00000 359 360/* DRAM detection stuff */ 361#define MV_DRAM_AUTO_SIZE 362 363/* Board clock detection */ 364#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ 365#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ 366#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ 367#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ 368 369/* PEX-PCI\PCI-PCI Bridge*/ 370#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ 371 372 373 374#endif /* __INCmvSysHwConfigh */ 375 376