1/******************************************************************************* 2Copyright (C) Marvell International Ltd. and its affiliates 3 4This software file (the "File") is owned and distributed by Marvell 5International Ltd. and/or its affiliates ("Marvell") under the following 6alternative licensing terms. Once you have made an election to distribute the 7File under one of the following license alternatives, please (i) delete this 8introductory statement regarding license alternatives, (ii) delete the two 9license alternatives that you have not elected to use and (iii) preserve the 10Marvell copyright notice above. 11 12 13******************************************************************************** 14Marvell GPL License Option 15 16If you received this File from Marvell, you may opt to use, redistribute and/or 17modify this File in accordance with the terms and conditions of the General 18Public License Version 2, June 1991 (the "GPL License"), a copy of which is 19available along with the File in the license.txt file or by writing to the Free 20Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or 21on the worldwide web at http://www.gnu.org/licenses/gpl.txt. 22 23THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED 24WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY 25DISCLAIMED. The GPL License provides additional details about this warranty 26disclaimer. 27*******************************************************************************/ 28/******************************************************************************* 29* mvOsCpuArchLib.c - Marvell CPU architecture library 30* 31* DESCRIPTION: 32* This library introduce Marvell API for OS dependent CPU architecture 33* APIs. This library introduce single CPU architecture services APKI 34* cross OS. 35* 36* DEPENDENCIES: 37* None. 38* 39*******************************************************************************/ 40 41/* includes */ 42#include <asm/processor.h> 43#include "mvOs.h" 44 45static MV_U32 read_p15_c0 (void); 46 47/* defines */ 48#define ARM_ID_REVISION_OFFS 0 49#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) 50 51#define ARM_ID_PART_NUM_OFFS 4 52#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) 53 54#define ARM_ID_ARCH_OFFS 16 55#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) 56 57#define ARM_ID_VAR_OFFS 20 58#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) 59 60#define ARM_ID_ASCII_OFFS 24 61#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) 62 63 64 65void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, 66 MV_U32 *memHandle) 67{ 68 void *p = kmalloc( size, GFP_KERNEL ); 69 *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); 70 return p; 71} 72void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, 73 MV_U32 *memHandle) 74{ 75 return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); 76} 77 78void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, 79 MV_U32 memHandle) 80{ 81 return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); 82} 83 84void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, 85 MV_U32 memHandle ) 86{ 87 return kfree( pVirtAddr ); 88} 89 90int mvOsRand(void) 91{ 92 int rand; 93 get_random_bytes(&rand, sizeof(rand) ); 94 return rand; 95} 96 97/******************************************************************************* 98* mvOsCpuVerGet() - 99* 100* DESCRIPTION: 101* 102* INPUT: 103* None. 104* 105* OUTPUT: 106* None. 107* 108* RETURN: 109* 32bit CPU Revision 110* 111*******************************************************************************/ 112MV_U32 mvOsCpuRevGet( MV_VOID ) 113{ 114 return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); 115} 116/******************************************************************************* 117* mvOsCpuPartGet() - 118* 119* DESCRIPTION: 120* 121* INPUT: 122* None. 123* 124* OUTPUT: 125* None. 126* 127* RETURN: 128* 32bit CPU Part number 129* 130*******************************************************************************/ 131MV_U32 mvOsCpuPartGet( MV_VOID ) 132{ 133 return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); 134} 135/******************************************************************************* 136* mvOsCpuArchGet() - 137* 138* DESCRIPTION: 139* 140* INPUT: 141* None. 142* 143* OUTPUT: 144* None. 145* 146* RETURN: 147* 32bit CPU Architicture number 148* 149*******************************************************************************/ 150MV_U32 mvOsCpuArchGet( MV_VOID ) 151{ 152 return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); 153} 154/******************************************************************************* 155* mvOsCpuVarGet() - 156* 157* DESCRIPTION: 158* 159* INPUT: 160* None. 161* 162* OUTPUT: 163* None. 164* 165* RETURN: 166* 32bit CPU Variant number 167* 168*******************************************************************************/ 169MV_U32 mvOsCpuVarGet( MV_VOID ) 170{ 171 return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); 172} 173/******************************************************************************* 174* mvOsCpuAsciiGet() - 175* 176* DESCRIPTION: 177* 178* INPUT: 179* None. 180* 181* OUTPUT: 182* None. 183* 184* RETURN: 185* 32bit CPU Variant number 186* 187*******************************************************************************/ 188MV_U32 mvOsCpuAsciiGet( MV_VOID ) 189{ 190 return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); 191} 192 193 194 195/* 196static unsigned long read_p15_c0 (void) 197*/ 198/* read co-processor 15, register #0 (ID register) */ 199static MV_U32 read_p15_c0 (void) 200{ 201 MV_U32 value; 202 203 __asm__ __volatile__( 204 "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" 205 : "=r" (value) 206 : 207 : "memory"); 208 209 return value; 210} 211 212