1/* 2 * Atheros AR71xx built-in ethernet mac driver 3 * 4 * Copyright (c) 2013 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Based on Atheros' AG7100 driver 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 */ 14 15#ifndef __AG71XX_H 16#define __AG71XX_H 17 18#include <linux/kernel.h> 19#include <linux/version.h> 20#include <linux/module.h> 21#include <linux/init.h> 22#include <linux/types.h> 23#include <linux/random.h> 24#include <linux/spinlock.h> 25#include <linux/interrupt.h> 26#include <linux/platform_device.h> 27#include <linux/ethtool.h> 28#include <linux/etherdevice.h> 29#include <linux/if_vlan.h> 30#include <linux/phy.h> 31#include <linux/skbuff.h> 32#include <linux/dma-mapping.h> 33#include <linux/workqueue.h> 34#include <linux/prefetch.h> 35 36#include <linux/bitops.h> 37 38#include <asm/mach-ath79/ar71xx_regs.h> 39#include <asm/mach-ath79/ath79.h> 40#include <asm/mach-ath79/ag71xx_platform.h> 41 42#define AG71XX_DRV_NAME "ag71xx" 43#define AG71XX_DRV_VERSION "0.5.35" 44 45#define AG71XX_NAPI_WEIGHT 64 46#define AG71XX_OOM_REFILL (1 + HZ/10) 47 48#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) 49#define AG71XX_INT_TX (AG71XX_INT_TX_PS) 50#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) 51 52#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) 53#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) 54 55#define AG71XX_TX_MTU_LEN 1540 56#define AG71XX_RX_PKT_SIZE \ 57 (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 58#define AG71XX_RX_BUF_SIZE (AG71XX_RX_PKT_SIZE + NET_SKB_PAD + NET_IP_ALIGN) 59 60#define AG71XX_TX_RING_SIZE_DEFAULT 64 61#define AG71XX_RX_RING_SIZE_DEFAULT 128 62 63#define AG71XX_TX_RING_SIZE_MAX 256 64#define AG71XX_RX_RING_SIZE_MAX 256 65 66#define AG71XX_JUMBO_LEN 9000 67 68#ifdef CONFIG_AG71XX_DEBUG 69#define DBG(fmt, args...) pr_debug(fmt, ## args) 70#else 71#define DBG(fmt, args...) do {} while (0) 72#endif 73 74#define ag71xx_assert(_cond) \ 75do { \ 76 if (_cond) \ 77 break; \ 78 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ 79 BUG(); \ 80} while (0) 81 82struct ag71xx_desc { 83 volatile u32 data; 84 volatile u32 ctrl; 85#define DESC_EMPTY BIT(31) 86#define DESC_MORE BIT(24) 87#define DESC_PKTLEN_M 0xfff 88 volatile u32 next; 89 volatile u32 pad; 90} __attribute__((aligned(4))); 91 92struct ag71xx_buf { 93 struct sk_buff *skb; 94 struct ag71xx_desc *desc; 95 dma_addr_t dma_addr; 96 unsigned long timestamp; 97}; 98 99struct ag71xx_ring { 100 struct ag71xx_buf *buf; 101 u8 *descs_cpu; 102 dma_addr_t descs_dma; 103 unsigned int desc_size; 104 unsigned int curr; 105 unsigned int dirty; 106 unsigned int size; 107 unsigned int mask; 108 unsigned int used; 109}; 110 111struct ag71xx_mdio { 112 struct mii_bus *mii_bus; 113 int mii_irq[PHY_MAX_ADDR]; 114 void __iomem *mdio_base; 115 struct ag71xx_mdio_platform_data *pdata; 116}; 117 118struct ag71xx_int_stats { 119 unsigned long rx_pr; 120 unsigned long rx_be; 121 unsigned long rx_of; 122 unsigned long tx_ps; 123 unsigned long tx_be; 124 unsigned long tx_ur; 125 unsigned long total; 126}; 127 128struct ag71xx_napi_stats { 129 unsigned long napi_calls; 130 unsigned long rx_count; 131 unsigned long rx_packets; 132 unsigned long rx_packets_max; 133 unsigned long tx_count; 134 unsigned long tx_packets; 135 unsigned long tx_packets_max; 136 137 unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; 138 unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; 139}; 140 141struct ag71xx_debug { 142 struct dentry *debugfs_dir; 143 144 struct ag71xx_int_stats int_stats; 145 struct ag71xx_napi_stats napi_stats; 146}; 147 148struct ag71xx { 149 void __iomem *mac_base; 150 151 spinlock_t lock; 152 struct platform_device *pdev; 153 struct net_device *dev; 154 struct napi_struct napi; 155 u32 msg_enable; 156 157 struct ag71xx_desc *stop_desc; 158 dma_addr_t stop_desc_dma; 159 160 bool tx_stopped; 161 162 struct ag71xx_ring rx_ring; 163 struct ag71xx_ring tx_ring; 164 unsigned int rx_buf_offset; 165 unsigned int rx_buf_size; 166 167 struct mii_bus *mii_bus; 168 struct phy_device *phy_dev; 169 void *phy_priv; 170 171 unsigned int link; 172 unsigned int speed; 173 int duplex; 174 175 struct work_struct restart_work; 176 struct delayed_work link_work; 177 struct timer_list oom_timer; 178 179#ifdef CONFIG_AG71XX_DEBUG_FS 180 struct ag71xx_debug debug; 181#endif 182}; 183 184extern struct ethtool_ops ag71xx_ethtool_ops; 185void ag71xx_link_adjust(struct ag71xx *ag); 186 187int ag71xx_mdio_driver_init(void) __init; 188void ag71xx_mdio_driver_exit(void); 189 190int ag71xx_phy_connect(struct ag71xx *ag); 191void ag71xx_phy_disconnect(struct ag71xx *ag); 192void ag71xx_phy_start(struct ag71xx *ag); 193void ag71xx_phy_stop(struct ag71xx *ag); 194 195static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) 196{ 197 return ag->pdev->dev.platform_data; 198} 199 200/* Register offsets */ 201#define AG71XX_REG_MAC_CFG1 0x0000 202#define AG71XX_REG_MAC_CFG2 0x0004 203#define AG71XX_REG_MAC_IPG 0x0008 204#define AG71XX_REG_MAC_HDX 0x000c 205#define AG71XX_REG_MAC_MFL 0x0010 206#define AG71XX_REG_MII_CFG 0x0020 207#define AG71XX_REG_MII_CMD 0x0024 208#define AG71XX_REG_MII_ADDR 0x0028 209#define AG71XX_REG_MII_CTRL 0x002c 210#define AG71XX_REG_MII_STATUS 0x0030 211#define AG71XX_REG_MII_IND 0x0034 212#define AG71XX_REG_MAC_IFCTL 0x0038 213#define AG71XX_REG_MAC_ADDR1 0x0040 214#define AG71XX_REG_MAC_ADDR2 0x0044 215#define AG71XX_REG_FIFO_CFG0 0x0048 216#define AG71XX_REG_FIFO_CFG1 0x004c 217#define AG71XX_REG_FIFO_CFG2 0x0050 218#define AG71XX_REG_FIFO_CFG3 0x0054 219#define AG71XX_REG_FIFO_CFG4 0x0058 220#define AG71XX_REG_FIFO_CFG5 0x005c 221#define AG71XX_REG_FIFO_RAM0 0x0060 222#define AG71XX_REG_FIFO_RAM1 0x0064 223#define AG71XX_REG_FIFO_RAM2 0x0068 224#define AG71XX_REG_FIFO_RAM3 0x006c 225#define AG71XX_REG_FIFO_RAM4 0x0070 226#define AG71XX_REG_FIFO_RAM5 0x0074 227#define AG71XX_REG_FIFO_RAM6 0x0078 228#define AG71XX_REG_FIFO_RAM7 0x007c 229 230#define AG71XX_REG_TX_CTRL 0x0180 231#define AG71XX_REG_TX_DESC 0x0184 232#define AG71XX_REG_TX_STATUS 0x0188 233#define AG71XX_REG_RX_CTRL 0x018c 234#define AG71XX_REG_RX_DESC 0x0190 235#define AG71XX_REG_RX_STATUS 0x0194 236#define AG71XX_REG_INT_ENABLE 0x0198 237#define AG71XX_REG_INT_STATUS 0x019c 238 239#define AG71XX_REG_FIFO_DEPTH 0x01a8 240#define AG71XX_REG_RX_SM 0x01b0 241#define AG71XX_REG_TX_SM 0x01b4 242 243#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ 244#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ 245#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ 246#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ 247#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ 248#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ 249#define MAC_CFG1_LB BIT(8) /* Loopback mode */ 250#define MAC_CFG1_SR BIT(31) /* Soft Reset */ 251 252#define MAC_CFG2_FDX BIT(0) 253#define MAC_CFG2_CRC_EN BIT(1) 254#define MAC_CFG2_PAD_CRC_EN BIT(2) 255#define MAC_CFG2_LEN_CHECK BIT(4) 256#define MAC_CFG2_HUGE_FRAME_EN BIT(5) 257#define MAC_CFG2_IF_1000 BIT(9) 258#define MAC_CFG2_IF_10_100 BIT(8) 259 260#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ 261#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ 262#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ 263#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ 264#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ 265#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ 266 | FIFO_CFG0_TXS | FIFO_CFG0_TXF) 267 268#define FIFO_CFG0_ENABLE_SHIFT 8 269 270#define FIFO_CFG4_DE BIT(0) /* Drop Event */ 271#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ 272#define FIFO_CFG4_FC BIT(2) /* False Carrier */ 273#define FIFO_CFG4_CE BIT(3) /* Code Error */ 274#define FIFO_CFG4_CR BIT(4) /* CRC error */ 275#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ 276#define FIFO_CFG4_LO BIT(6) /* Length out of range */ 277#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ 278#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ 279#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ 280#define FIFO_CFG4_DR BIT(10) /* Dribble */ 281#define FIFO_CFG4_LE BIT(11) /* Long Event */ 282#define FIFO_CFG4_CF BIT(12) /* Control Frame */ 283#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ 284#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ 285#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ 286#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ 287#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ 288 289#define FIFO_CFG5_DE BIT(0) /* Drop Event */ 290#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ 291#define FIFO_CFG5_FC BIT(2) /* False Carrier */ 292#define FIFO_CFG5_CE BIT(3) /* Code Error */ 293#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ 294#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ 295#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ 296#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ 297#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ 298#define FIFO_CFG5_DR BIT(9) /* Dribble */ 299#define FIFO_CFG5_CF BIT(10) /* Control Frame */ 300#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ 301#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ 302#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ 303#define FIFO_CFG5_LE BIT(14) /* Long Event */ 304#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ 305#define FIFO_CFG5_16 BIT(16) /* unknown */ 306#define FIFO_CFG5_17 BIT(17) /* unknown */ 307#define FIFO_CFG5_SF BIT(18) /* Short Frame */ 308#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ 309 310#define AG71XX_INT_TX_PS BIT(0) 311#define AG71XX_INT_TX_UR BIT(1) 312#define AG71XX_INT_TX_BE BIT(3) 313#define AG71XX_INT_RX_PR BIT(4) 314#define AG71XX_INT_RX_OF BIT(6) 315#define AG71XX_INT_RX_BE BIT(7) 316 317#define MAC_IFCTL_SPEED BIT(16) 318 319#define MII_CFG_CLK_DIV_4 0 320#define MII_CFG_CLK_DIV_6 2 321#define MII_CFG_CLK_DIV_8 3 322#define MII_CFG_CLK_DIV_10 4 323#define MII_CFG_CLK_DIV_14 5 324#define MII_CFG_CLK_DIV_20 6 325#define MII_CFG_CLK_DIV_28 7 326#define MII_CFG_CLK_DIV_34 8 327#define MII_CFG_CLK_DIV_42 9 328#define MII_CFG_CLK_DIV_50 10 329#define MII_CFG_CLK_DIV_58 11 330#define MII_CFG_CLK_DIV_66 12 331#define MII_CFG_CLK_DIV_74 13 332#define MII_CFG_CLK_DIV_82 14 333#define MII_CFG_CLK_DIV_98 15 334#define MII_CFG_RESET BIT(31) 335 336#define MII_CMD_WRITE 0x0 337#define MII_CMD_READ 0x1 338#define MII_ADDR_SHIFT 8 339#define MII_IND_BUSY BIT(0) 340#define MII_IND_INVALID BIT(2) 341 342#define TX_CTRL_TXE BIT(0) /* Tx Enable */ 343 344#define TX_STATUS_PS BIT(0) /* Packet Sent */ 345#define TX_STATUS_UR BIT(1) /* Tx Underrun */ 346#define TX_STATUS_BE BIT(3) /* Bus Error */ 347 348#define RX_CTRL_RXE BIT(0) /* Rx Enable */ 349 350#define RX_STATUS_PR BIT(0) /* Packet Received */ 351#define RX_STATUS_OF BIT(2) /* Rx Overflow */ 352#define RX_STATUS_BE BIT(3) /* Bus Error */ 353 354static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) 355{ 356 switch (reg) { 357 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: 358 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM: 359 case AG71XX_REG_MII_CFG: 360 break; 361 362 default: 363 BUG(); 364 } 365} 366 367static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) 368{ 369 void __iomem *r; 370 371 ag71xx_check_reg_offset(ag, reg); 372 373 r = ag->mac_base + reg; 374 __raw_writel(value, r); 375 /* flush write */ 376 (void) __raw_readl(r); 377} 378 379static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) 380{ 381 void __iomem *r; 382 383 ag71xx_check_reg_offset(ag, reg); 384 385 r = ag->mac_base + reg; 386 return __raw_readl(r); 387} 388 389static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) 390{ 391 void __iomem *r; 392 393 ag71xx_check_reg_offset(ag, reg); 394 395 r = ag->mac_base + reg; 396 __raw_writel(__raw_readl(r) | mask, r); 397 /* flush write */ 398 (void)__raw_readl(r); 399} 400 401static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) 402{ 403 void __iomem *r; 404 405 ag71xx_check_reg_offset(ag, reg); 406 407 r = ag->mac_base + reg; 408 __raw_writel(__raw_readl(r) & ~mask, r); 409 /* flush write */ 410 (void) __raw_readl(r); 411} 412 413static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) 414{ 415 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); 416} 417 418static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) 419{ 420 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); 421} 422 423#ifdef CONFIG_AG71XX_AR8216_SUPPORT 424void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); 425int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, 426 int pktlen); 427static inline int ag71xx_has_ar8216(struct ag71xx *ag) 428{ 429 return ag71xx_get_pdata(ag)->has_ar8216; 430} 431#else 432static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, 433 struct sk_buff *skb) 434{ 435} 436 437static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, 438 struct sk_buff *skb, 439 int pktlen) 440{ 441 return 0; 442} 443static inline int ag71xx_has_ar8216(struct ag71xx *ag) 444{ 445 return 0; 446} 447#endif 448 449#ifdef CONFIG_AG71XX_DEBUG_FS 450int ag71xx_debugfs_root_init(void); 451void ag71xx_debugfs_root_exit(void); 452int ag71xx_debugfs_init(struct ag71xx *ag); 453void ag71xx_debugfs_exit(struct ag71xx *ag); 454void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); 455void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); 456#else 457static inline int ag71xx_debugfs_root_init(void) { return 0; } 458static inline void ag71xx_debugfs_root_exit(void) {} 459static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } 460static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} 461static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, 462 u32 status) {} 463static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, 464 int rx, int tx) {} 465#endif /* CONFIG_AG71XX_DEBUG_FS */ 466 467void ag71xx_ar7240_start(struct ag71xx *ag); 468void ag71xx_ar7240_stop(struct ag71xx *ag); 469int ag71xx_ar7240_init(struct ag71xx *ag); 470void ag71xx_ar7240_cleanup(struct ag71xx *ag); 471 472int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg); 473void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val); 474 475u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, 476 unsigned reg_addr); 477int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, 478 unsigned reg_addr, u16 reg_val); 479 480#endif /* _AG71XX_H */ 481