1/*
2 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
3 * Permission to use, copy, modify, and/or distribute this software for
4 * any purpose with or without fee is hereby granted, provided that the
5 * above copyright notice and this permission notice appear in all copies.
6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13 */
14
15
16/**
17 * @defgroup isisc_mirror ISISC_MIRROR
18 * @{
19 */
20#include "sw.h"
21#include "hsl.h"
22#include "hsl_dev.h"
23#include "hsl_port_prop.h"
24#include "isisc_mirror.h"
25#include "isisc_reg.h"
26
27static sw_error_t
28_isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
29{
30	sw_error_t rv;
31	a_uint32_t val;
32
33	HSL_DEV_ID_CHECK(dev_id);
34	if (port_id != MIRROR_ANALYZER_NONE) {
35		if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
36			return SW_BAD_PARAM;
37		}
38	}
39	val = port_id;
40	HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
41                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
42	return rv;
43}
44
45static sw_error_t
46_isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
47{
48    sw_error_t rv;
49    a_uint32_t val;
50
51    HSL_DEV_ID_CHECK(dev_id);
52
53    HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
54                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
55    SW_RTN_ON_ERROR(rv);
56
57    *port_id = val;
58    return SW_OK;
59}
60
61static sw_error_t
62_isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
63{
64    sw_error_t rv;
65    a_uint32_t val;
66
67    HSL_DEV_ID_CHECK(dev_id);
68
69    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
70    {
71        return SW_BAD_PARAM;
72    }
73
74    if (A_TRUE == enable)
75    {
76        val = 1;
77    }
78    else if (A_FALSE == enable)
79    {
80        val = 0;
81    }
82    else
83    {
84        return SW_BAD_PARAM;
85    }
86
87    HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
88                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
89    return rv;
90}
91
92static sw_error_t
93_isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
94{
95    sw_error_t rv;
96    a_uint32_t val;
97
98    HSL_DEV_ID_CHECK(dev_id);
99
100    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
101    {
102        return SW_BAD_PARAM;
103    }
104
105    HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
106                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
107    SW_RTN_ON_ERROR(rv);
108
109    if (1 == val)
110    {
111        *enable = A_TRUE;
112    }
113    else
114    {
115        *enable = A_FALSE;
116    }
117
118    return SW_OK;
119}
120
121static sw_error_t
122_isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
123{
124    sw_error_t rv;
125    a_uint32_t val;
126
127    HSL_DEV_ID_CHECK(dev_id);
128
129    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
130    {
131        return SW_BAD_PARAM;
132    }
133
134    if (A_TRUE == enable)
135    {
136        val = 1;
137    }
138    else if (A_FALSE == enable)
139    {
140        val = 0;
141    }
142    else
143    {
144        return SW_BAD_PARAM;
145    }
146
147    HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
148                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
149    return rv;
150}
151
152static sw_error_t
153_isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
154{
155    sw_error_t rv;
156    a_uint32_t val;
157
158    HSL_DEV_ID_CHECK(dev_id);
159
160    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
161    {
162        return SW_BAD_PARAM;
163    }
164
165    HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
166                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
167    SW_RTN_ON_ERROR(rv);
168
169    if (1 == val)
170    {
171        *enable = A_TRUE;
172    }
173    else
174    {
175        *enable = A_FALSE;
176    }
177
178    return SW_OK;
179}
180
181/**
182 *   @details  Comments:
183 *   The analysis port works for both ingress and egress mirror.
184 * @brief Set mirror analyzer port on particular a device.
185 * @param[in] dev_id device id
186 * @param[in] port_id port id
187 * @return SW_OK or error code
188 */
189HSL_LOCAL sw_error_t
190isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
191{
192    sw_error_t rv;
193
194    HSL_API_LOCK;
195    rv = _isisc_mirr_analysis_port_set(dev_id, port_id);
196    HSL_API_UNLOCK;
197    return rv;
198}
199
200/**
201 * @brief Get mirror analysis port on particular a device.
202 * @param[in] dev_id device id
203 * @param[out] port_id port id
204 * @return SW_OK or error code
205 */
206HSL_LOCAL sw_error_t
207isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
208{
209    sw_error_t rv;
210
211    HSL_API_LOCK;
212    rv = _isisc_mirr_analysis_port_get(dev_id, port_id);
213    HSL_API_UNLOCK;
214    return rv;
215}
216
217/**
218 * @brief Set ingress mirror status on particular a port.
219 * @param[in] dev_id device id
220 * @param[in] port_id port id
221 * @param[in] enable A_TRUE or A_FALSE
222 * @return SW_OK or error code
223 */
224HSL_LOCAL sw_error_t
225isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
226{
227    sw_error_t rv;
228
229    HSL_API_LOCK;
230    rv = _isisc_mirr_port_in_set(dev_id, port_id, enable);
231    HSL_API_UNLOCK;
232    return rv;
233}
234
235/**
236 * @brief Get ingress mirror status on particular a port.
237 * @param[in] dev_id device id
238 * @param[in] port_id port id
239 * @param[out] enable A_TRUE or A_FALSE
240 * @return SW_OK or error code
241 */
242HSL_LOCAL sw_error_t
243isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
244{
245    sw_error_t rv;
246
247    HSL_API_LOCK;
248    rv = _isisc_mirr_port_in_get(dev_id, port_id, enable);
249    HSL_API_UNLOCK;
250    return rv;
251}
252
253/**
254 * @brief Set egress mirror status on a particular port.
255 * @param[in] dev_id device id
256 * @param[in] port_id port id
257 * @param[in] enable A_TRUE or A_FALSE
258 * @return SW_OK or error code
259 */
260HSL_LOCAL sw_error_t
261isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
262{
263    sw_error_t rv;
264
265    HSL_API_LOCK;
266    rv = _isisc_mirr_port_eg_set(dev_id, port_id, enable);
267    HSL_API_UNLOCK;
268    return rv;
269}
270
271/**
272 * @brief Get egress mirror status on a particular port.
273 * @param[in] dev_id device id
274 * @param[in] port_id port id
275 * @param[out] enable A_TRUE or A_FALSE
276 * @return SW_OK or error code
277 */
278HSL_LOCAL sw_error_t
279isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
280{
281    sw_error_t rv;
282
283    HSL_API_LOCK;
284    rv = _isisc_mirr_port_eg_get(dev_id, port_id, enable);
285    HSL_API_UNLOCK;
286    return rv;
287}
288
289sw_error_t
290isisc_mirr_init(a_uint32_t dev_id)
291{
292    HSL_DEV_ID_CHECK(dev_id);
293
294#ifndef HSL_STANDALONG
295    {
296        hsl_api_t *p_api;
297
298        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
299
300        p_api->mirr_analysis_port_set = isisc_mirr_analysis_port_set;
301        p_api->mirr_analysis_port_get = isisc_mirr_analysis_port_get;
302        p_api->mirr_port_in_set = isisc_mirr_port_in_set;
303        p_api->mirr_port_in_get = isisc_mirr_port_in_get;
304        p_api->mirr_port_eg_set = isisc_mirr_port_eg_set;
305        p_api->mirr_port_eg_get = isisc_mirr_port_eg_get;
306    }
307#endif
308
309    return SW_OK;
310}
311
312/**
313 * @}
314 */
315
316