1/*
2 * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
3 * Permission to use, copy, modify, and/or distribute this software for
4 * any purpose with or without fee is hereby granted, provided that the
5 * above copyright notice and this permission notice appear in all copies.
6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13 */
14
15
16/**
17 * @defgroup isis_port_ctrl ISIS_PORT_CONTROL
18 * @{
19 */
20#include "sw.h"
21#include "hsl.h"
22#include "hsl_dev.h"
23#include "hsl_port_prop.h"
24#include "isis_port_ctrl.h"
25#include "isis_reg.h"
26#include "hsl_phy.h"
27
28static a_bool_t
29_isis_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id)
30{
31    if ((0 == port_id) || (6 == port_id))
32    {
33        return A_FALSE;
34    }
35    else
36    {
37        return A_TRUE;
38    }
39}
40
41static sw_error_t
42_isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
43                      fal_port_duplex_t duplex)
44{
45    sw_error_t rv;
46    a_uint32_t phy_id, reg_save, reg_val, force, tmp;
47    hsl_phy_ops_t *phy_drv;
48
49    HSL_DEV_ID_CHECK(dev_id);
50
51    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
52    {
53        return SW_BAD_PARAM;
54    }
55
56    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
57    if (NULL == phy_drv->phy_duplex_set)
58        return SW_NOT_SUPPORTED;
59
60    if (FAL_DUPLEX_BUTT <= duplex)
61    {
62        return SW_BAD_PARAM;
63    }
64
65    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
66                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
67	SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val);
68
69    /* for those ports without PHY device we set MAC register */
70    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
71    {
72        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
73        if (FAL_HALF_DUPLEX == duplex)
74        {
75		if (tmp == 0)
76			return SW_OK;
77            SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
78        }
79        else
80        {
81		if (tmp == 1)
82			return SW_OK;
83            SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
84        }
85        reg_save = reg_val;
86    }
87    else
88    {
89        /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
90		rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
91		SW_RTN_ON_ERROR(rv);
92		rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp);
93		SW_RTN_ON_ERROR(rv);
94		if (tmp == duplex)
95			return SW_OK;
96        reg_save = reg_val;
97        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
98        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
99        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
100
101        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
102                          (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
103
104
105        rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
106        SW_RTN_ON_ERROR(rv);
107
108        /* If MAC not in sync with PHY mode, the behavior is undefine.
109           You must be careful... */
110        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
111        if (!force)
112        {
113            if (FAL_HALF_DUPLEX == duplex)
114            {
115                SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save);
116            }
117            else
118            {
119                SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save);
120            }
121        }
122    }
123
124    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
125                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
126    return rv;
127}
128
129static sw_error_t
130_isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
131                      fal_port_duplex_t * pduplex)
132{
133    sw_error_t rv;
134    a_uint32_t reg, field;
135    HSL_DEV_ID_CHECK(dev_id);
136
137    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
138    {
139        return SW_BAD_PARAM;
140    }
141    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
142                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
143    SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg);
144    if (field)
145    {
146        *pduplex = FAL_FULL_DUPLEX;
147    }
148    else
149    {
150        *pduplex = FAL_HALF_DUPLEX;
151    }
152
153    return SW_OK;
154}
155
156static sw_error_t
157_isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
158                     fal_port_speed_t speed)
159{
160    sw_error_t rv;
161    a_uint32_t phy_id, reg_save, reg_val, force, tmp;
162    hsl_phy_ops_t *phy_drv;
163
164    HSL_DEV_ID_CHECK(dev_id);
165
166    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
167    {
168        return SW_BAD_PARAM;
169    }
170
171    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
172    if (NULL == phy_drv->phy_speed_set)
173        return SW_NOT_SUPPORTED;
174
175    if (FAL_SPEED_1000 < speed)
176    {
177        return SW_BAD_PARAM;
178    }
179
180    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
181                      (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
182	SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val);
183
184    /* for those ports without PHY device we set MAC register */
185    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
186    {
187        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
188        if (FAL_SPEED_10 == speed)
189        {
190		if (tmp == 0)
191			return SW_OK;
192            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
193        }
194        else if (FAL_SPEED_100 == speed)
195        {
196		if (tmp == 1)
197			return SW_OK;
198            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
199        }
200        else
201        {
202		if (tmp == 2)
203			return SW_OK;
204            SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
205        }
206        reg_save = reg_val;
207
208    }
209    else
210    {
211        /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
212		rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
213		SW_RTN_ON_ERROR(rv);
214		rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp);
215		SW_RTN_ON_ERROR(rv);
216		if (tmp == speed)
217			return SW_OK;
218        reg_save = reg_val;
219        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg_val);
220        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
221        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
222
223        HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
224                          (a_uint8_t *) (&reg_val), sizeof (a_uint32_t));
225
226        rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
227        SW_RTN_ON_ERROR(rv);
228
229        /* If MAC not in sync with PHY mode, the behavior is undefine.
230           You must be careful... */
231        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
232        if (!force)
233        {
234            if (FAL_SPEED_10 == speed)
235            {
236                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save);
237            }
238            else if (FAL_SPEED_100 == speed)
239            {
240                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save);
241            }
242            else
243            {
244                SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save);
245            }
246        }
247    }
248
249    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
250                      (a_uint8_t *) (&reg_save), sizeof (a_uint32_t));
251    return rv;
252}
253
254static sw_error_t
255_isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
256                     fal_port_speed_t * pspeed)
257{
258    sw_error_t rv = SW_OK;
259    a_uint32_t reg, field;
260
261    HSL_DEV_ID_CHECK(dev_id);
262
263    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
264    {
265        return SW_BAD_PARAM;
266    }
267
268    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
269                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
270    SW_RTN_ON_ERROR(rv);
271
272    SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg);
273    if (0 == field)
274    {
275        *pspeed = FAL_SPEED_10;
276    }
277    else if (1 == field)
278    {
279        *pspeed = FAL_SPEED_100;
280    }
281    else if (2 == field)
282    {
283        *pspeed = FAL_SPEED_1000;
284    }
285    else
286    {
287        *pspeed = FAL_SPEED_BUTT;
288        rv = SW_READ_ERROR;
289    }
290
291    return rv;
292}
293
294static sw_error_t
295_isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
296                              a_bool_t * status)
297{
298    a_uint32_t phy_id;
299    sw_error_t rv;
300    hsl_phy_ops_t *phy_drv;
301
302    HSL_DEV_ID_CHECK(dev_id);
303
304    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
305    {
306        return SW_BAD_PARAM;
307    }
308
309    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
310    if (NULL == phy_drv->phy_autoneg_status_get)
311        return SW_NOT_SUPPORTED;
312
313    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
314    SW_RTN_ON_ERROR(rv);
315
316    *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);
317
318    return SW_OK;
319}
320
321static sw_error_t
322_isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
323{
324    sw_error_t rv;
325    a_uint32_t phy_id;
326    hsl_phy_ops_t *phy_drv;
327
328    HSL_DEV_ID_CHECK(dev_id);
329
330    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
331    {
332        return SW_BAD_PARAM;
333    }
334
335   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
336   if (NULL == phy_drv->phy_autoneg_enable_set)
337       return SW_NOT_SUPPORTED;
338
339    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
340    SW_RTN_ON_ERROR(rv);
341
342    rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id);
343    return rv;
344}
345
346static sw_error_t
347_isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
348{
349    sw_error_t rv;
350    a_uint32_t phy_id;
351    hsl_phy_ops_t *phy_drv;
352
353    HSL_DEV_ID_CHECK(dev_id);
354
355    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
356    {
357        return SW_BAD_PARAM;
358    }
359
360    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
361    if (NULL == phy_drv->phy_restart_autoneg)
362        return SW_NOT_SUPPORTED;
363
364    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
365    SW_RTN_ON_ERROR(rv);
366
367    rv = phy_drv->phy_restart_autoneg (dev_id, phy_id);
368    return rv;
369}
370
371static sw_error_t
372_isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
373                           a_uint32_t autoadv)
374{
375    sw_error_t rv;
376    a_uint32_t phy_id;
377    hsl_phy_ops_t *phy_drv;
378
379    HSL_DEV_ID_CHECK(dev_id);
380
381    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
382    {
383        return SW_BAD_PARAM;
384    }
385
386    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
387    if (NULL == phy_drv->phy_autoneg_adv_set)
388        return SW_NOT_SUPPORTED;
389
390    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
391    SW_RTN_ON_ERROR(rv);
392
393    rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv);
394    SW_RTN_ON_ERROR(rv);
395
396    return SW_OK;
397}
398
399static sw_error_t
400_isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
401                           a_uint32_t * autoadv)
402{
403    sw_error_t rv;
404    a_uint32_t phy_id;
405    hsl_phy_ops_t *phy_drv;
406
407    HSL_DEV_ID_CHECK(dev_id);
408
409    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
410    {
411        return SW_BAD_PARAM;
412    }
413
414    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
415    if (NULL == phy_drv->phy_autoneg_adv_get)
416        return SW_NOT_SUPPORTED;
417
418    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
419    SW_RTN_ON_ERROR(rv);
420
421    *autoadv = 0;
422    rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv);
423    SW_RTN_ON_ERROR(rv);
424
425    return SW_OK;
426}
427
428static sw_error_t
429_isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
430{
431    sw_error_t rv;
432    a_uint32_t val, force, reg, tmp;
433
434    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
435    {
436        return SW_BAD_PARAM;
437    }
438
439    if (A_TRUE == enable)
440    {
441        val = 1;
442    }
443    else if (A_FALSE == enable)
444    {
445        val = 0;
446    }
447    else
448    {
449        return SW_BAD_PARAM;
450    }
451
452    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
453                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
454    SW_RTN_ON_ERROR(rv);
455
456    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
457    if (force)
458    {
459        /* flow control isn't in force mode so can't set */
460        return SW_DISABLE;
461    }
462	tmp = reg;
463
464    SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
465    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
466    SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
467	if (tmp == reg)
468		return SW_OK;
469
470    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
471                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
472    return rv;
473}
474
475static sw_error_t
476_isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
477                        a_bool_t * enable)
478{
479    sw_error_t rv;
480    a_uint32_t rx, reg;
481
482    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
483    {
484        return SW_BAD_PARAM;
485    }
486
487    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
488                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
489    SW_RTN_ON_ERROR(rv);
490
491    SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
492
493    if (1 == rx)
494    {
495        *enable = A_TRUE;
496    }
497    else
498    {
499        *enable = A_FALSE;
500    }
501
502    return SW_OK;
503}
504
505static sw_error_t
506_isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
507                                  a_bool_t enable)
508{
509    sw_error_t rv;
510    a_uint32_t reg, tmp;
511
512    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
513    {
514        return SW_BAD_PARAM;
515    }
516
517    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
518                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
519    SW_RTN_ON_ERROR(rv);
520	SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg);
521
522    if (A_TRUE == enable)
523    {
524		if (tmp == 0)
525			return SW_OK;
526        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
527    }
528    else if (A_FALSE == enable)
529    {
530        /* for those ports without PHY, it can't sync flow control status */
531        if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
532        {
533            return SW_DISABLE;
534        }
535		if (tmp == 1)
536			return SW_OK;
537        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
538    }
539    else
540    {
541        return SW_BAD_PARAM;
542    }
543
544    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
545                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
546    return rv;
547}
548
549static sw_error_t
550_isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
551                                  a_bool_t * enable)
552{
553    sw_error_t rv;
554    a_uint32_t force, reg;
555
556    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
557    {
558        return SW_BAD_PARAM;
559    }
560
561    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
562                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
563    SW_RTN_ON_ERROR(rv);
564
565    SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
566    if (0 == force)
567    {
568        *enable = A_TRUE;
569    }
570    else
571    {
572        *enable = A_FALSE;
573    }
574
575    return SW_OK;
576}
577
578static sw_error_t
579_isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
580{
581    sw_error_t rv;
582    a_uint32_t phy_id = 0;
583    hsl_phy_ops_t *phy_drv;
584
585    HSL_DEV_ID_CHECK(dev_id);
586
587    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
588    {
589        return SW_BAD_PARAM;
590    }
591
592   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
593   if (NULL == phy_drv->phy_powersave_set)
594       return SW_NOT_SUPPORTED;
595
596    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
597    SW_RTN_ON_ERROR(rv);
598
599    rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable);
600
601    return rv;
602}
603
604static sw_error_t
605_isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
606                         a_bool_t * enable)
607{
608    sw_error_t rv;
609    a_uint32_t phy_id = 0;
610    hsl_phy_ops_t *phy_drv;
611
612    HSL_DEV_ID_CHECK(dev_id);
613
614    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
615    {
616        return SW_BAD_PARAM;
617    }
618
619   SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
620   if (NULL == phy_drv->phy_powersave_get)
621       return SW_NOT_SUPPORTED;
622
623    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
624    SW_RTN_ON_ERROR(rv);
625
626    rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable);
627
628    return rv;
629}
630
631static sw_error_t
632_isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
633{
634    sw_error_t rv;
635    a_uint32_t phy_id = 0;
636    hsl_phy_ops_t *phy_drv;
637
638    HSL_DEV_ID_CHECK(dev_id);
639
640    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
641    {
642        return SW_BAD_PARAM;
643    }
644
645    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
646    if (NULL == phy_drv->phy_hibernation_set)
647        return SW_NOT_SUPPORTED;
648
649    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
650    SW_RTN_ON_ERROR(rv);
651
652    rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable);
653
654    return rv;
655}
656
657static sw_error_t
658_isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
659                         a_bool_t * enable)
660{
661    sw_error_t rv;
662    a_uint32_t phy_id = 0;
663    hsl_phy_ops_t *phy_drv;
664
665    HSL_DEV_ID_CHECK(dev_id);
666
667    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
668    {
669        return SW_BAD_PARAM;
670    }
671
672    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
673    if (NULL == phy_drv->phy_hibernation_get)
674        return SW_NOT_SUPPORTED;
675
676    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
677    SW_RTN_ON_ERROR(rv);
678
679    rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable);
680
681    return rv;
682}
683
684static sw_error_t
685_isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
686               fal_cable_status_t * cable_status, a_uint32_t * cable_len)
687{
688    sw_error_t rv;
689    a_uint32_t phy_id = 0;
690    hsl_phy_ops_t *phy_drv;
691
692    HSL_DEV_ID_CHECK(dev_id);
693
694    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
695    {
696        return SW_BAD_PARAM;
697    }
698
699    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
700    if (NULL == phy_drv->phy_cdt)
701        return SW_NOT_SUPPORTED;
702
703    rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
704    SW_RTN_ON_ERROR(rv);
705
706    rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
707
708    return rv;
709}
710
711static sw_error_t
712_isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
713                          fal_port_header_mode_t mode)
714{
715    sw_error_t rv;
716    a_uint32_t val;
717
718    HSL_DEV_ID_CHECK(dev_id);
719
720    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
721    {
722        return SW_BAD_PARAM;
723    }
724
725    if (FAL_NO_HEADER_EN == mode)
726    {
727        val = 0;
728    }
729    else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
730    {
731        val = 1;
732    }
733    else if (FAL_ALL_TYPE_FRAME_EN == mode)
734    {
735        val = 2;
736    }
737    else
738    {
739        return SW_BAD_PARAM;
740    }
741
742    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
743                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
744    return rv;
745}
746
747static sw_error_t
748_isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
749                          fal_port_header_mode_t * mode)
750{
751    sw_error_t rv;
752    a_uint32_t val;
753
754    HSL_DEV_ID_CHECK(dev_id);
755
756    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
757    {
758        return SW_BAD_PARAM;
759    }
760
761    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
762                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
763    SW_RTN_ON_ERROR(rv);
764
765    if (1 == val)
766    {
767        *mode = FAL_ONLY_MANAGE_FRAME_EN;
768    }
769    else if (2 == val)
770    {
771        *mode = FAL_ALL_TYPE_FRAME_EN;
772    }
773    else
774    {
775        *mode = FAL_NO_HEADER_EN;
776    }
777
778    return SW_OK;
779}
780
781static sw_error_t
782_isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
783                          fal_port_header_mode_t mode)
784{
785    sw_error_t rv;
786    a_uint32_t val;
787
788    HSL_DEV_ID_CHECK(dev_id);
789
790    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
791    {
792        return SW_BAD_PARAM;
793    }
794
795    if (FAL_NO_HEADER_EN == mode)
796    {
797        val = 0;
798    }
799    else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
800    {
801        val = 1;
802    }
803    else if (FAL_ALL_TYPE_FRAME_EN == mode)
804    {
805        val = 2;
806    }
807    else
808    {
809        return SW_BAD_PARAM;
810    }
811
812    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
813                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
814    return rv;
815}
816
817static sw_error_t
818_isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
819                          fal_port_header_mode_t * mode)
820{
821    sw_error_t rv;
822    a_uint32_t val;
823
824    HSL_DEV_ID_CHECK(dev_id);
825
826    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
827    {
828        return SW_BAD_PARAM;
829    }
830
831    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
832                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
833    SW_RTN_ON_ERROR(rv);
834
835    if (1 == val)
836    {
837        *mode = FAL_ONLY_MANAGE_FRAME_EN;
838    }
839    else if (2 == val)
840    {
841        *mode = FAL_ALL_TYPE_FRAME_EN;
842    }
843    else
844    {
845        *mode = FAL_NO_HEADER_EN;
846    }
847
848    return SW_OK;
849}
850
851static sw_error_t
852_isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
853{
854    a_uint32_t reg;
855    sw_error_t rv;
856
857    HSL_DEV_ID_CHECK(dev_id);
858
859    HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
860                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
861    SW_RTN_ON_ERROR(rv);
862
863    if (A_TRUE == enable)
864    {
865        if (0xffff < type)
866        {
867            return SW_BAD_PARAM;
868        }
869        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg);
870        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg);
871    }
872    else if (A_FALSE == enable)
873    {
874        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg);
875        SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg);
876    }
877    else
878    {
879        return SW_BAD_PARAM;
880    }
881
882    HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0,
883                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
884    return rv;
885}
886
887static sw_error_t
888_isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
889{
890    a_uint32_t data, reg;
891    sw_error_t rv;
892
893    HSL_DEV_ID_CHECK(dev_id);
894
895    HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
896                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
897    SW_RTN_ON_ERROR(rv);
898
899    SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg);
900    if (data)
901    {
902        SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg);
903        *enable = A_TRUE;
904        *type = data;
905    }
906    else
907    {
908        *enable = A_FALSE;
909        *type = 0;
910    }
911
912    return SW_OK;
913}
914
915static sw_error_t
916_isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
917{
918    sw_error_t rv;
919    a_uint32_t reg, force, val, tmp;
920
921    HSL_DEV_ID_CHECK(dev_id);
922
923    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
924    {
925        return SW_BAD_PARAM;
926    }
927
928    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
929                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
930    SW_RTN_ON_ERROR(rv);
931
932    if (A_TRUE == enable)
933    {
934        val = 1;
935    }
936    else if (A_FALSE == enable)
937    {
938        val = 0;
939    }
940    else
941    {
942        return SW_BAD_PARAM;
943    }
944	tmp = reg;
945
946    /* for those ports without PHY device we set MAC register */
947    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
948    {
949        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg);
950        SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
951    }
952    else
953    {
954        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN,  force, reg);
955        if (force)
956        {
957            /* link isn't in force mode so can't set */
958            return SW_DISABLE;
959        }
960        else
961        {
962            SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
963        }
964    }
965	if (tmp == reg)
966		return SW_OK;
967    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
968                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
969    return rv;
970}
971
972static sw_error_t
973_isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
974{
975    sw_error_t rv;
976    a_uint32_t val;
977
978    HSL_DEV_ID_CHECK(dev_id);
979
980    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
981    {
982        return SW_BAD_PARAM;
983    }
984
985    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN,
986                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
987    SW_RTN_ON_ERROR(rv);
988
989    if (val)
990    {
991        *enable = A_TRUE;
992    }
993    else
994    {
995        *enable = A_FALSE;
996    }
997
998    return SW_OK;
999}
1000
1001static sw_error_t
1002_isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1003{
1004    sw_error_t rv;
1005    a_uint32_t reg, force, val, tmp;
1006
1007    HSL_DEV_ID_CHECK(dev_id);
1008
1009    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1010    {
1011        return SW_BAD_PARAM;
1012    }
1013
1014    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
1015                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1016    SW_RTN_ON_ERROR(rv);
1017
1018    if (A_TRUE == enable)
1019    {
1020        val = 1;
1021    }
1022    else if (A_FALSE == enable)
1023    {
1024        val = 0;
1025    }
1026    else
1027    {
1028        return SW_BAD_PARAM;
1029    }
1030	tmp = reg;
1031
1032    /* for those ports without PHY device we set MAC register */
1033    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
1034    {
1035        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN,  0, reg);
1036        SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
1037    }
1038    else
1039    {
1040        SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN,  force, reg);
1041        if (force)
1042        {
1043            /* link isn't in force mode so can't set */
1044            return SW_DISABLE;
1045        }
1046        else
1047        {
1048            SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
1049        }
1050    }
1051	if (tmp == reg)
1052		return SW_OK;
1053    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
1054                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1055    return rv;
1056}
1057
1058static sw_error_t
1059_isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
1060{
1061    sw_error_t rv;
1062    a_uint32_t val;
1063
1064    HSL_DEV_ID_CHECK(dev_id);
1065
1066    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1067    {
1068        return SW_BAD_PARAM;
1069    }
1070
1071    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN,
1072                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1073    SW_RTN_ON_ERROR(rv);
1074
1075    if (val)
1076    {
1077        *enable = A_TRUE;
1078    }
1079    else
1080    {
1081        *enable = A_FALSE;
1082    }
1083
1084    return SW_OK;
1085}
1086
1087static sw_error_t
1088_isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1089{
1090    sw_error_t rv;
1091    a_uint32_t val, reg, force, tmp;
1092
1093    HSL_DEV_ID_CHECK(dev_id);
1094
1095    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1096    {
1097        return SW_BAD_PARAM;
1098    }
1099
1100    if (A_TRUE == enable)
1101    {
1102        val = 1;
1103    }
1104    else if (A_FALSE == enable)
1105    {
1106        val = 0;
1107    }
1108    else
1109    {
1110        return SW_BAD_PARAM;
1111    }
1112
1113    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
1114                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1115    SW_RTN_ON_ERROR(rv);
1116	tmp = reg;
1117
1118    /* for those ports without PHY device we set MAC register */
1119    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
1120    {
1121        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
1122        SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN,   val, reg);
1123    }
1124    else
1125    {
1126        SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
1127        if (force)
1128        {
1129            /* flow control isn't in force mode so can't set */
1130            return SW_DISABLE;
1131        }
1132        else
1133        {
1134            SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
1135        }
1136    }
1137	if ( tmp == reg)
1138		return SW_OK;
1139    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
1140                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1141    return rv;
1142}
1143
1144static sw_error_t
1145_isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
1146{
1147    sw_error_t rv;
1148    a_uint32_t val;
1149
1150    HSL_DEV_ID_CHECK(dev_id);
1151
1152    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1153    {
1154        return SW_BAD_PARAM;
1155    }
1156
1157    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN,
1158                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1159    SW_RTN_ON_ERROR(rv);
1160
1161    if (val)
1162    {
1163        *enable = A_TRUE;
1164    }
1165    else
1166    {
1167        *enable = A_FALSE;
1168    }
1169
1170    return SW_OK;
1171}
1172
1173static sw_error_t
1174_isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1175{
1176    sw_error_t rv;
1177    a_uint32_t val, reg, force, tmp;
1178
1179    HSL_DEV_ID_CHECK(dev_id);
1180
1181    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1182    {
1183        return SW_BAD_PARAM;
1184    }
1185
1186    if (A_TRUE == enable)
1187    {
1188        val = 1;
1189    }
1190    else if (A_FALSE == enable)
1191    {
1192        val = 0;
1193    }
1194    else
1195    {
1196        return SW_BAD_PARAM;
1197    }
1198
1199    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
1200                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1201    SW_RTN_ON_ERROR(rv);
1202	tmp = reg;
1203
1204    /* for those ports without PHY device we set MAC register */
1205    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
1206    {
1207        SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
1208        SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN,   val, reg);
1209    }
1210    else
1211    {
1212        SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN,  force, reg);
1213        if (force)
1214        {
1215            /* flow control isn't in force mode so can't set */
1216            return SW_DISABLE;
1217        }
1218        else
1219        {
1220            SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
1221        }
1222    }
1223	if ( tmp == reg)
1224		return SW_OK;
1225    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
1226                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1227    return rv;
1228}
1229
1230static sw_error_t
1231_isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
1232{
1233    sw_error_t rv;
1234    a_uint32_t val;
1235
1236    HSL_DEV_ID_CHECK(dev_id);
1237
1238    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1239    {
1240        return SW_BAD_PARAM;
1241    }
1242
1243    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN,
1244                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1245    SW_RTN_ON_ERROR(rv);
1246
1247    if (val)
1248    {
1249        *enable = A_TRUE;
1250    }
1251    else
1252    {
1253        *enable = A_FALSE;
1254    }
1255
1256    return SW_OK;
1257}
1258
1259static sw_error_t
1260_isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1261{
1262    sw_error_t rv;
1263    a_uint32_t val, tmp;
1264
1265    HSL_DEV_ID_CHECK(dev_id);
1266
1267    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1268    {
1269        return SW_BAD_PARAM;
1270    }
1271
1272    if (A_TRUE == enable)
1273    {
1274        val = 1;
1275    }
1276    else if (A_FALSE == enable)
1277    {
1278        val = 0;
1279    }
1280    else
1281    {
1282        return SW_BAD_PARAM;
1283    }
1284	HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
1285                      (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
1286	if (tmp == val)
1287		return SW_OK;
1288    HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
1289                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1290    return rv;
1291}
1292
1293static sw_error_t
1294_isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
1295{
1296    sw_error_t rv;
1297    a_uint32_t val;
1298
1299    HSL_DEV_ID_CHECK(dev_id);
1300
1301    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1302    {
1303        return SW_BAD_PARAM;
1304    }
1305
1306    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
1307                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1308    SW_RTN_ON_ERROR(rv);
1309
1310    if (val)
1311    {
1312        *enable = A_TRUE;
1313    }
1314    else
1315    {
1316        *enable = A_FALSE;
1317    }
1318
1319    return SW_OK;
1320}
1321
1322static sw_error_t
1323_isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1324{
1325    sw_error_t rv;
1326    a_uint32_t reg, tmp;
1327
1328    HSL_DEV_ID_CHECK(dev_id);
1329
1330    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1331    {
1332        return SW_BAD_PARAM;
1333    }
1334
1335    HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
1336                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1337    SW_RTN_ON_ERROR(rv);
1338	SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg);
1339
1340    if (A_TRUE == enable)
1341    {
1342		if(tmp == 0)
1343			return SW_OK;
1344        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
1345    }
1346    else if (A_FALSE == enable)
1347    {
1348		if(tmp == 1)
1349			return SW_OK;
1350        /* for those ports without PHY, it can't sync link status */
1351        if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
1352        {
1353            return SW_DISABLE;
1354        }
1355        SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
1356    }
1357    else
1358    {
1359        return SW_BAD_PARAM;
1360    }
1361
1362    HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
1363                      (a_uint8_t *) (&reg), sizeof (a_uint32_t));
1364    return rv;
1365}
1366
1367static sw_error_t
1368_isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
1369{
1370    sw_error_t rv;
1371    a_uint32_t val;
1372
1373    HSL_DEV_ID_CHECK(dev_id);
1374
1375    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1376    {
1377        return SW_BAD_PARAM;
1378    }
1379
1380    HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN,
1381                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1382    SW_RTN_ON_ERROR(rv);
1383
1384    if (0 == val)
1385    {
1386        *enable = A_TRUE;
1387    }
1388    else
1389    {
1390        *enable = A_FALSE;
1391    }
1392
1393    return SW_OK;
1394}
1395
1396static sw_error_t
1397_isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
1398{
1399    sw_error_t rv;
1400    a_uint32_t phy_id;
1401    hsl_phy_ops_t *phy_drv;
1402
1403    HSL_DEV_ID_CHECK(dev_id);
1404
1405    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1406    {
1407        return SW_BAD_PARAM;
1408    }
1409
1410    SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
1411    if (NULL == phy_drv->phy_link_status_get)
1412         return SW_NOT_SUPPORTED;
1413
1414    /* for those ports without PHY device supposed always link up */
1415    if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
1416    {
1417        *status = A_TRUE;
1418    }
1419    else
1420    {
1421        rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
1422        SW_RTN_ON_ERROR(rv);
1423
1424        if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
1425        {
1426            *status = A_TRUE;
1427        }
1428        else
1429        {
1430            *status = A_FALSE;
1431        }
1432    }
1433
1434    return SW_OK;
1435}
1436
1437static sw_error_t
1438_isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1439{
1440    sw_error_t rv;
1441    a_uint32_t val;
1442
1443    HSL_DEV_ID_CHECK(dev_id);
1444
1445    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1446    {
1447        return SW_BAD_PARAM;
1448    }
1449
1450    if (A_TRUE == enable)
1451    {
1452        val = 1;
1453    }
1454    else if (A_FALSE == enable)
1455    {
1456        val = 0;
1457    }
1458    else
1459    {
1460        return SW_BAD_PARAM;
1461    }
1462
1463    HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
1464                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1465    return SW_OK;
1466}
1467
1468static sw_error_t
1469_isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
1470{
1471    sw_error_t rv;
1472    a_uint32_t val;
1473
1474    HSL_DEV_ID_CHECK(dev_id);
1475
1476    if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
1477    {
1478        return SW_BAD_PARAM;
1479    }
1480
1481    HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
1482                      (a_uint8_t *) (&val), sizeof (a_uint32_t));
1483    SW_RTN_ON_ERROR(rv);
1484
1485    if (0 == val)
1486    {
1487        *enable = A_FALSE;
1488    }
1489    else
1490    {
1491        *enable = A_TRUE;
1492    }
1493
1494    return SW_OK;
1495}
1496
1497/**
1498 * @brief Set duplex mode on a particular port.
1499 * @param[in] dev_id device id
1500 * @param[in] port_id port id
1501 * @param[in] duplex duplex mode
1502 * @return SW_OK or error code
1503 */
1504HSL_LOCAL sw_error_t
1505isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
1506                     fal_port_duplex_t duplex)
1507{
1508    sw_error_t rv;
1509
1510    HSL_API_LOCK;
1511    rv = _isis_port_duplex_set(dev_id, port_id, duplex);
1512    HSL_API_UNLOCK;
1513    return rv;
1514}
1515
1516/**
1517 * @brief Get duplex mode on a particular port.
1518 * @param[in] dev_id device id
1519 * @param[in] port_id port id
1520 * @param[out] duplex duplex mode
1521 * @return SW_OK or error code
1522 */
1523HSL_LOCAL sw_error_t
1524isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
1525                     fal_port_duplex_t * pduplex)
1526{
1527    sw_error_t rv;
1528
1529    HSL_API_LOCK;
1530    rv = _isis_port_duplex_get(dev_id, port_id, pduplex);
1531    HSL_API_UNLOCK;
1532    return rv;
1533}
1534
1535/**
1536 * @brief Set speed on a particular port.
1537 * @param[in] dev_id device id
1538 * @param[in] port_id port id
1539 * @param[in] speed port speed
1540 * @return SW_OK or error code
1541 */
1542HSL_LOCAL sw_error_t
1543isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
1544                    fal_port_speed_t speed)
1545{
1546    sw_error_t rv;
1547
1548    HSL_API_LOCK;
1549    rv = _isis_port_speed_set(dev_id, port_id, speed);
1550    HSL_API_UNLOCK;
1551    return rv;
1552}
1553
1554/**
1555 * @brief Get speed on a particular port.
1556 * @param[in] dev_id device id
1557 * @param[in] port_id port id
1558 * @param[out] speed port speed
1559 * @return SW_OK or error code
1560 */
1561HSL_LOCAL sw_error_t
1562isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
1563                    fal_port_speed_t * pspeed)
1564{
1565    sw_error_t rv;
1566
1567    HSL_API_LOCK;
1568    rv = _isis_port_speed_get(dev_id, port_id, pspeed);
1569    HSL_API_UNLOCK;
1570    return rv;
1571}
1572
1573/**
1574 * @brief Get auto negotiation status on a particular port.
1575 * @param[in] dev_id device id
1576 * @param[in] port_id port id
1577 * @param[out] status A_TRUE or A_FALSE
1578 * @return SW_OK or error code
1579 */
1580HSL_LOCAL sw_error_t
1581isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
1582                             a_bool_t * status)
1583{
1584    sw_error_t rv;
1585
1586    HSL_API_LOCK;
1587    rv = _isis_port_autoneg_status_get(dev_id, port_id, status);
1588    HSL_API_UNLOCK;
1589    return rv;
1590}
1591
1592/**
1593 * @brief Enable auto negotiation status on a particular port.
1594 * @param[in] dev_id device id
1595 * @param[in] port_id port id
1596 * @return SW_OK or error code
1597 */
1598HSL_LOCAL sw_error_t
1599isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
1600{
1601    sw_error_t rv;
1602
1603    HSL_API_LOCK;
1604    rv = _isis_port_autoneg_enable(dev_id, port_id);
1605    HSL_API_UNLOCK;
1606    return rv;
1607}
1608
1609/**
1610 * @brief Restart auto negotiation procedule on a particular port.
1611 * @param[in] dev_id device id
1612 * @param[in] port_id port id
1613 * @return SW_OK or error code
1614 */
1615HSL_LOCAL sw_error_t
1616isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
1617{
1618    sw_error_t rv;
1619
1620    HSL_API_LOCK;
1621    rv = _isis_port_autoneg_restart(dev_id, port_id);
1622    HSL_API_UNLOCK;
1623    return rv;
1624}
1625
1626/**
1627 * @brief Set auto negotiation advtisement ability on a particular port.
1628 *   @details  Comments:
1629 *   auto negotiation advtisement ability is defined by macro such as
1630 *   FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
1631 * @param[in] dev_id device id
1632 * @param[in] port_id port id
1633 * @param[in] autoadv auto negotiation advtisement ability bit map
1634 * @return SW_OK or error code
1635 */
1636HSL_LOCAL sw_error_t
1637isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
1638                          a_uint32_t autoadv)
1639{
1640    sw_error_t rv;
1641
1642    HSL_API_LOCK;
1643    rv = _isis_port_autoneg_adv_set(dev_id, port_id, autoadv);
1644    HSL_API_UNLOCK;
1645    return rv;
1646}
1647
1648/**
1649 * @brief Get auto negotiation advtisement ability on a particular port.
1650 * @param[in] dev_id device id
1651 * @param[in] port_id port id
1652 * @param[out] autoadv auto negotiation advtisement ability bit map
1653 * @return SW_OK or error code
1654 */
1655HSL_LOCAL sw_error_t
1656isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
1657                          a_uint32_t * autoadv)
1658{
1659    sw_error_t rv;
1660
1661    HSL_API_LOCK;
1662    rv = _isis_port_autoneg_adv_get(dev_id, port_id, autoadv);
1663    HSL_API_UNLOCK;
1664    return rv;
1665}
1666
1667/**
1668 * @brief Set flow control(rx/tx/bp) status on a particular port.
1669 * @param[in] dev_id device id
1670 * @param[in] port_id port id
1671 * @param[in] enable A_TRUE or A_FALSE
1672 * @return SW_OK or error code
1673 */
1674HSL_LOCAL sw_error_t
1675isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1676{
1677    sw_error_t rv;
1678
1679    HSL_API_LOCK;
1680    rv = _isis_port_flowctrl_set(dev_id, port_id, enable);
1681    HSL_API_UNLOCK;
1682    return rv;
1683}
1684
1685/**
1686 * @brief Get flow control status on a particular port.
1687 * @param[in] dev_id device id
1688 * @param[in] port_id port id
1689 * @param[out] enable A_TRUE or A_FALSE
1690 * @return SW_OK or error code
1691 */
1692HSL_LOCAL sw_error_t
1693isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
1694{
1695    sw_error_t rv;
1696
1697    HSL_API_LOCK;
1698    rv = _isis_port_flowctrl_get(dev_id, port_id, enable);
1699    HSL_API_UNLOCK;
1700    return rv;
1701}
1702
1703/**
1704 * @brief Set flow control force mode on a particular port.
1705 * @param[in] dev_id device id
1706 * @param[in] port_id port id
1707 * @param[out] enable A_TRUE or A_FALSE
1708 * @return SW_OK or error code
1709 */
1710HSL_LOCAL sw_error_t
1711isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
1712                                 a_bool_t enable)
1713{
1714    sw_error_t rv;
1715
1716    HSL_API_LOCK;
1717    rv = _isis_port_flowctrl_forcemode_set(dev_id, port_id, enable);
1718    HSL_API_UNLOCK;
1719    return rv;
1720}
1721
1722/**
1723 * @brief Get flow control force mode on a particular port.
1724 * @param[in] dev_id device id
1725 * @param[in] port_id port id
1726 * @param[out] enable A_TRUE or A_FALSE
1727 * @return SW_OK or error code
1728 */
1729HSL_LOCAL sw_error_t
1730isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
1731                                 a_bool_t * enable)
1732{
1733    sw_error_t rv;
1734
1735    HSL_API_LOCK;
1736    rv = _isis_port_flowctrl_forcemode_get(dev_id, port_id, enable);
1737    HSL_API_UNLOCK;
1738    return rv;
1739}
1740
1741/**
1742 * @brief Set powersaving status on a particular port.
1743 * @param[in] dev_id device id
1744 * @param[in] port_id port id
1745 * @param[out] enable A_TRUE or A_FALSE
1746 * @return SW_OK or error code
1747 */
1748HSL_LOCAL sw_error_t
1749isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1750{
1751    sw_error_t rv;
1752
1753    HSL_API_LOCK;
1754    rv = _isis_port_powersave_set(dev_id, port_id, enable);
1755    HSL_API_UNLOCK;
1756    return rv;
1757}
1758
1759/**
1760 * @brief Get powersaving status on a particular port.
1761 * @param[in] dev_id device id
1762 * @param[in] port_id port id
1763 * @param[out] enable A_TRUE or A_FALSE
1764 * @return SW_OK or error code
1765 */
1766HSL_LOCAL sw_error_t
1767isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
1768                        a_bool_t * enable)
1769{
1770    sw_error_t rv;
1771
1772    HSL_API_LOCK;
1773    rv = _isis_port_powersave_get(dev_id, port_id, enable);
1774    HSL_API_UNLOCK;
1775    return rv;
1776}
1777
1778/**
1779 * @brief Set hibernate status on a particular port.
1780 * @param[in] dev_id device id
1781 * @param[in] port_id port id
1782 * @param[out] enable A_TRUE or A_FALSE
1783 * @return SW_OK or error code
1784 */
1785HSL_LOCAL sw_error_t
1786isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1787{
1788    sw_error_t rv;
1789
1790    HSL_API_LOCK;
1791    rv = _isis_port_hibernate_set(dev_id, port_id, enable);
1792    HSL_API_UNLOCK;
1793    return rv;
1794}
1795
1796/**
1797 * @brief Get hibernate status on a particular port.
1798 * @param[in] dev_id device id
1799 * @param[in] port_id port id
1800 * @param[out] enable A_TRUE or A_FALSE
1801 * @return SW_OK or error code
1802 */
1803HSL_LOCAL sw_error_t
1804isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
1805                        a_bool_t * enable)
1806{
1807    sw_error_t rv;
1808
1809    HSL_API_LOCK;
1810    rv = _isis_port_hibernate_get(dev_id, port_id, enable);
1811    HSL_API_UNLOCK;
1812    return rv;
1813}
1814
1815/**
1816 * @brief Run cable diagnostic test on a particular port.
1817 * @param[in] dev_id device id
1818 * @param[in] port_id port id
1819 * @param[in] mdi_pair mdi pair id
1820 * @param[out] cable_status cable status
1821 * @param[out] cable_len cable len
1822 * @return SW_OK or error code
1823 */
1824HSL_LOCAL sw_error_t
1825isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
1826              fal_cable_status_t * cable_status, a_uint32_t * cable_len)
1827{
1828    sw_error_t rv;
1829
1830    HSL_API_LOCK;
1831    rv = _isis_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
1832    HSL_API_UNLOCK;
1833    return rv;
1834}
1835
1836/**
1837 * @brief Set status of Atheros header packets parsed on a particular port.
1838 * @param[in] dev_id device id
1839 * @param[in] port_id port id
1840 * @param[in] enable A_TRUE or A_FALSE
1841 * @return SW_OK or error code
1842 */
1843HSL_LOCAL sw_error_t
1844isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
1845                         fal_port_header_mode_t mode)
1846{
1847    sw_error_t rv;
1848
1849    HSL_API_LOCK;
1850    rv = _isis_port_rxhdr_mode_set(dev_id, port_id, mode);
1851    HSL_API_UNLOCK;
1852    return rv;
1853}
1854
1855/**
1856 * @brief Get status of Atheros header packets parsed on a particular port.
1857 * @param[in] dev_id device id
1858 * @param[in] port_id port id
1859 * @param[out] enable A_TRUE or A_FALSE
1860 * @return SW_OK or error code
1861 */
1862HSL_LOCAL sw_error_t
1863isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
1864                         fal_port_header_mode_t * mode)
1865{
1866    sw_error_t rv;
1867
1868    HSL_API_LOCK;
1869    rv = _isis_port_rxhdr_mode_get(dev_id, port_id, mode);
1870    HSL_API_UNLOCK;
1871    return rv;
1872}
1873
1874/**
1875 * @brief Set status of Atheros header packets parsed on a particular port.
1876 * @param[in] dev_id device id
1877 * @param[in] port_id port id
1878 * @param[in] enable A_TRUE or A_FALSE
1879 * @return SW_OK or error code
1880 */
1881HSL_LOCAL sw_error_t
1882isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
1883                         fal_port_header_mode_t mode)
1884{
1885    sw_error_t rv;
1886
1887    HSL_API_LOCK;
1888    rv = _isis_port_txhdr_mode_set(dev_id, port_id, mode);
1889    HSL_API_UNLOCK;
1890    return rv;
1891}
1892
1893/**
1894 * @brief Get status of Atheros header packets parsed on a particular port.
1895 * @param[in] dev_id device id
1896 * @param[in] port_id port id
1897 * @param[out] enable A_TRUE or A_FALSE
1898 * @return SW_OK or error code
1899 */
1900HSL_LOCAL sw_error_t
1901isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
1902                         fal_port_header_mode_t * mode)
1903{
1904    sw_error_t rv;
1905
1906    HSL_API_LOCK;
1907    rv = _isis_port_txhdr_mode_get(dev_id, port_id, mode);
1908    HSL_API_UNLOCK;
1909    return rv;
1910}
1911
1912/**
1913 * @brief Set status of Atheros header type value on a particular device.
1914 * @param[in] dev_id device id
1915 * @param[in] enable A_TRUE or A_FALSE
1916 * @param[in] type header type value
1917 * @return SW_OK or error code
1918 */
1919HSL_LOCAL sw_error_t
1920isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
1921{
1922    sw_error_t rv;
1923    HSL_API_LOCK;
1924    rv = _isis_header_type_set(dev_id, enable, type);
1925    HSL_API_UNLOCK;
1926    return rv;
1927}
1928
1929/**
1930 * @brief Get status of Atheros header type value on a particular device.
1931 * @param[in] dev_id device id
1932 * @param[out] enable A_TRUE or A_FALSE
1933 * @param[out] type header type value
1934 * @return SW_OK or error code
1935 */
1936HSL_LOCAL sw_error_t
1937isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
1938{
1939    sw_error_t rv;
1940
1941    HSL_API_LOCK;
1942    rv = _isis_header_type_get(dev_id, enable, type);
1943    HSL_API_UNLOCK;
1944    return rv;
1945}
1946
1947/**
1948 * @brief Set status of txmac on a particular port.
1949 * @param[in] dev_id device id
1950 * @param[in] port_id port id
1951 * @param[in] enable A_TRUE or A_FALSE
1952 * @return SW_OK or error code
1953 */
1954HSL_LOCAL sw_error_t
1955isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1956{
1957    sw_error_t rv;
1958    HSL_API_LOCK;
1959    rv = _isis_port_txmac_status_set(dev_id, port_id, enable);
1960    HSL_API_UNLOCK;
1961    return rv;
1962}
1963
1964/**
1965 * @brief Get status of txmac on a particular port.
1966 * @param[in] dev_id device id
1967 * @param[in] port_id port id
1968 * @param[out] enable A_TRUE or A_FALSE
1969 * @return SW_OK or error code
1970 */
1971HSL_LOCAL sw_error_t
1972isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
1973{
1974    sw_error_t rv;
1975
1976    HSL_API_LOCK;
1977    rv = _isis_port_txmac_status_get(dev_id, port_id, enable);
1978    HSL_API_UNLOCK;
1979    return rv;
1980}
1981
1982/**
1983 * @brief Set status of rxmac on a particular port.
1984 * @param[in] dev_id device id
1985 * @param[in] port_id port id
1986 * @param[in] enable A_TRUE or A_FALSE
1987 * @return SW_OK or error code
1988 */
1989HSL_LOCAL sw_error_t
1990isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
1991{
1992    sw_error_t rv;
1993    HSL_API_LOCK;
1994    rv = _isis_port_rxmac_status_set(dev_id, port_id, enable);
1995    HSL_API_UNLOCK;
1996    return rv;
1997}
1998
1999/**
2000 * @brief Get status of rxmac on a particular port.
2001 * @param[in] dev_id device id
2002 * @param[in] port_id port id
2003 * @param[out] enable A_TRUE or A_FALSE
2004 * @return SW_OK or error code
2005 */
2006HSL_LOCAL sw_error_t
2007isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
2008{
2009    sw_error_t rv;
2010
2011    HSL_API_LOCK;
2012    rv = _isis_port_rxmac_status_get(dev_id, port_id, enable);
2013    HSL_API_UNLOCK;
2014    return rv;
2015}
2016
2017/**
2018 * @brief Set status of tx flow control on a particular port.
2019 * @param[in] dev_id device id
2020 * @param[in] port_id port id
2021 * @param[in] enable A_TRUE or A_FALSE
2022 * @return SW_OK or error code
2023 */
2024HSL_LOCAL sw_error_t
2025isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
2026{
2027    sw_error_t rv;
2028    HSL_API_LOCK;
2029    rv = _isis_port_txfc_status_set(dev_id, port_id, enable);
2030    HSL_API_UNLOCK;
2031    return rv;
2032}
2033
2034/**
2035 * @brief Get status of tx flow control on a particular port.
2036 * @param[in] dev_id device id
2037 * @param[in] port_id port id
2038 * @param[out] enable A_TRUE or A_FALSE
2039 * @return SW_OK or error code
2040 */
2041HSL_LOCAL sw_error_t
2042isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
2043{
2044    sw_error_t rv;
2045
2046    HSL_API_LOCK;
2047    rv = _isis_port_txfc_status_get(dev_id, port_id, enable);
2048    HSL_API_UNLOCK;
2049    return rv;
2050}
2051
2052/**
2053 * @brief Set status of rx flow control on a particular port.
2054 * @param[in] dev_id device id
2055 * @param[in] port_id port id
2056 * @param[in] enable A_TRUE or A_FALSE
2057 * @return SW_OK or error code
2058 */
2059HSL_LOCAL sw_error_t
2060isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
2061{
2062    sw_error_t rv;
2063    HSL_API_LOCK;
2064    rv = _isis_port_rxfc_status_set(dev_id, port_id, enable);
2065    HSL_API_UNLOCK;
2066    return rv;
2067}
2068
2069/**
2070 * @brief Set status of rx flow control on a particular port.
2071 * @param[in] dev_id device id
2072 * @param[in] port_id port id
2073 * @param[out] enable A_TRUE or A_FALSE
2074 * @return SW_OK or error code
2075 */
2076HSL_LOCAL sw_error_t
2077isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
2078{
2079    sw_error_t rv;
2080
2081    HSL_API_LOCK;
2082    rv = _isis_port_rxfc_status_get(dev_id, port_id, enable);
2083    HSL_API_UNLOCK;
2084    return rv;
2085}
2086
2087/**
2088 * @brief Set status of back pressure on a particular port.
2089 * @param[in] dev_id device id
2090 * @param[in] port_id port id
2091 * @param[in] enable A_TRUE or A_FALSE
2092 * @return SW_OK or error code
2093 */
2094HSL_LOCAL sw_error_t
2095isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
2096{
2097    sw_error_t rv;
2098    HSL_API_LOCK;
2099    rv = _isis_port_bp_status_set(dev_id, port_id, enable);
2100    HSL_API_UNLOCK;
2101    return rv;
2102}
2103
2104/**
2105 * @brief Set status of back pressure on a particular port.
2106 * @param[in] dev_id device id
2107 * @param[in] port_id port id
2108 * @param[out] enable A_TRUE or A_FALSE
2109 * @return SW_OK or error code
2110 */
2111HSL_LOCAL sw_error_t
2112isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
2113{
2114    sw_error_t rv;
2115
2116    HSL_API_LOCK;
2117    rv = _isis_port_bp_status_get(dev_id, port_id, enable);
2118    HSL_API_UNLOCK;
2119    return rv;
2120}
2121
2122/**
2123 * @brief Set link force mode on a particular port.
2124 * @param[in] dev_id device id
2125 * @param[in] port_id port id
2126 * @param[in] enable A_TRUE or A_FALSE
2127 * @return SW_OK or error code
2128 */
2129HSL_LOCAL sw_error_t
2130isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
2131{
2132    sw_error_t rv;
2133    HSL_API_LOCK;
2134    rv = _isis_port_link_forcemode_set(dev_id, port_id, enable);
2135    HSL_API_UNLOCK;
2136    return rv;
2137}
2138
2139/**
2140 * @brief Get link force mode on a particular port.
2141 * @param[in] dev_id device id
2142 * @param[in] port_id port id
2143 * @param[out] enable A_TRUE or A_FALSE
2144 * @return SW_OK or error code
2145 */
2146HSL_LOCAL sw_error_t
2147isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
2148{
2149    sw_error_t rv;
2150
2151    HSL_API_LOCK;
2152    rv = _isis_port_link_forcemode_get(dev_id, port_id, enable);
2153    HSL_API_UNLOCK;
2154    return rv;
2155}
2156
2157/**
2158 * @brief Get link status on particular port.
2159 * @param[in] dev_id device id
2160 * @param[in] port_id port id
2161 * @param[out] status link status up (A_TRUE) or down (A_FALSE)
2162 * @return SW_OK or error code
2163 */
2164HSL_LOCAL sw_error_t
2165isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
2166{
2167    sw_error_t rv;
2168
2169    HSL_API_LOCK;
2170    rv = _isis_port_link_status_get(dev_id, port_id, status);
2171    HSL_API_UNLOCK;
2172    return rv;
2173}
2174
2175/**
2176 * @brief Set mac loop back on a particular port.
2177 * @param[in] dev_id device id
2178 * @param[in] port_id port id
2179 * @param[in] enable A_TRUE or A_FALSE
2180 * @return SW_OK or error code
2181 */
2182HSL_LOCAL sw_error_t
2183isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
2184{
2185    sw_error_t rv;
2186    HSL_API_LOCK;
2187    rv = _isis_port_mac_loopback_set(dev_id, port_id, enable);
2188    HSL_API_UNLOCK;
2189    return rv;
2190}
2191
2192/**
2193 * @brief Get mac loop back on a particular port.
2194 * @param[in] dev_id device id
2195 * @param[in] port_id port id
2196 * @param[out] enable A_TRUE or A_FALSE
2197 * @return SW_OK or error code
2198 */
2199HSL_LOCAL sw_error_t
2200isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
2201{
2202    sw_error_t rv;
2203
2204    HSL_API_LOCK;
2205    rv = _isis_port_mac_loopback_get(dev_id, port_id, enable);
2206    HSL_API_UNLOCK;
2207    return rv;
2208}
2209
2210sw_error_t
2211isis_port_ctrl_init(a_uint32_t dev_id)
2212{
2213    HSL_DEV_ID_CHECK(dev_id);
2214
2215#ifndef HSL_STANDALONG
2216    {
2217        hsl_api_t *p_api;
2218
2219        SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
2220
2221        p_api->port_duplex_get = isis_port_duplex_get;
2222        p_api->port_duplex_set = isis_port_duplex_set;
2223        p_api->port_speed_get = isis_port_speed_get;
2224        p_api->port_speed_set = isis_port_speed_set;
2225        p_api->port_autoneg_status_get = isis_port_autoneg_status_get;
2226        p_api->port_autoneg_enable = isis_port_autoneg_enable;
2227        p_api->port_autoneg_restart = isis_port_autoneg_restart;
2228        p_api->port_autoneg_adv_get = isis_port_autoneg_adv_get;
2229        p_api->port_autoneg_adv_set = isis_port_autoneg_adv_set;
2230        p_api->port_flowctrl_set = isis_port_flowctrl_set;
2231        p_api->port_flowctrl_get = isis_port_flowctrl_get;
2232        p_api->port_flowctrl_forcemode_set = isis_port_flowctrl_forcemode_set;
2233        p_api->port_flowctrl_forcemode_get = isis_port_flowctrl_forcemode_get;
2234        p_api->port_powersave_set = isis_port_powersave_set;
2235        p_api->port_powersave_get = isis_port_powersave_get;
2236        p_api->port_hibernate_set = isis_port_hibernate_set;
2237        p_api->port_hibernate_get = isis_port_hibernate_get;
2238        p_api->port_cdt = isis_port_cdt;
2239        p_api->port_rxhdr_mode_set = isis_port_rxhdr_mode_set;
2240        p_api->port_rxhdr_mode_get = isis_port_rxhdr_mode_get;
2241        p_api->port_txhdr_mode_set = isis_port_txhdr_mode_set;
2242        p_api->port_txhdr_mode_get = isis_port_txhdr_mode_get;
2243        p_api->header_type_set = isis_header_type_set;
2244        p_api->header_type_get = isis_header_type_get;
2245        p_api->port_txmac_status_set = isis_port_txmac_status_set;
2246        p_api->port_txmac_status_get = isis_port_txmac_status_get;
2247        p_api->port_rxmac_status_set = isis_port_rxmac_status_set;
2248        p_api->port_rxmac_status_get = isis_port_rxmac_status_get;
2249        p_api->port_txfc_status_set = isis_port_txfc_status_set;
2250        p_api->port_txfc_status_get = isis_port_txfc_status_get;
2251        p_api->port_rxfc_status_set = isis_port_rxfc_status_set;
2252        p_api->port_rxfc_status_get = isis_port_rxfc_status_get;
2253        p_api->port_bp_status_set = isis_port_bp_status_set;
2254        p_api->port_bp_status_get = isis_port_bp_status_get;
2255        p_api->port_link_forcemode_set = isis_port_link_forcemode_set;
2256        p_api->port_link_forcemode_get = isis_port_link_forcemode_get;
2257        p_api->port_link_status_get = isis_port_link_status_get;
2258        p_api->port_mac_loopback_set = isis_port_mac_loopback_set;
2259        p_api->port_mac_loopback_get = isis_port_mac_loopback_get;
2260    }
2261#endif
2262
2263    return SW_OK;
2264}
2265
2266/**
2267 * @}
2268 */
2269
2270