1/* 2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 * Permission to use, copy, modify, and/or distribute this software for 4 * any purpose with or without fee is hereby granted, provided that the 5 * above copyright notice and this permission notice appear in all copies. 6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 13 */ 14 15 16/** 17 * @defgroup dess_port_ctrl DESS_PORT_CONTROL 18 * @{ 19 */ 20#include "sw.h" 21#include "hsl.h" 22#include "hsl_dev.h" 23#include "hsl_port_prop.h" 24#include "dess_port_ctrl.h" 25#include "dess_reg.h" 26#include "hsl_phy.h" 27 28#define DMA_MAX_VIRT_RING 8 29extern a_bool_t dess_mac_port_valid_check (fal_port_t port_id); 30 31/* 32PORT0 egress 6 queues 33PORT1~4 egress 4 queues 34PORT5 egress 6 queues 35*/ 36static a_uint32_t port_queue[6] = { 6, 4, 4, 4, 4, 6 }; 37 38 39static a_bool_t 40_dess_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id) 41{ 42 if (0 == port_id) 43 { 44 return A_FALSE; 45 } 46 else 47 { 48 49 return dess_mac_port_valid_check (port_id); 50 } 51} 52 53static sw_error_t 54_dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, 55 fal_port_duplex_t duplex) 56{ 57 sw_error_t rv; 58 a_uint32_t phy_id, reg_save, reg_val, force; 59 hsl_phy_ops_t *phy_drv; 60 61 HSL_DEV_ID_CHECK (dev_id); 62 63 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 64 { 65 return SW_BAD_PARAM; 66 } 67 68 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 69 if (NULL == phy_drv->phy_duplex_set) 70 return SW_NOT_SUPPORTED; 71 72 if (FAL_DUPLEX_BUTT <= duplex) 73 { 74 return SW_BAD_PARAM; 75 } 76 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 77 SW_RTN_ON_ERROR (rv); 78 79 rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); 80 SW_RTN_ON_ERROR (rv); 81#if 0 82 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 83 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 84 85 /* for those ports without PHY device we set MAC register */ 86 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 87 { 88 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); 89 if (FAL_HALF_DUPLEX == duplex) 90 { 91 SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 0, reg_val); 92 } 93 else 94 { 95 SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 1, reg_val); 96 } 97 reg_save = reg_val; 98 } 99 else 100 { 101 /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ 102 reg_save = reg_val; 103 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); 104 SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, 0, reg_val); 105 SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, 0, reg_val); 106 107 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 108 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 109 110 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 111 SW_RTN_ON_ERROR (rv); 112 113 rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); 114 SW_RTN_ON_ERROR (rv); 115 116 /* If MAC not in sync with PHY mode, the behavior is undefine. 117 You must be careful... */ 118 SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg_save); 119 if (!force) 120 { 121 if (FAL_HALF_DUPLEX == duplex) 122 { 123 SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 0, reg_save); 124 } 125 else 126 { 127 SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 1, reg_save); 128 } 129 } 130 } 131 132 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 133 (a_uint8_t *) (®_save), sizeof (a_uint32_t)); 134 #endif 135 return rv; 136} 137 138static sw_error_t 139_dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, 140 fal_port_duplex_t * pduplex) 141{ 142 sw_error_t rv = SW_OK; 143 a_uint32_t phy_id,reg, field; 144 hsl_phy_ops_t *phy_drv; 145 146 HSL_DEV_ID_CHECK (dev_id); 147 148 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 149 { 150 return SW_BAD_PARAM; 151 } 152 153 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 154 if (NULL == phy_drv->phy_duplex_get) 155 return SW_NOT_SUPPORTED; 156 157 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 158 SW_RTN_ON_ERROR (rv); 159 160 rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex); 161 SW_RTN_ON_ERROR (rv); 162 163#if 0 164 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 165 (a_uint8_t *) (®), sizeof (a_uint32_t)); 166 SW_GET_FIELD_BY_REG (PORT_STATUS, DUPLEX_MODE, field, reg); 167 if (field) 168 { 169 *pduplex = FAL_FULL_DUPLEX; 170 } 171 else 172 { 173 *pduplex = FAL_HALF_DUPLEX; 174 } 175 176#endif 177 178 return rv; 179} 180 181static sw_error_t 182_dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, 183 fal_port_speed_t speed) 184{ 185 sw_error_t rv; 186 a_uint32_t phy_id, reg_save, reg_val, force; 187 hsl_phy_ops_t *phy_drv; 188 189 HSL_DEV_ID_CHECK (dev_id); 190 191 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 192 { 193 return SW_BAD_PARAM; 194 } 195 196 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 197 if (NULL == phy_drv->phy_speed_set) 198 return SW_NOT_SUPPORTED; 199 200 if (FAL_SPEED_1000 < speed) 201 { 202 return SW_BAD_PARAM; 203 } 204 205 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 206 SW_RTN_ON_ERROR (rv); 207 208 rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); 209 SW_RTN_ON_ERROR (rv); 210#if 0 211 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 212 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 213 214 /* for those ports without PHY device we set MAC register */ 215 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 216 { 217 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); 218 if (FAL_SPEED_10 == speed) 219 { 220 SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 0, reg_val); 221 } 222 else if (FAL_SPEED_100 == speed) 223 { 224 SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 1, reg_val); 225 } 226 else 227 { 228 SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 2, reg_val); 229 } 230 reg_save = reg_val; 231 232 } 233 else 234 { 235 /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ 236 reg_save = reg_val; 237 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); 238 SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, 0, reg_val); 239 SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, 0, reg_val); 240 241 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 242 (a_uint8_t *) (®_val), sizeof (a_uint32_t)); 243 244 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 245 SW_RTN_ON_ERROR (rv); 246 247 rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); 248 SW_RTN_ON_ERROR (rv); 249 250 /* If MAC not in sync with PHY mode, the behavior is undefine. 251 You must be careful... */ 252 SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg_save); 253 if (!force) 254 { 255 if (FAL_SPEED_10 == speed) 256 { 257 SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 0, reg_save); 258 } 259 else if (FAL_SPEED_100 == speed) 260 { 261 SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 1, reg_save); 262 } 263 else 264 { 265 SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 2, reg_save); 266 } 267 } 268 } 269 270 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 271 (a_uint8_t *) (®_save), sizeof (a_uint32_t)); 272 #endif 273 return rv; 274} 275 276static sw_error_t 277_dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, 278 fal_port_speed_t * pspeed) 279{ 280 sw_error_t rv = SW_OK; 281 a_uint32_t phy_id,reg, field; 282 hsl_phy_ops_t *phy_drv; 283 284 HSL_DEV_ID_CHECK (dev_id); 285 286 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 287 { 288 return SW_BAD_PARAM; 289 } 290 291 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 292 if (NULL == phy_drv->phy_speed_get) 293 return SW_NOT_SUPPORTED; 294 295 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 296 SW_RTN_ON_ERROR (rv); 297 298 rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed); 299 SW_RTN_ON_ERROR (rv); 300 301#if 0 302 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 303 (a_uint8_t *) (®), sizeof (a_uint32_t)); 304 SW_RTN_ON_ERROR (rv); 305 306 SW_GET_FIELD_BY_REG (PORT_STATUS, SPEED_MODE, field, reg); 307 if (0 == field) 308 { 309 *pspeed = FAL_SPEED_10; 310 } 311 else if (1 == field) 312 { 313 *pspeed = FAL_SPEED_100; 314 } 315 else if (2 == field) 316 { 317 *pspeed = FAL_SPEED_1000; 318 } 319 else 320 { 321 *pspeed = FAL_SPEED_BUTT; 322 rv = SW_READ_ERROR; 323 } 324#endif 325 326 return rv; 327} 328 329static sw_error_t 330_dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, 331 a_bool_t * status) 332{ 333 a_uint32_t phy_id; 334 sw_error_t rv; 335 hsl_phy_ops_t *phy_drv; 336 337 HSL_DEV_ID_CHECK (dev_id); 338 339 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 340 { 341 return SW_BAD_PARAM; 342 } 343 344 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 345 if (NULL == phy_drv->phy_autoneg_status_get) 346 return SW_NOT_SUPPORTED; 347 348 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 349 SW_RTN_ON_ERROR (rv); 350 351 *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); 352 353 return SW_OK; 354} 355 356static sw_error_t 357_dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) 358{ 359 sw_error_t rv; 360 a_uint32_t phy_id; 361 hsl_phy_ops_t *phy_drv; 362 363 HSL_DEV_ID_CHECK (dev_id); 364 365 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 366 { 367 return SW_BAD_PARAM; 368 } 369 370 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 371 if (NULL == phy_drv->phy_autoneg_enable_set) 372 return SW_NOT_SUPPORTED; 373 374 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 375 SW_RTN_ON_ERROR (rv); 376 377 rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id); 378 return rv; 379} 380 381static sw_error_t 382_dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) 383{ 384 sw_error_t rv; 385 a_uint32_t phy_id; 386 hsl_phy_ops_t *phy_drv; 387 388 HSL_DEV_ID_CHECK (dev_id); 389 390 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 391 { 392 return SW_BAD_PARAM; 393 } 394 395 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 396 if (NULL == phy_drv->phy_restart_autoneg) 397 return SW_NOT_SUPPORTED; 398 399 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 400 SW_RTN_ON_ERROR (rv); 401 402 rv = phy_drv->phy_restart_autoneg (dev_id, phy_id); 403 return rv; 404} 405 406static sw_error_t 407_dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, 408 a_uint32_t autoadv) 409{ 410 sw_error_t rv; 411 a_uint32_t phy_id; 412 hsl_phy_ops_t *phy_drv; 413 414 HSL_DEV_ID_CHECK (dev_id); 415 416 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 417 { 418 return SW_BAD_PARAM; 419 } 420 421 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 422 if (NULL == phy_drv->phy_autoneg_adv_set) 423 return SW_NOT_SUPPORTED; 424 425 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 426 SW_RTN_ON_ERROR (rv); 427 428 rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv); 429 SW_RTN_ON_ERROR (rv); 430 431 return SW_OK; 432} 433 434static sw_error_t 435_dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, 436 a_uint32_t * autoadv) 437{ 438 sw_error_t rv; 439 a_uint32_t phy_id; 440 hsl_phy_ops_t *phy_drv; 441 442 HSL_DEV_ID_CHECK (dev_id); 443 444 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 445 { 446 return SW_BAD_PARAM; 447 } 448 449 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 450 if (NULL == phy_drv->phy_autoneg_adv_get) 451 return SW_NOT_SUPPORTED; 452 453 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 454 SW_RTN_ON_ERROR (rv); 455 456 *autoadv = 0; 457 rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv); 458 SW_RTN_ON_ERROR (rv); 459 460 return SW_OK; 461} 462 463static sw_error_t 464_dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, 465 a_bool_t enable) 466{ 467 sw_error_t rv; 468 a_uint32_t val, force, reg, tmp; 469 470 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 471 { 472 return SW_BAD_PARAM; 473 } 474 475 if (A_TRUE == enable) 476 { 477 val = 1; 478 } 479 else if (A_FALSE == enable) 480 { 481 val = 0; 482 } 483 else 484 { 485 return SW_BAD_PARAM; 486 } 487 488 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 489 (a_uint8_t *) (®), sizeof (a_uint32_t)); 490 SW_RTN_ON_ERROR (rv); 491 492 SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); 493 if (force) 494 { 495 /* flow control isn't in force mode so can't set */ 496 return SW_DISABLE; 497 } 498 tmp = reg; 499 500 SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg); 501 SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg); 502 SW_SET_REG_BY_FIELD (PORT_STATUS, TX_HALF_FLOW_EN, val, reg); 503 if (reg == tmp) 504 return SW_OK; 505 506 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 507 (a_uint8_t *) (®), sizeof (a_uint32_t)); 508 return rv; 509} 510 511static sw_error_t 512_dess_port_flowctrl_thresh_set (a_uint32_t dev_id, fal_port_t port_id, 513 a_uint8_t on, a_uint8_t off) 514{ 515 sw_error_t rv; 516 a_uint32_t reg; 517 518 reg = (on << 16) | off; 519 HSL_REG_ENTRY_SET (rv, dev_id, PORT_FLOC_CTRL_THRESH, port_id, 520 (a_uint8_t *) (®), sizeof (a_uint32_t)); 521 return rv; 522} 523 524static sw_error_t 525_dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id, 526 a_bool_t * enable) 527{ 528 sw_error_t rv; 529 a_uint32_t rx, reg; 530 531 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 532 { 533 return SW_BAD_PARAM; 534 } 535 536 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 537 (a_uint8_t *) (®), sizeof (a_uint32_t)); 538 SW_RTN_ON_ERROR (rv); 539 540 SW_GET_FIELD_BY_REG (PORT_STATUS, RX_FLOW_EN, rx, reg); 541 542 if (1 == rx) 543 { 544 *enable = A_TRUE; 545 } 546 else 547 { 548 *enable = A_FALSE; 549 } 550 551 return SW_OK; 552} 553 554static sw_error_t 555_dess_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, 556 a_bool_t enable) 557{ 558 sw_error_t rv; 559 a_uint32_t reg, tmp; 560 561 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 562 { 563 return SW_BAD_PARAM; 564 } 565 566 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 567 (a_uint8_t *) (®), sizeof (a_uint32_t)); 568 SW_RTN_ON_ERROR (rv); 569 SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg); 570 571 if (A_TRUE == enable) 572 { 573 if (tmp== 0) 574 return SW_OK; 575 SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg); 576 } 577 else if (A_FALSE == enable) 578 { 579 /* for those ports without PHY, it can't sync flow control status */ 580 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 581 { 582 return SW_DISABLE; 583 } 584 if (tmp == 1) 585 return SW_OK; 586 SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 1, reg); 587 } 588 else 589 { 590 return SW_BAD_PARAM; 591 } 592 593 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 594 (a_uint8_t *) (®), sizeof (a_uint32_t)); 595 return rv; 596} 597 598static sw_error_t 599_dess_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, 600 a_bool_t * enable) 601{ 602 sw_error_t rv; 603 a_uint32_t force, reg; 604 605 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 606 { 607 return SW_BAD_PARAM; 608 } 609 610 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 611 (a_uint8_t *) (®), sizeof (a_uint32_t)); 612 SW_RTN_ON_ERROR (rv); 613 614 SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); 615 if (0 == force) 616 { 617 *enable = A_TRUE; 618 } 619 else 620 { 621 *enable = A_FALSE; 622 } 623 624 return SW_OK; 625} 626 627static sw_error_t 628_dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, 629 a_bool_t enable) 630{ 631 sw_error_t rv; 632 a_uint32_t phy_id = 0; 633 hsl_phy_ops_t *phy_drv; 634 635 HSL_DEV_ID_CHECK (dev_id); 636 637 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 638 { 639 return SW_BAD_PARAM; 640 } 641 642 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 643 if (NULL == phy_drv->phy_powersave_set) 644 return SW_NOT_SUPPORTED; 645 646 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 647 SW_RTN_ON_ERROR (rv); 648 649 rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable); 650 651 return rv; 652} 653 654static sw_error_t 655_dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, 656 a_bool_t * enable) 657{ 658 sw_error_t rv; 659 a_uint32_t phy_id = 0; 660 hsl_phy_ops_t *phy_drv; 661 662 HSL_DEV_ID_CHECK (dev_id); 663 664 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 665 { 666 return SW_BAD_PARAM; 667 } 668 669 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 670 if (NULL == phy_drv->phy_powersave_get) 671 return SW_NOT_SUPPORTED; 672 673 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 674 SW_RTN_ON_ERROR (rv); 675 676 rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable); 677 678 return rv; 679} 680 681static sw_error_t 682_dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, 683 a_bool_t enable) 684{ 685 sw_error_t rv; 686 a_uint32_t phy_id = 0; 687 hsl_phy_ops_t *phy_drv; 688 689 HSL_DEV_ID_CHECK (dev_id); 690 691 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 692 { 693 return SW_BAD_PARAM; 694 } 695 696 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 697 if (NULL == phy_drv->phy_hibernation_set) 698 return SW_NOT_SUPPORTED; 699 700 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 701 SW_RTN_ON_ERROR (rv); 702 703 rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable); 704 705 return rv; 706} 707 708static sw_error_t 709_dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, 710 a_bool_t * enable) 711{ 712 sw_error_t rv; 713 a_uint32_t phy_id = 0; 714 hsl_phy_ops_t *phy_drv; 715 716 HSL_DEV_ID_CHECK (dev_id); 717 718 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 719 { 720 return SW_BAD_PARAM; 721 } 722 723 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 724 if (NULL == phy_drv->phy_hibernation_get) 725 return SW_NOT_SUPPORTED; 726 727 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 728 SW_RTN_ON_ERROR (rv); 729 730 rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable); 731 732 return rv; 733} 734 735static sw_error_t 736_dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, 737 fal_cable_status_t * cable_status, a_uint32_t * cable_len) 738{ 739 sw_error_t rv; 740 a_uint32_t phy_id = 0; 741 hsl_phy_ops_t *phy_drv; 742 743 HSL_DEV_ID_CHECK (dev_id); 744 745 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 746 { 747 return SW_BAD_PARAM; 748 } 749 750 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 751 if (NULL == phy_drv->phy_cdt) 752 return SW_NOT_SUPPORTED; 753 754 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 755 SW_RTN_ON_ERROR (rv); 756 757 rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len); 758 759 return rv; 760} 761 762static sw_error_t 763_dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, 764 fal_port_header_mode_t mode) 765{ 766 sw_error_t rv; 767 a_uint32_t val; 768 769 HSL_DEV_ID_CHECK (dev_id); 770 771 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 772 { 773 return SW_BAD_PARAM; 774 } 775 776 if (FAL_NO_HEADER_EN == mode) 777 { 778 val = 0; 779 } 780 else if (FAL_ONLY_MANAGE_FRAME_EN == mode && port_id != 0) 781 { 782 val = 1; 783 } 784 else if (FAL_ALL_TYPE_FRAME_EN == mode) 785 { 786 val = 2; 787 } 788 else 789 { 790 return SW_BAD_PARAM; 791 } 792 793 HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, 794 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 795 return rv; 796} 797 798static sw_error_t 799_dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, 800 fal_port_header_mode_t * mode) 801{ 802 sw_error_t rv; 803 a_uint32_t val; 804 805 HSL_DEV_ID_CHECK (dev_id); 806 807 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 808 { 809 return SW_BAD_PARAM; 810 } 811 812 HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, 813 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 814 SW_RTN_ON_ERROR (rv); 815 816 if (1 == val) 817 { 818 *mode = FAL_ONLY_MANAGE_FRAME_EN; 819 } 820 else if (2 == val) 821 { 822 *mode = FAL_ALL_TYPE_FRAME_EN; 823 } 824 else 825 { 826 *mode = FAL_NO_HEADER_EN; 827 } 828 829 return SW_OK; 830} 831 832static sw_error_t 833_dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, 834 fal_port_header_mode_t mode) 835{ 836 sw_error_t rv; 837 a_uint32_t val; 838 839 HSL_DEV_ID_CHECK (dev_id); 840 841 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) 842 { 843 return SW_BAD_PARAM; 844 } 845 846 if (FAL_NO_HEADER_EN == mode) 847 { 848 val = 0; 849 } 850 else if (FAL_ONLY_MANAGE_FRAME_EN == mode) 851 { 852 val = 1; 853 } 854 else if (FAL_ALL_TYPE_FRAME_EN == mode) 855 { 856 val = 2; 857 } 858 else 859 { 860 return SW_BAD_PARAM; 861 } 862 863 HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, 864 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 865 return rv; 866} 867 868static sw_error_t 869_dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, 870 fal_port_header_mode_t * mode) 871{ 872 sw_error_t rv; 873 a_uint32_t val; 874 875 HSL_DEV_ID_CHECK (dev_id); 876 877 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) 878 { 879 return SW_BAD_PARAM; 880 } 881 882 HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, 883 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 884 SW_RTN_ON_ERROR (rv); 885 886 if (1 == val) 887 { 888 *mode = FAL_ONLY_MANAGE_FRAME_EN; 889 } 890 else if (2 == val) 891 { 892 *mode = FAL_ALL_TYPE_FRAME_EN; 893 } 894 else 895 { 896 *mode = FAL_NO_HEADER_EN; 897 } 898 899 return SW_OK; 900} 901 902static sw_error_t 903_dess_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) 904{ 905 a_uint32_t reg; 906 sw_error_t rv; 907 908 HSL_DEV_ID_CHECK (dev_id); 909 910 HSL_REG_ENTRY_GET (rv, dev_id, HEADER_CTL, 0, 911 (a_uint8_t *) (®), sizeof (a_uint32_t)); 912 SW_RTN_ON_ERROR (rv); 913 914 if (A_TRUE == enable) 915 { 916 if (0xffff < type) 917 { 918 return SW_BAD_PARAM; 919 } 920 SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_LEN, 1, reg); 921 SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_VAL, type, reg); 922 } 923 else if (A_FALSE == enable) 924 { 925 SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_LEN, 0, reg); 926 SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_VAL, 0, reg); 927 } 928 else 929 { 930 return SW_BAD_PARAM; 931 } 932 933 HSL_REG_ENTRY_SET (rv, dev_id, HEADER_CTL, 0, 934 (a_uint8_t *) (®), sizeof (a_uint32_t)); 935 return rv; 936} 937 938static sw_error_t 939_dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable, 940 a_uint32_t * type) 941{ 942 a_uint32_t data, reg; 943 sw_error_t rv; 944 945 HSL_DEV_ID_CHECK (dev_id); 946 947 HSL_REG_ENTRY_GET (rv, dev_id, HEADER_CTL, 0, 948 (a_uint8_t *) (®), sizeof (a_uint32_t)); 949 SW_RTN_ON_ERROR (rv); 950 951 SW_GET_FIELD_BY_REG (HEADER_CTL, TYPE_LEN, data, reg); 952 if (data) 953 { 954 SW_GET_FIELD_BY_REG (HEADER_CTL, TYPE_VAL, data, reg); 955 *enable = A_TRUE; 956 *type = data; 957 } 958 else 959 { 960 *enable = A_FALSE; 961 *type = 0; 962 } 963 964 return SW_OK; 965} 966 967static sw_error_t 968_dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id, 969 a_bool_t enable) 970{ 971 sw_error_t rv; 972 a_uint32_t reg, force, val, tmp; 973 974 HSL_DEV_ID_CHECK (dev_id); 975 976 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 977 { 978 return SW_BAD_PARAM; 979 } 980 981 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 982 (a_uint8_t *) (®), sizeof (a_uint32_t)); 983 SW_RTN_ON_ERROR (rv); 984 985 if (A_TRUE == enable) 986 { 987 val = 1; 988 } 989 else if (A_FALSE == enable) 990 { 991 val = 0; 992 } 993 else 994 { 995 return SW_BAD_PARAM; 996 } 997 tmp = reg; 998 999 /* for those ports without PHY device we set MAC register */ 1000 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 1001 { 1002 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg); 1003 SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, val, reg); 1004 } 1005 else 1006 { 1007 SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg); 1008 if (force) 1009 { 1010 /* link isn't in force mode so can't set */ 1011 return SW_DISABLE; 1012 } 1013 else 1014 { 1015 SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, val, reg); 1016 } 1017 } 1018 if (tmp == reg) 1019 return SW_OK; 1020 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 1021 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1022 return rv; 1023} 1024 1025static sw_error_t 1026_dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id, 1027 a_bool_t * enable) 1028{ 1029 sw_error_t rv; 1030 a_uint32_t val; 1031 1032 HSL_DEV_ID_CHECK (dev_id); 1033 1034 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1035 { 1036 return SW_BAD_PARAM; 1037 } 1038 1039 HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TXMAC_EN, 1040 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1041 SW_RTN_ON_ERROR (rv); 1042 1043 if (val) 1044 { 1045 *enable = A_TRUE; 1046 } 1047 else 1048 { 1049 *enable = A_FALSE; 1050 } 1051 1052 return SW_OK; 1053} 1054 1055static sw_error_t 1056_dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id, 1057 a_bool_t enable) 1058{ 1059 sw_error_t rv; 1060 a_uint32_t reg, force, val, tmp; 1061 1062 HSL_DEV_ID_CHECK (dev_id); 1063 1064 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1065 { 1066 return SW_BAD_PARAM; 1067 } 1068 1069 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 1070 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1071 SW_RTN_ON_ERROR (rv); 1072 1073 if (A_TRUE == enable) 1074 { 1075 val = 1; 1076 } 1077 else if (A_FALSE == enable) 1078 { 1079 val = 0; 1080 } 1081 else 1082 { 1083 return SW_BAD_PARAM; 1084 } 1085 tmp = reg; 1086 1087 /* for those ports without PHY device we set MAC register */ 1088 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 1089 { 1090 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg); 1091 SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, val, reg); 1092 } 1093 else 1094 { 1095 SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg); 1096 if (force) 1097 { 1098 /* link isn't in force mode so can't set */ 1099 return SW_DISABLE; 1100 } 1101 else 1102 { 1103 SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, val, reg); 1104 } 1105 } 1106 if (tmp == reg) 1107 return SW_OK; 1108 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 1109 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1110 return rv; 1111} 1112 1113static sw_error_t 1114_dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id, 1115 a_bool_t * enable) 1116{ 1117 sw_error_t rv; 1118 a_uint32_t val; 1119 1120 HSL_DEV_ID_CHECK (dev_id); 1121 1122 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1123 { 1124 return SW_BAD_PARAM; 1125 } 1126 1127 HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, RXMAC_EN, 1128 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1129 SW_RTN_ON_ERROR (rv); 1130 1131 if (val) 1132 { 1133 *enable = A_TRUE; 1134 } 1135 else 1136 { 1137 *enable = A_FALSE; 1138 } 1139 1140 return SW_OK; 1141} 1142 1143static sw_error_t 1144_dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id, 1145 a_bool_t enable) 1146{ 1147 sw_error_t rv; 1148 a_uint32_t val, reg, force, tmp; 1149 1150 HSL_DEV_ID_CHECK (dev_id); 1151 1152 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1153 { 1154 return SW_BAD_PARAM; 1155 } 1156 1157 if (A_TRUE == enable) 1158 { 1159 val = 1; 1160 } 1161 else if (A_FALSE == enable) 1162 { 1163 val = 0; 1164 } 1165 else 1166 { 1167 return SW_BAD_PARAM; 1168 } 1169 1170 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 1171 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1172 SW_RTN_ON_ERROR (rv); 1173 tmp = reg; 1174 1175 /* for those ports without PHY device we set MAC register */ 1176 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 1177 { 1178 SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg); 1179 SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg); 1180 } 1181 else 1182 { 1183 SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); 1184 if (force) 1185 { 1186 /* flow control isn't in force mode so can't set */ 1187 return SW_DISABLE; 1188 } 1189 else 1190 { 1191 SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg); 1192 } 1193 } 1194 if (tmp == reg) 1195 return SW_OK; 1196 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 1197 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1198 return rv; 1199} 1200 1201static sw_error_t 1202_dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id, 1203 a_bool_t * enable) 1204{ 1205 sw_error_t rv; 1206 a_uint32_t val; 1207 1208 HSL_DEV_ID_CHECK (dev_id); 1209 1210 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1211 { 1212 return SW_BAD_PARAM; 1213 } 1214 1215 HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN, 1216 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1217 SW_RTN_ON_ERROR (rv); 1218 1219 if (val) 1220 { 1221 *enable = A_TRUE; 1222 } 1223 else 1224 { 1225 *enable = A_FALSE; 1226 } 1227 1228 return SW_OK; 1229} 1230 1231static sw_error_t 1232_dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id, 1233 a_bool_t enable) 1234{ 1235 sw_error_t rv; 1236 a_uint32_t val, reg, force, tmp; 1237 1238 HSL_DEV_ID_CHECK (dev_id); 1239 1240 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) 1241 { 1242 return SW_BAD_PARAM; 1243 } 1244 1245 if (A_TRUE == enable) 1246 { 1247 val = 1; 1248 } 1249 else if (A_FALSE == enable) 1250 { 1251 val = 0; 1252 } 1253 else 1254 { 1255 return SW_BAD_PARAM; 1256 } 1257 1258 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 1259 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1260 SW_RTN_ON_ERROR (rv); 1261 tmp = reg; 1262 1263 /* for those ports without PHY device we set MAC register */ 1264 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 1265 { 1266 SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg); 1267 SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg); 1268 } 1269 else 1270 { 1271 SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); 1272 if (force) 1273 { 1274 /* flow control isn't in force mode so can't set */ 1275 return SW_DISABLE; 1276 } 1277 else 1278 { 1279 SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg); 1280 } 1281 } 1282 if (tmp == reg) 1283 return SW_OK; 1284 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 1285 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1286 return rv; 1287} 1288 1289static sw_error_t 1290_dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id, 1291 a_bool_t * enable) 1292{ 1293 sw_error_t rv; 1294 a_uint32_t val; 1295 1296 HSL_DEV_ID_CHECK (dev_id); 1297 1298 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) 1299 { 1300 return SW_BAD_PARAM; 1301 } 1302 1303 HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN, 1304 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1305 SW_RTN_ON_ERROR (rv); 1306 1307 if (val) 1308 { 1309 *enable = A_TRUE; 1310 } 1311 else 1312 { 1313 *enable = A_FALSE; 1314 } 1315 1316 return SW_OK; 1317} 1318 1319static sw_error_t 1320_dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id, 1321 a_bool_t enable) 1322{ 1323 sw_error_t rv; 1324 a_uint32_t val, tmp; 1325 1326 HSL_DEV_ID_CHECK (dev_id); 1327 1328 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1329 { 1330 return SW_BAD_PARAM; 1331 } 1332 1333 if (A_TRUE == enable) 1334 { 1335 val = 1; 1336 } 1337 else if (A_FALSE == enable) 1338 { 1339 val = 0; 1340 } 1341 else 1342 { 1343 return SW_BAD_PARAM; 1344 } 1345 HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, 1346 (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); 1347 if (tmp == val) 1348 return SW_OK; 1349 1350 HSL_REG_FIELD_SET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, 1351 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1352 return rv; 1353} 1354 1355static sw_error_t 1356_dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id, 1357 a_bool_t * enable) 1358{ 1359 sw_error_t rv; 1360 a_uint32_t val; 1361 1362 HSL_DEV_ID_CHECK (dev_id); 1363 1364 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1365 { 1366 return SW_BAD_PARAM; 1367 } 1368 1369 HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, 1370 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1371 SW_RTN_ON_ERROR (rv); 1372 1373 if (val) 1374 { 1375 *enable = A_TRUE; 1376 } 1377 else 1378 { 1379 *enable = A_FALSE; 1380 } 1381 1382 return SW_OK; 1383} 1384 1385static sw_error_t 1386_dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, 1387 a_bool_t enable) 1388{ 1389 sw_error_t rv; 1390 a_uint32_t reg, tmp; 1391 1392 HSL_DEV_ID_CHECK (dev_id); 1393 1394 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) 1395 { 1396 return SW_BAD_PARAM; 1397 } 1398 1399 HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, 1400 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1401 SW_RTN_ON_ERROR (rv); 1402 SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg); 1403 1404 if (A_TRUE == enable) 1405 { 1406 if(tmp == 0) 1407 return SW_OK; 1408 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg); 1409 } 1410 else if (A_FALSE == enable) 1411 { 1412 if(tmp == 1) 1413 return SW_OK; 1414 /* for those ports without PHY, it can't sync link status */ 1415 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 1416 { 1417 return SW_DISABLE; 1418 } 1419 SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 1, reg); 1420 } 1421 else 1422 { 1423 return SW_BAD_PARAM; 1424 } 1425 1426 HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, 1427 (a_uint8_t *) (®), sizeof (a_uint32_t)); 1428 return rv; 1429} 1430 1431static sw_error_t 1432_dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, 1433 a_bool_t * enable) 1434{ 1435 sw_error_t rv; 1436 a_uint32_t val; 1437 1438 HSL_DEV_ID_CHECK (dev_id); 1439 1440 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) 1441 { 1442 return SW_BAD_PARAM; 1443 } 1444 1445 HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, LINK_EN, 1446 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1447 SW_RTN_ON_ERROR (rv); 1448 1449 if (0 == val) 1450 { 1451 *enable = A_TRUE; 1452 } 1453 else 1454 { 1455 *enable = A_FALSE; 1456 } 1457 1458 return SW_OK; 1459} 1460 1461static sw_error_t 1462_dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, 1463 a_bool_t * status) 1464{ 1465 sw_error_t rv; 1466 a_uint32_t phy_id; 1467 hsl_phy_ops_t *phy_drv; 1468 1469 HSL_DEV_ID_CHECK (dev_id); 1470 1471 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) 1472 { 1473 return SW_BAD_PARAM; 1474 } 1475 1476 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1477 if (NULL == phy_drv->phy_link_status_get) 1478 return SW_NOT_SUPPORTED; 1479 1480 /* for those ports without PHY device supposed always link up */ 1481 if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) 1482 { 1483 *status = A_TRUE; 1484 } 1485 else 1486 { 1487 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1488 SW_RTN_ON_ERROR (rv); 1489 1490 if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) 1491 { 1492 *status = A_TRUE; 1493 } 1494 else 1495 { 1496 *status = A_FALSE; 1497 } 1498 } 1499 1500 return SW_OK; 1501} 1502 1503static sw_error_t 1504_dess_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) 1505{ 1506 sw_error_t rv; 1507 a_uint32_t port_id; 1508 a_uint32_t phy_id; 1509 hsl_dev_t *pdev = NULL; 1510 hsl_phy_ops_t *phy_drv; 1511 1512 HSL_DEV_ID_CHECK(dev_id); 1513 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1514 if (NULL == phy_drv->phy_link_status_get) 1515 return SW_NOT_SUPPORTED; 1516 1517 pdev = hsl_dev_ptr_get(dev_id); 1518 if (pdev == NULL) 1519 return SW_NOT_INITIALIZED; 1520 1521 *status = 0x0; 1522 for (port_id = 0; port_id < pdev->nr_ports; port_id++) 1523 { 1524 /* for those ports without PHY device supposed always link up */ 1525 if (A_FALSE == _dess_port_phy_connected(dev_id, port_id)) 1526 { 1527 *status |= (0x1 << port_id); 1528 } 1529 else 1530 { 1531 rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); 1532 SW_RTN_ON_ERROR(rv); 1533 1534 if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) 1535 { 1536 *status |= (0x1 << port_id); 1537 } 1538 else 1539 { 1540 *status &= ~(0x1 << port_id); 1541 } 1542 } 1543 } 1544 return SW_OK; 1545} 1546 1547static sw_error_t 1548_dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id, 1549 a_bool_t enable) 1550{ 1551 sw_error_t rv = SW_OK; 1552 a_uint32_t val; 1553 1554 HSL_DEV_ID_CHECK (dev_id); 1555 1556 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1557 { 1558 return SW_BAD_PARAM; 1559 } 1560 1561 if (A_TRUE == enable) 1562 { 1563 val = 1; 1564 } 1565 else if (A_FALSE == enable) 1566 { 1567 val = 0; 1568 } 1569 else 1570 { 1571 return SW_BAD_PARAM; 1572 } 1573 1574 HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, 1575 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1576 return rv; 1577} 1578 1579static sw_error_t 1580_dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id, 1581 a_bool_t * enable) 1582{ 1583 sw_error_t rv; 1584 a_uint32_t val; 1585 1586 HSL_DEV_ID_CHECK (dev_id); 1587 1588 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1589 { 1590 return SW_BAD_PARAM; 1591 } 1592 1593 HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, 1594 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1595 SW_RTN_ON_ERROR (rv); 1596 1597 if (0 == val) 1598 { 1599 *enable = A_FALSE; 1600 } 1601 else 1602 { 1603 *enable = A_TRUE; 1604 } 1605 1606 return SW_OK; 1607} 1608 1609 1610static sw_error_t 1611_dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id, 1612 a_uint32_t queue_id, a_bool_t enable) 1613{ 1614 sw_error_t rv = SW_OK; 1615 a_uint32_t val, offset = 0, field = 0; 1616 1617 HSL_DEV_ID_CHECK (dev_id); 1618 1619 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1620 { 1621 return SW_BAD_PARAM; 1622 } 1623 1624 if (queue_id >= port_queue[port_id]) 1625 { 1626 return SW_BAD_PARAM; 1627 } 1628 1629 if (port_id != 0) 1630 offset = port_id * 4 + 2; 1631 offset += queue_id; 1632 1633 if (A_TRUE == enable) 1634 { 1635 field = 1 << offset; 1636 } 1637 else if (A_FALSE == enable) 1638 { 1639 field = ~(1 << offset); 1640 } 1641 else 1642 { 1643 return SW_BAD_PARAM; 1644 } 1645 1646 1647 1648 HSL_REG_ENTRY_GET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0, 1649 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1650 if (A_TRUE == enable) 1651 { 1652 val = val | field; 1653 } 1654 else 1655 { 1656 val = val & field; 1657 } 1658 1659 HSL_REG_ENTRY_SET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0, 1660 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1661 return rv; 1662} 1663 1664 1665static sw_error_t 1666_dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id, 1667 a_uint32_t queue_id, a_bool_t * enable) 1668{ 1669 sw_error_t rv = SW_OK; 1670 a_uint32_t val, offset = 0; 1671 1672 HSL_DEV_ID_CHECK (dev_id); 1673 1674 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) 1675 { 1676 return SW_BAD_PARAM; 1677 } 1678 1679 if (queue_id >= port_queue[port_id]) 1680 { 1681 return SW_BAD_PARAM; 1682 } 1683 1684 if (port_id != 0) 1685 offset = port_id * 4 + 2; 1686 offset += queue_id; 1687 1688 HSL_REG_ENTRY_GET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0, 1689 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1690 val = (val >> offset) & 0x1; 1691 if (val == 0) 1692 { 1693 *enable = A_FALSE; 1694 } 1695 else if (val == 1) 1696 { 1697 *enable = A_TRUE; 1698 } 1699 return rv; 1700} 1701 1702static sw_error_t 1703_dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id, 1704 a_uint8_t on_thres, a_uint8_t off_thres) 1705{ 1706 sw_error_t rv; 1707 a_uint32_t val = 0; 1708 1709 HSL_DEV_ID_CHECK (dev_id); 1710 1711 if (ring_id >= DMA_MAX_VIRT_RING) 1712 { 1713 return SW_BAD_PARAM; 1714 } 1715 1716 if (on_thres > off_thres || on_thres == 0) 1717 { 1718 return SW_BAD_PARAM; 1719 } 1720 1721 SW_SET_REG_BY_FIELD (RING_FLOW_CTRL_THRES, XON, on_thres, val); 1722 SW_SET_REG_BY_FIELD (RING_FLOW_CTRL_THRES, XOFF, off_thres, val); 1723 HSL_REG_ENTRY_SET (rv, dev_id, RING_FLOW_CTRL_THRES, ring_id, 1724 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1725 1726 1727 return rv; 1728} 1729 1730 1731static sw_error_t 1732_dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id, 1733 a_uint8_t * on_thres, a_uint8_t * off_thres) 1734{ 1735 1736 sw_error_t rv; 1737 a_uint32_t val = 0; 1738 a_uint8_t hthres, lthres; 1739 1740 HSL_DEV_ID_CHECK (dev_id); 1741 1742 if (ring_id >= DMA_MAX_VIRT_RING) 1743 { 1744 return SW_BAD_PARAM; 1745 } 1746 1747 HSL_REG_ENTRY_GET (rv, dev_id, RING_FLOW_CTRL_THRES, ring_id, 1748 (a_uint8_t *) (&val), sizeof (a_uint32_t)); 1749 1750 SW_GET_FIELD_BY_REG (RING_FLOW_CTRL_THRES, XON, hthres, val); 1751 SW_GET_FIELD_BY_REG (RING_FLOW_CTRL_THRES, XOFF, lthres, val); 1752 1753 *on_thres = hthres; 1754 *off_thres = lthres; 1755 1756 return rv; 1757} 1758 1759static sw_error_t 1760_dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 1761{ 1762 sw_error_t rv; 1763 a_uint32_t phy_id = 0; 1764 hsl_phy_ops_t *phy_drv; 1765 1766 HSL_DEV_ID_CHECK (dev_id); 1767 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1768 { 1769 return SW_BAD_PARAM; 1770 } 1771 1772 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1773 if (NULL == phy_drv->phy_8023az_set) 1774 return SW_NOT_SUPPORTED; 1775 1776 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1777 SW_RTN_ON_ERROR (rv); 1778 1779 rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable); 1780 1781 return rv; 1782} 1783 1784static sw_error_t 1785_dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, 1786 a_bool_t * enable) 1787{ 1788 sw_error_t rv; 1789 a_uint32_t phy_id = 0; 1790 hsl_phy_ops_t *phy_drv; 1791 1792 HSL_DEV_ID_CHECK (dev_id); 1793 1794 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1795 { 1796 return SW_BAD_PARAM; 1797 } 1798 1799 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1800 if (NULL == phy_drv->phy_8023az_get) 1801 return SW_NOT_SUPPORTED; 1802 1803 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1804 SW_RTN_ON_ERROR (rv); 1805 1806 rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable); 1807 1808 return rv; 1809} 1810 1811static sw_error_t 1812_dess_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id, 1813 fal_port_mdix_mode_t mode) 1814{ 1815 sw_error_t rv; 1816 a_uint32_t phy_id = 0; 1817 hsl_phy_ops_t *phy_drv; 1818 1819 HSL_DEV_ID_CHECK (dev_id); 1820 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1821 { 1822 return SW_BAD_PARAM; 1823 } 1824 1825 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1826 if (NULL == phy_drv->phy_mdix_set) 1827 return SW_NOT_SUPPORTED; 1828 1829 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1830 SW_RTN_ON_ERROR (rv); 1831 1832 rv = phy_drv->phy_mdix_set (dev_id, phy_id, mode); 1833 1834 return rv; 1835} 1836 1837static sw_error_t 1838_dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, 1839 fal_port_mdix_mode_t * mode) 1840{ 1841 sw_error_t rv; 1842 a_uint32_t phy_id = 0; 1843 hsl_phy_ops_t *phy_drv; 1844 1845 HSL_DEV_ID_CHECK (dev_id); 1846 1847 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1848 { 1849 return SW_BAD_PARAM; 1850 } 1851 1852 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1853 if (NULL == phy_drv->phy_mdix_get) 1854 return SW_NOT_SUPPORTED; 1855 1856 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1857 SW_RTN_ON_ERROR (rv); 1858 1859 rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode); 1860 1861 return rv; 1862} 1863 1864static sw_error_t 1865_dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, 1866 fal_port_mdix_status_t * mode) 1867{ 1868 sw_error_t rv; 1869 a_uint32_t phy_id = 0; 1870 hsl_phy_ops_t *phy_drv; 1871 1872 HSL_DEV_ID_CHECK (dev_id); 1873 1874 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1875 { 1876 return SW_BAD_PARAM; 1877 } 1878 1879 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1880 if (NULL == phy_drv->phy_mdix_status_get) 1881 return SW_NOT_SUPPORTED; 1882 1883 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1884 SW_RTN_ON_ERROR (rv); 1885 1886 rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode); 1887 1888 return rv; 1889} 1890 1891static sw_error_t 1892_dess_port_combo_prefer_medium_set (a_uint32_t dev_id, fal_port_t port_id, 1893 fal_port_medium_t phy_medium) 1894{ 1895 sw_error_t rv; 1896 a_uint32_t phy_id = 0; 1897 hsl_phy_ops_t *phy_drv; 1898 1899 HSL_DEV_ID_CHECK (dev_id); 1900 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1901 { 1902 return SW_BAD_PARAM; 1903 } 1904 1905 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1906 if (NULL == phy_drv->phy_combo_prefer_medium_set) 1907 return SW_NOT_SUPPORTED; 1908 1909 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1910 SW_RTN_ON_ERROR (rv); 1911 1912 rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, phy_medium); 1913 1914 return rv; 1915} 1916 1917static sw_error_t 1918_dess_port_combo_prefer_medium_get (a_uint32_t dev_id, fal_port_t port_id, 1919 fal_port_medium_t * phy_medium) 1920{ 1921 sw_error_t rv; 1922 a_uint32_t phy_id = 0; 1923 hsl_phy_ops_t *phy_drv; 1924 1925 HSL_DEV_ID_CHECK (dev_id); 1926 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1927 { 1928 return SW_BAD_PARAM; 1929 } 1930 1931 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1932 if (NULL == phy_drv->phy_combo_prefer_medium_get) 1933 return SW_NOT_SUPPORTED; 1934 1935 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1936 SW_RTN_ON_ERROR (rv); 1937 1938 rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, phy_medium); 1939 1940 return rv; 1941} 1942 1943static sw_error_t 1944_dess_port_combo_medium_status_get (a_uint32_t dev_id, fal_port_t port_id, 1945 fal_port_medium_t * phy_medium) 1946{ 1947 sw_error_t rv; 1948 a_uint32_t phy_id = 0; 1949 hsl_phy_ops_t *phy_drv; 1950 1951 HSL_DEV_ID_CHECK (dev_id); 1952 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1953 { 1954 return SW_BAD_PARAM; 1955 } 1956 1957 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1958 if (NULL == phy_drv->phy_combo_medium_status_get) 1959 return SW_NOT_SUPPORTED; 1960 1961 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1962 SW_RTN_ON_ERROR (rv); 1963 1964 rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, phy_medium); 1965 1966 return rv; 1967} 1968 1969static sw_error_t 1970_dess_port_combo_fiber_mode_set (a_uint32_t dev_id, fal_port_t port_id, 1971 fal_port_fiber_mode_t fiber_mode) 1972{ 1973 sw_error_t rv; 1974 a_uint32_t phy_id = 0; 1975 hsl_phy_ops_t *phy_drv; 1976 1977 HSL_DEV_ID_CHECK (dev_id); 1978 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 1979 { 1980 return SW_BAD_PARAM; 1981 } 1982 1983 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 1984 if (NULL == phy_drv->phy_combo_fiber_mode_set) 1985 return SW_NOT_SUPPORTED; 1986 1987 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 1988 SW_RTN_ON_ERROR (rv); 1989 1990 rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, fiber_mode); 1991 1992 return rv; 1993} 1994 1995static sw_error_t 1996_dess_port_combo_fiber_mode_get (a_uint32_t dev_id, fal_port_t port_id, 1997 fal_port_fiber_mode_t * fiber_mode) 1998{ 1999 sw_error_t rv; 2000 a_uint32_t phy_id = 0; 2001 hsl_phy_ops_t *phy_drv; 2002 2003 HSL_DEV_ID_CHECK (dev_id); 2004 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2005 { 2006 return SW_BAD_PARAM; 2007 } 2008 2009 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2010 if (NULL == phy_drv->phy_combo_fiber_mode_get) 2011 return SW_NOT_SUPPORTED; 2012 2013 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2014 SW_RTN_ON_ERROR (rv); 2015 2016 rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, fiber_mode); 2017 2018 return rv; 2019} 2020 2021static sw_error_t 2022_dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, 2023 a_bool_t enable) 2024{ 2025 sw_error_t rv; 2026 a_uint32_t phy_id = 0; 2027 hsl_phy_ops_t *phy_drv; 2028 2029 HSL_DEV_ID_CHECK (dev_id); 2030 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2031 { 2032 return SW_BAD_PARAM; 2033 } 2034 2035 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2036 if (NULL == phy_drv->phy_local_loopback_set) 2037 return SW_NOT_SUPPORTED; 2038 2039 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2040 SW_RTN_ON_ERROR (rv); 2041 2042 rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable); 2043 2044 return rv; 2045} 2046 2047static sw_error_t 2048_dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, 2049 a_bool_t * enable) 2050{ 2051 sw_error_t rv; 2052 a_uint32_t phy_id = 0; 2053 hsl_phy_ops_t *phy_drv; 2054 2055 HSL_DEV_ID_CHECK (dev_id); 2056 2057 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2058 { 2059 return SW_BAD_PARAM; 2060 } 2061 2062 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2063 if (NULL == phy_drv->phy_local_loopback_get) 2064 return SW_NOT_SUPPORTED; 2065 2066 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2067 SW_RTN_ON_ERROR (rv); 2068 2069 rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable); 2070 2071 return rv; 2072} 2073 2074static sw_error_t 2075_dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, 2076 a_bool_t enable) 2077{ 2078 sw_error_t rv; 2079 a_uint32_t phy_id = 0; 2080 hsl_phy_ops_t *phy_drv; 2081 2082 HSL_DEV_ID_CHECK (dev_id); 2083 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2084 { 2085 return SW_BAD_PARAM; 2086 } 2087 2088 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2089 if (NULL == phy_drv->phy_remote_loopback_set) 2090 return SW_NOT_SUPPORTED; 2091 2092 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2093 SW_RTN_ON_ERROR (rv); 2094 2095 rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable); 2096 2097 return rv; 2098} 2099 2100static sw_error_t 2101_dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, 2102 a_bool_t * enable) 2103{ 2104 sw_error_t rv; 2105 a_uint32_t phy_id = 0; 2106 hsl_phy_ops_t *phy_drv; 2107 2108 HSL_DEV_ID_CHECK (dev_id); 2109 2110 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2111 { 2112 return SW_BAD_PARAM; 2113 } 2114 2115 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2116 if (NULL == phy_drv->phy_remote_loopback_get) 2117 return SW_NOT_SUPPORTED; 2118 2119 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2120 SW_RTN_ON_ERROR (rv); 2121 2122 rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable); 2123 2124 return rv; 2125} 2126 2127static sw_error_t 2128_dess_port_reset (a_uint32_t dev_id, fal_port_t port_id) 2129{ 2130 sw_error_t rv; 2131 a_uint32_t phy_id = 0; 2132 hsl_phy_ops_t *phy_drv; 2133 2134 HSL_DEV_ID_CHECK (dev_id); 2135 2136 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2137 { 2138 return SW_BAD_PARAM; 2139 } 2140 2141 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2142 if (NULL == phy_drv->phy_reset) 2143 return SW_NOT_SUPPORTED; 2144 2145 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2146 SW_RTN_ON_ERROR (rv); 2147 2148 rv = phy_drv->phy_reset(dev_id, phy_id); 2149 2150 return rv; 2151} 2152 2153static sw_error_t 2154_dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id) 2155{ 2156 sw_error_t rv; 2157 a_uint32_t phy_id = 0; 2158 hsl_phy_ops_t *phy_drv; 2159 2160 HSL_DEV_ID_CHECK (dev_id); 2161 2162 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2163 { 2164 return SW_BAD_PARAM; 2165 } 2166 2167 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2168 if (NULL == phy_drv->phy_power_off) 2169 return SW_NOT_SUPPORTED; 2170 2171 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2172 SW_RTN_ON_ERROR (rv); 2173 2174 rv = phy_drv->phy_power_off(dev_id, phy_id); 2175 2176 return rv; 2177} 2178 2179static sw_error_t 2180_dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id) 2181{ 2182 sw_error_t rv; 2183 a_uint32_t phy_id = 0; 2184 hsl_phy_ops_t *phy_drv; 2185 2186 HSL_DEV_ID_CHECK (dev_id); 2187 2188 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2189 { 2190 return SW_BAD_PARAM; 2191 } 2192 2193 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2194 if (NULL == phy_drv->phy_power_on) 2195 return SW_NOT_SUPPORTED; 2196 2197 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2198 SW_RTN_ON_ERROR (rv); 2199 2200 rv = phy_drv->phy_power_on(dev_id, phy_id); 2201 2202 return rv; 2203} 2204 2205static sw_error_t 2206_dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, 2207 a_bool_t enable) 2208{ 2209 sw_error_t rv; 2210 a_uint32_t phy_id = 0; 2211 hsl_phy_ops_t *phy_drv; 2212 2213 HSL_DEV_ID_CHECK (dev_id); 2214 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2215 { 2216 return SW_BAD_PARAM; 2217 } 2218 2219 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2220 if (NULL == phy_drv->phy_wol_status_set) 2221 return SW_NOT_SUPPORTED; 2222 2223 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2224 SW_RTN_ON_ERROR (rv); 2225 2226 rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable); 2227 2228 return rv; 2229} 2230 2231static sw_error_t 2232_dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, 2233 a_bool_t * enable) 2234{ 2235 sw_error_t rv; 2236 a_uint32_t phy_id = 0; 2237 hsl_phy_ops_t *phy_drv; 2238 2239 HSL_DEV_ID_CHECK (dev_id); 2240 2241 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2242 { 2243 return SW_BAD_PARAM; 2244 } 2245 2246 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2247 if (NULL == phy_drv->phy_wol_status_get) 2248 return SW_NOT_SUPPORTED; 2249 2250 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2251 SW_RTN_ON_ERROR (rv); 2252 2253 rv = phy_drv->phy_wol_status_get (dev_id, phy_id, enable); 2254 2255 return rv; 2256} 2257 2258static sw_error_t 2259_dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, 2260 a_uint16_t * org_id, a_uint16_t * rev_id) 2261{ 2262 sw_error_t rv; 2263 a_uint32_t phy_id = 0; 2264 hsl_phy_ops_t *phy_drv; 2265 2266 HSL_DEV_ID_CHECK (dev_id); 2267 2268 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2269 { 2270 return SW_BAD_PARAM; 2271 } 2272 2273 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2274 if (NULL == phy_drv->phy_id_get) 2275 return SW_NOT_SUPPORTED; 2276 2277 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2278 SW_RTN_ON_ERROR (rv); 2279 2280 rv = phy_drv->phy_id_get (dev_id, phy_id,org_id,rev_id); 2281 2282 return rv; 2283} 2284 2285static sw_error_t 2286_dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, 2287 fal_mac_addr_t * mac) 2288{ 2289 sw_error_t rv; 2290 a_uint32_t phy_id = 0; 2291 hsl_phy_ops_t *phy_drv; 2292 2293 HSL_DEV_ID_CHECK (dev_id); 2294 2295 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2296 { 2297 return SW_BAD_PARAM; 2298 } 2299 2300 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2301 if (NULL == phy_drv->phy_magic_frame_mac_set) 2302 return SW_NOT_SUPPORTED; 2303 2304 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2305 SW_RTN_ON_ERROR (rv); 2306 2307 rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac); 2308 2309 return rv; 2310} 2311 2312static sw_error_t 2313_dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, 2314 fal_mac_addr_t * mac) 2315{ 2316 sw_error_t rv; 2317 a_uint32_t phy_id = 0; 2318 hsl_phy_ops_t *phy_drv; 2319 2320 HSL_DEV_ID_CHECK (dev_id); 2321 2322 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2323 { 2324 return SW_BAD_PARAM; 2325 } 2326 2327 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2328 if (NULL == phy_drv->phy_magic_frame_mac_get) 2329 return SW_NOT_SUPPORTED; 2330 2331 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2332 SW_RTN_ON_ERROR (rv); 2333 2334 rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac); 2335 2336 return rv; 2337} 2338 2339static sw_error_t 2340_dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, 2341 fal_port_interface_mode_t mode) 2342{ 2343 sw_error_t rv; 2344 a_uint32_t phy_id = 0; 2345 hsl_phy_ops_t *phy_drv; 2346 2347 HSL_DEV_ID_CHECK (dev_id); 2348 2349 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2350 { 2351 return SW_BAD_PARAM; 2352 } 2353 2354 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2355 if (NULL == phy_drv->phy_interface_mode_set) 2356 return SW_NOT_SUPPORTED; 2357 2358 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2359 SW_RTN_ON_ERROR (rv); 2360 2361 rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode); 2362 2363 return rv; 2364} 2365 2366static sw_error_t 2367_dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, 2368 fal_port_interface_mode_t * mode) 2369{ 2370 sw_error_t rv; 2371 a_uint32_t phy_id = 0; 2372 hsl_phy_ops_t *phy_drv; 2373 2374 HSL_DEV_ID_CHECK (dev_id); 2375 2376 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2377 { 2378 return SW_BAD_PARAM; 2379 } 2380 2381 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2382 if (NULL == phy_drv->phy_interface_mode_get) 2383 return SW_NOT_SUPPORTED; 2384 2385 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2386 SW_RTN_ON_ERROR (rv); 2387 2388 rv = phy_drv->phy_interface_mode_get (dev_id, phy_id,mode); 2389 2390 return rv; 2391} 2392 2393static sw_error_t 2394_dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, 2395 fal_port_interface_mode_t * mode) 2396{ 2397 sw_error_t rv; 2398 a_uint32_t phy_id = 0; 2399 hsl_phy_ops_t *phy_drv; 2400 2401 HSL_DEV_ID_CHECK (dev_id); 2402 2403 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2404 { 2405 return SW_BAD_PARAM; 2406 } 2407 2408 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2409 if (NULL == phy_drv->phy_interface_mode_status_get) 2410 return SW_NOT_SUPPORTED; 2411 2412 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2413 SW_RTN_ON_ERROR (rv); 2414 2415 rv = phy_drv->phy_interface_mode_status_get (dev_id, phy_id,mode); 2416 2417 return rv; 2418} 2419 2420static sw_error_t 2421_dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 2422{ 2423 sw_error_t rv; 2424 a_uint32_t phy_id = 0; 2425 hsl_phy_ops_t *phy_drv; 2426 2427 HSL_DEV_ID_CHECK (dev_id); 2428 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2429 { 2430 return SW_BAD_PARAM; 2431 } 2432 2433 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2434 if (NULL == phy_drv->phy_counter_set) 2435 return SW_NOT_SUPPORTED; 2436 2437 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2438 SW_RTN_ON_ERROR (rv); 2439 2440 rv = phy_drv->phy_counter_set (dev_id, phy_id, enable); 2441 2442 return rv; 2443} 2444 2445static sw_error_t 2446_dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, 2447 a_bool_t * enable) 2448{ 2449 sw_error_t rv; 2450 a_uint32_t phy_id = 0; 2451 hsl_phy_ops_t *phy_drv; 2452 2453 HSL_DEV_ID_CHECK (dev_id); 2454 2455 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2456 { 2457 return SW_BAD_PARAM; 2458 } 2459 2460 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2461 if (NULL == phy_drv->phy_counter_get) 2462 return SW_NOT_SUPPORTED; 2463 2464 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2465 SW_RTN_ON_ERROR (rv); 2466 2467 rv = phy_drv->phy_counter_get (dev_id, phy_id, enable); 2468 2469 return rv; 2470} 2471 2472static sw_error_t 2473_dess_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, 2474 fal_port_counter_info_t * counter_info) 2475{ 2476 sw_error_t rv; 2477 a_uint32_t phy_id = 0; 2478 hsl_phy_ops_t *phy_drv; 2479 2480 HSL_DEV_ID_CHECK (dev_id); 2481 2482 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) 2483 { 2484 return SW_BAD_PARAM; 2485 } 2486 2487 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); 2488 if (NULL == phy_drv->phy_counter_show) 2489 return SW_NOT_SUPPORTED; 2490 2491 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); 2492 SW_RTN_ON_ERROR (rv); 2493 2494 rv = phy_drv->phy_counter_show (dev_id, phy_id,counter_info); 2495 2496 return rv; 2497} 2498 2499/** 2500 * @brief Set duplex mode on a particular port. 2501 * @param[in] dev_id device id 2502 * @param[in] port_id port id 2503 * @param[in] duplex duplex mode 2504 * @return SW_OK or error code 2505 */ 2506HSL_LOCAL sw_error_t 2507dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, 2508 fal_port_duplex_t duplex) 2509{ 2510 sw_error_t rv; 2511 2512 HSL_API_LOCK; 2513 rv = _dess_port_duplex_set (dev_id, port_id, duplex); 2514 HSL_API_UNLOCK; 2515 return rv; 2516} 2517 2518/** 2519 * @brief Get duplex mode on a particular port. 2520 * @param[in] dev_id device id 2521 * @param[in] port_id port id 2522 * @param[out] duplex duplex mode 2523 * @return SW_OK or error code 2524 */ 2525HSL_LOCAL sw_error_t 2526dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, 2527 fal_port_duplex_t * pduplex) 2528{ 2529 sw_error_t rv; 2530 2531 HSL_API_LOCK; 2532 rv = _dess_port_duplex_get (dev_id, port_id, pduplex); 2533 HSL_API_UNLOCK; 2534 return rv; 2535} 2536 2537/** 2538 * @brief Set speed on a particular port. 2539 * @param[in] dev_id device id 2540 * @param[in] port_id port id 2541 * @param[in] speed port speed 2542 * @return SW_OK or error code 2543 */ 2544HSL_LOCAL sw_error_t 2545dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, 2546 fal_port_speed_t speed) 2547{ 2548 sw_error_t rv; 2549 2550 HSL_API_LOCK; 2551 rv = _dess_port_speed_set (dev_id, port_id, speed); 2552 HSL_API_UNLOCK; 2553 return rv; 2554} 2555 2556/** 2557 * @brief Get speed on a particular port. 2558 * @param[in] dev_id device id 2559 * @param[in] port_id port id 2560 * @param[out] speed port speed 2561 * @return SW_OK or error code 2562 */ 2563HSL_LOCAL sw_error_t 2564dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, 2565 fal_port_speed_t * pspeed) 2566{ 2567 sw_error_t rv; 2568 2569 HSL_API_LOCK; 2570 rv = _dess_port_speed_get (dev_id, port_id, pspeed); 2571 HSL_API_UNLOCK; 2572 return rv; 2573} 2574 2575/** 2576 * @brief Get auto negotiation status on a particular port. 2577 * @param[in] dev_id device id 2578 * @param[in] port_id port id 2579 * @param[out] status A_TRUE or A_FALSE 2580 * @return SW_OK or error code 2581 */ 2582HSL_LOCAL sw_error_t 2583dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, 2584 a_bool_t * status) 2585{ 2586 sw_error_t rv; 2587 2588 HSL_API_LOCK; 2589 rv = _dess_port_autoneg_status_get (dev_id, port_id, status); 2590 HSL_API_UNLOCK; 2591 return rv; 2592} 2593 2594/** 2595 * @brief Enable auto negotiation status on a particular port. 2596 * @param[in] dev_id device id 2597 * @param[in] port_id port id 2598 * @return SW_OK or error code 2599 */ 2600HSL_LOCAL sw_error_t 2601dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) 2602{ 2603 sw_error_t rv; 2604 2605 HSL_API_LOCK; 2606 rv = _dess_port_autoneg_enable (dev_id, port_id); 2607 HSL_API_UNLOCK; 2608 return rv; 2609} 2610 2611/** 2612 * @brief Restart auto negotiation procedule on a particular port. 2613 * @param[in] dev_id device id 2614 * @param[in] port_id port id 2615 * @return SW_OK or error code 2616 */ 2617HSL_LOCAL sw_error_t 2618dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) 2619{ 2620 sw_error_t rv; 2621 2622 HSL_API_LOCK; 2623 rv = _dess_port_autoneg_restart (dev_id, port_id); 2624 HSL_API_UNLOCK; 2625 return rv; 2626} 2627 2628/** 2629 * @brief Set auto negotiation advtisement ability on a particular port. 2630 * @details Comments: 2631 * auto negotiation advtisement ability is defined by macro such as 2632 * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... 2633 * @param[in] dev_id device id 2634 * @param[in] port_id port id 2635 * @param[in] autoadv auto negotiation advtisement ability bit map 2636 * @return SW_OK or error code 2637 */ 2638HSL_LOCAL sw_error_t 2639dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, 2640 a_uint32_t autoadv) 2641{ 2642 sw_error_t rv; 2643 2644 HSL_API_LOCK; 2645 rv = _dess_port_autoneg_adv_set (dev_id, port_id, autoadv); 2646 HSL_API_UNLOCK; 2647 return rv; 2648} 2649 2650/** 2651 * @brief Get auto negotiation advtisement ability on a particular port. 2652 * @param[in] dev_id device id 2653 * @param[in] port_id port id 2654 * @param[out] autoadv auto negotiation advtisement ability bit map 2655 * @return SW_OK or error code 2656 */ 2657HSL_LOCAL sw_error_t 2658dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, 2659 a_uint32_t * autoadv) 2660{ 2661 sw_error_t rv; 2662 2663 HSL_API_LOCK; 2664 rv = _dess_port_autoneg_adv_get (dev_id, port_id, autoadv); 2665 HSL_API_UNLOCK; 2666 return rv; 2667} 2668 2669/** 2670 * @brief Set flow control(rx/tx/bp) status on a particular port. 2671 * @param[in] dev_id device id 2672 * @param[in] port_id port id 2673 * @param[in] enable A_TRUE or A_FALSE 2674 * @return SW_OK or error code 2675 */ 2676HSL_LOCAL sw_error_t 2677dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, 2678 a_bool_t enable) 2679{ 2680 sw_error_t rv; 2681 2682 HSL_API_LOCK; 2683 rv = _dess_port_flowctrl_set (dev_id, port_id, enable); 2684 HSL_API_UNLOCK; 2685 return rv; 2686} 2687 2688/** 2689 * @brief Set flow control(rx/tx/bp) threshold on a particular port. 2690 * @param[in] dev_id device id 2691 * @param[in] port_id port id 2692 * @param[in] on on threshold 2693 * @param[in] off off threshold 2694 * @return SW_OK or error code 2695 */ 2696HSL_LOCAL sw_error_t 2697dess_port_flowctrl_thresh_set (a_uint32_t dev_id, fal_port_t port_id, 2698 a_uint8_t on, a_uint8_t off) 2699{ 2700 sw_error_t rv; 2701 2702 HSL_API_LOCK; 2703 rv = _dess_port_flowctrl_thresh_set (dev_id, port_id, on, off); 2704 HSL_API_UNLOCK; 2705 return rv; 2706} 2707 2708/** 2709 * @brief Get flow control status on a particular port. 2710 * @param[in] dev_id device id 2711 * @param[in] port_id port id 2712 * @param[out] enable A_TRUE or A_FALSE 2713 * @return SW_OK or error code 2714 */ 2715HSL_LOCAL sw_error_t 2716dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id, 2717 a_bool_t * enable) 2718{ 2719 sw_error_t rv; 2720 2721 HSL_API_LOCK; 2722 rv = _dess_port_flowctrl_get (dev_id, port_id, enable); 2723 HSL_API_UNLOCK; 2724 return rv; 2725} 2726 2727/** 2728 * @brief Set flow control force mode on a particular port. 2729 * @param[in] dev_id device id 2730 * @param[in] port_id port id 2731 * @param[out] enable A_TRUE or A_FALSE 2732 * @return SW_OK or error code 2733 */ 2734HSL_LOCAL sw_error_t 2735dess_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, 2736 a_bool_t enable) 2737{ 2738 sw_error_t rv; 2739 2740 HSL_API_LOCK; 2741 rv = _dess_port_flowctrl_forcemode_set (dev_id, port_id, enable); 2742 HSL_API_UNLOCK; 2743 return rv; 2744} 2745 2746/** 2747 * @brief Get flow control force mode on a particular port. 2748 * @param[in] dev_id device id 2749 * @param[in] port_id port id 2750 * @param[out] enable A_TRUE or A_FALSE 2751 * @return SW_OK or error code 2752 */ 2753HSL_LOCAL sw_error_t 2754dess_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, 2755 a_bool_t * enable) 2756{ 2757 sw_error_t rv; 2758 2759 HSL_API_LOCK; 2760 rv = _dess_port_flowctrl_forcemode_get (dev_id, port_id, enable); 2761 HSL_API_UNLOCK; 2762 return rv; 2763} 2764 2765/** 2766 * @brief Set powersaving status on a particular port. 2767 * @param[in] dev_id device id 2768 * @param[in] port_id port id 2769 * @param[out] enable A_TRUE or A_FALSE 2770 * @return SW_OK or error code 2771 */ 2772HSL_LOCAL sw_error_t 2773dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, 2774 a_bool_t enable) 2775{ 2776 sw_error_t rv; 2777 2778 HSL_API_LOCK; 2779 rv = _dess_port_powersave_set (dev_id, port_id, enable); 2780 HSL_API_UNLOCK; 2781 return rv; 2782} 2783 2784/** 2785 * @brief Get powersaving status on a particular port. 2786 * @param[in] dev_id device id 2787 * @param[in] port_id port id 2788 * @param[out] enable A_TRUE or A_FALSE 2789 * @return SW_OK or error code 2790 */ 2791HSL_LOCAL sw_error_t 2792dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, 2793 a_bool_t * enable) 2794{ 2795 sw_error_t rv; 2796 2797 HSL_API_LOCK; 2798 rv = _dess_port_powersave_get (dev_id, port_id, enable); 2799 HSL_API_UNLOCK; 2800 return rv; 2801} 2802 2803/** 2804 * @brief Set hibernate status on a particular port. 2805 * @param[in] dev_id device id 2806 * @param[in] port_id port id 2807 * @param[out] enable A_TRUE or A_FALSE 2808 * @return SW_OK or error code 2809 */ 2810HSL_LOCAL sw_error_t 2811dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, 2812 a_bool_t enable) 2813{ 2814 sw_error_t rv; 2815 2816 HSL_API_LOCK; 2817 rv = _dess_port_hibernate_set (dev_id, port_id, enable); 2818 HSL_API_UNLOCK; 2819 return rv; 2820} 2821 2822/** 2823 * @brief Get hibernate status on a particular port. 2824 * @param[in] dev_id device id 2825 * @param[in] port_id port id 2826 * @param[out] enable A_TRUE or A_FALSE 2827 * @return SW_OK or error code 2828 */ 2829HSL_LOCAL sw_error_t 2830dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, 2831 a_bool_t * enable) 2832{ 2833 sw_error_t rv; 2834 2835 HSL_API_LOCK; 2836 rv = _dess_port_hibernate_get (dev_id, port_id, enable); 2837 HSL_API_UNLOCK; 2838 return rv; 2839} 2840 2841/** 2842 * @brief Run cable diagnostic test on a particular port. 2843 * @param[in] dev_id device id 2844 * @param[in] port_id port id 2845 * @param[in] mdi_pair mdi pair id 2846 * @param[out] cable_status cable status 2847 * @param[out] cable_len cable len 2848 * @return SW_OK or error code 2849 */ 2850HSL_LOCAL sw_error_t 2851dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, 2852 fal_cable_status_t * cable_status, a_uint32_t * cable_len) 2853{ 2854 sw_error_t rv; 2855 2856 HSL_API_LOCK; 2857 rv = _dess_port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len); 2858 HSL_API_UNLOCK; 2859 return rv; 2860} 2861 2862/** 2863 * @brief Set status of Atheros header packets parsed on a particular port. 2864 * @param[in] dev_id device id 2865 * @param[in] port_id port id 2866 * @param[in] enable A_TRUE or A_FALSE 2867 * @return SW_OK or error code 2868 */ 2869HSL_LOCAL sw_error_t 2870dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, 2871 fal_port_header_mode_t mode) 2872{ 2873 sw_error_t rv; 2874 2875 HSL_API_LOCK; 2876 rv = _dess_port_rxhdr_mode_set (dev_id, port_id, mode); 2877 HSL_API_UNLOCK; 2878 return rv; 2879} 2880 2881/** 2882 * @brief Get status of Atheros header packets parsed on a particular port. 2883 * @param[in] dev_id device id 2884 * @param[in] port_id port id 2885 * @param[out] enable A_TRUE or A_FALSE 2886 * @return SW_OK or error code 2887 */ 2888HSL_LOCAL sw_error_t 2889dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, 2890 fal_port_header_mode_t * mode) 2891{ 2892 sw_error_t rv; 2893 2894 HSL_API_LOCK; 2895 rv = _dess_port_rxhdr_mode_get (dev_id, port_id, mode); 2896 HSL_API_UNLOCK; 2897 return rv; 2898} 2899 2900/** 2901 * @brief Set status of Atheros header packets parsed on a particular port. 2902 * @param[in] dev_id device id 2903 * @param[in] port_id port id 2904 * @param[in] enable A_TRUE or A_FALSE 2905 * @return SW_OK or error code 2906 */ 2907HSL_LOCAL sw_error_t 2908dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, 2909 fal_port_header_mode_t mode) 2910{ 2911 sw_error_t rv; 2912 2913 HSL_API_LOCK; 2914 rv = _dess_port_txhdr_mode_set (dev_id, port_id, mode); 2915 HSL_API_UNLOCK; 2916 return rv; 2917} 2918 2919/** 2920 * @brief Get status of Atheros header packets parsed on a particular port. 2921 * @param[in] dev_id device id 2922 * @param[in] port_id port id 2923 * @param[out] enable A_TRUE or A_FALSE 2924 * @return SW_OK or error code 2925 */ 2926HSL_LOCAL sw_error_t 2927dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, 2928 fal_port_header_mode_t * mode) 2929{ 2930 sw_error_t rv; 2931 2932 HSL_API_LOCK; 2933 rv = _dess_port_txhdr_mode_get (dev_id, port_id, mode); 2934 HSL_API_UNLOCK; 2935 return rv; 2936} 2937 2938/** 2939 * @brief Set status of Atheros header type value on a particular device. 2940 * @param[in] dev_id device id 2941 * @param[in] enable A_TRUE or A_FALSE 2942 * @param[in] type header type value 2943 * @return SW_OK or error code 2944 */ 2945HSL_LOCAL sw_error_t 2946dess_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) 2947{ 2948 sw_error_t rv; 2949 HSL_API_LOCK; 2950 rv = _dess_header_type_set (dev_id, enable, type); 2951 HSL_API_UNLOCK; 2952 return rv; 2953} 2954 2955/** 2956 * @brief Get status of Atheros header type value on a particular device. 2957 * @param[in] dev_id device id 2958 * @param[out] enable A_TRUE or A_FALSE 2959 * @param[out] type header type value 2960 * @return SW_OK or error code 2961 */ 2962HSL_LOCAL sw_error_t 2963dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) 2964{ 2965 sw_error_t rv; 2966 2967 HSL_API_LOCK; 2968 rv = _dess_header_type_get (dev_id, enable, type); 2969 HSL_API_UNLOCK; 2970 return rv; 2971} 2972 2973/** 2974 * @brief Set status of txmac on a particular port. 2975 * @param[in] dev_id device id 2976 * @param[in] port_id port id 2977 * @param[in] enable A_TRUE or A_FALSE 2978 * @return SW_OK or error code 2979 */ 2980HSL_LOCAL sw_error_t 2981dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id, 2982 a_bool_t enable) 2983{ 2984 sw_error_t rv; 2985 HSL_API_LOCK; 2986 rv = _dess_port_txmac_status_set (dev_id, port_id, enable); 2987 HSL_API_UNLOCK; 2988 return rv; 2989} 2990 2991/** 2992 * @brief Get status of txmac on a particular port. 2993 * @param[in] dev_id device id 2994 * @param[in] port_id port id 2995 * @param[out] enable A_TRUE or A_FALSE 2996 * @return SW_OK or error code 2997 */ 2998HSL_LOCAL sw_error_t 2999dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id, 3000 a_bool_t * enable) 3001{ 3002 sw_error_t rv; 3003 3004 HSL_API_LOCK; 3005 rv = _dess_port_txmac_status_get (dev_id, port_id, enable); 3006 HSL_API_UNLOCK; 3007 return rv; 3008} 3009 3010/** 3011 * @brief Set status of rxmac on a particular port. 3012 * @param[in] dev_id device id 3013 * @param[in] port_id port id 3014 * @param[in] enable A_TRUE or A_FALSE 3015 * @return SW_OK or error code 3016 */ 3017HSL_LOCAL sw_error_t 3018dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id, 3019 a_bool_t enable) 3020{ 3021 sw_error_t rv; 3022 HSL_API_LOCK; 3023 rv = _dess_port_rxmac_status_set (dev_id, port_id, enable); 3024 HSL_API_UNLOCK; 3025 return rv; 3026} 3027 3028/** 3029 * @brief Get status of rxmac on a particular port. 3030 * @param[in] dev_id device id 3031 * @param[in] port_id port id 3032 * @param[out] enable A_TRUE or A_FALSE 3033 * @return SW_OK or error code 3034 */ 3035HSL_LOCAL sw_error_t 3036dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id, 3037 a_bool_t * enable) 3038{ 3039 sw_error_t rv; 3040 3041 HSL_API_LOCK; 3042 rv = _dess_port_rxmac_status_get (dev_id, port_id, enable); 3043 HSL_API_UNLOCK; 3044 return rv; 3045} 3046 3047/** 3048 * @brief Set status of tx flow control on a particular port. 3049 * @param[in] dev_id device id 3050 * @param[in] port_id port id 3051 * @param[in] enable A_TRUE or A_FALSE 3052 * @return SW_OK or error code 3053 */ 3054HSL_LOCAL sw_error_t 3055dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id, 3056 a_bool_t enable) 3057{ 3058 sw_error_t rv; 3059 HSL_API_LOCK; 3060 rv = _dess_port_txfc_status_set (dev_id, port_id, enable); 3061 HSL_API_UNLOCK; 3062 return rv; 3063} 3064 3065/** 3066 * @brief Get status of tx flow control on a particular port. 3067 * @param[in] dev_id device id 3068 * @param[in] port_id port id 3069 * @param[out] enable A_TRUE or A_FALSE 3070 * @return SW_OK or error code 3071 */ 3072HSL_LOCAL sw_error_t 3073dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id, 3074 a_bool_t * enable) 3075{ 3076 sw_error_t rv; 3077 3078 HSL_API_LOCK; 3079 rv = _dess_port_txfc_status_get (dev_id, port_id, enable); 3080 HSL_API_UNLOCK; 3081 return rv; 3082} 3083 3084/** 3085 * @brief Set status of rx flow control on a particular port. 3086 * @param[in] dev_id device id 3087 * @param[in] port_id port id 3088 * @param[in] enable A_TRUE or A_FALSE 3089 * @return SW_OK or error code 3090 */ 3091HSL_LOCAL sw_error_t 3092dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id, 3093 a_bool_t enable) 3094{ 3095 sw_error_t rv; 3096 HSL_API_LOCK; 3097 rv = _dess_port_rxfc_status_set (dev_id, port_id, enable); 3098 HSL_API_UNLOCK; 3099 return rv; 3100} 3101 3102/** 3103 * @brief Set status of rx flow control on a particular port. 3104 * @param[in] dev_id device id 3105 * @param[in] port_id port id 3106 * @param[out] enable A_TRUE or A_FALSE 3107 * @return SW_OK or error code 3108 */ 3109HSL_LOCAL sw_error_t 3110dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id, 3111 a_bool_t * enable) 3112{ 3113 sw_error_t rv; 3114 3115 HSL_API_LOCK; 3116 rv = _dess_port_rxfc_status_get (dev_id, port_id, enable); 3117 HSL_API_UNLOCK; 3118 return rv; 3119} 3120 3121/** 3122 * @brief Set status of back pressure on a particular port. 3123 * @param[in] dev_id device id 3124 * @param[in] port_id port id 3125 * @param[in] enable A_TRUE or A_FALSE 3126 * @return SW_OK or error code 3127 */ 3128HSL_LOCAL sw_error_t 3129dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id, 3130 a_bool_t enable) 3131{ 3132 sw_error_t rv; 3133 HSL_API_LOCK; 3134 rv = _dess_port_bp_status_set (dev_id, port_id, enable); 3135 HSL_API_UNLOCK; 3136 return rv; 3137} 3138 3139/** 3140 * @brief Set status of back pressure on a particular port. 3141 * @param[in] dev_id device id 3142 * @param[in] port_id port id 3143 * @param[out] enable A_TRUE or A_FALSE 3144 * @return SW_OK or error code 3145 */ 3146HSL_LOCAL sw_error_t 3147dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id, 3148 a_bool_t * enable) 3149{ 3150 sw_error_t rv; 3151 3152 HSL_API_LOCK; 3153 rv = _dess_port_bp_status_get (dev_id, port_id, enable); 3154 HSL_API_UNLOCK; 3155 return rv; 3156} 3157 3158/** 3159 * @brief Set link force mode on a particular port. 3160 * @param[in] dev_id device id 3161 * @param[in] port_id port id 3162 * @param[in] enable A_TRUE or A_FALSE 3163 * @return SW_OK or error code 3164 */ 3165HSL_LOCAL sw_error_t 3166dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, 3167 a_bool_t enable) 3168{ 3169 sw_error_t rv; 3170 HSL_API_LOCK; 3171 rv = _dess_port_link_forcemode_set (dev_id, port_id, enable); 3172 HSL_API_UNLOCK; 3173 return rv; 3174} 3175 3176/** 3177 * @brief Get link force mode on a particular port. 3178 * @param[in] dev_id device id 3179 * @param[in] port_id port id 3180 * @param[out] enable A_TRUE or A_FALSE 3181 * @return SW_OK or error code 3182 */ 3183HSL_LOCAL sw_error_t 3184dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, 3185 a_bool_t * enable) 3186{ 3187 sw_error_t rv; 3188 3189 HSL_API_LOCK; 3190 rv = _dess_port_link_forcemode_get (dev_id, port_id, enable); 3191 HSL_API_UNLOCK; 3192 return rv; 3193} 3194 3195/** 3196 * @brief Get link status on particular port. 3197 * @param[in] dev_id device id 3198 * @param[in] port_id port id 3199 * @param[out] status link status up (A_TRUE) or down (A_FALSE) 3200 * @return SW_OK or error code 3201 */ 3202HSL_LOCAL sw_error_t 3203dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, 3204 a_bool_t * status) 3205{ 3206 sw_error_t rv; 3207 3208 HSL_API_LOCK; 3209 rv = _dess_port_link_status_get (dev_id, port_id, status); 3210 HSL_API_UNLOCK; 3211 return rv; 3212} 3213 3214/** 3215 * @brief Get link status on all ports. 3216 * @param[in] dev_id device id 3217 * @param[out] status link status bitmap and bit 0 for port 0, bi 1 for port 1, ..., etc. 3218 * @return SW_OK or error code 3219 */ 3220HSL_LOCAL sw_error_t 3221dess_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) 3222{ 3223 sw_error_t rv; 3224 3225 HSL_API_LOCK; 3226 rv = _dess_ports_link_status_get(dev_id, status); 3227 HSL_API_UNLOCK; 3228 return rv; 3229} 3230 3231/** 3232 * @brief Set mac loop back on a particular port. 3233 * @param[in] dev_id device id 3234 * @param[in] port_id port id 3235 * @param[in] enable A_TRUE or A_FALSE 3236 * @return SW_OK or error code 3237 */ 3238HSL_LOCAL sw_error_t 3239dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id, 3240 a_bool_t enable) 3241{ 3242 sw_error_t rv; 3243 HSL_API_LOCK; 3244 rv = _dess_port_mac_loopback_set (dev_id, port_id, enable); 3245 HSL_API_UNLOCK; 3246 return rv; 3247} 3248 3249/** 3250 * @brief Get mac loop back on a particular port. 3251 * @param[in] dev_id device id 3252 * @param[in] port_id port id 3253 * @param[out] enable A_TRUE or A_FALSE 3254 * @return SW_OK or error code 3255 */ 3256HSL_LOCAL sw_error_t 3257dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id, 3258 a_bool_t * enable) 3259{ 3260 sw_error_t rv; 3261 3262 HSL_API_LOCK; 3263 rv = _dess_port_mac_loopback_get (dev_id, port_id, enable); 3264 HSL_API_UNLOCK; 3265 return rv; 3266} 3267 3268/** 3269 * @brief Set flow congestion drop on a particular port queue. 3270 * @param[in] dev_id device id 3271 * @param[in] port_id port id 3272 * @param[in] queue_id queue id 3273 * @param[in] enable A_TRUE or A_FALSE 3274 * @return SW_OK or error code 3275 */ 3276HSL_LOCAL sw_error_t 3277dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id, 3278 a_uint32_t queue_id, a_bool_t enable) 3279{ 3280 sw_error_t rv; 3281 HSL_API_LOCK; 3282 rv = _dess_port_congestion_drop_set (dev_id, port_id, queue_id, enable); 3283 HSL_API_UNLOCK; 3284 return rv; 3285} 3286 3287/** 3288 * @brief Set flow congestion drop on a particular port. 3289 * @param[in] dev_id device id 3290 * @param[in] port_id port id 3291 * @param[in] queue_id queue id 3292 * @param[out] enable A_TRUE or A_FALSE 3293 * @return SW_OK or error code 3294 */ 3295HSL_LOCAL sw_error_t 3296dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id, 3297 a_uint32_t queue_id, a_bool_t * enable) 3298{ 3299 sw_error_t rv; 3300 3301 HSL_API_LOCK; 3302 rv = _dess_port_congestion_drop_get (dev_id, port_id, queue_id, enable); 3303 HSL_API_UNLOCK; 3304 return rv; 3305} 3306 3307/** 3308 * @brief Set flow ctrl thres on a particular DMA ring. 3309 * @param[in] dev_id device id 3310 * @param[in] ring_id ring id 3311 * @param[in] on_thres on_thres 3312 * @param[in] off_thres off_thres 3313 * @return SW_OK or error code 3314 */ 3315HSL_LOCAL sw_error_t 3316dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id, 3317 a_uint8_t on_thres, a_uint8_t off_thres) 3318{ 3319 sw_error_t rv; 3320 HSL_API_LOCK; 3321 rv = _dess_ring_flow_ctrl_thres_set (dev_id, ring_id, on_thres, off_thres); 3322 HSL_API_UNLOCK; 3323 return rv; 3324} 3325 3326/** 3327 * @brief Set flow ctrl thres on a particular DMA ring. 3328 * @param[in] dev_id device id 3329 * @param[in] ring_id ring id 3330 * @param[out] on_thres on_thres 3331 * @param[out] off_thres off_thres 3332 * @return SW_OK or error code 3333 */ 3334HSL_LOCAL sw_error_t 3335dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id, 3336 a_uint8_t * on_thres, a_uint8_t * off_thres) 3337{ 3338 sw_error_t rv; 3339 3340 HSL_API_LOCK; 3341 rv = _dess_ring_flow_ctrl_thres_get (dev_id, ring_id, on_thres, off_thres); 3342 HSL_API_UNLOCK; 3343 return rv; 3344} 3345 3346/** 3347 * @brief Set 802.3az status on a particular port. 3348 * @param[in] dev_id device id 3349 * @param[in] port_id port id 3350 * @param[out] enable A_TRUE or A_FALSE 3351 * @return SW_OK or error code 3352 */ 3353HSL_LOCAL sw_error_t 3354dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 3355{ 3356 sw_error_t rv; 3357 3358 HSL_API_LOCK; 3359 rv = _dess_port_8023az_set (dev_id, port_id, enable); 3360 HSL_API_UNLOCK; 3361 return rv; 3362} 3363 3364/** 3365 * @brief Get 8023az status on a particular port. 3366 * @param[in] dev_id device id 3367 * @param[in] port_id port id 3368 * @param[out] enable A_TRUE or A_FALSE 3369 * @return SW_OK or error code 3370 */ 3371HSL_LOCAL sw_error_t 3372dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, 3373 a_bool_t * enable) 3374{ 3375 sw_error_t rv; 3376 3377 HSL_API_LOCK; 3378 rv = _dess_port_8023az_get (dev_id, port_id, enable); 3379 HSL_API_UNLOCK; 3380 return rv; 3381} 3382 3383/** 3384 * @brief Set mdix on a particular port. 3385 * @param[in] dev_id device id 3386 * @param[in] port_id port id 3387 * @param[out] mode 3388 * @return SW_OK or error code 3389 */ 3390HSL_LOCAL sw_error_t 3391dess_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id, 3392 fal_port_mdix_mode_t mode) 3393{ 3394 sw_error_t rv; 3395 3396 HSL_API_LOCK; 3397 rv = _dess_port_mdix_set (dev_id, phy_id, mode); 3398 HSL_API_UNLOCK; 3399 return rv; 3400} 3401 3402/** 3403 * @brief Get mdix configuration on a particular port. 3404 * @param[in] dev_id device id 3405 * @param[in] port_id port id 3406 * @param[out] mode 3407 * @return SW_OK or error code 3408 */ 3409 3410HSL_LOCAL sw_error_t 3411dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, 3412 fal_port_mdix_mode_t * mode) 3413{ 3414 sw_error_t rv; 3415 3416 HSL_API_LOCK; 3417 rv = _dess_port_mdix_get (dev_id, port_id, mode); 3418 HSL_API_UNLOCK; 3419 return rv; 3420} 3421 3422/** 3423 * @brief Get mdix status on a particular port. 3424 * @param[in] dev_id device id 3425 * @param[in] port_id port id 3426 * @param[out] mode 3427 * @return SW_OK or error code 3428 */ 3429 3430HSL_LOCAL sw_error_t 3431dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, 3432 fal_port_mdix_status_t * mode) 3433{ 3434 sw_error_t rv; 3435 3436 HSL_API_LOCK; 3437 rv = _dess_port_mdix_status_get (dev_id, port_id, mode); 3438 HSL_API_UNLOCK; 3439 return rv; 3440} 3441 3442/** 3443 * @brief Set combo prefer medium on a particular port. 3444 * @param[in] dev_id device id 3445 * @param[in] port_id port id 3446 * @param[out] phy_medium [fiber or copper] 3447 * @return SW_OK or error code 3448 */ 3449HSL_LOCAL sw_error_t 3450dess_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id, 3451 fal_port_medium_t phy_medium) 3452{ 3453 sw_error_t rv; 3454 3455 HSL_API_LOCK; 3456 rv = _dess_port_combo_prefer_medium_set (dev_id, phy_id, phy_medium); 3457 HSL_API_UNLOCK; 3458 return rv; 3459} 3460 3461/** 3462 * @brief Get combo prefer medium on a particular port. 3463 * @param[in] dev_id device id 3464 * @param[in] port_id port id 3465 * @param[out] phy_medium [fiber or copper] 3466 * @return SW_OK or error code 3467 */ 3468HSL_LOCAL sw_error_t 3469dess_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id, 3470 fal_port_medium_t * phy_medium) 3471{ 3472 sw_error_t rv; 3473 3474 HSL_API_LOCK; 3475 rv = _dess_port_combo_prefer_medium_get (dev_id, phy_id, phy_medium); 3476 HSL_API_UNLOCK; 3477 return rv; 3478} 3479 3480/** 3481 * @brief Get current combo medium status on a particular port. 3482 * @param[in] dev_id device id 3483 * @param[in] port_id port id 3484 * @param[out] phy_medium [fiber or copper] 3485 * @return SW_OK or error code 3486 */ 3487HSL_LOCAL sw_error_t 3488dess_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id, 3489 fal_port_medium_t * phy_medium) 3490{ 3491 sw_error_t rv; 3492 3493 HSL_API_LOCK; 3494 rv = _dess_port_combo_medium_status_get (dev_id, phy_id, phy_medium); 3495 HSL_API_UNLOCK; 3496 return rv; 3497} 3498 3499/** 3500 * @brief Set fiber mode on a particular port. 3501 * @param[in] dev_id device id 3502 * @param[in] port_id port id 3503 * @param[out] fiber mode [1000bx or 100fx] 3504 * @return SW_OK or error code 3505 */ 3506HSL_LOCAL sw_error_t 3507dess_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id, 3508 fal_port_fiber_mode_t fiber_mode) 3509{ 3510 sw_error_t rv; 3511 3512 HSL_API_LOCK; 3513 rv = _dess_port_combo_fiber_mode_set (dev_id, phy_id, fiber_mode); 3514 HSL_API_UNLOCK; 3515 return rv; 3516} 3517 3518/** 3519 * @brief Get fiber mode on a particular port. 3520 * @param[in] dev_id device id 3521 * @param[in] port_id port id 3522 * @param[out] fiber mode [1000bx or 100fx] 3523 * @return SW_OK or error code 3524 */ 3525HSL_LOCAL sw_error_t 3526dess_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id, 3527 fal_port_fiber_mode_t * fiber_mode) 3528{ 3529 sw_error_t rv; 3530 3531 HSL_API_LOCK; 3532 rv = _dess_port_combo_fiber_mode_get (dev_id, phy_id, fiber_mode); 3533 HSL_API_UNLOCK; 3534 return rv; 3535} 3536 3537/** 3538 * @brief Set phy local loop back on a particular port. 3539 * @param[in] dev_id device id 3540 * @param[in] port_id port id 3541 * @param[in] enable A_TRUE or A_FALSE 3542 * @return SW_OK or error code 3543 */ 3544HSL_LOCAL sw_error_t 3545dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, 3546 a_bool_t enable) 3547{ 3548 sw_error_t rv; 3549 HSL_API_LOCK; 3550 rv = _dess_port_local_loopback_set (dev_id, port_id, enable); 3551 HSL_API_UNLOCK; 3552 return rv; 3553} 3554 3555/** 3556 * @brief Get phy local loop back on a particular port. 3557 * @param[in] dev_id device id 3558 * @param[in] port_id port id 3559 * @param[out] enable A_TRUE or A_FALSE 3560 * @return SW_OK or error code 3561 */ 3562HSL_LOCAL sw_error_t 3563dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, 3564 a_bool_t * enable) 3565{ 3566 sw_error_t rv; 3567 3568 HSL_API_LOCK; 3569 rv = _dess_port_local_loopback_get (dev_id, port_id, enable); 3570 HSL_API_UNLOCK; 3571 return rv; 3572} 3573 3574/** 3575 * @brief Set phy remote loop back on a particular port. 3576 * @param[in] dev_id device id 3577 * @param[in] port_id port id 3578 * @param[in] enable A_TRUE or A_FALSE 3579 * @return SW_OK or error code 3580 */ 3581HSL_LOCAL sw_error_t 3582dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, 3583 a_bool_t enable) 3584{ 3585 sw_error_t rv; 3586 HSL_API_LOCK; 3587 rv = _dess_port_remote_loopback_set (dev_id, port_id, enable); 3588 HSL_API_UNLOCK; 3589 return rv; 3590} 3591 3592/** 3593 * @brief Get phy remote loop back on a particular port. 3594 * @param[in] dev_id device id 3595 * @param[in] port_id port id 3596 * @param[out] enable A_TRUE or A_FALSE 3597 * @return SW_OK or error code 3598 */ 3599HSL_LOCAL sw_error_t 3600dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, 3601 a_bool_t * enable) 3602{ 3603 sw_error_t rv; 3604 3605 HSL_API_LOCK; 3606 rv = _dess_port_remote_loopback_get (dev_id, port_id, enable); 3607 HSL_API_UNLOCK; 3608 return rv; 3609} 3610 3611/** 3612 * @brief software reset on a particular port. 3613 * @param[in] dev_id device id 3614 * @param[in] port_id port id 3615 * @param[in] 3616 * @return SW_OK or error code 3617 */ 3618HSL_LOCAL sw_error_t 3619dess_port_reset (a_uint32_t dev_id, fal_port_t port_id) 3620{ 3621 sw_error_t rv; 3622 HSL_API_LOCK; 3623 rv = _dess_port_reset (dev_id, port_id); 3624 HSL_API_UNLOCK; 3625 return rv; 3626} 3627 3628/** 3629 * @brief phy power off on a particular port. 3630 * @param[in] dev_id device id 3631 * @param[in] port_id port id 3632 * @param[in] 3633 * @return SW_OK or error code 3634 */ 3635HSL_LOCAL sw_error_t 3636dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id) 3637{ 3638 sw_error_t rv; 3639 HSL_API_LOCK; 3640 rv = _dess_port_power_off (dev_id, port_id); 3641 HSL_API_UNLOCK; 3642 return rv; 3643} 3644 3645/** 3646 * @brief phy power on on a particular port. 3647 * @param[in] dev_id device id 3648 * @param[in] port_id port id 3649 * @param[in] 3650 * @return SW_OK or error code 3651 */ 3652HSL_LOCAL sw_error_t 3653dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id) 3654{ 3655 sw_error_t rv; 3656 HSL_API_LOCK; 3657 rv = _dess_port_power_on (dev_id, port_id); 3658 HSL_API_UNLOCK; 3659 return rv; 3660} 3661 3662/** 3663 * @brief Set phy wol enable on a particular port. 3664 * @param[in] dev_id device id 3665 * @param[in] port_id port id 3666 * @param[in] enable A_TRUE or A_FALSE 3667 * @return SW_OK or error code 3668 */ 3669HSL_LOCAL sw_error_t 3670dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, 3671 a_bool_t enable) 3672{ 3673 sw_error_t rv; 3674 HSL_API_LOCK; 3675 rv = _dess_port_wol_status_set (dev_id, port_id, enable); 3676 HSL_API_UNLOCK; 3677 return rv; 3678} 3679 3680/** 3681 * @brief Get phy wol status on a particular port. 3682 * @param[in] dev_id device id 3683 * @param[in] port_id port id 3684 * @param[out] enable A_TRUE or A_FALSE 3685 * @return SW_OK or error code 3686 */ 3687HSL_LOCAL sw_error_t 3688dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, 3689 a_bool_t * enable) 3690{ 3691 sw_error_t rv; 3692 3693 HSL_API_LOCK; 3694 rv = _dess_port_wol_status_get (dev_id, port_id, enable); 3695 HSL_API_UNLOCK; 3696 return rv; 3697} 3698 3699/** 3700 * @brief Get phy id on a particular port. 3701 * @param[in] dev_id device id 3702 * @param[in] port_id port id 3703 * @param[out] org_id and rev_id 3704 * @return SW_OK or error code 3705 */ 3706HSL_LOCAL sw_error_t 3707dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, 3708 a_uint16_t * org_id, a_uint16_t * rev_id) 3709{ 3710 sw_error_t rv; 3711 3712 HSL_API_LOCK; 3713 rv = _dess_port_phy_id_get (dev_id, port_id, org_id,rev_id); 3714 HSL_API_UNLOCK; 3715 return rv; 3716} 3717 3718/** 3719 * @brief Set phy magic frame mac on a particular port. 3720 * @param[in] dev_id device id 3721 * @param[in] port_id port id 3722 * @param[in] mac address 3723 * @return SW_OK or error code 3724 */ 3725HSL_LOCAL sw_error_t 3726dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, 3727 fal_mac_addr_t * mac) 3728{ 3729 sw_error_t rv; 3730 HSL_API_LOCK; 3731 rv = _dess_port_magic_frame_mac_set (dev_id, port_id, mac); 3732 HSL_API_UNLOCK; 3733 return rv; 3734} 3735 3736/** 3737 * @brief Get phy magic frame mac on a particular port. 3738 * @param[in] dev_id device id 3739 * @param[in] port_id port id 3740 * @param[out] mac address 3741 * @return SW_OK or error code 3742 */ 3743HSL_LOCAL sw_error_t 3744dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, 3745 fal_mac_addr_t * mac) 3746{ 3747 sw_error_t rv; 3748 HSL_API_LOCK; 3749 rv = _dess_port_magic_frame_mac_get (dev_id, port_id, mac); 3750 HSL_API_UNLOCK; 3751 return rv; 3752} 3753 3754 3755/** 3756 * @brief Set phy interface mode. 3757 * @param[in] dev_id device id 3758 * @param[in] port_id port id 3759 * @param[in] interface mode.. 3760 * @return SW_OK or error code 3761 */ 3762HSL_LOCAL sw_error_t 3763dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, 3764 fal_port_interface_mode_t mode) 3765{ 3766 sw_error_t rv; 3767 HSL_API_LOCK; 3768 rv = _dess_port_interface_mode_set (dev_id, port_id, mode); 3769 HSL_API_UNLOCK; 3770 return rv; 3771} 3772 3773/** 3774 * @brief Set phy interface mode. 3775 * @param[in] dev_id device id 3776 * @param[in] port_id port id 3777 * @param[out] interface mode.. 3778 * @return SW_OK or error code 3779 */ 3780HSL_LOCAL sw_error_t 3781dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, 3782 fal_port_interface_mode_t * mode) 3783{ 3784 sw_error_t rv; 3785 HSL_API_LOCK; 3786 rv = _dess_port_interface_mode_get (dev_id, port_id, mode); 3787 HSL_API_UNLOCK; 3788 return rv; 3789} 3790 3791/** 3792 * @brief Set phy interface mode status. 3793 * @param[in] dev_id device id 3794 * @param[in] port_id port id 3795 * @param[out] interface mode.. 3796 * @return SW_OK or error code 3797 */ 3798HSL_LOCAL sw_error_t 3799dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, 3800 fal_port_interface_mode_t * mode) 3801{ 3802 sw_error_t rv; 3803 HSL_API_LOCK; 3804 rv = _dess_port_interface_mode_status_get (dev_id, port_id, mode); 3805 HSL_API_UNLOCK; 3806 return rv; 3807} 3808 3809/** 3810 * @brief Set counter status on a particular port. 3811 * @param[in] dev_id device id 3812 * @param[in] port_id port id 3813 * @param[out] enable A_TRUE or A_FALSE 3814 * @return SW_OK or error code 3815 */ 3816HSL_LOCAL sw_error_t 3817dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) 3818{ 3819 sw_error_t rv; 3820 3821 HSL_API_LOCK; 3822 rv = _dess_port_counter_set (dev_id, port_id, enable); 3823 HSL_API_UNLOCK; 3824 return rv; 3825} 3826 3827/** 3828 * @brief Get counter status on a particular port. 3829 * @param[in] dev_id device id 3830 * @param[in] port_id port id 3831 * @param[out] enable A_TRUE or A_FALSE 3832 * @return SW_OK or error code 3833 */ 3834HSL_LOCAL sw_error_t 3835dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, 3836 a_bool_t * enable) 3837{ 3838 sw_error_t rv; 3839 3840 HSL_API_LOCK; 3841 rv = _dess_port_counter_get (dev_id, port_id, enable); 3842 HSL_API_UNLOCK; 3843 return rv; 3844} 3845 3846/** 3847 * @brief Get counter statistics on a particular port. 3848 * @param[in] dev_id device id 3849 * @param[in] port_id port id 3850 * @param[out] frame counter statistics 3851 * @return SW_OK or error code 3852 */ 3853HSL_LOCAL sw_error_t 3854dess_port_counter_show(a_uint32_t dev_id, fal_port_t port_id, 3855 fal_port_counter_info_t * counter_info) 3856{ 3857 sw_error_t rv; 3858 3859 HSL_API_LOCK; 3860 rv = _dess_port_counter_show (dev_id, port_id, counter_info); 3861 HSL_API_UNLOCK; 3862 return rv; 3863} 3864 3865sw_error_t 3866dess_port_ctrl_init (a_uint32_t dev_id) 3867{ 3868 HSL_DEV_ID_CHECK (dev_id); 3869 3870#ifndef HSL_STANDALONG 3871 { 3872 hsl_api_t *p_api; 3873 3874 SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); 3875 3876 p_api->port_duplex_get = dess_port_duplex_get; 3877 p_api->port_duplex_set = dess_port_duplex_set; 3878 p_api->port_speed_get = dess_port_speed_get; 3879 p_api->port_speed_set = dess_port_speed_set; 3880 p_api->port_autoneg_status_get = dess_port_autoneg_status_get; 3881 p_api->port_autoneg_enable = dess_port_autoneg_enable; 3882 p_api->port_autoneg_restart = dess_port_autoneg_restart; 3883 p_api->port_autoneg_adv_get = dess_port_autoneg_adv_get; 3884 p_api->port_autoneg_adv_set = dess_port_autoneg_adv_set; 3885 p_api->port_flowctrl_set = dess_port_flowctrl_set; 3886 p_api->port_flowctrl_get = dess_port_flowctrl_get; 3887 p_api->port_flowctrl_thresh_set = dess_port_flowctrl_thresh_set; 3888 p_api->port_flowctrl_forcemode_set = dess_port_flowctrl_forcemode_set; 3889 p_api->port_flowctrl_forcemode_get = dess_port_flowctrl_forcemode_get; 3890 p_api->port_powersave_set = dess_port_powersave_set; 3891 p_api->port_powersave_get = dess_port_powersave_get; 3892 p_api->port_hibernate_set = dess_port_hibernate_set; 3893 p_api->port_hibernate_get = dess_port_hibernate_get; 3894 p_api->port_cdt = dess_port_cdt; 3895 p_api->port_rxhdr_mode_set = dess_port_rxhdr_mode_set; 3896 p_api->port_rxhdr_mode_get = dess_port_rxhdr_mode_get; 3897 p_api->port_txhdr_mode_set = dess_port_txhdr_mode_set; 3898 p_api->port_txhdr_mode_get = dess_port_txhdr_mode_get; 3899 p_api->header_type_set = dess_header_type_set; 3900 p_api->header_type_get = dess_header_type_get; 3901 p_api->port_txmac_status_set = dess_port_txmac_status_set; 3902 p_api->port_txmac_status_get = dess_port_txmac_status_get; 3903 p_api->port_rxmac_status_set = dess_port_rxmac_status_set; 3904 p_api->port_rxmac_status_get = dess_port_rxmac_status_get; 3905 p_api->port_txfc_status_set = dess_port_txfc_status_set; 3906 p_api->port_txfc_status_get = dess_port_txfc_status_get; 3907 p_api->port_rxfc_status_set = dess_port_rxfc_status_set; 3908 p_api->port_rxfc_status_get = dess_port_rxfc_status_get; 3909 p_api->port_bp_status_set = dess_port_bp_status_set; 3910 p_api->port_bp_status_get = dess_port_bp_status_get; 3911 p_api->port_link_forcemode_set = dess_port_link_forcemode_set; 3912 p_api->port_link_forcemode_get = dess_port_link_forcemode_get; 3913 p_api->port_link_status_get = dess_port_link_status_get; 3914 p_api->ports_link_status_get = dess_ports_link_status_get; 3915 p_api->port_mac_loopback_set = dess_port_mac_loopback_set; 3916 p_api->port_mac_loopback_get = dess_port_mac_loopback_get; 3917 p_api->port_congestion_drop_set = dess_port_congestion_drop_set; 3918 p_api->port_congestion_drop_get = dess_port_congestion_drop_get; 3919 p_api->ring_flow_ctrl_thres_set = dess_ring_flow_ctrl_thres_set; 3920 p_api->ring_flow_ctrl_thres_get = dess_ring_flow_ctrl_thres_get; 3921 p_api->port_8023az_set = dess_port_8023az_set; 3922 p_api->port_8023az_get = dess_port_8023az_get; 3923 p_api->port_mdix_set = dess_port_mdix_set; 3924 p_api->port_mdix_get = dess_port_mdix_get; 3925 p_api->port_mdix_status_get = dess_port_mdix_status_get; 3926 p_api->port_combo_prefer_medium_set = dess_port_combo_prefer_medium_set; 3927 p_api->port_combo_prefer_medium_get = dess_port_combo_prefer_medium_get; 3928 p_api->port_combo_medium_status_get = dess_port_combo_medium_status_get; 3929 p_api->port_combo_fiber_mode_set = dess_port_combo_fiber_mode_set; 3930 p_api->port_combo_fiber_mode_get = dess_port_combo_fiber_mode_get; 3931 p_api->port_local_loopback_set = dess_port_local_loopback_set; 3932 p_api->port_local_loopback_get = dess_port_local_loopback_get; 3933 p_api->port_remote_loopback_set = dess_port_remote_loopback_set; 3934 p_api->port_remote_loopback_get = dess_port_remote_loopback_get; 3935 p_api->port_reset = dess_port_reset; 3936 p_api->port_power_off = dess_port_power_off; 3937 p_api->port_power_on = dess_port_power_on; 3938 p_api->port_phy_id_get = dess_port_phy_id_get; 3939 p_api->port_wol_status_set = dess_port_wol_status_set; 3940 p_api->port_wol_status_get = dess_port_wol_status_get; 3941 p_api->port_magic_frame_mac_set = dess_port_magic_frame_mac_set; 3942 p_api->port_magic_frame_mac_get = dess_port_magic_frame_mac_get; 3943 p_api->port_interface_mode_set = dess_port_interface_mode_set; 3944 p_api->port_interface_mode_get = dess_port_interface_mode_get; 3945 p_api->port_interface_mode_status_get = dess_port_interface_mode_status_get; 3946 p_api->port_counter_set = dess_port_counter_set; 3947 p_api->port_counter_get = dess_port_counter_get; 3948 p_api->port_counter_show = dess_port_counter_show; 3949 } 3950#endif 3951 3952 return SW_OK; 3953} 3954 3955/** 3956 * @} 3957 */ 3958