1/* 2 * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. 3 * Permission to use, copy, modify, and/or distribute this software for 4 * any purpose with or without fee is hereby granted, provided that the 5 * above copyright notice and this permission notice appear in all copies. 6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 13 */ 14 15 16 17#ifndef _F2_PHY_H_ 18#define _F2_PHY_H_ 19 20#ifdef __cplusplus 21extern "C" { 22#endif /* __cplusplus */ 23 24 /* Athena PHY Registers */ 25#define F2_PHY_CONTROL 0 26#define F2_PHY_STATUS 1 27#define F2_PHY_ID1 2 28#define F2_PHY_ID2 3 29#define F2_AUTONEG_ADVERT 4 30#define F2_LINK_PARTNER_ABILITY 5 31#define F2_AUTONEG_EXPANSION 6 32#define F2_NEXT_PAGE_TRANSMIT 7 33#define F2_LINK_PARTNER_NEXT_PAGE 8 34#define F2_1000BASET_CONTROL 9 35#define F2_1000BASET_STATUS 10 36#define F2_PHY_SPEC_CONTROL 16 37#define F2_PHY_SPEC_STATUS 17 38#define F2_PHY_CDT_CONTROL 22 39#define F2_PHY_CDT_STATUS 28 40#define F2_DEBUG_PORT_ADDRESS 29 41#define F2_DEBUG_PORT_DATA 30 42 43 /* Athena PHY Registers Field*/ 44 45 /* Control Register fields offset:0*/ 46 /* bits 6,13: 10=1000, 01=100, 00=10 */ 47#define F2_CTRL_SPEED_MSB 0x0040 48 49 /* Collision test enable */ 50#define F2_CTRL_COLL_TEST_ENABLE 0x0080 51 52 /* FDX =1, half duplex =0 */ 53#define F2_CTRL_FULL_DUPLEX 0x0100 54 55 /* Restart auto negotiation */ 56#define F2_CTRL_RESTART_AUTONEGOTIATION 0x0200 57 58 /* Isolate PHY from MII */ 59#define F2_CTRL_ISOLATE 0x0400 60 61 /* Power down */ 62#define F2_CTRL_POWER_DOWN 0x0800 63 64 /* Auto Neg Enable */ 65#define F2_CTRL_AUTONEGOTIATION_ENABLE 0x1000 66 67 /* bits 6,13: 10=1000, 01=100, 00=10 */ 68#define F2_CTRL_SPEED_LSB 0x2000 69 70 /* 0 = normal, 1 = loopback */ 71#define F2_CTRL_LOOPBACK 0x4000 72#define F2_CTRL_SOFTWARE_RESET 0x8000 73 74#define F2_CTRL_SPEED_MASK 0x2040 75#define F2_CTRL_SPEED_1000 0x0040 76#define F2_CTRL_SPEED_100 0x2000 77#define F2_CTRL_SPEED_10 0x0000 78 79#define F2_RESET_DONE(phy_control) \ 80 (((phy_control) & (F2_CTRL_SOFTWARE_RESET)) == 0) 81 82 /* Status Register fields offset:1*/ 83 /* Extended register capabilities */ 84#define F2_STATUS_EXTENDED_CAPS 0x0001 85 86 /* Jabber Detected */ 87#define F2_STATUS_JABBER_DETECT 0x0002 88 89 /* Link Status 1 = link */ 90#define F2_STATUS_LINK_STATUS_UP 0x0004 91 92 /* Auto Neg Capable */ 93#define F2_STATUS_AUTONEG_CAPS 0x0008 94 95 /* Remote Fault Detect */ 96#define F2_STATUS_REMOTE_FAULT 0x0010 97 98 /* Auto Neg Complete */ 99#define F2_STATUS_AUTO_NEG_DONE 0x0020 100 101 /* Preamble may be suppressed */ 102#define F2_STATUS_PREAMBLE_SUPPRESS 0x0040 103 104 /* Ext. status info in Reg 0x0F */ 105#define F2_STATUS_EXTENDED_STATUS 0x0100 106 107 /* 100T2 Half Duplex Capable */ 108#define F2_STATUS_100T2_HD_CAPS 0x0200 109 110 /* 100T2 Full Duplex Capable */ 111#define F2_STATUS_100T2_FD_CAPS 0x0400 112 113 /* 10T Half Duplex Capable */ 114#define F2_STATUS_10T_HD_CAPS 0x0800 115 116 /* 10T Full Duplex Capable */ 117#define F2_STATUS_10T_FD_CAPS 0x1000 118 119 /* 100X Half Duplex Capable */ 120#define F2_STATUS_100X_HD_CAPS 0x2000 121 122 /* 100X Full Duplex Capable */ 123#define F2_STATUS_100X_FD_CAPS 0x4000 124 125 /* 100T4 Capable */ 126#define F2_STATUS_100T4_CAPS 0x8000 127 128#define F2_AUTONEG_DONE(ip_phy_status) \ 129 (((ip_phy_status) & (F2_STATUS_AUTO_NEG_DONE)) == \ 130 (F2_STATUS_AUTO_NEG_DONE)) 131 132 /* PHY identifier1 offset:2*/ 133//Organizationally Unique Identifier bits 3:18 134 135 /* PHY identifier2 offset:3*/ 136//Organizationally Unique Identifier bits 19:24 137 138 /* Auto-Negotiation Advertisement register. offset:4*/ 139 /* indicates IEEE 802.3 CSMA/CD */ 140#define F2_ADVERTISE_SELECTOR_FIELD 0x0001 141 142 /* 10T Half Duplex Capable */ 143#define F2_ADVERTISE_10HALF 0x0020 144 145 /* 10T Full Duplex Capable */ 146#define F2_ADVERTISE_10FULL 0x0040 147 148 /* 100TX Half Duplex Capable */ 149#define F2_ADVERTISE_100HALF 0x0080 150 151 /* 100TX Full Duplex Capable */ 152#define F2_ADVERTISE_100FULL 0x0100 153 154 /* 100T4 Capable */ 155#define F2_ADVERTISE_100T4 0x0200 156 157 /* Pause operation desired */ 158#define F2_ADVERTISE_PAUSE 0x0400 159 160 /* Asymmetric Pause Direction bit */ 161#define F2_ADVERTISE_ASYM_PAUSE 0x0800 162 163 /* Remote Fault detected */ 164#define F2_ADVERTISE_REMOTE_FAULT 0x2000 165 166 /* Next Page ability supported */ 167#define F2_ADVERTISE_NEXT_PAGE 0x8000 168 169#define F2_ADVERTISE_ALL \ 170 (F2_ADVERTISE_10HALF | F2_ADVERTISE_10FULL | \ 171 F2_ADVERTISE_100HALF | F2_ADVERTISE_100FULL ) 172 173 /* Link Partner ability offset:5*/ 174 /* Same as advertise selector */ 175#define F2_LINK_SLCT 0x001f 176 177 /* Can do 10mbps half-duplex */ 178#define F2_LINK_10BASETX_HALF_DUPLEX 0x0020 179 180 /* Can do 10mbps full-duplex */ 181#define F2_LINK_10BASETX_FULL_DUPLEX 0x0040 182 183 /* Can do 100mbps half-duplex */ 184#define F2_LINK_100BASETX_HALF_DUPLEX 0x0080 185 186 /* Can do 100mbps full-duplex */ 187#define F2_LINK_100BASETX_FULL_DUPLEX 0x0100 188 189 /* 100BASE-T4 */ 190#define F2_LINK_100BASE4 0x0200 191 192 /* PAUSE */ 193#define F2_LINK_PAUSE 0x0400 194 195 /* Asymmetrical PAUSE */ 196#define F2_LINK_ASYPAUSE 0x0800 197 198 /* Link partner faulted */ 199#define F2_LINK_RFAULT 0x2000 200 201 /* Link partner acked us */ 202#define F2_LINK_LPACK 0x4000 203 204 /* Next page bit */ 205#define F2_LINK_NPAGE 0x8000 206 207 /* Auto-Negotiation Expansion Register offset:6 */ 208 209 /* Next Page Transmit Register offset:7 */ 210 211 /* Link partner Next Page Register offset:8*/ 212 213 /* 1000BASE-T Control Register offset:9*/ 214 /* Advertise 1000T HD capability */ 215#define F2_CTL_1000T_HD_CAPS 0x0100 216 217 /* Advertise 1000T FD capability */ 218#define F2_CTL_1000T_FD_CAPS 0x0200 219 220 /* 1=Repeater/switch device port 0=DTE device*/ 221#define F2_CTL_1000T_REPEATER_DTE 0x0400 222 223 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 224#define F2_CTL_1000T_MS_VALUE 0x0800 225 226 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 227#define F2_CTL_1000T_MS_ENABLE 0x1000 228 229 /* Normal Operation */ 230#define F2_CTL_1000T_TEST_MODE_NORMAL 0x0000 231 232 /* Transmit Waveform test */ 233#define F2_CTL_1000T_TEST_MODE_1 0x2000 234 235 /* Master Transmit Jitter test */ 236#define F2_CTL_1000T_TEST_MODE_2 0x4000 237 238 /* Slave Transmit Jitter test */ 239#define F2_CTL_1000T_TEST_MODE_3 0x6000 240 241 /* Transmitter Distortion test */ 242#define F2_CTL_1000T_TEST_MODE_4 0x8000 243#define F2_CTL_1000T_SPEED_MASK 0x0300 244#define F2_CTL_1000T_DEFAULT_CAP_MASK 0x0300 245 246 /* 1000BASE-T Status Register offset:10 */ 247 /* LP is 1000T HD capable */ 248#define F2_STATUS_1000T_LP_HD_CAPS 0x0400 249 250 /* LP is 1000T FD capable */ 251#define F2_STATUS_1000T_LP_FD_CAPS 0x0800 252 253 /* Remote receiver OK */ 254#define F2_STATUS_1000T_REMOTE_RX_STATUS 0x1000 255 256 /* Local receiver OK */ 257#define F2_STATUS_1000T_LOCAL_RX_STATUS 0x2000 258 259 /* 1=Local TX is Master, 0=Slave */ 260#define F2_STATUS_1000T_MS_CONFIG_RES 0x4000 261 262#define F2_STATUS_1000T_MS_CONFIG_FAULT 0x8000 263 264 /* Master/Slave config fault */ 265#define F2_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 266#define F2_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 267 268 /* Phy Specific Control Register offset:16*/ 269 /* 1=Jabber Function disabled */ 270#define F2_CTL_JABBER_DISABLE 0x0001 271 272 /* 1=Polarity Reversal enabled */ 273#define F2_CTL_POLARITY_REVERSAL 0x0002 274 275 /* 1=SQE Test enabled */ 276#define F2_CTL_SQE_TEST 0x0004 277#define F2_CTL_MAC_POWERDOWN 0x0008 278 279 /* 1=CLK125 low, 0=CLK125 toggling 280 #define F2_CTL_CLK125_DISABLE 0x0010 281 */ 282 /* MDI Crossover Mode bits 6:5 */ 283 /* Manual MDI configuration */ 284#define F2_CTL_MDI_MANUAL_MODE 0x0000 285 286 /* Manual MDIX configuration */ 287#define F2_CTL_MDIX_MANUAL_MODE 0x0020 288 289 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 290#define F2_CTL_AUTO_X_1000T 0x0040 291 292 /* Auto crossover enabled all speeds */ 293#define F2_CTL_AUTO_X_MODE 0x0060 294 295 /* 1=Enable Extended 10BASE-T distance 296 * (Lower 10BASE-T RX Threshold) 297 * 0=Normal 10BASE-T RX Threshold */ 298#define F2_CTL_10BT_EXT_DIST_ENABLE 0x0080 299 300 /* 1=5-Bit interface in 100BASE-TX 301 * 0=MII interface in 100BASE-TX */ 302#define F2_CTL_MII_5BIT_ENABLE 0x0100 303 304 /* 1=Scrambler disable */ 305#define F2_CTL_SCRAMBLER_DISABLE 0x0200 306 307 /* 1=Force link good */ 308#define F2_CTL_FORCE_LINK_GOOD 0x0400 309 310 /* 1=Assert CRS on Transmit */ 311#define F2_CTL_ASSERT_CRS_ON_TX 0x0800 312 313#define F2_CTL_POLARITY_REVERSAL_SHIFT 1 314#define F2_CTL_AUTO_X_MODE_SHIFT 5 315#define F2_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 316 317 /* Phy Specific status fields offset:17*/ 318 /* 1=Speed & Duplex resolved */ 319#define F2_STATUS_RESOVLED 0x0800 320 321 /* 1=Duplex 0=Half Duplex */ 322#define F2_STATUS_FULL_DUPLEX 0x2000 323 324 /* Speed, bits 14:15 */ 325#define F2_STATUS_SPEED 0xC000 326#define F2_STATUS_SPEED_MASK 0xC000 327 328 /* 00=10Mbs */ 329#define F2_STATUS_SPEED_10MBS 0x0000 330 331 /* 01=100Mbs */ 332#define F2_STATUS_SPEED_100MBS 0x4000 333 334 /* 10=1000Mbs */ 335#define F2_STATUS_SPEED_1000MBS 0x8000 336#define F2_SPEED_DUPLEX_RESOVLED(phy_status) \ 337 (((phy_status) & \ 338 (F2_STATUS_RESOVLED)) == \ 339 (F2_STATUS_RESOVLED)) 340 341 /*phy debug port1 register offset:29*/ 342 /*phy debug port2 register offset:30*/ 343 344 sw_error_t 345 f2_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); 346 347 sw_error_t 348 f2_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); 349 350 sw_error_t 351 f2_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); 352 353 sw_error_t 354 f2_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); 355 356 sw_error_t 357 f2_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, 358 fal_cable_status_t *cable_status, a_uint32_t *cable_len) ; 359 360 sw_error_t 361 f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, 362 fal_port_duplex_t duplex); 363 364 sw_error_t 365 f2_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, 366 fal_port_duplex_t * duplex); 367 368 sw_error_t 369 f2_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, 370 fal_port_speed_t speed); 371 372 sw_error_t 373 f2_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, 374 fal_port_speed_t * speed); 375 376 sw_error_t 377 f2_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); 378 379 sw_error_t 380 f2_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); 381 382 sw_error_t 383 f2_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, 384 a_uint32_t autoneg); 385 386 sw_error_t 387 f2_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, 388 a_uint32_t * autoneg); 389 390 a_bool_t 391 f2_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id); 392 393 int f2_phy_init(void); 394 395 396#ifdef __cplusplus 397} 398#endif /* __cplusplus */ 399#endif /* _F2_PHY_H_ */ 400