1/* 2 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 3 * Permission to use, copy, modify, and/or distribute this software for 4 * any purpose with or without fee is hereby granted, provided that the 5 * above copyright notice and this permission notice appear in all copies. 6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 13 */ 14 15 16 17#ifndef _ISIS_REG_H_ 18#define _ISIS_REG_H_ 19 20#ifdef __cplusplus 21extern "C" { 22#endif /* __cplusplus */ 23 24#define S16E_DEVICE_ID 0x11 25#define S17_DEVICE_ID 0x12 26#define S17_REVISION_A 0x01 27 28#define MAX_ENTRY_LEN 128 29 30#define HSL_RW 1 31#define HSL_RO 0 32 33 34 /* ISIS Mask Control Register */ 35#define MASK_CTL 36#define MASK_CTL_ID 0 37#define MASK_CTL_OFFSET 0x0000 38#define MASK_CTL_E_LENGTH 4 39#define MASK_CTL_E_OFFSET 0 40#define MASK_CTL_NR_E 1 41 42#define SOFT_RST 43#define MASK_CTL_SOFT_RST_BOFFSET 31 44#define MASK_CTL_SOFT_RST_BLEN 1 45#define MASK_CTL_SOFT_RST_FLAG HSL_RW 46 47#define LOAD_EEPROM 48#define MASK_CTL_LOAD_EEPROM_BOFFSET 16 49#define MASK_CTL_LOAD_EEPROM_BLEN 1 50#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW 51 52#define DEVICE_ID 53#define MASK_CTL_DEVICE_ID_BOFFSET 8 54#define MASK_CTL_DEVICE_ID_BLEN 8 55#define MASK_CTL_DEVICE_ID_FLAG HSL_RO 56 57#define REV_ID 58#define MASK_CTL_REV_ID_BOFFSET 0 59#define MASK_CTL_REV_ID_BLEN 8 60#define MASK_CTL_REV_ID_FLAG HSL_RO 61 62 63 64 65 /* Port0 Pad Control Register */ 66#define PORT0_PAD_CTRL 67#define PORT0_PAD_CTRL_ID 0 68#define PORT0_PAD_CTRL_OFFSET 0x0004 69#define PORT0_PAD_CTRL_E_LENGTH 4 70#define PORT0_PAD_CTRL_E_OFFSET 0 71#define PORT0_PAD_CTRL_NR_E 1 72 73#define MAC0_RGMII_EN 74#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BOFFSET 26 75#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BLEN 1 76#define PORT0_PAD_CTRL_MAC0_RGMII_EN_FLAG HSL_RW 77 78#define MAC0_RGMII_TXCLK_DELAY_EN 79#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BOFFSET 25 80#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BLEN 1 81#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW 82 83#define MAC0_RGMII_RXCLK_DELAY_EN 84#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BOFFSET 24 85#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BLEN 1 86#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW 87 88#define MAC0_RGMII_TXCLK_DELAY_SEL 89#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 90#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BLEN 2 91#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW 92 93#define MAC0_RGMII_RXCLK_DELAY_SEL 94#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 95#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BLEN 2 96#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW 97 98#define SGMII_CLK125M_RX_SEL 99#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BOFFSET 19 100#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BLEN 1 101#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_FLAG HSL_RW 102 103#define SGMII_CLK125M_TX_SEL 104#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BOFFSET 18 105#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BLEN 1 106#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_FLAG HSL_RW 107 108#define MAC0_PHY_GMII_EN 109#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BOFFSET 14 110#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BLEN 1 111#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_FLAG HSL_RW 112 113#define MAC0_PHY_GMII_TXCLK_SEL 114#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BOFFSET 13 115#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BLEN 1 116#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_FLAG HSL_RW 117 118#define MAC0_PHY_GMII_RXCLK_SEL 119#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BOFFSET 12 120#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BLEN 1 121#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_FLAG HSL_RW 122 123#define MAC0_PHY_MII_PIPE_RXCLK_SEL 124#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 125#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 126#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW 127 128#define MAC0_PHY_MII_EN 129#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BOFFSET 10 130#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BLEN 1 131#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_FLAG HSL_RW 132 133#define MAC0_PHY_MII_TXCLK_SEL 134#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BOFFSET 9 135#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BLEN 1 136#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_FLAG HSL_RW 137 138#define MAC0_PHY_MII_RXCLK_SEL 139#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BOFFSET 8 140#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BLEN 1 141#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_FLAG HSL_RW 142 143#define MAC0_SGMII_EN 144#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BOFFSET 7 145#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BLEN 1 146#define PORT0_PAD_CTRL_MAC0_SGMII_EN_FLAG HSL_RW 147 148#define MAC0_MAC_GMII_EN 149#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BOFFSET 6 150#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BLEN 1 151#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_FLAG HSL_RW 152 153#define MAC0_MAC_GMII_TXCLK_SEL 154#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BOFFSET 5 155#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BLEN 1 156#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_FLAG HSL_RW 157 158#define MAC0_MAC_GMII_RXCLK_SEL 159#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BOFFSET 4 160#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BLEN 1 161#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_FLAG HSL_RW 162 163#define MAC0_MAC_MII_EN 164#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BOFFSET 2 165#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BLEN 1 166#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_FLAG HSL_RW 167 168#define MAC0_MAC_MII_TXCLK_SEL 169#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1 170#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1 171#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW 172 173#define MAC0_MAC_MII_RXCLK_SEL 174#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BOFFSET 0 175#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BLEN 1 176#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_FLAG HSL_RW 177 178 179 180 181 /* Port5 Pad Control Register */ 182#define PORT5_PAD_CTRL 183#define PORT5_PAD_CTRL_ID 0 184#define PORT5_PAD_CTRL_OFFSET 0x0008 185#define PORT5_PAD_CTRL_E_LENGTH 4 186#define PORT5_PAD_CTRL_E_OFFSET 0 187#define PORT5_PAD_CTRL_NR_E 1 188 189#define MAC5_RGMII_EN 190#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BOFFSET 26 191#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BLEN 1 192#define PORT5_PAD_CTRL_MAC5_RGMII_EN_FLAG HSL_RW 193 194#define MAC5_RGMII_TXCLK_DELAY_EN 195#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BOFFSET 25 196#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BLEN 1 197#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW 198 199#define MAC5_RGMII_RXCLK_DELAY_EN 200#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BOFFSET 24 201#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BLEN 1 202#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW 203 204#define MAC5_RGMII_TXCLK_DELAY_SEL 205#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 206#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BLEN 2 207#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW 208 209#define MAC5_RGMII_RXCLK_DELAY_SEL 210#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 211#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BLEN 2 212#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW 213 214#define MAC5_PHY_MII_PIPE_RXCLK_SEL 215#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 216#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 217#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW 218 219#define MAC5_PHY_MII_EN 220#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BOFFSET 10 221#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BLEN 1 222#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_FLAG HSL_RW 223 224#define MAC5_PHY_MII_TXCLK_SEL 225#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BOFFSET 9 226#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BLEN 1 227#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_FLAG HSL_RW 228 229#define MAC5_PHY_MII_RXCLK_SEL 230#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BOFFSET 8 231#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BLEN 1 232#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_FLAG HSL_RW 233 234#define MAC5_MAC_MII_EN 235#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BOFFSET 2 236#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BLEN 1 237#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_FLAG HSL_RW 238 239#define MAC5_MAC_MII_TXCLK_SEL 240#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1 241#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1 242#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW 243 244#define MAC5_MAC_MII_RXCLK_SEL 245#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BOFFSET 0 246#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BLEN 1 247#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_FLAG HSL_RW 248 249 250 251 252 /* Port6 Pad Control Register */ 253#define PORT6_PAD_CTRL 254#define PORT6_PAD_CTRL_ID 0 255#define PORT6_PAD_CTRL_OFFSET 0x000c 256#define PORT6_PAD_CTRL_E_LENGTH 4 257#define PORT6_PAD_CTRL_E_OFFSET 0 258#define PORT6_PAD_CTRL_NR_E 1 259 260#define MAC6_RGMII_EN 261#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BOFFSET 26 262#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BLEN 1 263#define PORT6_PAD_CTRL_MAC6_RGMII_EN_FLAG HSL_RW 264 265#define MAC6_RGMII_TXCLK_DELAY_EN 266#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BOFFSET 25 267#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BLEN 1 268#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW 269 270#define MAC6_RGMII_RXCLK_DELAY_EN 271#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BOFFSET 24 272#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BLEN 1 273#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW 274 275#define MAC6_RGMII_TXCLK_DELAY_SEL 276#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 277#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BLEN 2 278#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW 279 280#define MAC6_RGMII_RXCLK_DELAY_SEL 281#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 282#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BLEN 2 283#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW 284 285#define PHY4_MII_EN 286#define PORT6_PAD_CTRL_PHY4_MII_EN_BOFFSET 18 287#define PORT6_PAD_CTRL_PHY4_MII_EN_BLEN 1 288#define PORT6_PAD_CTRL_PHY4_MII_EN_FLAG HSL_RW 289 290#define PHY4_RGMII_EN 291#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BOFFSET 17 292#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BLEN 1 293#define PORT6_PAD_CTRL_PHY4_RGMII_EN_FLAG HSL_RW 294 295#define PHY4_GMII_EN 296#define PORT6_PAD_CTRL_PHY4_GMII_EN_BOFFSET 16 297#define PORT6_PAD_CTRL_PHY4_GMII_EN_BLEN 1 298#define PORT6_PAD_CTRL_PHY4_GMII_EN_FLAG HSL_RW 299 300#define MAC6_PHY_GMII_EN 301#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BOFFSET 14 302#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BLEN 1 303#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_FLAG HSL_RW 304 305#define MAC6_PHY_GMII_TXCLK_SEL 306#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BOFFSET 13 307#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BLEN 1 308#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_FLAG HSL_RW 309 310#define MAC6_PHY_GMII_RXCLK_SEL 311#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BOFFSET 12 312#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BLEN 1 313#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_FLAG HSL_RW 314 315#define MAC6_PHY_MII_PIPE_RXCLK_SEL 316#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 317#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 318#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW 319 320#define MAC6_PHY_MII_EN 321#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BOFFSET 10 322#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BLEN 1 323#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_FLAG HSL_RW 324 325#define MAC6_PHY_MII_TXCLK_SEL 326#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BOFFSET 9 327#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BLEN 1 328#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_FLAG HSL_RW 329 330#define MAC6_PHY_MII_RXCLK_SEL 331#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BOFFSET 8 332#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BLEN 1 333#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_FLAG HSL_RW 334 335#define MAC6_SGMII_EN 336#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BOFFSET 7 337#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BLEN 1 338#define PORT6_PAD_CTRL_MAC6_SGMII_EN_FLAG HSL_RW 339 340#define MAC6_MAC_GMII_EN 341#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BOFFSET 6 342#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BLEN 1 343#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_FLAG HSL_RW 344 345#define MAC6_MAC_GMII_TXCLK_SEL 346#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BOFFSET 5 347#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BLEN 1 348#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_FLAG HSL_RW 349 350#define MAC6_MAC_GMII_RXCLK_SEL 351#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BOFFSET 4 352#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BLEN 1 353#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_FLAG HSL_RW 354 355#define MAC6_MAC_MII_EN 356#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BOFFSET 2 357#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BLEN 1 358#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_FLAG HSL_RW 359 360#define MAC6_MAC_MII_TXCLK_SEL 361#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BOFFSET 1 362#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BLEN 1 363#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_FLAG HSL_RW 364 365#define MAC6_MAC_MII_RXCLK_SEL 366#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BOFFSET 0 367#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BLEN 1 368#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_FLAG HSL_RW 369 370 371 372 373 /* SGMII Control Register */ 374#define SGMII_CTRL 375#define SGMII_CTRL_ID 0 376#define SGMII_CTRL_OFFSET 0x00e0 377#define SGMII_CTRL_E_LENGTH 4 378#define SGMII_CTRL_E_OFFSET 0 379#define SGMII_CTRL_NR_E 1 380 381#define FULL_25M 382#define SGMII_CTRL_FULL_25M_BOFFSET 31 383#define SGMII_CTRL_FULL_25M_BLEN 1 384#define SGMII_CTRL_FULL_25M_FLAG HSL_RW 385 386#define HALF_25M 387#define SGMII_CTRL_HALF_25M_BOFFSET 30 388#define SGMII_CTRL_HALF_25M_BLEN 1 389#define SGMII_CTRL_HALF_25M_FLAG HSL_RW 390 391#define REMOTE_25M 392#define SGMII_CTRL_REMOTE_25M_BOFFSET 28 393#define SGMII_CTRL_REMOTE_25M_BLEN 2 394#define SGMII_CTRL_REMOTE_25M_FLAG HSL_RW 395 396#define NEXT_PAGE_25M 397#define SGMII_CTRL_NEXT_PAGE_25M_BOFFSET 27 398#define SGMII_CTRL_NEXT_PAGE_25M_BLEN 1 399#define SGMII_CTRL_NEXT_PAGE_25M_FLAG HSL_RW 400 401#define PAUSE_25M 402#define SGMII_CTRL_PAUSE_25M_BOFFSET 26 403#define SGMII_CTRL_PAUSE_25M_BLEN 1 404#define SGMII_CTRL_PAUSE_25M_FLAG HSL_RW 405 406#define ASYM_PAUSE_25M 407#define SGMII_CTRL_ASYM_PAUSE_25M_BOFFSET 25 408#define SGMII_CTRL_ASYM_PAUSE_25M_BLEN 1 409#define SGMII_CTRL_ASYM_PAUSE_25M_FLAG HSL_RW 410 411#define PAUSE_SG_25M 412#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24 413#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1 414#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW 415 416#define PAUSE_SG_25M 417#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24 418#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1 419#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW 420 421#define MODE_CTRL_25M 422#define SGMII_CTRL_MODE_CTRL_25M_BOFFSET 22 423#define SGMII_CTRL_MODE_CTRL_25M_BLEN 2 424#define SGMII_CTRL_MODE_CTRL_25M_FLAG HSL_RW 425 426#define MR_LOOPBACK 427#define SGMII_CTRL_MR_LOOPBACK_BOFFSET 21 428#define SGMII_CTRL_MR_LOOPBACK_BLEN 1 429#define SGMII_CTRL_MR_LOOPBACK_FLAG HSL_RW 430 431#define MR_REG4_25M 432#define SGMII_CTRL_MR_REG4_25M_BOFFSET 20 433#define SGMII_CTRL_MR_REG4_25M_BLEN 1 434#define SGMII_CTRL_MR_REG4_25M_FLAG HSL_RW 435 436#define AUTO_LPI_25M 437#define SGMII_CTRL_AUTO_LPI_25M_BOFFSET 19 438#define SGMII_CTRL_AUTO_LPI_25M_BLEN 1 439#define SGMII_CTRL_AUTO_LPI_25M_FLAG HSL_RW 440 441#define PRBS_EN 442#define SGMII_CTRL_PRBS_EN_BOFFSET 18 443#define SGMII_CTRL_PRBS_EN_BLEN 1 444#define SGMII_CTRL_PRBS_EN_FLAG HSL_RW 445 446#define SGMII_TH_LOS1 447#define SGMII_CTRL_SGMII_TH_LOS1_BOFFSET 17 448#define SGMII_CTRL_SGMII_TH_LOS1_BLEN 1 449#define SGMII_CTRL_SGMII_TH_LOS1_FLAG HSL_RW 450 451#define DIS_AUTO_LPI_25M 452#define SGMII_CTRL_DIS_AUTO_LPI_25M_BOFFSET 16 453#define SGMII_CTRL_DIS_AUTO_LPI_25M_BLEN 1 454#define SGMII_CTRL_DIS_AUTO_LPI_25M_FLAG HSL_RW 455 456#define SGMII_TH_LOS0 457#define SGMII_CTRL_SGMII_TH_LOS0_BOFFSET 15 458#define SGMII_CTRL_SGMII_TH_LOS0_BLEN 1 459#define SGMII_CTRL_SGMII_TH_LOS0_FLAG HSL_RW 460 461#define SGMII_CDR_BW 462#define SGMII_CTRL_SGMII_CDR_BW_BOFFSET 13 463#define SGMII_CTRL_SGMII_CDR_BW_BLEN 2 464#define SGMII_CTRL_SGMII_CDR_BW_FLAG HSL_RW 465 466#define SGMII_TXDR_CTRL 467#define SGMII_CTRL_SGMII_TXDR_CTRL_BOFFSET 10 468#define SGMII_CTRL_SGMII_TXDR_CTRL_BLEN 3 469#define SGMII_CTRL_SGMII_TXDR_CTRL_FLAG HSL_RW 470 471#define SGMII_FIBER_MODE 472#define SGMII_CTRL_SGMII_FIBER_MODE_BOFFSET 8 473#define SGMII_CTRL_SGMII_FIBER_MODE_BLEN 2 474#define SGMII_CTRL_SGMII_FIBER_MODE_FLAG HSL_RW 475 476#define SGMII_SEL_125M 477#define SGMII_CTRL_SGMII_SEL_125M_BOFFSET 7 478#define SGMII_CTRL_SGMII_SEL_125M_BLEN 1 479#define SGMII_CTRL_SGMII_SEL_125M_FLAG HSL_RW 480 481#define SGMII_PLL_BW 482#define SGMII_CTRL_SGMII_PLL_BW_BOFFSET 6 483#define SGMII_CTRL_SGMII_PLL_BW_BLEN 1 484#define SGMII_CTRL_SGMII_PLL_BW_FLAG HSL_RW 485 486#define SGMII_HALFTX 487#define SGMII_CTRL_SGMII_HALFTX_BOFFSET 5 488#define SGMII_CTRL_SGMII_HALFTX_BLEN 1 489#define SGMII_CTRL_SGMII_HALFTX_FLAG HSL_RW 490 491#define SGMII_EN_SD 492#define SGMII_CTRL_SGMII_EN_SD_BOFFSET 4 493#define SGMII_CTRL_SGMII_EN_SD_BLEN 1 494#define SGMII_CTRL_SGMII_EN_SD_FLAG HSL_RW 495 496#define SGMII_EN_TX 497#define SGMII_CTRL_SGMII_EN_TX_BOFFSET 3 498#define SGMII_CTRL_SGMII_EN_TX_BLEN 1 499#define SGMII_CTRL_SGMII_EN_TX_FLAG HSL_RW 500 501#define SGMII_EN_RX 502#define SGMII_CTRL_SGMII_EN_RX_BOFFSET 2 503#define SGMII_CTRL_SGMII_EN_RX_BLEN 1 504#define SGMII_CTRL_SGMII_EN_RX_FLAG HSL_RW 505 506#define SGMII_EN_PLL 507#define SGMII_CTRL_SGMII_EN_PLL_BOFFSET 1 508#define SGMII_CTRL_SGMII_EN_PLL_BLEN 1 509#define SGMII_CTRL_SGMII_EN_PLL_FLAG HSL_RW 510 511#define SGMII_EN_LCKDT 512#define SGMII_CTRL_SGMII_EN_LCKDT_BOFFSET 0 513#define SGMII_CTRL_SGMII_EN_LCKDT_BLEN 1 514#define SGMII_CTRL_SGMII_EN_LCKDT_FLAG HSL_RW 515 516 517 518 519 /* Power On Strip Register */ 520#define POWER_STRIP 521#define POWER_STRIP_ID 0 522#define POWER_STRIP_OFFSET 0x0010 523#define POWER_STRIP_E_LENGTH 4 524#define POWER_STRIP_E_OFFSET 0 525#define POWER_STRIP_NR_E 1 526 527#define POWER_ON_SEL 528#define POWER_STRIP_POWER_ON_SEL_BOFFSET 31 529#define POWER_STRIP_POWER_ON_SEL_BLEN 1 530#define POWER_STRIP_POWER_ON_SEL_FLAG HSL_RW 531 532#define PKG128_EN 533#define POWER_STRIP_PKG128_EN_BOFFSET 30 534#define POWER_STRIP_PKG128_EN_BLEN 1 535#define POWER_STRIP_PKG128_EN_FLAG HSL_RW 536 537#define PKG128_EN_LED 538#define POWER_STRIP_PKG128_EN_LED_BOFFSET 29 539#define POWER_STRIP_PKG128_EN_LED_BLEN 1 540#define POWER_STRIP_PKG128_EN_LED_FLAG HSL_RW 541 542#define S16_MODE 543#define POWER_STRIP_S16_MODE_BOFFSET 28 544#define POWER_STRIP_S16_MODE_BLEN 1 545#define POWER_STRIP_S16_MODE_FLAG HSL_RW 546 547#define INPUT_MODE 548#define POWER_STRIP_INPUT_MODE_BOFFSET 27 549#define POWER_STRIP_INPUT_MODE_BLEN 1 550#define POWER_STRIP_INPUT_MODE_FLAG HSL_RW 551 552#define SGMII_POWER_ON_SEL 553#define POWER_STRIP_SGMII_POWER_ON_SEL_BOFFSET 26 554#define POWER_STRIP_SGMII_POWER_ON_SEL_BLEN 1 555#define POWER_STRIP_SGMII_POWER_ON_SEL_FLAG HSL_RW 556 557#define SPI_EN 558#define POWER_STRIP_SPI_EN_BOFFSET 25 559#define POWER_STRIP_SPI_EN_BLEN 1 560#define POWER_STRIP_SPI_EN_FLAG HSL_RW 561 562#define LED_OPEN_EN 563#define POWER_STRIP_LED_OPEN_EN_BOFFSET 24 564#define POWER_STRIP_LED_OPEN_EN_BLEN 1 565#define POWER_STRIP_LED_OPEN_EN_FLAG HSL_RW 566 567#define SGMII_RXIMP_50_70 568#define POWER_STRIP_SGMII_RXIMP_50_70_BOFFSET 23 569#define POWER_STRIP_SGMII_RXIMP_50_70_BLEN 1 570#define POWER_STRIP_SGMII_RXIMP_50_70_FLAG HSL_RW 571 572#define SGMII_TXIMP_50_70 573#define POWER_STRIP_SGMII_TXIMP_50_70_BOFFSET 22 574#define POWER_STRIP_SGMII_TXIMP_50_70_BLEN 1 575#define POWER_STRIP_SGMII_TXIMP_50_70_FLAG HSL_RW 576 577#define SGMII_SIGNAL_DETECT 578#define POWER_STRIP_SGMII_SIGNAL_DETECT_BOFFSET 21 579#define POWER_STRIP_SGMII_SIGNAL_DETECT_BLEN 1 580#define POWER_STRIP_SGMII_SIGNAL_DETECT_FLAG HSL_RW 581 582#define LPW_EXIT 583#define POWER_STRIP_LPW_EXIT_BOFFSET 20 584#define POWER_STRIP_LPW_EXIT_BLEN 1 585#define POWER_STRIP_LPW_EXIT_FLAG HSL_RW 586 587#define MAN_EN 588#define POWER_STRIP_MAN_EN_BOFFSET 18 589#define POWER_STRIP_MAN_EN_BLEN 1 590#define POWER_STRIP_MAN_EN_FLAG HSL_RW 591 592#define HIB_EN 593#define POWER_STRIP_HIB_EN_BOFFSET 17 594#define POWER_STRIP_HIB_EN_BLEN 1 595#define POWER_STRIP_HIB_EN_FLAG HSL_RW 596 597#define POWER_DOWN_HW 598#define POWER_STRIP_POWER_DOWN_HW_BOFFSET 16 599#define POWER_STRIP_POWER_DOWN_HW_BLEN 1 600#define POWER_STRIP_POWER_DOWN_HW_FLAG HSL_RW 601 602#define BIST_BYPASS_CEL 603#define POWER_STRIP_BIST_BYPASS_CEL_BOFFSET 15 604#define POWER_STRIP_BIST_BYPASS_CEL_BLEN 1 605#define POWER_STRIP_BIST_BYPASS_CEL_FLAG HSL_RW 606 607#define BIST_BYPASS_CSR 608#define POWER_STRIP_BIST_BYPASS_CSR_BOFFSET 14 609#define POWER_STRIP_BIST_BYPASS_CSR_BLEN 1 610#define POWER_STRIP_BIST_BYPASS_CSR_FLAG HSL_RW 611 612#define HIB_PULSE_HW 613#define POWER_STRIP_HIB_PULSE_HW_BOFFSET 12 614#define POWER_STRIP_HIB_PULSE_HW_BLEN 1 615#define POWER_STRIP_HIB_PULSE_HW_FLAG HSL_RW 616 617#define GATE_25M_EN 618#define POWER_STRIP_GATE_25M_EN_BOFFSET 10 619#define POWER_STRIP_GATE_25M_EN_BLEN 1 620#define POWER_STRIP_GATE_25M_EN_FLAG HSL_RW 621 622#define SEL_ANA_RST 623#define POWER_STRIP_SEL_ANA_RST_BOFFSET 9 624#define POWER_STRIP_SEL_ANA_RST_BLEN 1 625#define POWER_STRIP_SEL_ANA_RST_FLAG HSL_RW 626 627#define SERDES_EN 628#define POWER_STRIP_SERDES_EN_BOFFSET 8 629#define POWER_STRIP_SERDES_EN_BLEN 1 630#define POWER_STRIP_SERDES_EN_FLAG HSL_RW 631 632#define SERDES_AN_EN 633#define POWER_STRIP_SERDES_AN_EN_BOFFSET 7 634#define POWER_STRIP_SERDES_AN_EN_BLEN 1 635#define POWER_STRIP_SERDES_AN_EN_FLAG HSL_RW 636 637#define RTL_MODE 638#define POWER_STRIP_RTL_MODE_BOFFSET 5 639#define POWER_STRIP_RTL_MODE_BLEN 1 640#define POWER_STRIP_RTL_MODE_FLAG HSL_RW 641 642#define PAD_CTRL_FOR25M 643#define POWER_STRIP_PAD_CTRL_FOR25M_BOFFSET 3 644#define POWER_STRIP_PAD_CTRL_FOR25M_BLEN 2 645#define POWER_STRIP_PAD_CTRL_FOR25M_FLAG HSL_RW 646 647#define PAD_CTRL 648#define POWER_STRIP_PAD_CTRL_BOFFSET 0 649#define POWER_STRIP_PAD_CTRL_BLEN 2 650#define POWER_STRIP_PAD_CTRL_FLAG HSL_RW 651 652 653 654 655 /* Global Interrupt Status Register1 */ 656#define GBL_INT_STATUS1 657#define GBL_INT_STATUS1_ID 1 658#define GBL_INT_STATUS1_OFFSET 0x0024 659#define GBL_INT_STATUS1_E_LENGTH 4 660#define GBL_INT_STATUS1_E_OFFSET 0 661#define GBL_INT_STATUS1_NR_E 1 662 663#define PHY_INT_S 664#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET 15 665#define GBL_INT_STATUS1_PHY_INT_S_BLEN 1 666#define GBL_INT_STATUS1_PHY_INT_S_FLAG HSL_RO 667 668 669 670 671 /* Global Interrupt Mask Register1 */ 672#define GBL_INT_MASK1 673#define GBL_INT_MASK1_ID 1 674#define GBL_INT_MASK1_OFFSET 0x002c 675#define GBL_INT_MASK1_E_LENGTH 4 676#define GBL_INT_MASK1_E_OFFSET 0 677#define GBL_INT_MASK1_NR_E 1 678 679#define PHY_INT_M 680#define GBL_INT_MASK1_PHY_INT_M_BOFFSET 15 681#define GBL_INT_MASK1_PHY_INT_M_BLEN 1 682#define GBL_INT_MASK1_PHY_INT_M_FLAG HSL_RO 683 684 685 686 687 /* Module Enable Register */ 688#define MOD_ENABLE 689#define MOD_ENABLE_OFFSET 0x0030 690#define MOD_ENABLE_E_LENGTH 4 691#define MOD_ENABLE_E_OFFSET 0 692#define MOD_ENABLE_NR_E 1 693 694#define L3_EN 695#define MOD_ENABLE_L3_EN_BOFFSET 2 696#define MOD_ENABLE_L3_EN_BLEN 1 697#define MOD_ENABLE_L3_EN_FLAG HSL_RW 698 699#define ACL_EN 700#define MOD_ENABLE_ACL_EN_BOFFSET 1 701#define MOD_ENABLE_ACL_EN_BLEN 1 702#define MOD_ENABLE_ACL_EN_FLAG HSL_RW 703 704#define MIB_EN 705#define MOD_ENABLE_MIB_EN_BOFFSET 0 706#define MOD_ENABLE_MIB_EN_BLEN 1 707#define MOD_ENABLE_MIB_EN_FLAG HSL_RW 708 709 710 711 712 /* MIB Function Register */ 713#define MIB_FUNC 714#define MIB_FUNC_OFFSET 0x0034 715#define MIB_FUNC_E_LENGTH 4 716#define MIB_FUNC_E_OFFSET 0 717#define MIB_FUNC_NR_E 1 718 719#define MIB_FUN 720#define MIB_FUNC_MIB_FUN_BOFFSET 24 721#define MIB_FUNC_MIB_FUN_BLEN 3 722#define MIB_FUNC_MIB_FUN_FLAG HSL_RW 723 724#define MIB_BUSY 725#define MIB_FUNC_MIB_BUSY_BOFFSET 17 726#define MIB_FUNC_MIB_BUSY_BLEN 1 727#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW 728 729#define MIB_AT_HALF_EN 730#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 731#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 732#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW 733 734#define MIB_TIMER 735#define MIB_FUNC_MIB_TIMER_BOFFSET 0 736#define MIB_FUNC_MIB_TIMER_BLEN 16 737#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW 738 739 740 741 742 /* Service tag Register */ 743#define SERVICE_TAG 744#define SERVICE_TAG_OFFSET 0x0048 745#define SERVICE_TAG_E_LENGTH 4 746#define SERVICE_TAG_E_OFFSET 0 747#define SERVICE_TAG_NR_E 1 748 749#define STAG_MODE 750#define SERVICE_TAG_STAG_MODE_BOFFSET 17 751#define SERVICE_TAG_STAG_MODE_BLEN 1 752#define SERVICE_TAG_STAG_MODE_FLAG HSL_RW 753 754#define TAG_VALUE 755#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 756#define SERVICE_TAG_TAG_VALUE_BLEN 16 757#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW 758 759 760 761 762 /* Global MAC Address Register */ 763#define GLOBAL_MAC_ADDR0 764#define GLOBAL_MAC_ADDR0_OFFSET 0x0060 765#define GLOBAL_MAC_ADDR0_E_LENGTH 4 766#define GLOBAL_MAC_ADDR0_E_OFFSET 0 767#define GLOBAL_MAC_ADDR0_NR_E 1 768 769#define GLB_BYTE4 770#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 771#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 772#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW 773 774#define GLB_BYTE5 775#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 776#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 777#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW 778 779#define GLOBAL_MAC_ADDR1 780#define GLOBAL_MAC_ADDR1_ID 4 781#define GLOBAL_MAC_ADDR1_OFFSET 0x0064 782#define GLOBAL_MAC_ADDR1_E_LENGTH 4 783#define GLOBAL_MAC_ADDR1_E_OFFSET 0 784#define GLOBAL_MAC_ADDR1_NR_E 1 785 786#define GLB_BYTE0 787#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 788#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 789#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW 790 791#define GLB_BYTE1 792#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 793#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 794#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW 795 796#define GLB_BYTE2 797#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 798#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 799#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW 800 801#define GLB_BYTE3 802#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 803#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 804#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW 805 806 807 808 809 /* Max Size Register */ 810#define MAX_SIZE 811#define MAX_SIZE_OFFSET 0x0078 812#define MAX_SIZE_E_LENGTH 4 813#define MAX_SIZE_E_OFFSET 0 814#define MAX_SIZE_NR_E 1 815 816#define MAX_FRAME_SIZE 817#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET 0 818#define MAX_SIZE_MAX_FRAME_SIZE_BLEN 14 819#define MAX_SIZE_MAX_FRAME_SIZE_FLAG HSL_RW 820 821 822 823 824 /* Flow Control Register */ 825#define FLOW_CTL0 "fctl" 826#define FLOW_CTL0_ID 6 827#define FLOW_CTL0_OFFSET 0x0034 828#define FLOW_CTL0_E_LENGTH 4 829#define FLOW_CTL0_E_OFFSET 0 830#define FLOW_CTL0_NR_E 1 831 832#define TEST_PAUSE "fctl_tps" 833#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31 834#define FLOW_CTL0_TEST_PAUSE_BLEN 1 835#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW 836 837 838#define GOL_PAUSE_ON_THRES "fctl_gont" 839#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16 840#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8 841#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW 842 843#define GOL_PAUSE_OFF_THRES "fctl_gofft" 844#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0 845#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8 846#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW 847 848 849 850 851 /* Flow Control1 Register */ 852#define FLOW_CTL1 "fctl1" 853#define FLOW_CTL1_ID 6 854#define FLOW_CTL1_OFFSET 0x0038 855#define FLOW_CTL1_E_LENGTH 4 856#define FLOW_CTL1_E_OFFSET 0 857#define FLOW_CTL1_NR_E 1 858 859#define PORT_PAUSE_ON_THRES "fctl1_pont" 860#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16 861#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8 862#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW 863 864#define PORT_PAUSE_OFF_THRES "fctl1_pofft" 865#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0 866#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8 867#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW 868 869 870 871 872 /* Port Status Register */ 873#define PORT_STATUS 874#define PORT_STATUS_OFFSET 0x007c 875#define PORT_STATUS_E_LENGTH 4 876#define PORT_STATUS_E_OFFSET 0x0004 877#define PORT_STATUS_NR_E 7 878 879#define FLOW_LINK_EN 880#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 881#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 882#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW 883 884#define AUTO_RX_FLOW 885#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET 11 886#define PORT_STATUS_AUTO_RX_FLOW_BLEN 1 887#define PORT_STATUS_AUTO_RX_FLOW_FLAG HSL_RO 888 889#define AUTO_TX_FLOW 890#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET 10 891#define PORT_STATUS_AUTO_TX_FLOW_BLEN 1 892#define PORT_STATUS_AUTO_TX_FLOW_FLAG HSL_RO 893 894#define LINK_EN 895#define PORT_STATUS_LINK_EN_BOFFSET 9 896#define PORT_STATUS_LINK_EN_BLEN 1 897#define PORT_STATUS_LINK_EN_FLAG HSL_RW 898 899#define LINK 900#define PORT_STATUS_LINK_BOFFSET 8 901#define PORT_STATUS_LINK_BLEN 1 902#define PORT_STATUS_LINK_FLAG HSL_RO 903 904#define TX_HALF_FLOW_EN 905#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 906#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 907#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW 908 909#define DUPLEX_MODE 910#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 911#define PORT_STATUS_DUPLEX_MODE_BLEN 1 912#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW 913 914#define RX_FLOW_EN 915#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 916#define PORT_STATUS_RX_FLOW_EN_BLEN 1 917#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW 918 919#define TX_FLOW_EN 920#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 921#define PORT_STATUS_TX_FLOW_EN_BLEN 1 922#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW 923 924#define RXMAC_EN 925#define PORT_STATUS_RXMAC_EN_BOFFSET 3 926#define PORT_STATUS_RXMAC_EN_BLEN 1 927#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW 928 929#define TXMAC_EN 930#define PORT_STATUS_TXMAC_EN_BOFFSET 2 931#define PORT_STATUS_TXMAC_EN_BLEN 1 932#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW 933 934#define SPEED_MODE 935#define PORT_STATUS_SPEED_MODE_BOFFSET 0 936#define PORT_STATUS_SPEED_MODE_BLEN 2 937#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW 938 939 940 941 942 /* Header Ctl Register */ 943#define HEADER_CTL 944#define HEADER_CTL_OFFSET 0x0098 945#define HEADER_CTL_E_LENGTH 4 946#define HEADER_CTL_E_OFFSET 0x0004 947#define HEADER_CTL_NR_E 1 948 949#define TYPE_LEN 950#define HEADER_CTL_TYPE_LEN_BOFFSET 16 951#define HEADER_CTL_TYPE_LEN_BLEN 1 952#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW 953 954#define TYPE_VAL 955#define HEADER_CTL_TYPE_VAL_BOFFSET 0 956#define HEADER_CTL_TYPE_VAL_BLEN 16 957#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW 958 959 960 961 962 /* Port Header Ctl Register */ 963#define PORT_HDR_CTL 964#define PORT_HDR_CTL_OFFSET 0x009c 965#define PORT_HDR_CTL_E_LENGTH 4 966#define PORT_HDR_CTL_E_OFFSET 0x0004 967#define PORT_HDR_CTL_NR_E 7 968 969#define IPG_DEC_EN 970#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET 5 971#define PORT_HDR_CTL_IPG_DEC_EN_BLEN 1 972#define PORT_HDR_CTL_IPG_DEC_EN_FLAG HSL_RW 973 974#define LOOPBACK_EN 975#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET 4 976#define PORT_HDR_CTL_LOOPBACK_EN_BLEN 1 977#define PORT_HDR_CTL_LOOPBACK_EN_FLAG HSL_RW 978 979#define RXHDR_MODE 980#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2 981#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2 982#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW 983 984#define TXHDR_MODE 985#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0 986#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2 987#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW 988 989 990 991 992 /* EEE control Register */ 993#define EEE_CTL 994#define EEE_CTL_OFFSET 0x0100 995#define EEE_CTL_E_LENGTH 4 996#define EEE_CTL_E_OFFSET 0 997#define EEE_CTL_NR_E 1 998 999#define LPI_STATE_REMAP_EN_5 1000#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET 13 1001#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN 1 1002#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG HSL_RW 1003 1004#define LPI_EN_5 1005#define EEE_CTL_LPI_EN_5_BOFFSET 12 1006#define EEE_CTL_LPI_EN_5_BLEN 1 1007#define EEE_CTL_LPI_EN_5_FLAG HSL_RW 1008 1009#define LPI_STATE_REMAP_EN_4 1010#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET 11 1011#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN 1 1012#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG HSL_RW 1013 1014#define LPI_EN_4 1015#define EEE_CTL_LPI_EN_4_BOFFSET 10 1016#define EEE_CTL_LPI_EN_4_BLEN 1 1017#define EEE_CTL_LPI_EN_4_FLAG HSL_RW 1018 1019#define LPI_STATE_REMAP_EN_3 1020#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET 9 1021#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN 1 1022#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG HSL_RW 1023 1024#define LPI_EN_3 1025#define EEE_CTL_LPI_EN_3_BOFFSET 8 1026#define EEE_CTL_LPI_EN_3_BLEN 1 1027#define EEE_CTL_LPI_EN_3_FLAG HSL_RW 1028 1029#define LPI_STATE_REMAP_EN_2 1030#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET 7 1031#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN 1 1032#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG HSL_RW 1033 1034#define LPI_EN_2 1035#define EEE_CTL_LPI_EN_2_BOFFSET 6 1036#define EEE_CTL_LPI_EN_2_BLEN 1 1037#define EEE_CTL_LPI_EN_2_FLAG HSL_RW 1038 1039#define LPI_STATE_REMAP_EN_1 1040#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET 5 1041#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN 1 1042#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG HSL_RW 1043 1044#define LPI_EN_1 1045#define EEE_CTL_LPI_EN_1_BOFFSET 4 1046#define EEE_CTL_LPI_EN_1_BLEN 1 1047#define EEE_CTL_LPI_EN_1_FLAG HSL_RW 1048 1049 1050 1051 1052 /* Frame Ack Ctl0 Register */ 1053#define FRAME_ACK_CTL0 1054#define FRAME_ACK_CTL0_OFFSET 0x0210 1055#define FRAME_ACK_CTL0_E_LENGTH 4 1056#define FRAME_ACK_CTL0_E_OFFSET 0 1057#define FRAME_ACK_CTL0_NR_E 1 1058 1059#define ARP_REQ_EN 1060#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET 6 1061#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN 1 1062#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG HSL_RW 1063 1064#define ARP_REP_EN 1065#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET 5 1066#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN 1 1067#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG HSL_RW 1068 1069#define DHCP_EN 1070#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET 4 1071#define FRAME_ACK_CTL0_DHCP_EN_BLEN 1 1072#define FRAME_ACK_CTL0_DHCP_EN_FLAG HSL_RW 1073 1074#define EAPOL_EN 1075#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET 3 1076#define FRAME_ACK_CTL0_EAPOL_EN_BLEN 1 1077#define FRAME_ACK_CTL0_EAPOL_EN_FLAG HSL_RW 1078 1079#define LEAVE_EN 1080#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET 2 1081#define FRAME_ACK_CTL0_LEAVE_EN_BLEN 1 1082#define FRAME_ACK_CTL0_LEAVE_EN_FLAG HSL_RW 1083 1084#define JOIN_EN 1085#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET 1 1086#define FRAME_ACK_CTL0_JOIN_EN_BLEN 1 1087#define FRAME_ACK_CTL0_JOIN_EN_FLAG HSL_RW 1088 1089#define IGMP_MLD_EN 1090#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET 0 1091#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN 1 1092#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG HSL_RW 1093 1094 1095 1096 1097 /* Frame Ack Ctl1 Register */ 1098#define FRAME_ACK_CTL1 1099#define FRAME_ACK_CTL1_OFFSET 0x0214 1100#define FRAME_ACK_CTL1_E_LENGTH 4 1101#define FRAME_ACK_CTL1_E_OFFSET 0 1102#define FRAME_ACK_CTL1_NR_E 1 1103 1104#define PPPOE_EN 1105#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET 25 1106#define FRAME_ACK_CTL1_PPPOE_EN_BLEN 1 1107#define FRAME_ACK_CTL1_PPPOE_EN_FLAG HSL_RW 1108 1109#define IGMP_V3_EN 1110#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET 24 1111#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN 1 1112#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG HSL_RW 1113 1114 1115 1116 1117 /* Window Rule Ctl0 Register */ 1118#define WIN_RULE_CTL0 1119#define WIN_RULE_CTL0_OFFSET 0x0218 1120#define WIN_RULE_CTL0_E_LENGTH 4 1121#define WIN_RULE_CTL0_E_OFFSET 0x4 1122#define WIN_RULE_CTL0_NR_E 7 1123 1124#define L4_LENGTH 1125#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET 24 1126#define WIN_RULE_CTL0_L4_LENGTH_BLEN 4 1127#define WIN_RULE_CTL0_L4_LENGTH_FLAG HSL_RW 1128 1129#define L3_LENGTH 1130#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET 20 1131#define WIN_RULE_CTL0_L3_LENGTH_BLEN 4 1132#define WIN_RULE_CTL0_L3_LENGTH_FLAG HSL_RW 1133 1134#define L2_LENGTH 1135#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET 16 1136#define WIN_RULE_CTL0_L2_LENGTH_BLEN 4 1137#define WIN_RULE_CTL0_L2_LENGTH_FLAG HSL_RW 1138 1139#define L4_OFFSET 1140#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET 10 1141#define WIN_RULE_CTL0_L4_OFFSET_BLEN 5 1142#define WIN_RULE_CTL0_L4_OFFSET_FLAG HSL_RW 1143 1144#define L3_OFFSET 1145#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET 5 1146#define WIN_RULE_CTL0_L3_OFFSET_BLEN 5 1147#define WIN_RULE_CTL0_L3_OFFSET_FLAG HSL_RW 1148 1149#define L2_OFFSET 1150#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET 0 1151#define WIN_RULE_CTL0_L2_OFFSET_BLEN 5 1152#define WIN_RULE_CTL0_L2_OFFSET_FLAG HSL_RW 1153 1154 1155 1156 1157 /* Window Rule Ctl1 Register */ 1158#define WIN_RULE_CTL1 1159#define WIN_RULE_CTL1_OFFSET 0x0234 1160#define WIN_RULE_CTL1_E_LENGTH 4 1161#define WIN_RULE_CTL1_E_OFFSET 0x4 1162#define WIN_RULE_CTL1_NR_E 7 1163 1164#define L3P_LENGTH 1165#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET 20 1166#define WIN_RULE_CTL1_L3P_LENGTH_BLEN 4 1167#define WIN_RULE_CTL1_L3P_LENGTH_FLAG HSL_RW 1168 1169#define L2S_LENGTH 1170#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET 16 1171#define WIN_RULE_CTL1_L2S_LENGTH_BLEN 4 1172#define WIN_RULE_CTL1_L2S_LENGTH_FLAG HSL_RW 1173 1174#define L3P_OFFSET 1175#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET 5 1176#define WIN_RULE_CTL1_L3P_OFFSET_BLEN 5 1177#define WIN_RULE_CTL1_L3P_OFFSET_FLAG HSL_RW 1178 1179#define L2S_OFFSET 1180#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET 0 1181#define WIN_RULE_CTL1_L2S_OFFSET_BLEN 5 1182#define WIN_RULE_CTL1_L2S_OFFSET_FLAG HSL_RW 1183 1184 1185 1186 1187 /* Trunk Hash Mode Register */ 1188#define TRUNK_HASH_MODE 1189#define TRUNK_HASH_MODE_OFFSET 0x0270 1190#define TRUNK_HASH_MODE_E_LENGTH 4 1191#define TRUNK_HASH_MODE_E_OFFSET 0x4 1192#define TRUNK_HASH_MODE_NR_E 1 1193 1194#define SIP_EN 1195#define TRUNK_HASH_MODE_SIP_EN_BOFFSET 3 1196#define TRUNK_HASH_MODE_SIP_EN_BLEN 1 1197#define TRUNK_HASH_MODE_SIP_EN_FLAG HSL_RW 1198 1199#define DIP_EN 1200#define TRUNK_HASH_MODE_DIP_EN_BOFFSET 2 1201#define TRUNK_HASH_MODE_DIP_EN_BLEN 1 1202#define TRUNK_HASH_MODE_DIP_EN_FLAG HSL_RW 1203 1204#define SA_EN 1205#define TRUNK_HASH_MODE_SA_EN_BOFFSET 1 1206#define TRUNK_HASH_MODE_SA_EN_BLEN 1 1207#define TRUNK_HASH_MODE_SA_EN_FLAG HSL_RW 1208 1209#define DA_EN 1210#define TRUNK_HASH_MODE_DA_EN_BOFFSET 0 1211#define TRUNK_HASH_MODE_DA_EN_BLEN 1 1212#define TRUNK_HASH_MODE_DA_EN_FLAG HSL_RW 1213 1214 1215 1216 1217 /* Vlan Table Function0 Register */ 1218#define VLAN_TABLE_FUNC0 1219#define VLAN_TABLE_FUNC0_OFFSET 0x0610 1220#define VLAN_TABLE_FUNC0_E_LENGTH 4 1221#define VLAN_TABLE_FUNC0_E_OFFSET 0 1222#define VLAN_TABLE_FUNC0_NR_E 1 1223 1224#define VT_VALID 1225#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET 20 1226#define VLAN_TABLE_FUNC0_VT_VALID_BLEN 1 1227#define VLAN_TABLE_FUNC0_VT_VALID_FLAG HSL_RW 1228 1229#define IVL_EN 1230#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET 19 1231#define VLAN_TABLE_FUNC0_IVL_EN_BLEN 1 1232#define VLAN_TABLE_FUNC0_IVL_EN_FLAG HSL_RW 1233 1234#define LEARN_DIS 1235#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET 18 1236#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN 1 1237#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG HSL_RW 1238 1239#define VID_MEM 1240#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET 4 1241#define VLAN_TABLE_FUNC0_VID_MEM_BLEN 14 1242#define VLAN_TABLE_FUNC0_VID_MEM_FLAG HSL_RW 1243 1244#define VT_PRI_EN 1245#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 3 1246#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 1247#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW 1248 1249#define VT_PRI 1250#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 0 1251#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 1252#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW 1253 1254 /* Vlan Table Function1 Register */ 1255#define VLAN_TABLE_FUNC1 1256#define VLAN_TABLE_FUNC1_OFFSET 0x0614 1257#define VLAN_TABLE_FUNC1_E_LENGTH 4 1258#define VLAN_TABLE_FUNC1_E_OFFSET 0 1259#define VLAN_TABLE_FUNC1_NR_E 1 1260 1261#define VT_BUSY 1262#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET 31 1263#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN 1 1264#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG HSL_RW 1265 1266#define VLAN_ID 1267#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET 16 1268#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN 12 1269#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG HSL_RW 1270 1271#define VT_PORT_NUM 1272#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET 8 1273#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN 4 1274#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG HSL_RW 1275 1276#define VT_FULL_VIO 1277#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET 4 1278#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN 1 1279#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG HSL_RW 1280 1281#define VT_FUNC 1282#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET 0 1283#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN 3 1284#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG HSL_RW 1285 1286 1287 1288 1289 /* Address Table Function0 Register */ 1290#define ADDR_TABLE_FUNC0 1291#define ADDR_TABLE_FUNC0_OFFSET 0x0600 1292#define ADDR_TABLE_FUNC0_E_LENGTH 4 1293#define ADDR_TABLE_FUNC0_E_OFFSET 0 1294#define ADDR_TABLE_FUNC0_NR_E 1 1295 1296 1297#define AT_ADDR_BYTE2 1298#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24 1299#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN 8 1300#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG HSL_RW 1301 1302#define AT_ADDR_BYTE3 1303#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16 1304#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN 8 1305#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG HSL_RW 1306 1307#define AT_ADDR_BYTE4 1308#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8 1309#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 1310#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW 1311 1312#define AT_ADDR_BYTE5 1313#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0 1314#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 1315#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW 1316 1317 /* Address Table Function1 Register */ 1318#define ADDR_TABLE_FUNC1 1319#define ADDR_TABLE_FUNC1_OFFSET 0x0604 1320#define ADDR_TABLE_FUNC1_E_LENGTH 4 1321#define ADDR_TABLE_FUNC1_E_OFFSET 0 1322#define ADDR_TABLE_FUNC1_NR_E 1 1323 1324#define SA_DROP_EN 1325#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET 30 1326#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN 1 1327#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG HSL_RW 1328 1329#define MIRROR_EN 1330#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET 29 1331#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN 1 1332#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG HSL_RW 1333 1334#define AT_PRI_EN 1335#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET 28 1336#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN 1 1337#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG HSL_RW 1338 1339#define AT_SVL_EN 1340#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET 27 1341#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN 1 1342#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG HSL_RW 1343 1344#define AT_PRI 1345#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET 24 1346#define ADDR_TABLE_FUNC1_AT_PRI_BLEN 3 1347#define ADDR_TABLE_FUNC1_AT_PRI_FLAG HSL_RW 1348 1349#define CROSS_PT 1350#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET 23 1351#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN 1 1352#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG HSL_RW 1353 1354#define DES_PORT 1355#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET 16 1356#define ADDR_TABLE_FUNC1_DES_PORT_BLEN 7 1357#define ADDR_TABLE_FUNC1_DES_PORT_FLAG HSL_RW 1358 1359#define AT_ADDR_BYTE0 1360#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8 1361#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 1362#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW 1363 1364#define AT_ADDR_BYTE1 1365#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0 1366#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 1367#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW 1368 1369 /* Address Table Function2 Register */ 1370#define ADDR_TABLE_FUNC2 1371#define ADDR_TABLE_FUNC2_OFFSET 0x0608 1372#define ADDR_TABLE_FUNC2_E_LENGTH 4 1373#define ADDR_TABLE_FUNC2_E_OFFSET 0 1374#define ADDR_TABLE_FUNC2_NR_E 1 1375 1376#define WL_EN 1377#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET 20 1378#define ADDR_TABLE_FUNC2_WL_EN_BLEN 1 1379#define ADDR_TABLE_FUNC2_WL_EN_FLAG HSL_RW 1380 1381#define AT_VID 1382#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET 8 1383#define ADDR_TABLE_FUNC2_AT_VID_BLEN 12 1384#define ADDR_TABLE_FUNC2_AT_VID_FLAG HSL_RW 1385 1386#define SHORT_LOOP 1387#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET 7 1388#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN 1 1389#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG HSL_RW 1390 1391#define COPY_TO_CPU 1392#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 6 1393#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 1394#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW 1395 1396#define REDRCT_TO_CPU 1397#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5 1398#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 1399#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW 1400 1401#define LEAKY_EN 1402#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 4 1403#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 1404#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW 1405 1406#define AT_STATUS 1407#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 0 1408#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 1409#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW 1410 1411 /* Address Table Function3 Register */ 1412#define ADDR_TABLE_FUNC3 1413#define ADDR_TABLE_FUNC3_OFFSET 0x060c 1414#define ADDR_TABLE_FUNC3_E_LENGTH 4 1415#define ADDR_TABLE_FUNC3_E_OFFSET 0 1416#define ADDR_TABLE_FUNC3_NR_E 1 1417 1418#define AT_BUSY 1419#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET 31 1420#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN 1 1421#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG HSL_RW 1422 1423#define NEW_PORT_NUM 1424#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET 22 1425#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN 3 1426#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG HSL_RW 1427 1428#define AT_INDEX 1429#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET 16 1430#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN 5 1431#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG HSL_RW 1432 1433#define AT_VID_EN 1434#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET 15 1435#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN 1 1436#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG HSL_RW 1437 1438#define AT_PORT_EN 1439#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET 14 1440#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN 1 1441#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG HSL_RW 1442 1443#define AT_MULTI_EN 1444#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET 13 1445#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN 1 1446#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG HSL_RW 1447 1448#define AT_FULL_VIO 1449#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET 12 1450#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN 1 1451#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG HSL_RW 1452 1453#define AT_PORT_NUM 1454#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET 8 1455#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN 4 1456#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG HSL_RW 1457 1458#define FLUSH_ST_EN 1459#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET 4 1460#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN 1 1461#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG HSL_RW 1462 1463#define AT_FUNC 1464#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET 0 1465#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN 4 1466#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG HSL_RW 1467 1468 1469 1470 1471 /* Reserve Address Table0 Register */ 1472#define RESV_ADDR_TBL0 1473#define RESV_ADDR_TBL0_OFFSET 0x3c000 1474#define RESV_ADDR_TBL0_E_LENGTH 4 1475#define RESV_ADDR_TBL0_E_OFFSET 0 1476#define RESV_ADDR_TBL0_NR_E 1 1477 1478#define RESV_ADDR_BYTE2 1479#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24 1480#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN 8 1481#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG HSL_RW 1482 1483#define RESV_ADDR_BYTE3 1484#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16 1485#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN 8 1486#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG HSL_RW 1487 1488#define RESV_ADDR_BYTE4 1489#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8 1490#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN 8 1491#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG HSL_RW 1492 1493#define RESV_ADDR_BYTE5 1494#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0 1495#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN 8 1496#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG HSL_RW 1497 1498 /* Reserve Address Table1 Register */ 1499#define RESV_ADDR_TBL1 1500#define RESV_ADDR_TBL1_OFFSET 0x3c004 1501#define RESV_ADDR_TBL1_E_LENGTH 4 1502#define RESV_ADDR_TBL1_E_OFFSET 0 1503#define RESV_ADDR_TBL1_NR_E 1 1504 1505#define RESV_COPY_TO_CPU 1506#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET 31 1507#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN 1 1508#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG HSL_RW 1509 1510#define RESV_REDRCT_TO_CPU 1511#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30 1512#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN 1 1513#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG HSL_RW 1514 1515#define RESV_LEAKY_EN 1516#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET 29 1517#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN 1 1518#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG HSL_RW 1519 1520#define RESV_MIRROR_EN 1521#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET 28 1522#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN 1 1523#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG HSL_RW 1524 1525#define RESV_PRI_EN 1526#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET 27 1527#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN 1 1528#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG HSL_RW 1529 1530#define RESV_PRI 1531#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET 24 1532#define RESV_ADDR_TBL1_RESV_PRI_BLEN 3 1533#define RESV_ADDR_TBL1_RESV_PRI_FLAG HSL_RW 1534 1535#define RESV_CROSS_PT 1536#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET 23 1537#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN 1 1538#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG HSL_RW 1539 1540#define RESV_DES_PORT 1541#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET 16 1542#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN 7 1543#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG HSL_RW 1544 1545#define RESV_ADDR_BYTE0 1546#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8 1547#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN 8 1548#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG HSL_RW 1549 1550#define RESV_ADDR_BYTE1 1551#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0 1552#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN 8 1553#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG HSL_RW 1554 1555 /* Reserve Address Table2 Register */ 1556#define RESV_ADDR_TBL2 1557#define RESV_ADDR_TBL2_OFFSET 0x3c008 1558#define RESV_ADDR_TBL2_E_LENGTH 4 1559#define RESV_ADDR_TBL2_E_OFFSET 0 1560#define RESV_ADDR_TBL2_NR_E 1 1561 1562#define RESV_STATUS 1563#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET 0 1564#define RESV_ADDR_TBL2_RESV_STATUS_BLEN 1 1565#define RESV_ADDR_TBL2_RESV_STATUS_FLAG HSL_RW 1566 1567 1568 1569 1570 /* Address Table Control Register */ 1571#define ADDR_TABLE_CTL 1572#define ADDR_TABLE_CTL_OFFSET 0x0618 1573#define ADDR_TABLE_CTL_E_LENGTH 4 1574#define ADDR_TABLE_CTL_E_OFFSET 0 1575#define ADDR_TABLE_CTL_NR_E 1 1576 1577#define ARL_INI_EN 1578#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 31 1579#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 1580#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW 1581 1582#define LEARN_CHANGE_EN 1583#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 30 1584#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 1585#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW 1586 1587#define IGMP_JOIN_LEAKY 1588#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET 29 1589#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN 1 1590#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW 1591 1592#define IGMP_CREAT_EN 1593#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET 28 1594#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN 1 1595#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG HSL_RW 1596 1597#define IGMP_PRI_EN 1598#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET 27 1599#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN 1 1600#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG HSL_RW 1601 1602#define IGMP_PRI 1603#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET 24 1604#define ADDR_TABLE_CTL_IGMP_PRI_BLEN 3 1605#define ADDR_TABLE_CTL_IGMP_PRI_FLAG HSL_RW 1606 1607#define IGMP_JOIN_STATIC 1608#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET 20 1609#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN 4 1610#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW 1611 1612#define AGE_EN 1613#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 19 1614#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 1615#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW 1616 1617#define LOOP_CHECK_TIMER 1618#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET 16 1619#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN 3 1620#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG HSL_RW 1621 1622#define AGE_TIME 1623#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 1624#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 1625#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW 1626 1627 1628 1629 1630 /* Global Forward Control0 Register */ 1631#define FORWARD_CTL0 1632#define FORWARD_CTL0_OFFSET 0x0620 1633#define FORWARD_CTL0_E_LENGTH 4 1634#define FORWARD_CTL0_E_OFFSET 0 1635#define FORWARD_CTL0_NR_E 1 1636 1637#define ARP_CMD 1638#define FORWARD_CTL0_ARP_CMD_BOFFSET 26 1639#define FORWARD_CTL0_ARP_CMD_BLEN 2 1640#define FORWARD_CTL0_ARP_CMD_FLAG HSL_RW 1641 1642#define IP_NOT_FOUND 1643#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET 24 1644#define FORWARD_CTL0_IP_NOT_FOUND_BLEN 2 1645#define FORWARD_CTL0_IP_NOT_FOUND_FLAG HSL_RW 1646 1647#define ARP_NOT_FOUND 1648#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET 22 1649#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN 2 1650#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG HSL_RW 1651 1652#define HASH_MODE 1653#define FORWARD_CTL0_HASH_MODE_BOFFSET 20 1654#define FORWARD_CTL0_HASH_MODE_BLEN 2 1655#define FORWARD_CTL0_HASH_MODE_FLAG HSL_RW 1656 1657#define NAT_NOT_FOUND_DROP 1658#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET 17 1659#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN 1 1660#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG HSL_RW 1661 1662#define SP_NOT_FOUND_DROP 1663#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET 16 1664#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN 1 1665#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG HSL_RW 1666 1667#define IGMP_LEAVE_DROP 1668#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET 14 1669#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN 1 1670#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG HSL_RW 1671 1672#define ARL_UNI_LEAKY 1673#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET 13 1674#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN 1 1675#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG HSL_RW 1676 1677#define ARL_MUL_LEAKY 1678#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET 12 1679#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN 1 1680#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG HSL_RW 1681 1682#define MANAGE_VID_VIO_DROP_EN 1683#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11 1684#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN 1 1685#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW 1686 1687#define CPU_PORT_EN 1688#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET 10 1689#define FORWARD_CTL0_CPU_PORT_EN_BLEN 1 1690#define FORWARD_CTL0_CPU_PORT_EN_FLAG HSL_RW 1691 1692#define PPPOE_RDT_EN 1693#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET 8 1694#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN 1 1695#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG HSL_RW 1696 1697#define MIRROR_PORT_NUM 1698#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET 4 1699#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN 4 1700#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG HSL_RW 1701 1702#define IGMP_COPY_EN 1703#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET 3 1704#define FORWARD_CTL0_IGMP_COPY_EN_BLEN 1 1705#define FORWARD_CTL0_IGMP_COPY_EN_FLAG HSL_RW 1706 1707#define RIP_CPY_EN 1708#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET 2 1709#define FORWARD_CTL0_RIP_CPY_EN_BLEN 1 1710#define FORWARD_CTL0_RIP_CPY_EN_FLAG HSL_RW 1711 1712#define EAPOL_CMD 1713#define FORWARD_CTL0_EAPOL_CMD_BOFFSET 0 1714#define FORWARD_CTL0_EAPOL_CMD_BLEN 1 1715#define FORWARD_CTL0_EAPOL_CMD_FLAG HSL_RW 1716 1717 /* Global Forward Control1 Register */ 1718#define FORWARD_CTL1 1719#define FORWARD_CTL1_OFFSET 0x0624 1720#define FORWARD_CTL1_E_LENGTH 4 1721#define FORWARD_CTL1_E_OFFSET 0 1722#define FORWARD_CTL1_NR_E 1 1723 1724#define IGMP_DP 1725#define FORWARD_CTL1_IGMP_DP_BOFFSET 24 1726#define FORWARD_CTL1_IGMP_DP_BLEN 7 1727#define FORWARD_CTL1_IGMP_DP_FLAG HSL_RW 1728 1729#define BC_FLOOD_DP 1730#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16 1731#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7 1732#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW 1733 1734#define MUL_FLOOD_DP 1735#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET 8 1736#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN 7 1737#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG HSL_RW 1738 1739#define UNI_FLOOD_DP 1740#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET 0 1741#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN 7 1742#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG HSL_RW 1743 1744 1745 1746 1747 /* Global Learn Limit Ctl Register */ 1748#define GLOBAL_LEARN_LIMIT_CTL 1749#define GLOBAL_LEARN_LIMIT_CTL_OFFSET 0x0628 1750#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH 4 1751#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET 0 1752#define GLOBAL_LEARN_LIMIT_CTL_NR_E 1 1753 1754#define GOL_SA_LEARN_LIMIT_EN 1755#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET 12 1756#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN 1 1757#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG HSL_RW 1758 1759#define GOL_SA_LEARN_LIMIT_DROP_EN 1760#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 11 1761#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 1762#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW 1763 1764#define GOL_SA_LEARN_CNT 1765#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET 0 1766#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN 11 1767#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG HSL_RW 1768 1769 1770 1771 1772 /* DSCP To Priority Register */ 1773#define DSCP_TO_PRI 1774#define DSCP_TO_PRI_OFFSET 0x0630 1775#define DSCP_TO_PRI_E_LENGTH 4 1776#define DSCP_TO_PRI_E_OFFSET 0x0004 1777#define DSCP_TO_PRI_NR_E 8 1778 1779 1780 1781 1782 /* UP To Priority Register */ 1783#define UP_TO_PRI 1784#define UP_TO_PRI_OFFSET 0x0650 1785#define UP_TO_PRI_E_LENGTH 4 1786#define UP_TO_PRI_E_OFFSET 0x0004 1787#define UP_TO_PRI_NR_E 1 1788 1789 1790 1791 1792 /* Port Lookup control Register */ 1793#define PORT_LOOKUP_CTL 1794#define PORT_LOOKUP_CTL_OFFSET 0x0660 1795#define PORT_LOOKUP_CTL_E_LENGTH 4 1796#define PORT_LOOKUP_CTL_E_OFFSET 0x000c 1797#define PORT_LOOKUP_CTL_NR_E 7 1798 1799#define MULTI_DROP_EN 1800#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET 31 1801#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN 1 1802#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG HSL_RW 1803 1804#define UNI_LEAKY_EN 1805#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET 28 1806#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN 1 1807#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG HSL_RW 1808 1809#define MUL_LEAKY_EN 1810#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET 27 1811#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN 1 1812#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG HSL_RW 1813 1814#define ARP_LEAKY_EN 1815#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET 26 1816#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN 1 1817#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG HSL_RW 1818 1819#define ING_MIRROR_EN 1820#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET 25 1821#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN 1 1822#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG HSL_RW 1823 1824#define PORT_LOOP_BACK 1825#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET 21 1826#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN 1 1827#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG HSL_RW 1828 1829#define LEARN_EN 1830#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET 20 1831#define PORT_LOOKUP_CTL_LEARN_EN_BLEN 1 1832#define PORT_LOOKUP_CTL_LEARN_EN_FLAG HSL_RW 1833 1834#define PORT_STATE 1835#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET 16 1836#define PORT_LOOKUP_CTL_PORT_STATE_BLEN 3 1837#define PORT_LOOKUP_CTL_PORT_STATE_FLAG HSL_RW 1838 1839#define FORCE_PVLAN 1840#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET 10 1841#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN 1 1842#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG HSL_RW 1843 1844#define DOT1Q_MODE 1845#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET 8 1846#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN 2 1847#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG HSL_RW 1848 1849#define PORT_VID_MEM 1850#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET 0 1851#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN 7 1852#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG HSL_RW 1853 1854 1855 1856 1857 /* Priority Control Register */ 1858#define PRI_CTL 1859#define PRI_CTL_OFFSET 0x0664 1860#define PRI_CTL_E_LENGTH 4 1861#define PRI_CTL_E_OFFSET 0x000c 1862#define PRI_CTL_NR_E 7 1863 1864#define EG_MAC_BASE_VLAN_EN 1865#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET 20 1866#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN 1 1867#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG HSL_RW 1868 1869#define DA_PRI_EN 1870#define PRI_CTL_DA_PRI_EN_BOFFSET 18 1871#define PRI_CTL_DA_PRI_EN_BLEN 1 1872#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW 1873 1874#define VLAN_PRI_EN 1875#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 1876#define PRI_CTL_VLAN_PRI_EN_BLEN 1 1877#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW 1878 1879#define IP_PRI_EN 1880#define PRI_CTL_IP_PRI_EN_BOFFSET 16 1881#define PRI_CTL_IP_PRI_EN_BLEN 1 1882#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW 1883 1884#define DA_PRI_SEL 1885#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 1886#define PRI_CTL_DA_PRI_SEL_BLEN 2 1887#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW 1888 1889#define VLAN_PRI_SEL 1890#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 1891#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 1892#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW 1893 1894#define IP_PRI_SEL 1895#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 1896#define PRI_CTL_IP_PRI_SEL_BLEN 2 1897#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW 1898 1899 1900 1901 /* Port Learn Limit Ctl Register */ 1902#define PORT_LEARN_LIMIT_CTL 1903#define PORT_LEARN_LIMIT_CTL_OFFSET 0x0668 1904#define PORT_LEARN_LIMIT_CTL_E_LENGTH 4 1905#define PORT_LEARN_LIMIT_CTL_E_OFFSET 0x000c 1906#define PORT_LEARN_LIMIT_CTL_NR_E 7 1907 1908#define IGMP_JOIN_LIMIT_EN 1909#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET 27 1910#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN 1 1911#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG HSL_RW 1912 1913#define IGMP_JOIN_LIMIT_DROP_EN 1914#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET 26 1915#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN 1 1916#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG HSL_RW 1917 1918#define IGMP_JOIN_CNT 1919#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET 16 1920#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN 10 1921#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG HSL_RW 1922 1923#define SA_LEARN_STATUS 1924#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET 12 1925#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN 4 1926#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG HSL_RW 1927 1928#define SA_LEARN_LIMIT_EN 1929#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET 11 1930#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN 1 1931#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG HSL_RW 1932 1933#define SA_LEARN_LIMIT_DROP_EN 1934#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 10 1935#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 1936#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW 1937 1938#define SA_LEARN_CNT 1939#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET 0 1940#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN 10 1941#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG HSL_RW 1942 1943 1944 1945 /* Global Trunk Ctl0 Register */ 1946#define GOL_TRUNK_CTL0 1947#define GOL_TRUNK_CTL0_OFFSET 0x0700 1948#define GOL_TRUNK_CTL0_E_LENGTH 4 1949#define GOL_TRUNK_CTL0_E_OFFSET 0x4 1950#define GOL_TRUNK_CTL0_NR_E 1 1951 1952 1953 /* Global Trunk Ctl1 Register */ 1954#define GOL_TRUNK_CTL1 1955#define GOL_TRUNK_CTL1_OFFSET 0x0704 1956#define GOL_TRUNK_CTL1_E_LENGTH 4 1957#define GOL_TRUNK_CTL1_E_OFFSET 0x4 1958#define GOL_TRUNK_CTL1_NR_E 2 1959 1960 1961 1962 1963 /* Port vlan0 Register */ 1964#define PORT_VLAN0 1965#define PORT_VLAN0_OFFSET 0x0420 1966#define PORT_VLAN0_E_LENGTH 4 1967#define PORT_VLAN0_E_OFFSET 0x0008 1968#define PORT_VLAN0_NR_E 7 1969 1970#define ING_CPRI 1971#define PORT_VLAN0_ING_CPRI_BOFFSET 29 1972#define PORT_VLAN0_ING_CPRI_BLEN 3 1973#define PORT_VLAN0_ING_CPRI_FLAG HSL_RW 1974 1975#define DEF_CVID 1976#define PORT_VLAN0_DEF_CVID_BOFFSET 16 1977#define PORT_VLAN0_DEF_CVID_BLEN 12 1978#define PORT_VLAN0_DEF_CVID_FLAG HSL_RW 1979 1980#define ING_SPRI 1981#define PORT_VLAN0_ING_SPRI_BOFFSET 13 1982#define PORT_VLAN0_ING_SPRI_BLEN 3 1983#define PORT_VLAN0_ING_SPRI_FLAG HSL_RW 1984 1985#define DEF_SVID 1986#define PORT_VLAN0_DEF_SVID_BOFFSET 0 1987#define PORT_VLAN0_DEF_SVID_BLEN 12 1988#define PORT_VLAN0_DEF_SVID_FLAG HSL_RW 1989 1990 /* Port vlan1 Register */ 1991#define PORT_VLAN1 1992#define PORT_VLAN1_OFFSET 0x0424 1993#define PORT_VLAN1_E_LENGTH 4 1994#define PORT_VLAN1_E_OFFSET 0x0008 1995#define PORT_VLAN1_NR_E 7 1996 1997#define EG_VLAN_MODE 1998#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET 12 1999#define PORT_VLAN1_EG_VLAN_MODE_BLEN 2 2000#define PORT_VLAN1_EG_VLAN_MODE_FLAG HSL_RW 2001 2002#define VLAN_DIS 2003#define PORT_VLAN1_VLAN_DIS_BOFFSET 11 2004#define PORT_VLAN1_VLAN_DIS_BLEN 1 2005#define PORT_VLAN1_VLAN_DIS_FLAG HSL_RW 2006 2007#define SP_CHECK_EN 2008#define PORT_VLAN1_SP_CHECK_EN_BOFFSET 10 2009#define PORT_VLAN1_SP_CHECK_EN_BLEN 1 2010#define PORT_VLAN1_SP_CHECK_EN_FLAG HSL_RW 2011 2012#define COREP_EN 2013#define PORT_VLAN1_COREP_EN_BOFFSET 9 2014#define PORT_VLAN1_COREP_EN_BLEN 1 2015#define PORT_VLAN1_COREP_EN_FLAG HSL_RW 2016 2017#define FORCE_DEF_VID 2018#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET 8 2019#define PORT_VLAN1_FORCE_DEF_VID_BLEN 1 2020#define PORT_VLAN1_FORCE_DEF_VID_FLAG HSL_RW 2021 2022#define TLS_EN 2023#define PORT_VLAN1_TLS_EN_BOFFSET 7 2024#define PORT_VLAN1_TLS_EN_BLEN 1 2025#define PORT_VLAN1_TLS_EN_FLAG HSL_RW 2026 2027#define PROPAGATION_EN 2028#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6 2029#define PORT_VLAN1_PROPAGATION_EN_BLEN 1 2030#define PORT_VLAN1_PROPAGATION_EN_FLAG HSL_RW 2031 2032#define CLONE 2033#define PORT_VLAN1_CLONE_BOFFSET 5 2034#define PORT_VLAN1_CLONE_BLEN 1 2035#define PORT_VLAN1_CLONE_FLAG HSL_RW 2036 2037#define PRI_PROPAGATION 2038#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET 4 2039#define PORT_VLAN1_PRI_PROPAGATION_BLEN 1 2040#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW 2041 2042#define IN_VLAN_MODE 2043#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET 2 2044#define PORT_VLAN1_IN_VLAN_MODE_BLEN 2 2045#define PORT_VLAN1_IN_VLAN_MODE_FLAG HSL_RW 2046 2047 2048 /* Route Default VID Register */ 2049#define ROUTER_DEFV 2050#define ROUTER_DEFV_OFFSET 0x0c70 2051#define ROUTER_DEFV_E_LENGTH 4 2052#define ROUTER_DEFV_E_OFFSET 0x0004 2053#define ROUTER_DEFV_NR_E 4 2054 2055 2056 /* Route Egress VLAN Mode Register */ 2057#define ROUTER_EG 2058#define ROUTER_EG_OFFSET 0x0c80 2059#define ROUTER_EG_E_LENGTH 4 2060#define ROUTER_EG_E_OFFSET 0x0004 2061#define ROUTER_EG_NR_E 1 2062 2063 2064 2065 2066 /* Mdio control Register */ 2067#define MDIO_CTRL "mctrl" 2068#define MDIO_CTRL_ID 24 2069#define MDIO_CTRL_OFFSET 0x0098 2070#define MDIO_CTRL_E_LENGTH 4 2071#define MDIO_CTRL_E_OFFSET 0 2072#define MDIO_CTRL_NR_E 1 2073 2074#define MSTER_EN "mctrl_msteren" 2075#define MDIO_CTRL_MSTER_EN_BOFFSET 30 2076#define MDIO_CTRL_MSTER_EN_BLEN 1 2077#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW 2078 2079#define MSTER_EN "mctrl_msteren" 2080#define MDIO_CTRL_MSTER_EN_BOFFSET 30 2081#define MDIO_CTRL_MSTER_EN_BLEN 1 2082#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW 2083 2084#define CMD "mctrl_cmd" 2085#define MDIO_CTRL_CMD_BOFFSET 27 2086#define MDIO_CTRL_CMD_BLEN 1 2087#define MDIO_CTRL_CMD_FLAG HSL_RW 2088 2089#define SUP_PRE "mctrl_spre" 2090#define MDIO_CTRL_SUP_PRE_BOFFSET 26 2091#define MDIO_CTRL_SUP_PRE_BLEN 1 2092#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW 2093 2094#define PHY_ADDR "mctrl_phyaddr" 2095#define MDIO_CTRL_PHY_ADDR_BOFFSET 21 2096#define MDIO_CTRL_PHY_ADDR_BLEN 5 2097#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW 2098 2099#define REG_ADDR "mctrl_regaddr" 2100#define MDIO_CTRL_REG_ADDR_BOFFSET 16 2101#define MDIO_CTRL_REG_ADDR_BLEN 5 2102#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW 2103 2104#define DATA "mctrl_data" 2105#define MDIO_CTRL_DATA_BOFFSET 0 2106#define MDIO_CTRL_DATA_BLEN 16 2107#define MDIO_CTRL_DATA_FLAG HSL_RW 2108 2109 2110 2111 2112 /* BIST control Register */ 2113#define BIST_CTRL "bctrl" 2114#define BIST_CTRL_ID 24 2115#define BIST_CTRL_OFFSET 0x00a0 2116#define BIST_CTRL_E_LENGTH 4 2117#define BIST_CTRL_E_OFFSET 0 2118#define BIST_CTRL_NR_E 1 2119 2120#define BIST_BUSY "bctrl_bb" 2121#define BIST_CTRL_BIST_BUSY_BOFFSET 31 2122#define BIST_CTRL_BIST_BUSY_BLEN 1 2123#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW 2124 2125#define ONE_ERR "bctrl_oe" 2126#define BIST_CTRL_ONE_ERR_BOFFSET 30 2127#define BIST_CTRL_ONE_ERR_BLEN 1 2128#define BIST_CTRL_ONE_ERR_FLAG HSL_RO 2129 2130#define ERR_MEM "bctrl_em" 2131#define BIST_CTRL_ERR_MEM_BOFFSET 24 2132#define BIST_CTRL_ERR_MEM_BLEN 4 2133#define BIST_CTRL_ERR_MEM_FLAG HSL_RO 2134 2135#define PTN_EN2 "bctrl_pe2" 2136#define BIST_CTRL_PTN_EN2_BOFFSET 22 2137#define BIST_CTRL_PTN_EN2_BLEN 1 2138#define BIST_CTRL_PTN_EN2_FLAG HSL_RW 2139 2140#define PTN_EN1 "bctrl_pe1" 2141#define BIST_CTRL_PTN_EN1_BOFFSET 21 2142#define BIST_CTRL_PTN_EN1_BLEN 1 2143#define BIST_CTRL_PTN_EN1_FLAG HSL_RW 2144 2145#define PTN_EN0 "bctrl_pe0" 2146#define BIST_CTRL_PTN_EN0_BOFFSET 20 2147#define BIST_CTRL_PTN_EN0_BLEN 1 2148#define BIST_CTRL_PTN_EN0_FLAG HSL_RW 2149 2150#define ERR_PTN "bctrl_ep" 2151#define BIST_CTRL_ERR_PTN_BOFFSET 16 2152#define BIST_CTRL_ERR_PTN_BLEN 2 2153#define BIST_CTRL_ERR_PTN_FLAG HSL_RO 2154 2155#define ERR_CNT "bctrl_ec" 2156#define BIST_CTRL_ERR_CNT_BOFFSET 13 2157#define BIST_CTRL_ERR_CNT_BLEN 2 2158#define BIST_CTRL_ERR_CNT_FLAG HSL_RO 2159 2160#define ERR_ADDR "bctrl_ea" 2161#define BIST_CTRL_ERR_ADDR_BOFFSET 0 2162#define BIST_CTRL_ERR_ADDR_BLEN 12 2163#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO 2164 2165 2166 2167 2168 /* BIST recover Register */ 2169#define BIST_RCV "brcv" 2170#define BIST_RCV_ID 24 2171#define BIST_RCV_OFFSET 0x00a4 2172#define BIST_RCV_E_LENGTH 4 2173#define BIST_RCV_E_OFFSET 0 2174#define BIST_RCV_NR_E 1 2175 2176#define RCV_EN "brcv_en" 2177#define BIST_RCV_RCV_EN_BOFFSET 31 2178#define BIST_RCV_RCV_EN_BLEN 1 2179#define BIST_RCV_RCV_EN_FLAG HSL_RW 2180 2181#define RCV_ADDR "brcv_addr" 2182#define BIST_RCV_RCV_ADDR_BOFFSET 0 2183#define BIST_RCV_RCV_ADDR_BLEN 12 2184#define BIST_RCV_RCV_ADDR_FLAG HSL_RW 2185 2186 2187 2188 2189 /* LED control Register */ 2190#define LED_CTRL "ledctrl" 2191#define LED_CTRL_ID 25 2192#define LED_CTRL_OFFSET 0x0050 2193#define LED_CTRL_E_LENGTH 4 2194#define LED_CTRL_E_OFFSET 0 2195#define LED_CTRL_NR_E 3 2196 2197#define PATTERN_EN "lctrl_pen" 2198#define LED_CTRL_PATTERN_EN_BOFFSET 14 2199#define LED_CTRL_PATTERN_EN_BLEN 2 2200#define LED_CTRL_PATTERN_EN_FLAG HSL_RW 2201 2202#define FULL_LIGHT_EN "lctrl_fen" 2203#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 2204#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 2205#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW 2206 2207#define HALF_LIGHT_EN "lctrl_hen" 2208#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 2209#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 2210#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW 2211 2212#define POWERON_LIGHT_EN "lctrl_poen" 2213#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 2214#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 2215#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW 2216 2217#define GE_LIGHT_EN "lctrl_geen" 2218#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 2219#define LED_CTRL_GE_LIGHT_EN_BLEN 1 2220#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW 2221 2222#define FE_LIGHT_EN "lctrl_feen" 2223#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 2224#define LED_CTRL_FE_LIGHT_EN_BLEN 1 2225#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW 2226 2227#define ETH_LIGHT_EN "lctrl_ethen" 2228#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 2229#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 2230#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW 2231 2232#define COL_BLINK_EN "lctrl_cen" 2233#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 2234#define LED_CTRL_COL_BLINK_EN_BLEN 1 2235#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW 2236 2237#define RX_BLINK_EN "lctrl_rxen" 2238#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 2239#define LED_CTRL_RX_BLINK_EN_BLEN 1 2240#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW 2241 2242#define TX_BLINK_EN "lctrl_txen" 2243#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 2244#define LED_CTRL_TX_BLINK_EN_BLEN 1 2245#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW 2246 2247#define LINKUP_OVER_EN "lctrl_loen" 2248#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 2249#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 2250#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW 2251 2252#define BLINK_FREQ "lctrl_bfreq" 2253#define LED_CTRL_BLINK_FREQ_BOFFSET 0 2254#define LED_CTRL_BLINK_FREQ_BLEN 2 2255#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW 2256 2257 /* LED control Register */ 2258#define LED_PATTERN "ledpatten" 2259#define LED_PATTERN_ID 25 2260#define LED_PATTERN_OFFSET 0x005c 2261#define LED_PATTERN_E_LENGTH 4 2262#define LED_PATTERN_E_OFFSET 0 2263#define LED_PATTERN_NR_E 1 2264 2265 2266#define P3L2_MODE 2267#define LED_PATTERN_P3L2_MODE_BOFFSET 24 2268#define LED_PATTERN_P3L2_MODE_BLEN 2 2269#define LED_PATTERN_P3L2_MODE_FLAG HSL_RW 2270 2271#define P3L1_MODE 2272#define LED_PATTERN_P3L1_MODE_BOFFSET 22 2273#define LED_PATTERN_P3L1_MODE_BLEN 2 2274#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW 2275 2276#define P3L0_MODE 2277#define LED_PATTERN_P3L0_MODE_BOFFSET 20 2278#define LED_PATTERN_P3L0_MODE_BLEN 2 2279#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW 2280 2281#define P2L2_MODE 2282#define LED_PATTERN_P2L2_MODE_BOFFSET 18 2283#define LED_PATTERN_P2L2_MODE_BLEN 2 2284#define LED_PATTERN_P2L2_MODE_FLAG HSL_RW 2285 2286#define P2L1_MODE 2287#define LED_PATTERN_P2L1_MODE_BOFFSET 16 2288#define LED_PATTERN_P2L1_MODE_BLEN 2 2289#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW 2290 2291#define P2L0_MODE 2292#define LED_PATTERN_P2L0_MODE_BOFFSET 14 2293#define LED_PATTERN_P2L0_MODE_BLEN 2 2294#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW 2295 2296#define P1L2_MODE 2297#define LED_PATTERN_P1L2_MODE_BOFFSET 12 2298#define LED_PATTERN_P1L2_MODE_BLEN 2 2299#define LED_PATTERN_P1L2_MODE_FLAG HSL_RW 2300 2301#define P1L1_MODE 2302#define LED_PATTERN_P1L1_MODE_BOFFSET 10 2303#define LED_PATTERN_P1L1_MODE_BLEN 2 2304#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW 2305 2306#define P1L0_MODE 2307#define LED_PATTERN_P1L0_MODE_BOFFSET 8 2308#define LED_PATTERN_P1L0_MODE_BLEN 2 2309#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW 2310 2311 2312 2313 2314 /* Pri To Queue Register */ 2315#define PRI_TO_QUEUE 2316#define PRI_TO_QUEUE_OFFSET 0x0814 2317#define PRI_TO_QUEUE_E_LENGTH 4 2318#define PRI_TO_QUEUE_E_OFFSET 0x0004 2319#define PRI_TO_QUEUE_NR_E 1 2320 2321 2322 2323 2324 /* Pri To EhQueue Register */ 2325#define PRI_TO_EHQUEUE 2326#define PRI_TO_EHQUEUE_OFFSET 0x0810 2327#define PRI_TO_EHQUEUE_E_LENGTH 4 2328#define PRI_TO_EHQUEUE_E_OFFSET 0x0004 2329#define PRI_TO_EHQUEUE_NR_E 1 2330 2331 2332 2333 2334 /* Port HOL CTL0 Register */ 2335#define PORT_HOL_CTL0 2336#define PORT_HOL_CTL0_OFFSET 0x0970 2337#define PORT_HOL_CTL0_E_LENGTH 4 2338#define PORT_HOL_CTL0_E_OFFSET 0x0008 2339#define PORT_HOL_CTL0_NR_E 7 2340 2341#define PORT_DESC_NR 2342#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24 2343#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 6 2344#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW 2345 2346#define QUEUE5_DESC_NR 2347#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET 20 2348#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN 4 2349#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG HSL_RW 2350 2351#define QUEUE4_DESC_NR 2352#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET 16 2353#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN 4 2354#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG HSL_RW 2355 2356#define QUEUE3_DESC_NR 2357#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET 12 2358#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN 4 2359#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG HSL_RW 2360 2361#define QUEUE2_DESC_NR 2362#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET 8 2363#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN 4 2364#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG HSL_RW 2365 2366#define QUEUE1_DESC_NR 2367#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET 4 2368#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN 4 2369#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG HSL_RW 2370 2371#define QUEUE0_DESC_NR 2372#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET 0 2373#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN 4 2374#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG HSL_RW 2375 2376 /* Port HOL CTL1 Register */ 2377#define PORT_HOL_CTL1 2378#define PORT_HOL_CTL1_OFFSET 0x0974 2379#define PORT_HOL_CTL1_E_LENGTH 4 2380#define PORT_HOL_CTL1_E_OFFSET 0x0008 2381#define PORT_HOL_CTL1_NR_E 7 2382 2383#define EG_MIRROR_EN 2384#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET 16 2385#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN 1 2386#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG HSL_RW 2387 2388#define PORT_DESC_EN 2389#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET 7 2390#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN 1 2391#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG HSL_RW 2392 2393#define QUEUE_DESC_EN 2394#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET 6 2395#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN 1 2396#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG HSL_RW 2397 2398#define PORT_IN_DESC_EN 2399#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0 2400#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 4 2401#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW 2402 2403 2404 2405 2406 /* Port Rate Limit0 Register */ 2407#define RATE_LIMIT0 "rlmt0" 2408#define RATE_LIMIT0_ID 32 2409#define RATE_LIMIT0_OFFSET 0x0110 2410#define RATE_LIMIT0_E_LENGTH 4 2411#define RATE_LIMIT0_E_OFFSET 0x0100 2412#define RATE_LIMIT0_NR_E 7 2413 2414 2415#define EG_RATE_EN "rlmt_egen" 2416#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23 2417#define RATE_LIMIT0_EG_RATE_EN_BLEN 1 2418#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW 2419 2420#define EG_MNG_RATE_EN "rlmt_egmngen" 2421#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22 2422#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1 2423#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW 2424 2425#define IN_MNG_RATE_EN "rlmt_inmngen" 2426#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21 2427#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1 2428#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW 2429 2430#define IN_MUL_RATE_EN "rlmt_inmulen" 2431#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20 2432#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1 2433#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW 2434 2435#define ING_RATE "rlmt_ingrate" 2436#define RATE_LIMIT0_ING_RATE_BOFFSET 0 2437#define RATE_LIMIT0_ING_RATE_BLEN 15 2438#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 /* mib memory info */ 2450#define MIB_RXBROAD 2451#define MIB_RXBROAD_OFFSET 0x01000 2452#define MIB_RXBROAD_E_LENGTH 4 2453#define MIB_RXBROAD_E_OFFSET 0x100 2454#define MIB_RXBROAD_NR_E 7 2455 2456#define MIB_RXPAUSE 2457#define MIB_RXPAUSE_OFFSET 0x01004 2458#define MIB_RXPAUSE_E_LENGTH 4 2459#define MIB_RXPAUSE_E_OFFSET 0x100 2460#define MIB_RXPAUSE_NR_E 7 2461 2462#define MIB_RXMULTI 2463#define MIB_RXMULTI_OFFSET 0x01008 2464#define MIB_RXMULTI_E_LENGTH 4 2465#define MIB_RXMULTI_E_OFFSET 0x100 2466#define MIB_RXMULTI_NR_E 7 2467 2468#define MIB_RXFCSERR 2469#define MIB_RXFCSERR_OFFSET 0x0100c 2470#define MIB_RXFCSERR_E_LENGTH 4 2471#define MIB_RXFCSERR_E_OFFSET 0x100 2472#define MIB_RXFCSERR_NR_E 7 2473 2474#define MIB_RXALLIGNERR 2475#define MIB_RXALLIGNERR_OFFSET 0x01010 2476#define MIB_RXALLIGNERR_E_LENGTH 4 2477#define MIB_RXALLIGNERR_E_OFFSET 0x100 2478#define MIB_RXALLIGNERR_NR_E 7 2479 2480#define MIB_RXRUNT 2481#define MIB_RXRUNT_OFFSET 0x01014 2482#define MIB_RXRUNT_E_LENGTH 4 2483#define MIB_RXRUNT_E_OFFSET 0x100 2484#define MIB_RXRUNT_NR_E 7 2485 2486#define MIB_RXFRAGMENT 2487#define MIB_RXFRAGMENT_OFFSET 0x01018 2488#define MIB_RXFRAGMENT_E_LENGTH 4 2489#define MIB_RXFRAGMENT_E_OFFSET 0x100 2490#define MIB_RXFRAGMENT_NR_E 7 2491 2492#define MIB_RX64BYTE 2493#define MIB_RX64BYTE_OFFSET 0x0101c 2494#define MIB_RX64BYTE_E_LENGTH 4 2495#define MIB_RX64BYTE_E_OFFSET 0x100 2496#define MIB_RX64BYTE_NR_E 7 2497 2498#define MIB_RX128BYTE 2499#define MIB_RX128BYTE_OFFSET 0x01020 2500#define MIB_RX128BYTE_E_LENGTH 4 2501#define MIB_RX128BYTE_E_OFFSET 0x100 2502#define MIB_RX128BYTE_NR_E 7 2503 2504#define MIB_RX256BYTE 2505#define MIB_RX256BYTE_OFFSET 0x01024 2506#define MIB_RX256BYTE_E_LENGTH 4 2507#define MIB_RX256BYTE_E_OFFSET 0x100 2508#define MIB_RX256BYTE_NR_E 7 2509 2510#define MIB_RX512BYTE 2511#define MIB_RX512BYTE_OFFSET 0x01028 2512#define MIB_RX512BYTE_E_LENGTH 4 2513#define MIB_RX512BYTE_E_OFFSET 0x100 2514#define MIB_RX512BYTE_NR_E 7 2515 2516#define MIB_RX1024BYTE 2517#define MIB_RX1024BYTE_OFFSET 0x0102c 2518#define MIB_RX1024BYTE_E_LENGTH 4 2519#define MIB_RX1024BYTE_E_OFFSET 0x100 2520#define MIB_RX1024BYTE_NR_E 7 2521 2522#define MIB_RX1518BYTE 2523#define MIB_RX1518BYTE_OFFSET 0x01030 2524#define MIB_RX1518BYTE_E_LENGTH 4 2525#define MIB_RX1518BYTE_E_OFFSET 0x100 2526#define MIB_RX1518BYTE_NR_E 7 2527 2528#define MIB_RXMAXBYTE 2529#define MIB_RXMAXBYTE_OFFSET 0x01034 2530#define MIB_RXMAXBYTE_E_LENGTH 4 2531#define MIB_RXMAXBYTE_E_OFFSET 0x100 2532#define MIB_RXMAXBYTE_NR_E 7 2533 2534#define MIB_RXTOOLONG 2535#define MIB_RXTOOLONG_OFFSET 0x01038 2536#define MIB_RXTOOLONG_E_LENGTH 4 2537#define MIB_RXTOOLONG_E_OFFSET 0x100 2538#define MIB_RXTOOLONG_NR_E 7 2539 2540#define MIB_RXGOODBYTE_LO 2541#define MIB_RXGOODBYTE_LO_OFFSET 0x0103c 2542#define MIB_RXGOODBYTE_LO_E_LENGTH 4 2543#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 2544#define MIB_RXGOODBYTE_LO_NR_E 7 2545 2546#define MIB_RXGOODBYTE_HI 2547#define MIB_RXGOODBYTE_HI_OFFSET 0x01040 2548#define MIB_RXGOODBYTE_HI_E_LENGTH 4 2549#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 2550#define MIB_RXGOODBYTE_HI_NR_E 7 2551 2552#define MIB_RXBADBYTE_LO 2553#define MIB_RXBADBYTE_LO_OFFSET 0x01044 2554#define MIB_RXBADBYTE_LO_E_LENGTH 4 2555#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 2556#define MIB_RXBADBYTE_LO_NR_E 7 2557 2558#define MIB_RXBADBYTE_HI 2559#define MIB_RXBADBYTE_HI_OFFSET 0x01048 2560#define MIB_RXBADBYTE_HI_E_LENGTH 4 2561#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 2562#define MIB_RXBADBYTE_HI_NR_E 7 2563 2564#define MIB_RXOVERFLOW 2565#define MIB_RXOVERFLOW_OFFSET 0x0104c 2566#define MIB_RXOVERFLOW_E_LENGTH 4 2567#define MIB_RXOVERFLOW_E_OFFSET 0x100 2568#define MIB_RXOVERFLOW_NR_E 7 2569 2570#define MIB_FILTERED 2571#define MIB_FILTERED_OFFSET 0x01050 2572#define MIB_FILTERED_E_LENGTH 4 2573#define MIB_FILTERED_E_OFFSET 0x100 2574#define MIB_FILTERED_NR_E 7 2575 2576#define MIB_TXBROAD 2577#define MIB_TXBROAD_OFFSET 0x01054 2578#define MIB_TXBROAD_E_LENGTH 4 2579#define MIB_TXBROAD_E_OFFSET 0x100 2580#define MIB_TXBROAD_NR_E 7 2581 2582#define MIB_TXPAUSE 2583#define MIB_TXPAUSE_OFFSET 0x01058 2584#define MIB_TXPAUSE_E_LENGTH 4 2585#define MIB_TXPAUSE_E_OFFSET 0x100 2586#define MIB_TXPAUSE_NR_E 7 2587 2588#define MIB_TXMULTI 2589#define MIB_TXMULTI_OFFSET 0x0105c 2590#define MIB_TXMULTI_E_LENGTH 4 2591#define MIB_TXMULTI_E_OFFSET 0x100 2592#define MIB_TXMULTI_NR_E 7 2593 2594#define MIB_TXUNDERRUN 2595#define MIB_TXUNDERRUN_OFFSET 0x01060 2596#define MIB_TXUNDERRUN_E_LENGTH 4 2597#define MIB_TXUNDERRUN_E_OFFSET 0x100 2598#define MIB_TXUNDERRUN_NR_E 7 2599 2600#define MIB_TX64BYTE 2601#define MIB_TX64BYTE_OFFSET 0x01064 2602#define MIB_TX64BYTE_E_LENGTH 4 2603#define MIB_TX64BYTE_E_OFFSET 0x100 2604#define MIB_TX64BYTE_NR_E 7 2605 2606#define MIB_TX128BYTE 2607#define MIB_TX128BYTE_OFFSET 0x01068 2608#define MIB_TX128BYTE_E_LENGTH 4 2609#define MIB_TX128BYTE_E_OFFSET 0x100 2610#define MIB_TX128BYTE_NR_E 7 2611 2612#define MIB_TX256BYTE 2613#define MIB_TX256BYTE_OFFSET 0x0106c 2614#define MIB_TX256BYTE_E_LENGTH 4 2615#define MIB_TX256BYTE_E_OFFSET 0x100 2616#define MIB_TX256BYTE_NR_E 7 2617 2618#define MIB_TX512BYTE 2619#define MIB_TX512BYTE_OFFSET 0x01070 2620#define MIB_TX512BYTE_E_LENGTH 4 2621#define MIB_TX512BYTE_E_OFFSET 0x100 2622#define MIB_TX512BYTE_NR_E 7 2623 2624#define MIB_TX1024BYTE 2625#define MIB_TX1024BYTE_OFFSET 0x01074 2626#define MIB_TX1024BYTE_E_LENGTH 4 2627#define MIB_TX1024BYTE_E_OFFSET 0x100 2628#define MIB_TX1024BYTE_NR_E 7 2629 2630#define MIB_TX1518BYTE 2631#define MIB_TX1518BYTE_OFFSET 0x01078 2632#define MIB_TX1518BYTE_E_LENGTH 4 2633#define MIB_TX1518BYTE_E_OFFSET 0x100 2634#define MIB_TX1518BYTE_NR_E 7 2635 2636#define MIB_TXMAXBYTE 2637#define MIB_TXMAXBYTE_OFFSET 0x0107c 2638#define MIB_TXMAXBYTE_E_LENGTH 4 2639#define MIB_TXMAXBYTE_E_OFFSET 0x100 2640#define MIB_TXMAXBYTE_NR_E 7 2641 2642#define MIB_TXOVERSIZE 2643#define MIB_TXOVERSIZE_OFFSET 0x01080 2644#define MIB_TXOVERSIZE_E_LENGTH 4 2645#define MIB_TXOVERSIZE_E_OFFSET 0x100 2646#define MIB_TXOVERSIZE_NR_E 7 2647 2648#define MIB_TXBYTE_LO 2649#define MIB_TXBYTE_LO_OFFSET 0x01084 2650#define MIB_TXBYTE_LO_E_LENGTH 4 2651#define MIB_TXBYTE_LO_E_OFFSET 0x100 2652#define MIB_TXBYTE_LO_NR_E 7 2653 2654#define MIB_TXBYTE_HI 2655#define MIB_TXBYTE_HI_OFFSET 0x01088 2656#define MIB_TXBYTE_HI_E_LENGTH 4 2657#define MIB_TXBYTE_HI_E_OFFSET 0x100 2658#define MIB_TXBYTE_HI_NR_E 7 2659 2660#define MIB_TXCOLLISION 2661#define MIB_TXCOLLISION_OFFSET 0x0108c 2662#define MIB_TXCOLLISION_E_LENGTH 4 2663#define MIB_TXCOLLISION_E_OFFSET 0x100 2664#define MIB_TXCOLLISION_NR_E 7 2665 2666#define MIB_TXABORTCOL 2667#define MIB_TXABORTCOL_OFFSET 0x01090 2668#define MIB_TXABORTCOL_E_LENGTH 4 2669#define MIB_TXABORTCOL_E_OFFSET 0x100 2670#define MIB_TXABORTCOL_NR_E 7 2671 2672#define MIB_TXMULTICOL 2673#define MIB_TXMULTICOL_OFFSET 0x01094 2674#define MIB_TXMULTICOL_E_LENGTH 4 2675#define MIB_TXMULTICOL_E_OFFSET 0x100 2676#define MIB_TXMULTICOL_NR_E 7 2677 2678#define MIB_TXSINGALCOL 2679#define MIB_TXSINGALCOL_OFFSET 0x01098 2680#define MIB_TXSINGALCOL_E_LENGTH 4 2681#define MIB_TXSINGALCOL_E_OFFSET 0x100 2682#define MIB_TXSINGALCOL_NR_E 7 2683 2684#define MIB_TXEXCDEFER 2685#define MIB_TXEXCDEFER_OFFSET 0x0109c 2686#define MIB_TXEXCDEFER_E_LENGTH 4 2687#define MIB_TXEXCDEFER_E_OFFSET 0x100 2688#define MIB_TXEXCDEFER_NR_E 7 2689 2690#define MIB_TXDEFER 2691#define MIB_TXDEFER_OFFSET 0x010a0 2692#define MIB_TXDEFER_E_LENGTH 4 2693#define MIB_TXDEFER_E_OFFSET 0x100 2694#define MIB_TXDEFER_NR_E 7 2695 2696#define MIB_TXLATECOL 2697#define MIB_TXLATECOL_OFFSET 0x010a4 2698#define MIB_TXLATECOL_E_LENGTH 4 2699#define MIB_TXLATECOL_E_OFFSET 0x100 2700#define MIB_TXLATECOL_NR_E 7 2701 2702 2703 2704 /* ACL Action Register */ 2705#define ACL_RSLT0 10 2706#define ACL_RSLT0_OFFSET 0x5a000 2707#define ACL_RSLT0_E_LENGTH 4 2708#define ACL_RSLT0_E_OFFSET 0x10 2709#define ACL_RSLT0_NR_E 96 2710 2711#define CTAGPRI 2712#define ACL_RSLT0_CTAGPRI_BOFFSET 29 2713#define ACL_RSLT0_CTAGPRI_BLEN 3 2714#define ACL_RSLT0_CTAGPRI_FLAG HSL_RW 2715 2716#define CTAGCFI 2717#define ACL_RSLT0_CTAGCFI_BOFFSET 28 2718#define ACL_RSLT0_CTAGCFI_BLEN 1 2719#define ACL_RSLT0_CTAGCFI_FLAG HSL_RW 2720 2721#define CTAGVID 2722#define ACL_RSLT0_CTAGVID_BOFFSET 16 2723#define ACL_RSLT0_CTAGVID_BLEN 12 2724#define ACL_RSLT0_CTAGVID_FLAG HSL_RW 2725 2726#define STAGPRI 2727#define ACL_RSLT0_STAGPRI_BOFFSET 13 2728#define ACL_RSLT0_STAGPRI_BLEN 3 2729#define ACL_RSLT0_STAGPRI_FLAG HSL_RW 2730 2731#define STAGDEI 2732#define ACL_RSLT0_STAGDEI_BOFFSET 12 2733#define ACL_RSLT0_STAGDEI_BLEN 1 2734#define ACL_RSLT0_STAGDEI_FLAG HSL_RW 2735 2736#define STAGVID 2737#define ACL_RSLT0_STAGVID_BOFFSET 0 2738#define ACL_RSLT0_STAGVID_BLEN 12 2739#define ACL_RSLT0_STAGVID_FLAG HSL_RW 2740 2741 2742#define ACL_RSLT1 11 2743#define ACL_RSLT1_OFFSET 0x5a004 2744#define ACL_RSLT1_E_LENGTH 4 2745#define ACL_RSLT1_E_OFFSET 0x10 2746#define ACL_RSLT1_NR_E 96 2747 2748#define DES_PORT0 2749#define ACL_RSLT1_DES_PORT0_BOFFSET 29 2750#define ACL_RSLT1_DES_PORT0_BLEN 3 2751#define ACL_RSLT1_DES_PORT0_FLAG HSL_RW 2752 2753#define PRI_QU_EN 2754#define ACL_RSLT1_PRI_QU_EN_BOFFSET 28 2755#define ACL_RSLT1_PRI_QU_EN_BLEN 1 2756#define ACL_RSLT1_PRI_QU_EN_FLAG HSL_RW 2757 2758#define PRI_QU 2759#define ACL_RSLT1_PRI_QU_BOFFSET 25 2760#define ACL_RSLT1_PRI_QU_BLEN 3 2761#define ACL_RSLT1_PRI_QU_FLAG HSL_RW 2762 2763#define WCMP_EN 2764#define ACL_RSLT1_WCMP_EN_BOFFSET 24 2765#define ACL_RSLT1_WCMP_EN_BLEN 1 2766#define ACL_RSLT1_WCMP_EN_FLAG HSL_RW 2767 2768#define ARP_PTR 2769#define ACL_RSLT1_ARP_PTR_BOFFSET 17 2770#define ACL_RSLT1_ARP_PTR_BLEN 7 2771#define ACL_RSLT1_ARP_PTR_FLAG HSL_RW 2772 2773#define ARP_PTR_EN 2774#define ACL_RSLT1_ARP_PTR_EN_BOFFSET 16 2775#define ACL_RSLT1_ARP_PTR_EN_BLEN 1 2776#define ACL_RSLT1_ARP_PTR_EN_FLAG HSL_RW 2777 2778#define FORCE_L3_MODE 2779#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET 14 2780#define ACL_RSLT1_FORCE_L3_MODE_BLEN 2 2781#define ACL_RSLT1_FORCE_L3_MODE_FLAG HSL_RW 2782 2783#define LOOK_VID_CHG 2784#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET 13 2785#define ACL_RSLT1_LOOK_VID_CHG_BLEN 1 2786#define ACL_RSLT1_LOOK_VID_CHG_FLAG HSL_RW 2787 2788#define TRANS_CVID_CHG 2789#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET 12 2790#define ACL_RSLT1_TRANS_CVID_CHG_BLEN 1 2791#define ACL_RSLT1_TRANS_CVID_CHG_FLAG HSL_RW 2792 2793#define TRANS_SVID_CHG 2794#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET 11 2795#define ACL_RSLT1_TRANS_SVID_CHG_BLEN 1 2796#define ACL_RSLT1_TRANS_SVID_CHG_FLAG HSL_RW 2797 2798#define CTAG_CFI_CHG 2799#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET 10 2800#define ACL_RSLT1_CTAG_CFI_CHG_BLEN 1 2801#define ACL_RSLT1_CTAG_CFI_CHG_FLAG HSL_RW 2802 2803#define CTAG_PRI_REMAP 2804#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET 9 2805#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN 1 2806#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG HSL_RW 2807 2808#define STAG_DEI_CHG 2809#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET 8 2810#define ACL_RSLT1_STAG_DEI_CHG_BLEN 1 2811#define ACL_RSLT1_STAG_DEI_CHG_FLAG HSL_RW 2812 2813#define STAG_PRI_REMAP 2814#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET 7 2815#define ACL_RSLT1_STAG_PRI_REMAP_BLEN 1 2816#define ACL_RSLT1_STAG_PRI_REMAP_FLAG HSL_RW 2817 2818#define DSCP_REMAP 2819#define ACL_RSLT1_DSCP_REMAP_BOFFSET 6 2820#define ACL_RSLT1_DSCP_REMAP_BLEN 1 2821#define ACL_RSLT1_DSCP_REMAP_FLAG HSL_RW 2822 2823#define DSCPV 2824#define ACL_RSLT1_DSCPV_BOFFSET 0 2825#define ACL_RSLT1_DSCPV_BLEN 6 2826#define ACL_RSLT1_DSCPV_FLAG HSL_RW 2827 2828#define ACL_RSLT2 12 2829#define ACL_RSLT2_OFFSET 0x5a008 2830#define ACL_RSLT2_E_LENGTH 4 2831#define ACL_RSLT2_E_OFFSET 0x10 2832#define ACL_RSLT2_NR_E 96 2833 2834#define TRIGGER_INTR 2835#define ACL_RSLT2_TRIGGER_INTR_BOFFSET 16 2836#define ACL_RSLT2_TRIGGER_INTR_BLEN 1 2837#define ACL_RSLT2_TRIGGER_INTR_FLAG HSL_RW 2838 2839#define EG_BYPASS 2840#define ACL_RSLT2_EG_BYPASS_BOFFSET 15 2841#define ACL_RSLT2_EG_BYPASS_BLEN 1 2842#define ACL_RSLT2_EG_BYPASS_FLAG HSL_RW 2843 2844#define POLICER_EN 2845#define ACL_RSLT2_POLICER_EN_BOFFSET 14 2846#define ACL_RSLT2_POLICER_EN_BLEN 1 2847#define ACL_RSLT2_POLICER_EN_FLAG HSL_RW 2848 2849#define POLICER_PTR 2850#define ACL_RSLT2_POLICER_PTR_BOFFSET 9 2851#define ACL_RSLT2_POLICER_PTR_BLEN 5 2852#define ACL_RSLT2_POLICER_PTR_FLAG HSL_RW 2853 2854#define FWD_CMD 2855#define ACL_RSLT2_FWD_CMD_BOFFSET 6 2856#define ACL_RSLT2_FWD_CMD_BLEN 3 2857#define ACL_RSLT2_FWD_CMD_FLAG HSL_RW 2858 2859#define MIRR_EN 2860#define ACL_RSLT2_MIRR_EN_BOFFSET 5 2861#define ACL_RSLT2_MIRR_EN_BLEN 1 2862#define ACL_RSLT2_MIRR_EN_FLAG HSL_RW 2863 2864#define DES_PORT_EN 2865#define ACL_RSLT2_DES_PORT_EN_BOFFSET 4 2866#define ACL_RSLT2_DES_PORT_EN_BLEN 1 2867#define ACL_RSLT2_DES_PORT_EN_FLAG HSL_RW 2868 2869#define DES_PORT1 2870#define ACL_RSLT2_DES_PORT1_BOFFSET 0 2871#define ACL_RSLT2_DES_PORT1_BLEN 4 2872#define ACL_RSLT2_DES_PORT1_FLAG HSL_RW 2873 2874 2875 2876 2877 /* MAC Type Rule Field Define */ 2878#define MAC_RUL_V0 0 2879#define MAC_RUL_V0_OFFSET 0x58000 2880#define MAC_RUL_V0_E_LENGTH 4 2881#define MAC_RUL_V0_E_OFFSET 0x20 2882#define MAC_RUL_V0_NR_E 96 2883 2884#define DAV_BYTE2 2885#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24 2886#define MAC_RUL_V0_DAV_BYTE2_BLEN 8 2887#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW 2888 2889#define DAV_BYTE3 2890#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16 2891#define MAC_RUL_V0_DAV_BYTE3_BLEN 8 2892#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW 2893 2894#define DAV_BYTE4 2895#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8 2896#define MAC_RUL_V0_DAV_BYTE4_BLEN 8 2897#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW 2898 2899#define DAV_BYTE5 2900#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0 2901#define MAC_RUL_V0_DAV_BYTE5_BLEN 8 2902#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW 2903 2904 2905#define MAC_RUL_V1 1 2906#define MAC_RUL_V1_OFFSET 0x58004 2907#define MAC_RUL_V1_E_LENGTH 4 2908#define MAC_RUL_V1_E_OFFSET 0x20 2909#define MAC_RUL_V1_NR_E 96 2910 2911#define SAV_BYTE4 2912#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24 2913#define MAC_RUL_V1_SAV_BYTE4_BLEN 8 2914#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW 2915 2916#define SAV_BYTE5 2917#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16 2918#define MAC_RUL_V1_SAV_BYTE5_BLEN 8 2919#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW 2920 2921#define DAV_BYTE0 2922#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8 2923#define MAC_RUL_V1_DAV_BYTE0_BLEN 8 2924#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW 2925 2926#define DAV_BYTE1 2927#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0 2928#define MAC_RUL_V1_DAV_BYTE1_BLEN 8 2929#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW 2930 2931 2932#define MAC_RUL_V2 2 2933#define MAC_RUL_V2_OFFSET 0x58008 2934#define MAC_RUL_V2_E_LENGTH 4 2935#define MAC_RUL_V2_E_OFFSET 0x20 2936#define MAC_RUL_V2_NR_E 96 2937 2938#define SAV_BYTE0 2939#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24 2940#define MAC_RUL_V2_SAV_BYTE0_BLEN 8 2941#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW 2942 2943#define SAV_BYTE1 2944#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16 2945#define MAC_RUL_V2_SAV_BYTE1_BLEN 8 2946#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW 2947 2948#define SAV_BYTE2 2949#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8 2950#define MAC_RUL_V2_SAV_BYTE2_BLEN 8 2951#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW 2952 2953#define SAV_BYTE3 2954#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0 2955#define MAC_RUL_V2_SAV_BYTE3_BLEN 8 2956#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW 2957 2958 2959#define MAC_RUL_V3 3 2960#define MAC_RUL_V3_ID 13 2961#define MAC_RUL_V3_OFFSET 0x5800c 2962#define MAC_RUL_V3_E_LENGTH 4 2963#define MAC_RUL_V3_E_OFFSET 0x20 2964#define MAC_RUL_V3_NR_E 96 2965 2966#define ETHTYPV 2967#define MAC_RUL_V3_ETHTYPV_BOFFSET 16 2968#define MAC_RUL_V3_ETHTYPV_BLEN 16 2969#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW 2970 2971#define VLANPRIV 2972#define MAC_RUL_V3_VLANPRIV_BOFFSET 13 2973#define MAC_RUL_V3_VLANPRIV_BLEN 3 2974#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW 2975 2976#define VLANCFIV 2977#define MAC_RUL_V3_VLANCFIV_BOFFSET 12 2978#define MAC_RUL_V3_VLANCFIV_BLEN 1 2979#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW 2980 2981#define VLANIDV 2982#define MAC_RUL_V3_VLANIDV_BOFFSET 0 2983#define MAC_RUL_V3_VLANIDV_BLEN 12 2984#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW 2985 2986 2987#define MAC_RUL_V4 4 2988#define MAC_RUL_V4_OFFSET 0x58010 2989#define MAC_RUL_V4_E_LENGTH 4 2990#define MAC_RUL_V4_E_OFFSET 0x20 2991#define MAC_RUL_V4_NR_E 96 2992 2993#define RULE_INV 2994#define MAC_RUL_V4_RULE_INV_BOFFSET 7 2995#define MAC_RUL_V4_RULE_INV_BLEN 1 2996#define MAC_RUL_V4_RULE_INV_FLAG HSL_RW 2997 2998#define SRC_PT 2999#define MAC_RUL_V4_SRC_PT_BOFFSET 0 3000#define MAC_RUL_V4_SRC_PT_BLEN 7 3001#define MAC_RUL_V4_SRC_PT_FLAG HSL_RW 3002 3003 3004#define MAC_RUL_M0 5 3005#define MAC_RUL_M0_OFFSET 0x59000 3006#define MAC_RUL_M0_E_LENGTH 4 3007#define MAC_RUL_M0_E_OFFSET 0x20 3008#define MAC_RUL_M0_NR_E 96 3009 3010#define DAM_BYTE2 3011#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24 3012#define MAC_RUL_M0_DAM_BYTE2_BLEN 8 3013#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW 3014 3015#define DAM_BYTE3 3016#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16 3017#define MAC_RUL_M0_DAM_BYTE3_BLEN 8 3018#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW 3019 3020#define DAM_BYTE4 3021#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8 3022#define MAC_RUL_M0_DAM_BYTE4_BLEN 8 3023#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW 3024 3025#define DAM_BYTE5 3026#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0 3027#define MAC_RUL_M0_DAM_BYTE5_BLEN 8 3028#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW 3029 3030 3031#define MAC_RUL_M1 6 3032#define MAC_RUL_M1_OFFSET 0x59004 3033#define MAC_RUL_M1_E_LENGTH 4 3034#define MAC_RUL_M1_E_OFFSET 0x20 3035#define MAC_RUL_M1_NR_E 96 3036 3037#define SAM_BYTE4 3038#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24 3039#define MAC_RUL_M1_SAM_BYTE4_BLEN 8 3040#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW 3041 3042#define SAM_BYTE5 3043#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16 3044#define MAC_RUL_M1_SAM_BYTE5_BLEN 8 3045#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW 3046 3047#define DAM_BYTE0 3048#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8 3049#define MAC_RUL_M1_DAM_BYTE0_BLEN 8 3050#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW 3051 3052#define DAM_BYTE1 3053#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0 3054#define MAC_RUL_M1_DAM_BYTE1_BLEN 8 3055#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW 3056 3057 3058#define MAC_RUL_M2 7 3059#define MAC_RUL_M2_OFFSET 0x59008 3060#define MAC_RUL_M2_E_LENGTH 4 3061#define MAC_RUL_M2_E_OFFSET 0x20 3062#define MAC_RUL_M2_NR_E 96 3063 3064#define SAM_BYTE0 3065#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24 3066#define MAC_RUL_M2_SAM_BYTE0_BLEN 8 3067#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW 3068 3069#define SAM_BYTE1 3070#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16 3071#define MAC_RUL_M2_SAM_BYTE1_BLEN 8 3072#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW 3073 3074#define SAM_BYTE2 3075#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8 3076#define MAC_RUL_M2_SAM_BYTE2_BLEN 8 3077#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW 3078 3079#define SAM_BYTE3 3080#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0 3081#define MAC_RUL_M2_SAM_BYTE3_BLEN 8 3082#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW 3083 3084 3085#define MAC_RUL_M3 8 3086#define MAC_RUL_M3_OFFSET 0x5900c 3087#define MAC_RUL_M3_E_LENGTH 4 3088#define MAC_RUL_M3_E_OFFSET 0x20 3089#define MAC_RUL_M3_NR_E 96 3090 3091#define ETHTYPM 3092#define MAC_RUL_M3_ETHTYPM_BOFFSET 16 3093#define MAC_RUL_M3_ETHTYPM_BLEN 16 3094#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW 3095 3096#define VLANPRIM 3097#define MAC_RUL_M3_VLANPRIM_BOFFSET 13 3098#define MAC_RUL_M3_VLANPRIM_BLEN 3 3099#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW 3100 3101#define VLANCFIM 3102#define MAC_RUL_M3_VLANCFIM_BOFFSET 12 3103#define MAC_RUL_M3_VLANCFIM_BLEN 1 3104#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW 3105 3106#define VLANIDM 3107#define MAC_RUL_M3_VLANIDM_BOFFSET 0 3108#define MAC_RUL_M3_VLANIDM_BLEN 12 3109#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW 3110 3111 3112#define MAC_RUL_M4 9 3113#define MAC_RUL_M4_OFFSET 0x59010 3114#define MAC_RUL_M4_E_LENGTH 4 3115#define MAC_RUL_M4_E_OFFSET 0x20 3116#define MAC_RUL_M4_NR_E 96 3117 3118#define RULE_VALID 3119#define MAC_RUL_M4_RULE_VALID_BOFFSET 6 3120#define MAC_RUL_M4_RULE_VALID_BLEN 2 3121#define MAC_RUL_M4_RULE_VALID_FLAG HSL_RW 3122 3123#define TAGGEDM 3124#define MAC_RUL_M4_TAGGEDM_BOFFSET 5 3125#define MAC_RUL_M4_TAGGEDM_BLEN 1 3126#define MAC_RUL_M4_TAGGEDM_FLAG HSL_RW 3127 3128#define TAGGEDV 3129#define MAC_RUL_M4_TAGGEDV_BOFFSET 4 3130#define MAC_RUL_M4_TAGGEDV_BLEN 1 3131#define MAC_RUL_M4_TAGGEDV_FLAG HSL_RW 3132 3133#define VIDMSK 3134#define MAC_RUL_M4_VIDMSK_BOFFSET 3 3135#define MAC_RUL_M4_VIDMSK_BLEN 1 3136#define MAC_RUL_M4_VIDMSK_FLAG HSL_RW 3137 3138#define RULE_TYP 3139#define MAC_RUL_M4_RULE_TYP_BOFFSET 0 3140#define MAC_RUL_M4_RULE_TYP_BLEN 3 3141#define MAC_RUL_M4_RULE_TYP_FLAG HSL_RW 3142 3143 3144 3145 3146 /* IP4 Type Rule Field Define */ 3147#define IP4_RUL_V0 0 3148#define IP4_RUL_V0_OFFSET 0x58000 3149#define IP4_RUL_V0_E_LENGTH 4 3150#define IP4_RUL_V0_E_OFFSET 0x20 3151#define IP4_RUL_V0_NR_E 96 3152 3153#define DIPV 3154#define IP4_RUL_V0_DIPV_BOFFSET 0 3155#define IP4_RUL_V0_DIPV_BLEN 32 3156#define IP4_RUL_V0_DIPV_FLAG HSL_RW 3157 3158 3159#define IP4_RUL_V1 1 3160#define IP4_RUL_V1_OFFSET 0x58004 3161#define IP4_RUL_V1_E_LENGTH 4 3162#define IP4_RUL_V1_E_OFFSET 0x20 3163#define IP4_RUL_V1_NR_E 96 3164 3165#define SIPV 3166#define IP4_RUL_V1_SIPV_BOFFSET 0 3167#define IP4_RUL_V1_SIPV_BLEN 32 3168#define IP4_RUL_V1_SIPV_FLAG HSL_RW 3169 3170 3171#define IP4_RUL_V2 2 3172#define IP4_RUL_V2_OFFSET 0x58008 3173#define IP4_RUL_V2_E_LENGTH 4 3174#define IP4_RUL_V2_E_OFFSET 0x20 3175#define IP4_RUL_V2_NR_E 96 3176 3177#define IP4PROTV 3178#define IP4_RUL_V2_IP4PROTV_BOFFSET 0 3179#define IP4_RUL_V2_IP4PROTV_BLEN 8 3180#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW 3181 3182#define IP4DSCPV 3183#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8 3184#define IP4_RUL_V2_IP4DSCPV_BLEN 8 3185#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW 3186 3187#define IP4DPORTV 3188#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16 3189#define IP4_RUL_V2_IP4DPORTV_BLEN 16 3190#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW 3191 3192 3193#define IP4_RUL_V3 3 3194#define IP4_RUL_V3_OFFSET 0x5800c 3195#define IP4_RUL_V3_E_LENGTH 4 3196#define IP4_RUL_V3_E_OFFSET 0x20 3197#define IP4_RUL_V3_NR_E 96 3198 3199#define IP4TCPFLAGV 3200#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET 24 3201#define IP4_RUL_V3_IP4TCPFLAGV_BLEN 6 3202#define IP4_RUL_V3_IP4TCPFLAGV_FLAG HSL_RW 3203 3204#define IP4DHCPV 3205#define IP4_RUL_V3_IP4DHCPV_BOFFSET 22 3206#define IP4_RUL_V3_IP4DHCPV_BLEN 1 3207#define IP4_RUL_V3_IP4DHCPV_FLAG HSL_RW 3208 3209#define IP4RIPV 3210#define IP4_RUL_V3_IP4RIPV_BOFFSET 21 3211#define IP4_RUL_V3_IP4RIPV_BLEN 1 3212#define IP4_RUL_V3_IP4RIPV_FLAG HSL_RW 3213 3214#define ICMP_EN 3215#define IP4_RUL_V3_ICMP_EN_BOFFSET 20 3216#define IP4_RUL_V3_ICMP_EN_BLEN 1 3217#define IP4_RUL_V3_ICMP_EN_FLAG HSL_RW 3218 3219#define IP4SPORTV 3220#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0 3221#define IP4_RUL_V3_IP4SPORTV_BLEN 16 3222#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW 3223 3224#define IP4ICMPTYPV 3225#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET 8 3226#define IP4_RUL_V3_IP4ICMPTYPV_BLEN 8 3227#define IP4_RUL_V3_IP4ICMPTYPV_FLAG HSL_RW 3228 3229#define IP4ICMPCODEV 3230#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET 0 3231#define IP4_RUL_V3_IP4ICMPCODEV_BLEN 8 3232#define IP4_RUL_V3_IP4ICMPCODEV_FLAG HSL_RW 3233 3234 3235#define IP4_RUL_V4 4 3236#define IP4_RUL_V4_OFFSET 0x58010 3237#define IP4_RUL_V4_E_LENGTH 4 3238#define IP4_RUL_V4_E_OFFSET 0x20 3239#define IP4_RUL_V4_NR_E 96 3240 3241 3242#define IP4_RUL_M0 5 3243#define IP4_RUL_M0_OFFSET 0x59000 3244#define IP4_RUL_M0_E_LENGTH 4 3245#define IP4_RUL_M0_E_OFFSET 0x20 3246#define IP4_RUL_M0_NR_E 96 3247 3248#define DIPM 3249#define IP4_RUL_M0_DIPM_BOFFSET 0 3250#define IP4_RUL_M0_DIPM_BLEN 32 3251#define IP4_RUL_M0_DIPM_FLAG HSL_RW 3252 3253 3254#define IP4_RUL_M1 6 3255#define IP4_RUL_M1_OFFSET 0x59004 3256#define IP4_RUL_M1_E_LENGTH 4 3257#define IP4_RUL_M1_E_OFFSET 0x20 3258#define IP4_RUL_M1_NR_E 96 3259 3260#define SIPM 3261#define IP4_RUL_M1_SIPM_BOFFSET 0 3262#define IP4_RUL_M1_SIPM_BLEN 32 3263#define IP4_RUL_M1_SIPM_FLAG HSL_RW 3264 3265 3266#define IP4_RUL_M2 7 3267#define IP4_RUL_M2_OFFSET 0x59008 3268#define IP4_RUL_M2_E_LENGTH 4 3269#define IP4_RUL_M2_E_OFFSET 0x20 3270#define IP4_RUL_M2_NR_E 96 3271 3272#define IP4PROTM 3273#define IP4_RUL_M2_IP4PROTM_BOFFSET 0 3274#define IP4_RUL_M2_IP4PROTM_BLEN 8 3275#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW 3276 3277#define IP4DSCPM 3278#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8 3279#define IP4_RUL_M2_IP4DSCPM_BLEN 8 3280#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW 3281 3282#define IP4DPORTM 3283#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16 3284#define IP4_RUL_M2_IP4DPORTM_BLEN 16 3285#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW 3286 3287 3288#define IP4_RUL_M3 8 3289#define IP4_RUL_M3_OFFSET 0x5900c 3290#define IP4_RUL_M3_E_LENGTH 4 3291#define IP4_RUL_M3_E_OFFSET 0x20 3292#define IP4_RUL_M3_NR_E 96 3293 3294#define IP4TCPFLAGM 3295#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET 24 3296#define IP4_RUL_M3_IP4TCPFLAGM_BLEN 6 3297#define IP4_RUL_M3_IP4TCPFLAGM_FLAG HSL_RW 3298 3299#define IP4DHCPM 3300#define IP4_RUL_M3_IP4DHCPM_BOFFSET 22 3301#define IP4_RUL_M3_IP4DHCPM_BLEN 1 3302#define IP4_RUL_M3_IP4DHCPM_FLAG HSL_RW 3303 3304#define IP4RIPM 3305#define IP4_RUL_M3_IP4RIPM_BOFFSET 21 3306#define IP4_RUL_M3_IP4RIPM_BLEN 1 3307#define IP4_RUL_M3_IP4RIPM_FLAG HSL_RW 3308 3309#define IP4DPORTM_EN 3310#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17 3311#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1 3312#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW 3313 3314#define IP4SPORTM_EN 3315#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16 3316#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1 3317#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW 3318 3319#define IP4SPORTM 3320#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0 3321#define IP4_RUL_M3_IP4SPORTM_BLEN 16 3322#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW 3323 3324#define IP4ICMPTYPM 3325#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET 8 3326#define IP4_RUL_M3_IP4ICMPTYPM_BLEN 8 3327#define IP4_RUL_M3_IP4ICMPTYPM_FLAG HSL_RW 3328 3329#define IP4ICMPCODEM 3330#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET 0 3331#define IP4_RUL_M3_IP4ICMPCODEM_BLEN 8 3332#define IP4_RUL_M3_IP4ICMPCODEM_FLAG HSL_RW 3333 3334 3335#define IP4_RUL_M4 9 3336#define IP4_RUL_M4_OFFSET 0x59010 3337#define IP4_RUL_M4_E_LENGTH 4 3338#define IP4_RUL_M4_E_OFFSET 0x20 3339#define IP4_RUL_M4_NR_E 32 3340 3341 3342 3343 3344 /* IP6 Type1 Rule Field Define */ 3345#define IP6_RUL1_V0 0 3346#define IP6_RUL1_V0_OFFSET 0x58000 3347#define IP6_RUL1_V0_E_LENGTH 4 3348#define IP6_RUL1_V0_E_OFFSET 0x20 3349#define IP6_RUL1_V0_NR_E 96 3350 3351#define IP6_DIPV0 3352#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0 3353#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32 3354#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW 3355 3356 3357#define IP6_RUL1_V1 1 3358#define IP6_RUL1_V1_OFFSET 0x58004 3359#define IP6_RUL1_V1_E_LENGTH 4 3360#define IP6_RUL1_V1_E_OFFSET 0x20 3361#define IP6_RUL1_V1_NR_E 96 3362 3363#define IP6_DIPV1 3364#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0 3365#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32 3366#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW 3367 3368 3369#define IP6_RUL1_V2 2 3370#define IP6_RUL1_V2_OFFSET 0x58008 3371#define IP6_RUL1_V2_E_LENGTH 4 3372#define IP6_RUL1_V2_E_OFFSET 0x20 3373#define IP6_RUL1_V2_NR_E 96 3374 3375#define IP6_DIPV2 3376#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0 3377#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32 3378#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW 3379 3380 3381#define IP6_RUL1_V3 3 3382#define IP6_RUL1_V3_OFFSET 0x5800c 3383#define IP6_RUL1_V3_E_LENGTH 4 3384#define IP6_RUL1_V3_E_OFFSET 0x20 3385#define IP6_RUL1_V3_NR_E 96 3386 3387#define IP6_DIPV3 3388#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0 3389#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32 3390#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW 3391 3392 3393#define IP6_RUL1_V4 4 3394#define IP6_RUL1_V4_OFFSET 0x58010 3395#define IP6_RUL1_V4_E_LENGTH 4 3396#define IP6_RUL1_V4_E_OFFSET 0x20 3397#define IP6_RUL1_V4_NR_E 96 3398 3399 3400#define IP6_RUL1_M0 5 3401#define IP6_RUL1_M0_OFFSET 0x59000 3402#define IP6_RUL1_M0_E_LENGTH 4 3403#define IP6_RUL1_M0_E_OFFSET 0x20 3404#define IP6_RUL1_M0_NR_E 96 3405 3406#define IP6_DIPM0 3407#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0 3408#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32 3409#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW 3410 3411 3412#define IP6_RUL1_M1 6 3413#define IP6_RUL1_M1_OFFSET 0x59004 3414#define IP6_RUL1_M1_E_LENGTH 4 3415#define IP6_RUL1_M1_E_OFFSET 0x20 3416#define IP6_RUL1_M1_NR_E 96 3417 3418#define IP6_DIPM1 3419#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0 3420#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32 3421#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW 3422 3423 3424#define IP6_RUL1_M2 7 3425#define IP6_RUL1_M2_OFFSET 0x59008 3426#define IP6_RUL1_M2_E_LENGTH 4 3427#define IP6_RUL1_M2_E_OFFSET 0x20 3428#define IP6_RUL1_M2_NR_E 96 3429 3430#define IP6_DIPM2 3431#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0 3432#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32 3433#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW 3434 3435 3436#define IP6_RUL1_M3 8 3437#define IP6_RUL1_M3_OFFSET 0x5900c 3438#define IP6_RUL1_M3_E_LENGTH 4 3439#define IP6_RUL1_M3_E_OFFSET 0x20 3440#define IP6_RUL1_M3_NR_E 96 3441 3442#define IP6_DIPM3 3443#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0 3444#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32 3445#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW 3446 3447 3448#define IP6_RUL1_M4 9 3449#define IP6_RUL1_M4_OFFSET 0x59010 3450#define IP6_RUL1_M4_E_LENGTH 4 3451#define IP6_RUL1_M4_E_OFFSET 0x20 3452#define IP6_RUL1_M4_NR_E 96 3453 3454 3455 3456 3457 /* IP6 Type2 Rule Field Define */ 3458#define IP6_RUL2_V0 0 3459#define IP6_RUL2_V0_OFFSET 0x58000 3460#define IP6_RUL2_V0_E_LENGTH 4 3461#define IP6_RUL2_V0_E_OFFSET 0x20 3462#define IP6_RUL2_V0_NR_E 96 3463 3464#define IP6_SIPV0 3465#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0 3466#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32 3467#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW 3468 3469 3470#define IP6_RUL2_V1 1 3471#define IP6_RUL2_V1_OFFSET 0x58004 3472#define IP6_RUL2_V1_E_LENGTH 4 3473#define IP6_RUL2_V1_E_OFFSET 0x20 3474#define IP6_RUL2_V1_NR_E 96 3475 3476#define IP6_SIPV1 3477#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0 3478#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32 3479#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW 3480 3481 3482#define IP6_RUL2_V2 2 3483#define IP6_RUL2_V2_OFFSET 0x58008 3484#define IP6_RUL2_V2_E_LENGTH 4 3485#define IP6_RUL2_V2_E_OFFSET 0x20 3486#define IP6_RUL2_V2_NR_E 96 3487 3488#define IP6_SIPV2 3489#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0 3490#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32 3491#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW 3492 3493 3494#define IP6_RUL2_V3 3 3495#define IP6_RUL2_V3_OFFSET 0x5800c 3496#define IP6_RUL2_V3_E_LENGTH 4 3497#define IP6_RUL2_V3_E_OFFSET 0x20 3498#define IP6_RUL2_V3_NR_E 96 3499 3500#define IP6_SIPV3 3501#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0 3502#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32 3503#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW 3504 3505 3506#define IP6_RUL2_V4 4 3507#define IP6_RUL2_V4_OFFSET 0x58010 3508#define IP6_RUL2_V4_E_LENGTH 4 3509#define IP6_RUL2_V4_E_OFFSET 0x20 3510#define IP6_RUL2_V4_NR_E 96 3511 3512 3513#define IP6_RUL2_M0 5 3514#define IP6_RUL2_M0_OFFSET 0x59000 3515#define IP6_RUL2_M0_E_LENGTH 4 3516#define IP6_RUL2_M0_E_OFFSET 0x20 3517#define IP6_RUL2_M0_NR_E 96 3518 3519#define IP6_SIPM0 3520#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0 3521#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32 3522#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW 3523 3524 3525#define IP6_RUL2_M1 6 3526#define IP6_RUL2_M1_OFFSET 0x59004 3527#define IP6_RUL2_M1_E_LENGTH 4 3528#define IP6_RUL2_M1_E_OFFSET 0x20 3529#define IP6_RUL2_M1_NR_E 96 3530 3531#define IP6_SIPM1 3532#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0 3533#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32 3534#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW 3535 3536 3537#define IP6_RUL2_M2 7 3538#define IP6_RUL2_M2_OFFSET 0x59008 3539#define IP6_RUL2_M2_E_LENGTH 4 3540#define IP6_RUL2_M2_E_OFFSET 0x20 3541#define IP6_RUL2_M2_NR_E 96 3542 3543#define IP6_SIPM2 3544#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0 3545#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32 3546#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW 3547 3548 3549#define IP6_RUL2_M3 8 3550#define IP6_RUL2_M3_OFFSET 0x5900c 3551#define IP6_RUL2_M3_E_LENGTH 4 3552#define IP6_RUL2_M3_E_OFFSET 0x20 3553#define IP6_RUL2_M3_NR_E 96 3554 3555#define IP6_SIPM3 3556#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0 3557#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32 3558#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW 3559 3560 3561#define IP6_RUL2_M4 9 3562#define IP6_RUL2_M4_OFFSET 0x59010 3563#define IP6_RUL2_M4_E_LENGTH 4 3564#define IP6_RUL2_M4_E_OFFSET 0x20 3565#define IP6_RUL2_M4_NR_E 96 3566 3567 3568 3569 3570 /* IP6 Type3 Rule Field Define */ 3571#define IP6_RUL3_V0 0 3572#define IP6_RUL3_V0_OFFSET 0x58000 3573#define IP6_RUL3_V0_E_LENGTH 4 3574#define IP6_RUL3_V0_E_OFFSET 0x20 3575#define IP6_RUL3_V0_NR_E 96 3576 3577#define IP6PROTV 3578#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0 3579#define IP6_RUL3_V0_IP6PROTV_BLEN 8 3580#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW 3581 3582#define IP6DSCPV 3583#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8 3584#define IP6_RUL3_V0_IP6DSCPV_BLEN 8 3585#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW 3586 3587 3588#define IP6_RUL3_V1 1 3589#define IP6_RUL3_V1_OFFSET 0x58004 3590#define IP6_RUL3_V1_E_LENGTH 4 3591#define IP6_RUL3_V1_E_OFFSET 0x20 3592#define IP6_RUL3_V1_NR_E 96 3593 3594#define IP6LABEL1V 3595#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16 3596#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16 3597#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW 3598 3599 3600#define IP6_RUL3_V2 2 3601#define IP6_RUL3_V2_OFFSET 0x58008 3602#define IP6_RUL3_V2_E_LENGTH 4 3603#define IP6_RUL3_V2_E_OFFSET 0x20 3604#define IP6_RUL3_V2_NR_E 96 3605 3606#define IP6LABEL2V 3607#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0 3608#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4 3609#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW 3610 3611#define IP6DPORTV 3612#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16 3613#define IP6_RUL3_V2_IP6DPORTV_BLEN 16 3614#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW 3615 3616 3617#define IP6_RUL3_V3 3 3618#define IP6_RUL3_V3_OFFSET 0x5800c 3619#define IP6_RUL3_V3_E_LENGTH 4 3620#define IP6_RUL3_V3_E_OFFSET 0x20 3621#define IP6_RUL3_V3_NR_E 96 3622 3623#define IP6TCPFLAGV 3624#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET 24 3625#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN 6 3626#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG HSL_RW 3627 3628#define IP6FWDTYPV 3629#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET 23 3630#define IP6_RUL3_V3_IP6FWDTYPV_BLEN 1 3631#define IP6_RUL3_V3_IP6FWDTYPV_FLAG HSL_RW 3632 3633#define IP6DHCPV 3634#define IP6_RUL3_V3_IP6DHCPV_BOFFSET 22 3635#define IP6_RUL3_V3_IP6DHCPV_BLEN 1 3636#define IP6_RUL3_V3_IP6DHCPV_FLAG HSL_RW 3637 3638#define ICMP6_EN 3639#define IP6_RUL3_V3_ICMP6_EN_BOFFSET 20 3640#define IP6_RUL3_V3_ICMP6_EN_BLEN 1 3641#define IP6_RUL3_V3_ICMP6_EN_FLAG HSL_RW 3642 3643#define IP6SPORTV 3644#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0 3645#define IP6_RUL3_V3_IP6SPORTV_BLEN 16 3646#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW 3647 3648#define IP6ICMPTYPV 3649#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET 8 3650#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN 8 3651#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG HSL_RW 3652 3653#define IP6ICMPCODEV 3654#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET 0 3655#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN 8 3656#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG HSL_RW 3657 3658 3659#define IP6_RUL3_V4 4 3660#define IP6_RUL3_V4_OFFSET 0x58010 3661#define IP6_RUL3_V4_E_LENGTH 4 3662#define IP6_RUL3_V4_E_OFFSET 0x20 3663#define IP6_RUL3_V4_NR_E 96 3664 3665 3666#define IP6_RUL3_M0 5 3667#define IP6_RUL3_M0_OFFSET 0x59000 3668#define IP6_RUL3_M0_E_LENGTH 4 3669#define IP6_RUL3_M0_E_OFFSET 0x20 3670#define IP6_RUL3_M0_NR_E 96 3671 3672#define IP6PROTM 3673#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0 3674#define IP6_RUL3_M0_IP6PROTM_BLEN 8 3675#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW 3676 3677#define IP6DSCPM 3678#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8 3679#define IP6_RUL3_M0_IP6DSCPM_BLEN 8 3680#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW 3681 3682 3683#define IP6_RUL3_M1 6 3684#define IP6_RUL3_M1_OFFSET 0x59004 3685#define IP6_RUL3_M1_E_LENGTH 4 3686#define IP6_RUL3_M1_E_OFFSET 0x20 3687#define IP6_RUL3_M1_NR_E 96 3688 3689#define IP6LABEL1M 3690#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16 3691#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16 3692#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW 3693 3694 3695#define IP6_RUL3_M2 7 3696#define IP6_RUL3_M2_OFFSET 0x59008 3697#define IP6_RUL3_M2_E_LENGTH 4 3698#define IP6_RUL3_M2_E_OFFSET 0x20 3699#define IP6_RUL3_M2_NR_E 96 3700 3701#define IP6LABEL2M 3702#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0 3703#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4 3704#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW 3705 3706#define IP6DPORTM 3707#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16 3708#define IP6_RUL3_M2_IP6DPORTM_BLEN 16 3709#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW 3710 3711 3712#define IP6_RUL3_M3 8 3713#define IP6_RUL3_M3_OFFSET 0x5900c 3714#define IP6_RUL3_M3_E_LENGTH 4 3715#define IP6_RUL3_M3_E_OFFSET 0x20 3716#define IP6_RUL3_M3_NR_E 96 3717 3718#define IP6TCPFLAGM 3719#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET 24 3720#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN 6 3721#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG HSL_RW 3722 3723#define IP6RWDTYPM 3724#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET 23 3725#define IP6_RUL3_M3_IP6RWDTYPV_BLEN 1 3726#define IP6_RUL3_M3_IP6RWDTYPV_FLAG HSL_RW 3727 3728#define IP6DHCPM 3729#define IP6_RUL3_M3_IP6DHCPM_BOFFSET 22 3730#define IP6_RUL3_M3_IP6DHCPM_BLEN 1 3731#define IP6_RUL3_M3_IP6DHCPM_FLAG HSL_RW 3732 3733#define IP6DPORTM_EN 3734#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17 3735#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1 3736#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW 3737 3738#define IP6SPORTM_EN 3739#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16 3740#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1 3741#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW 3742 3743#define IP6SPORTM 3744#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0 3745#define IP6_RUL3_M3_IP6SPORTM_BLEN 16 3746#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW 3747 3748#define IP6ICMPTYPM 3749#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET 8 3750#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN 8 3751#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG HSL_RW 3752 3753#define IP6ICMPCODEM 3754#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET 0 3755#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN 8 3756#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG HSL_RW 3757 3758 3759#define IP6_RUL3_M4 9 3760#define IP6_RUL3_M4_OFFSET 0x59010 3761#define IP6_RUL3_M4_E_LENGTH 4 3762#define IP6_RUL3_M4_E_OFFSET 0x20 3763#define IP6_RUL3_M4_NR_E 96 3764 3765 3766 3767 3768 /* Enhanced MAC Type Rule Field Define */ 3769#define EHMAC_RUL_V0 0 3770#define EHMAC_RUL_V0_OFFSET 0x58000 3771#define EHMAC_RUL_V0_E_LENGTH 4 3772#define EHMAC_RUL_V0_E_OFFSET 0x20 3773#define EHMAC_RUL_V0_NR_E 96 3774 3775#define DAV_BYTE2 3776#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET 24 3777#define EHMAC_RUL_V0_DAV_BYTE2_BLEN 8 3778#define EHMAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW 3779 3780#define DAV_BYTE3 3781#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET 16 3782#define EHMAC_RUL_V0_DAV_BYTE3_BLEN 8 3783#define EHMAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW 3784 3785#define DAV_BYTE4 3786#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET 8 3787#define EHMAC_RUL_V0_DAV_BYTE4_BLEN 8 3788#define EHMAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW 3789 3790#define DAV_BYTE5 3791#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET 0 3792#define EHMAC_RUL_V0_DAV_BYTE5_BLEN 8 3793#define EHMAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW 3794 3795 3796#define EHMAC_RUL_V1 1 3797#define EHMAC_RUL_V1_OFFSET 0x58004 3798#define EHMAC_RUL_V1_E_LENGTH 4 3799#define EHMAC_RUL_V1_E_OFFSET 0x20 3800#define EHMAC_RUL_V1_NR_E 96 3801 3802#define SAV_BYTE4 3803#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET 24 3804#define EHMAC_RUL_V1_SAV_BYTE4_BLEN 8 3805#define EHMAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW 3806 3807#define SAV_BYTE5 3808#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET 16 3809#define EHMAC_RUL_V1_SAV_BYTE5_BLEN 8 3810#define EHMAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW 3811 3812#define DAV_BYTE0 3813#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET 8 3814#define EHMAC_RUL_V1_DAV_BYTE0_BLEN 8 3815#define EHMAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW 3816 3817#define DAV_BYTE1 3818#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET 0 3819#define EHMAC_RUL_V1_DAV_BYTE1_BLEN 8 3820#define EHMAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW 3821 3822 3823#define EHMAC_RUL_V2 2 3824#define EHMAC_RUL_V2_OFFSET 0x58008 3825#define EHMAC_RUL_V2_E_LENGTH 4 3826#define EHMAC_RUL_V2_E_OFFSET 0x20 3827#define EHMAC_RUL_V2_NR_E 96 3828 3829#define CTAG_VIDLV 3830#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET 24 3831#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN 8 3832#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG HSL_RW 3833 3834#define STAG_PRIV 3835#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET 21 3836#define EHMAC_RUL_V2_STAG_PRIV_BLEN 3 3837#define EHMAC_RUL_V2_STAG_PRIV_FLAG HSL_RW 3838 3839#define STAG_DEIV 3840#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET 20 3841#define EHMAC_RUL_V2_STAG_DEIV_BLEN 1 3842#define EHMAC_RUL_V2_STAG_DEIV_FLAG HSL_RW 3843 3844#define STAG_VIDV 3845#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET 8 3846#define EHMAC_RUL_V2_STAG_VIDV_BLEN 12 3847#define EHMAC_RUL_V2_STAG_VIDV_FLAG HSL_RW 3848 3849#define SAV_BYTE3 3850#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET 0 3851#define EHMAC_RUL_V2_SAV_BYTE3_BLEN 8 3852#define EHMAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW 3853 3854 3855#define EHMAC_RUL_V3 3 3856#define EHMAC_RUL_V3_ID 13 3857#define EHMAC_RUL_V3_OFFSET 0x5800c 3858#define EHMAC_RUL_V3_E_LENGTH 4 3859#define EHMAC_RUL_V3_E_OFFSET 0x20 3860#define EHMAC_RUL_V3_NR_E 96 3861 3862#define STAGGEDM 3863#define EHMAC_RUL_V3_STAGGEDM_BOFFSET 31 3864#define EHMAC_RUL_V3_STAGGEDM_BLEN 1 3865#define EHMAC_RUL_V3_STAGGEDM_FLAG HSL_RW 3866 3867#define STAGGEDV 3868#define EHMAC_RUL_V3_STAGGEDV_BOFFSET 30 3869#define EHMAC_RUL_V3_STAGGEDV_BLEN 1 3870#define EHMAC_RUL_V3_STAGGEDV_FLAG HSL_RW 3871 3872#define DA_EN 3873#define EHMAC_RUL_V3_DA_EN_BOFFSET 25 3874#define EHMAC_RUL_V3_DA_EN_BLEN 1 3875#define EHMAC_RUL_V3_DA_EN_FLAG HSL_RW 3876 3877#define SVIDMSK 3878#define EHMAC_RUL_V3_SVIDMSK_BOFFSET 24 3879#define EHMAC_RUL_V3_SVIDMSK_BLEN 1 3880#define EHMAC_RUL_V3_SVIDMSK_FLAG HSL_RW 3881 3882#define ETHTYPV 3883#define EHMAC_RUL_V3_ETHTYPV_BOFFSET 8 3884#define EHMAC_RUL_V3_ETHTYPV_BLEN 16 3885#define EHMAC_RUL_V3_ETHTYPV_FLAG HSL_RW 3886 3887#define CTAG_PRIV 3888#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET 5 3889#define EHMAC_RUL_V3_CTAG_PRIV_BLEN 3 3890#define EHMAC_RUL_V3_CTAG_PRIV_FLAG HSL_RW 3891 3892#define CTAG_CFIV 3893#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET 4 3894#define EHMAC_RUL_V3_CTAG_CFIV_BLEN 1 3895#define EHMAC_RUL_V3_CTAG_CFIV_FLAG HSL_RW 3896 3897#define CTAG_VIDHV 3898#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET 0 3899#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN 4 3900#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG HSL_RW 3901 3902 3903#define EHMAC_RUL_V4 4 3904#define EHMAC_RUL_V4_OFFSET 0x58010 3905#define EHMAC_RUL_V4_E_LENGTH 4 3906#define EHMAC_RUL_V4_E_OFFSET 0x20 3907#define EHMAC_RUL_V4_NR_E 96 3908 3909 3910#define EHMAC_RUL_M0 5 3911#define EHMAC_RUL_M0_OFFSET 0x59000 3912#define EHMAC_RUL_M0_E_LENGTH 4 3913#define EHMAC_RUL_M0_E_OFFSET 0x20 3914#define EHMAC_RUL_M0_NR_E 96 3915 3916#define DAM_BYTE2 3917#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET 24 3918#define EHMAC_RUL_M0_DAM_BYTE2_BLEN 8 3919#define EHMAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW 3920 3921#define DAM_BYTE3 3922#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET 16 3923#define EHMAC_RUL_M0_DAM_BYTE3_BLEN 8 3924#define EHMAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW 3925 3926#define DAM_BYTE4 3927#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET 8 3928#define EHMAC_RUL_M0_DAM_BYTE4_BLEN 8 3929#define EHMAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW 3930 3931#define DAM_BYTE5 3932#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET 0 3933#define EHMAC_RUL_M0_DAM_BYTE5_BLEN 8 3934#define EHMAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW 3935 3936 3937#define EHMAC_RUL_M1 6 3938#define EHMAC_RUL_M1_OFFSET 0x59004 3939#define EHMAC_RUL_M1_E_LENGTH 4 3940#define EHMAC_RUL_M1_E_OFFSET 0x20 3941#define EHMAC_RUL_M1_NR_E 96 3942 3943#define SAM_BYTE4 3944#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET 24 3945#define EHMAC_RUL_M1_SAM_BYTE4_BLEN 8 3946#define EHMAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW 3947 3948#define SAM_BYTE5 3949#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET 16 3950#define EHMAC_RUL_M1_SAM_BYTE5_BLEN 8 3951#define EHMAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW 3952 3953#define DAM_BYTE0 3954#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET 8 3955#define EHMAC_RUL_M1_DAM_BYTE0_BLEN 8 3956#define EHMAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW 3957 3958#define DAM_BYTE1 3959#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET 0 3960#define EHMAC_RUL_M1_DAM_BYTE1_BLEN 8 3961#define EHMAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW 3962 3963 3964#define EHMAC_RUL_M2 7 3965#define EHMAC_RUL_M2_OFFSET 0x59008 3966#define EHMAC_RUL_M2_E_LENGTH 4 3967#define EHMAC_RUL_M2_E_OFFSET 0x20 3968#define EHMAC_RUL_M2_NR_E 96 3969 3970#define CTAG_VIDLM 3971#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET 24 3972#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN 8 3973#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG HSL_RW 3974 3975#define STAG_PRIM 3976#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET 21 3977#define EHMAC_RUL_M2_STAG_PRIM_BLEN 3 3978#define EHMAC_RUL_M2_STAG_PRIM_FLAG HSL_RW 3979 3980#define STAG_DEIM 3981#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET 20 3982#define EHMAC_RUL_M2_STAG_DEIM_BLEN 1 3983#define EHMAC_RUL_M2_STAG_DEIM_FLAG HSL_RW 3984 3985#define STAG_VIDM 3986#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET 8 3987#define EHMAC_RUL_M2_STAG_VIDM_BLEN 12 3988#define EHMAC_RUL_M2_STAG_VIDM_FLAG HSL_RW 3989 3990#define SAM_BYTE3 3991#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET 0 3992#define EHMAC_RUL_M2_SAM_BYTE3_BLEN 8 3993#define EHMAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW 3994 3995 3996#define EHMAC_RUL_M3 8 3997#define EHMAC_RUL_M3_OFFSET 0x5900c 3998#define EHMAC_RUL_M3_E_LENGTH 4 3999#define EHMAC_RUL_M3_E_OFFSET 0x20 4000#define EHMAC_RUL_M3_NR_E 96 4001 4002#define ETHTYPM 4003#define EHMAC_RUL_M3_ETHTYPM_BOFFSET 8 4004#define EHMAC_RUL_M3_ETHTYPM_BLEN 16 4005#define EHMAC_RUL_M3_ETHTYPM_FLAG HSL_RW 4006 4007#define CTAG_PRIM 4008#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET 5 4009#define EHMAC_RUL_M3_CTAG_PRIM_BLEN 3 4010#define EHMAC_RUL_M3_CTAG_PRIM_FLAG HSL_RW 4011 4012#define CTAG_CFIM 4013#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET 4 4014#define EHMAC_RUL_M3_CTAG_CFIM_BLEN 1 4015#define EHMAC_RUL_M3_CTAG_CFIM_FLAG HSL_RW 4016 4017#define CTAG_VIDHM 4018#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET 0 4019#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN 4 4020#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG HSL_RW 4021 4022 4023#define EHMAC_RUL_M4 9 4024#define EHMAC_RUL_M4_OFFSET 0x59010 4025#define EHMAC_RUL_M4_E_LENGTH 4 4026#define EHMAC_RUL_M4_E_OFFSET 0x20 4027#define EHMAC_RUL_M4_NR_E 96 4028 4029#define CTAGGEDM 4030#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET 5 4031#define EHMAC_RUL_M4_CTAGGEDM_BLEN 1 4032#define EHMAC_RUL_M4_CTAGGEDM_FLAG HSL_RW 4033 4034#define CTAGGEDV 4035#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET 4 4036#define EHMAC_RUL_M4_CTAGGEDV_BLEN 1 4037#define EHMAC_RUL_M4_CTAGGEDV_FLAG HSL_RW 4038 4039#define CVIDMSK 4040#define EHMAC_RUL_M4_CVIDMSK_BOFFSET 3 4041#define EHMAC_RUL_M4_CVIDMSK_BLEN 1 4042#define EHMAC_RUL_M4_CVIDMSK_FLAG HSL_RW 4043 4044 4045 4046 4047 /* PPPoE Session Table Define */ 4048#define PPPOE_SESSION 4049#define PPPOE_SESSION_OFFSET 0x5f000 4050#define PPPOE_SESSION_E_LENGTH 4 4051#define PPPOE_SESSION_E_OFFSET 0x4 4052#define PPPOE_SESSION_NR_E 16 4053 4054#define ENTRY_VALID 4055#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 16 4056#define PPPOE_SESSION_ENTRY_VALID_BLEN 2 4057#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW 4058 4059#define SEESION_ID 4060#define PPPOE_SESSION_SEESION_ID_BOFFSET 0 4061#define PPPOE_SESSION_SEESION_ID_BLEN 16 4062#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW 4063 4064 4065#define PPPOE_EDIT 4066#define PPPOE_EDIT_OFFSET 0x02200 4067#define PPPOE_EDIT_E_LENGTH 4 4068#define PPPOE_EDIT_E_OFFSET 0x10 4069#define PPPOE_EDIT_NR_E 16 4070 4071#define EDIT_ID 4072#define PPPOE_EDIT_EDIT_ID_BOFFSET 0 4073#define PPPOE_EDIT_EDIT_ID_BLEN 16 4074#define PPPOE_EDIT_EDIT_ID_FLAG HSL_RW 4075 4076 4077 4078 4079 /* L3 Host Entry Defile */ 4080#define HOST_ENTRY0 4081#define HOST_ENTRY0_OFFSET 0x0e48 4082#define HOST_ENTRY0_E_LENGTH 4 4083#define HOST_ENTRY0_E_OFFSET 0x0 4084#define HOST_ENTRY0_NR_E 1 4085 4086#define IP_ADDR 4087#define HOST_ENTRY0_IP_ADDR_BOFFSET 0 4088#define HOST_ENTRY0_IP_ADDR_BLEN 32 4089#define HOST_ENTRY0_IP_ADDR_FLAG HSL_RW 4090 4091#define HOST_ENTRY1 4092#define HOST_ENTRY1_OFFSET 0x0e4c 4093#define HOST_ENTRY1_E_LENGTH 4 4094#define HOST_ENTRY1_E_OFFSET 0x0 4095#define HOST_ENTRY1_NR_E 1 4096 4097#define MAC_ADDR2 4098#define HOST_ENTRY1_MAC_ADDR2_BOFFSET 24 4099#define HOST_ENTRY1_MAC_ADDR2_BLEN 8 4100#define HOST_ENTRY1_MAC_ADDR2_FLAG HSL_RW 4101 4102#define MAC_ADDR3 4103#define HOST_ENTRY1_MAC_ADDR3_BOFFSET 16 4104#define HOST_ENTRY1_MAC_ADDR3_BLEN 8 4105#define HOST_ENTRY1_MAC_ADDR3_FLAG HSL_RW 4106 4107#define MAC_ADDR4 4108#define HOST_ENTRY1_MAC_ADDR4_BOFFSET 8 4109#define HOST_ENTRY1_MAC_ADDR4_BLEN 8 4110#define HOST_ENTRY1_MAC_ADDR4_FLAG HSL_RW 4111 4112#define MAC_ADDR5 4113#define HOST_ENTRY1_MAC_ADDR5_BOFFSET 0 4114#define HOST_ENTRY1_MAC_ADDR5_BLEN 8 4115#define HOST_ENTRY1_MAC_ADDR5_FLAG HSL_RW 4116 4117#define HOST_ENTRY2 4118#define HOST_ENTRY2_OFFSET 0x0e50 4119#define HOST_ENTRY2_E_LENGTH 4 4120#define HOST_ENTRY2_E_OFFSET 0x0 4121#define HOST_ENTRY2_NR_E 1 4122 4123#define CPU_ADDR 4124#define HOST_ENTRY2_CPU_ADDR_BOFFSET 31 4125#define HOST_ENTRY2_CPU_ADDR_BLEN 1 4126#define HOST_ENTRY2_CPU_ADDR_FLAG HSL_RW 4127 4128#define SRC_PORT 4129#define HOST_ENTRY2_SRC_PORT_BOFFSET 28 4130#define HOST_ENTRY2_SRC_PORT_BLEN 3 4131#define HOST_ENTRY2_SRC_PORT_FLAG HSL_RW 4132 4133#define INTF_ID 4134#define HOST_ENTRY2_INTF_ID_BOFFSET 16 4135#define HOST_ENTRY2_INTF_ID_BLEN 12 4136#define HOST_ENTRY2_INTF_ID_FLAG HSL_RW 4137 4138#define MAC_ADDR0 4139#define HOST_ENTRY2_MAC_ADDR0_BOFFSET 8 4140#define HOST_ENTRY2_MAC_ADDR0_BLEN 8 4141#define HOST_ENTRY2_MAC_ADDR0_FLAG HSL_RW 4142 4143#define MAC_ADDR1 4144#define HOST_ENTRY2_MAC_ADDR1_BOFFSET 0 4145#define HOST_ENTRY2_MAC_ADDR1_BLEN 8 4146#define HOST_ENTRY2_MAC_ADDR1_FLAG HSL_RW 4147 4148 4149#define HOST_ENTRY3 4150#define HOST_ENTRY3_OFFSET 0x0e54 4151#define HOST_ENTRY3_E_LENGTH 4 4152#define HOST_ENTRY3_E_OFFSET 0x0 4153#define HOST_ENTRY3_NR_E 1 4154 4155#define IP_VER 4156#define HOST_ENTRY3_IP_VER_BOFFSET 15 4157#define HOST_ENTRY3_IP_VER_BLEN 1 4158#define HOST_ENTRY3_IP_VER_FLAG HSL_RW 4159 4160#define AGE_FLAG 4161#define HOST_ENTRY3_AGE_FLAG_BOFFSET 12 4162#define HOST_ENTRY3_AGE_FLAG_BLEN 3 4163#define HOST_ENTRY3_AGE_FLAG_FLAG HSL_RW 4164 4165#define PPPOE_EN 4166#define HOST_ENTRY3_PPPOE_EN_BOFFSET 11 4167#define HOST_ENTRY3_PPPOE_EN_BLEN 1 4168#define HOST_ENTRY3_PPPOE_EN_FLAG HSL_RW 4169 4170#define PPPOE_IDX 4171#define HOST_ENTRY3_PPPOE_IDX_BOFFSET 7 4172#define HOST_ENTRY3_PPPOE_IDX_BLEN 4 4173#define HOST_ENTRY3_PPPOE_IDX_FLAG HSL_RW 4174 4175#define CNT_EN 4176#define HOST_ENTRY3_CNT_EN_BOFFSET 6 4177#define HOST_ENTRY3_CNT_EN_BLEN 1 4178#define HOST_ENTRY3_CNT_EN_FLAG HSL_RW 4179 4180#define CNT_IDX 4181#define HOST_ENTRY3_CNT_IDX_BOFFSET 2 4182#define HOST_ENTRY3_CNT_IDX_BLEN 4 4183#define HOST_ENTRY3_CNT_IDX_FLAG HSL_RW 4184 4185#define ACTION 4186#define HOST_ENTRY3_ACTION_BOFFSET 0 4187#define HOST_ENTRY3_ACTION_BLEN 2 4188#define HOST_ENTRY3_ACTION_FLAG HSL_RW 4189 4190 4191#define HOST_ENTRY4 4192#define HOST_ENTRY4_OFFSET 0x0e58 4193#define HOST_ENTRY4_E_LENGTH 4 4194#define HOST_ENTRY4_E_OFFSET 0x0 4195#define HOST_ENTRY4_NR_E 1 4196 4197#define TBL_BUSY 4198#define HOST_ENTRY4_TBL_BUSY_BOFFSET 31 4199#define HOST_ENTRY4_TBL_BUSY_BLEN 1 4200#define HOST_ENTRY4_TBL_BUSY_FLAG HSL_RW 4201 4202#define SPEC_SP 4203#define HOST_ENTRY4_SPEC_SP_BOFFSET 22 4204#define HOST_ENTRY4_SPEC_SP_BLEN 1 4205#define HOST_ENTRY4_SPEC_SP_FLAG HSL_RW 4206 4207#define SPEC_VID 4208#define HOST_ENTRY4_SPEC_VID_BOFFSET 21 4209#define HOST_ENTRY4_SPEC_VID_BLEN 1 4210#define HOST_ENTRY4_SPEC_VID_FLAG HSL_RW 4211 4212#define SPEC_PIP 4213#define HOST_ENTRY4_SPEC_PIP_BOFFSET 20 4214#define HOST_ENTRY4_SPEC_PIP_BLEN 1 4215#define HOST_ENTRY4_SPEC_PIP_FLAG HSL_RW 4216 4217#define SPEC_SIP 4218#define HOST_ENTRY4_SPEC_SIP_BOFFSET 19 4219#define HOST_ENTRY4_SPEC_SIP_BLEN 1 4220#define HOST_ENTRY4_SPEC_SIP_FLAG HSL_RW 4221 4222#define SPEC_STATUS 4223#define HOST_ENTRY4_SPEC_STATUS_BOFFSET 18 4224#define HOST_ENTRY4_SPEC_STATUS_BLEN 1 4225#define HOST_ENTRY4_SPEC_STATUS_FLAG HSL_RW 4226 4227#define TBL_IDX 4228#define HOST_ENTRY4_TBL_IDX_BOFFSET 8 4229#define HOST_ENTRY4_TBL_IDX_BLEN 10 4230#define HOST_ENTRY4_TBL_IDX_FLAG HSL_RW 4231 4232#define TBL_STAUS 4233#define HOST_ENTRY4_TBL_STAUS_BOFFSET 7 4234#define HOST_ENTRY4_TBL_STAUS_BLEN 1 4235#define HOST_ENTRY4_TBL_STAUS_FLAG HSL_RW 4236 4237#define TBL_SEL 4238#define HOST_ENTRY4_TBL_SEL_BOFFSET 4 4239#define HOST_ENTRY4_TBL_SEL_BLEN 2 4240#define HOST_ENTRY4_TBL_SEL_FLAG HSL_RW 4241 4242#define ENTRY_FUNC 4243#define HOST_ENTRY4_ENTRY_FUNC_BOFFSET 0 4244#define HOST_ENTRY4_ENTRY_FUNC_BLEN 3 4245#define HOST_ENTRY4_ENTRY_FUNC_FLAG HSL_RW 4246 4247 4248 4249 4250#define NAT_ENTRY0 4251#define NAT_ENTRY0_OFFSET 0x0e48 4252#define NAT_ENTRY0_E_LENGTH 4 4253#define NAT_ENTRY0_E_OFFSET 0x0 4254#define NAT_ENTRY0_NR_E 1 4255 4256#define IP_ADDR 4257#define NAT_ENTRY0_IP_ADDR_BOFFSET 0 4258#define NAT_ENTRY0_IP_ADDR_BLEN 32 4259#define NAT_ENTRY0_IP_ADDR_FLAG HSL_RW 4260 4261 4262#define NAT_ENTRY1 4263#define NAT_ENTRY1_OFFSET 0x0e4c 4264#define NAT_ENTRY1_E_LENGTH 4 4265#define NAT_ENTRY1_E_OFFSET 0x0 4266#define NAT_ENTRY1_NR_E 1 4267 4268#define PRV_IPADDR0 4269#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET 24 4270#define NAT_ENTRY1_PRV_IPADDR0_BLEN 8 4271#define NAT_ENTRY1_PRV_IPADDR0_FLAG HSL_RW 4272 4273#define PORT_RANGE 4274#define NAT_ENTRY1_PORT_RANGE_BOFFSET 16 4275#define NAT_ENTRY1_PORT_RANGE_BLEN 8 4276#define NAT_ENTRY1_PORT_RANGE_FLAG HSL_RW 4277 4278#define PORT_NUM 4279#define NAT_ENTRY1_PORT_NUM_BOFFSET 0 4280#define NAT_ENTRY1_PORT_NUM_BLEN 16 4281#define NAT_ENTRY1_PORT_NUM_FLAG HSL_RW 4282 4283 4284#define NAT_ENTRY2 4285#define NAT_ENTRY2_OFFSET 0x0e50 4286#define NAT_ENTRY2_E_LENGTH 4 4287#define NAT_ENTRY2_E_OFFSET 0x0 4288#define NAT_ENTRY2_NR_E 1 4289 4290#define ENTRY_VALID 4291#define NAT_ENTRY2_ENTRY_VALID_BOFFSET 15 4292#define NAT_ENTRY2_ENTRY_VALID_BLEN 1 4293#define NAT_ENTRY2_ENTRY_VALID_FLAG HSL_RW 4294 4295#define PORT_EN 4296#define NAT_ENTRY2_PORT_EN_BOFFSET 14 4297#define NAT_ENTRY2_PORT_EN_BLEN 1 4298#define NAT_ENTRY2_PORT_EN_FLAG HSL_RW 4299 4300#define PRO_TYP 4301#define NAT_ENTRY2_PRO_TYP_BOFFSET 12 4302#define NAT_ENTRY2_PRO_TYP_BLEN 2 4303#define NAT_ENTRY2_PRO_TYP_FLAG HSL_RW 4304 4305#define HASH_KEY 4306#define NAT_ENTRY2_HASH_KEY_BOFFSET 10 4307#define NAT_ENTRY2_HASH_KEY_BLEN 2 4308#define NAT_ENTRY2_HASH_KEY_FLAG HSL_RW 4309 4310#define ACTION 4311#define NAT_ENTRY2_ACTION_BOFFSET 8 4312#define NAT_ENTRY2_ACTION_BLEN 2 4313#define NAT_ENTRY2_ACTION_FLAG HSL_RW 4314 4315#define CNT_EN 4316#define NAT_ENTRY2_CNT_EN_BOFFSET 7 4317#define NAT_ENTRY2_CNT_EN_BLEN 1 4318#define NAT_ENTRY2_CNT_EN_FLAG HSL_RW 4319 4320#define CNT_IDX 4321#define NAT_ENTRY2_CNT_IDX_BOFFSET 4 4322#define NAT_ENTRY2_CNT_IDX_BLEN 3 4323#define NAT_ENTRY2_CNT_IDX_FLAG HSL_RW 4324 4325#define PRV_IPADDR1 4326#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET 0 4327#define NAT_ENTRY2_PRV_IPADDR1_BLEN 4 4328#define NAT_ENTRY2_PRV_IPADDR1_FLAG HSL_RW 4329 4330 4331 4332 4333#define NAPT_ENTRY0 4334#define NAPT_ENTRY0_OFFSET 0x0e48 4335#define NAPT_ENTRY0_E_LENGTH 4 4336#define NAPT_ENTRY0_E_OFFSET 0x0 4337#define NAPT_ENTRY0_NR_E 1 4338 4339#define DST_IPADDR 4340#define NAPT_ENTRY0_DST_IPADDR_BOFFSET 0 4341#define NAPT_ENTRY0_DST_IPADDR_BLEN 32 4342#define NAPT_ENTRY0_DST_IPADDR_FLAG HSL_RW 4343 4344 4345#define NAPT_ENTRY1 4346#define NAPT_ENTRY1_OFFSET 0x0e4c 4347#define NAPT_ENTRY1_E_LENGTH 4 4348#define NAPT_ENTRY1_E_OFFSET 0x0 4349#define NAPT_ENTRY1_NR_E 1 4350 4351#define SRC_PORT 4352#define NAPT_ENTRY1_SRC_PORT_BOFFSET 16 4353#define NAPT_ENTRY1_SRC_PORT_BLEN 16 4354#define NAPT_ENTRY1_SRC_PORT_FLAG HSL_RW 4355 4356#define DST_PORT 4357#define NAPT_ENTRY1_DST_PORT_BOFFSET 0 4358#define NAPT_ENTRY1_DST_PORT_BLEN 16 4359#define NAPT_ENTRY1_DST_PORT_FLAG HSL_RW 4360 4361 4362#define NAPT_ENTRY2 4363#define NAPT_ENTRY2_OFFSET 0x0e50 4364#define NAPT_ENTRY2_E_LENGTH 4 4365#define NAPT_ENTRY2_E_OFFSET 0x0 4366#define NAPT_ENTRY2_NR_E 1 4367 4368#define SRC_IPADDR 4369#define NAPT_ENTRY2_SRC_IPADDR_BOFFSET 20 4370#define NAPT_ENTRY2_SRC_IPADDR_BLEN 12 4371#define NAPT_ENTRY2_SRC_IPADDR_FLAG HSL_RW 4372 4373#define TRANS_IPADDR 4374#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET 16 4375#define NAPT_ENTRY2_TRANS_IPADDR_BLEN 4 4376#define NAPT_ENTRY2_TRANS_IPADDR_FLAG HSL_RW 4377 4378#define TRANS_PORT 4379#define NAPT_ENTRY2_TRANS_PORT_BOFFSET 0 4380#define NAPT_ENTRY2_TRANS_PORT_BLEN 16 4381#define NAPT_ENTRY2_TRANS_PORT_FLAG HSL_RW 4382 4383 4384#define NAPT_ENTRY3 4385#define NAPT_ENTRY3_OFFSET 0x0e54 4386#define NAPT_ENTRY3_E_LENGTH 4 4387#define NAPT_ENTRY3_E_OFFSET 0x0 4388#define NAPT_ENTRY3_NR_E 1 4389 4390#define AGE_FLAG 4391#define NAPT_ENTRY3_AGE_FLAG_BOFFSET 12 4392#define NAPT_ENTRY3_AGE_FLAG_BLEN 4 4393#define NAPT_ENTRY3_AGE_FLAG_FLAG HSL_RW 4394 4395#define CNT_EN 4396#define NAPT_ENTRY3_CNT_EN_BOFFSET 7 4397#define NAPT_ENTRY3_CNT_EN_BLEN 1 4398#define NAPT_ENTRY3_CNT_EN_FLAG HSL_RW 4399 4400#define CNT_IDX 4401#define NAPT_ENTRY3_CNT_IDX_BOFFSET 4 4402#define NAPT_ENTRY3_CNT_IDX_BLEN 3 4403#define NAPT_ENTRY3_CNT_IDX_FLAG HSL_RW 4404 4405#define PROT_TYP 4406#define NAPT_ENTRY3_PROT_TYP_BOFFSET 2 4407#define NAPT_ENTRY3_PROT_TYP_BLEN 2 4408#define NAPT_ENTRY3_PROT_TYP_FLAG HSL_RW 4409 4410#define ACTION 4411#define NAPT_ENTRY3_ACTION_BOFFSET 0 4412#define NAPT_ENTRY3_ACTION_BLEN 2 4413#define NAPT_ENTRY3_ACTION_FLAG HSL_RW 4414 4415 4416 4417 4418#define ROUTER_CTRL 4419#define ROUTER_CTRL_OFFSET 0x0e00 4420#define ROUTER_CTRL_E_LENGTH 4 4421#define ROUTER_CTRL_E_OFFSET 0x0 4422#define ROUTER_CTRL_NR_E 1 4423 4424#define ARP_LEARN_MODE 4425#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET 19 4426#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN 1 4427#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG HSL_RW 4428 4429#define GLB_LOCKTIME 4430#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET 16 4431#define ROUTER_CTRL_GLB_LOCKTIME_BLEN 2 4432#define ROUTER_CTRL_GLB_LOCKTIME_FLAG HSL_RW 4433 4434#define ARP_AGE_TIME 4435#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET 8 4436#define ROUTER_CTRL_ARP_AGE_TIME_BLEN 8 4437#define ROUTER_CTRL_ARP_AGE_TIME_FLAG HSL_RW 4438 4439#define WCMP_HAHS_DP 4440#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET 7 4441#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN 1 4442#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG HSL_RW 4443 4444#define WCMP_HAHS_DIP 4445#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET 6 4446#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN 1 4447#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG HSL_RW 4448 4449#define WCMP_HAHS_SP 4450#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET 5 4451#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN 1 4452#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG HSL_RW 4453 4454#define WCMP_HAHS_SIP 4455#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET 4 4456#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN 1 4457#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG HSL_RW 4458 4459#define ARP_AGE_MODE 4460#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET 1 4461#define ROUTER_CTRL_ARP_AGE_MODE_BLEN 1 4462#define ROUTER_CTRL_ARP_AGE_MODE_FLAG HSL_RW 4463 4464#define ROUTER_EN 4465#define ROUTER_CTRL_ROUTER_EN_BOFFSET 0 4466#define ROUTER_CTRL_ROUTER_EN_BLEN 1 4467#define ROUTER_CTRL_ROUTER_EN_FLAG HSL_RW 4468 4469 4470 4471 4472#define ROUTER_PTCTRL0 4473#define ROUTER_PTCTRL0_OFFSET 0x0e04 4474#define ROUTER_PTCTRL0_E_LENGTH 4 4475#define ROUTER_PTCTRL0_E_OFFSET 0x0 4476#define ROUTER_PTCTRL0_NR_E 1 4477 4478 4479 4480 4481#define ROUTER_PTCTRL1 4482#define ROUTER_PTCTRL1_OFFSET 0x0e08 4483#define ROUTER_PTCTRL1_E_LENGTH 4 4484#define ROUTER_PTCTRL1_E_OFFSET 0x0 4485#define ROUTER_PTCTRL1_NR_E 1 4486 4487 4488 4489#define ROUTER_PTCTRL2 4490#define ROUTER_PTCTRL2_OFFSET 0x0e0c 4491#define ROUTER_PTCTRL2_E_LENGTH 4 4492#define ROUTER_PTCTRL2_E_OFFSET 0x0 4493#define ROUTER_PTCTRL2_NR_E 1 4494 4495#define ARP_PT_UP 4496#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET 16 4497#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN 7 4498#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG HSL_RW 4499 4500#define ARP_LEARN_ACK 4501#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET 8 4502#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN 7 4503#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG HSL_RW 4504 4505#define ARP_LEARN_REQ 4506#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET 0 4507#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN 7 4508#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG HSL_RW 4509 4510 4511 4512 4513#define NAT_CTRL 4514#define NAT_CTRL_OFFSET 0x0e38 4515#define NAT_CTRL_E_LENGTH 4 4516#define NAT_CTRL_E_OFFSET 0x0 4517#define NAT_CTRL_NR_E 1 4518 4519#define NAT_HASH_MODE 4520#define NAT_CTRL_NAT_HASH_MODE_BOFFSET 5 4521#define NAT_CTRL_NAT_HASH_MODE_BLEN 2 4522#define NAT_CTRL_NAT_HASH_MODE_FLAG HSL_RW 4523 4524#define NAPT_OVERRIDE 4525#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET 4 4526#define NAT_CTRL_NAPT_OVERRIDE_BLEN 1 4527#define NAT_CTRL_NAPT_OVERRIDE_FLAG HSL_RW 4528 4529#define NAPT_MODE 4530#define NAT_CTRL_NAPT_MODE_BOFFSET 2 4531#define NAT_CTRL_NAPT_MODE_BLEN 2 4532#define NAT_CTRL_NAPT_MODE_FLAG HSL_RW 4533 4534#define NAT_EN 4535#define NAT_CTRL_NAT_EN_BOFFSET 1 4536#define NAT_CTRL_NAT_EN_BLEN 1 4537#define NAT_CTRL_NAT_EN_FLAG HSL_RW 4538 4539#define NAPT_EN 4540#define NAT_CTRL_NAPT_EN_BOFFSET 0 4541#define NAT_CTRL_NAPT_EN_BLEN 1 4542#define NAT_CTRL_NAPT_EN_FLAG HSL_RW 4543 4544 4545 4546 4547#define PRV_BASEADDR 4548#define PRV_BASEADDR_OFFSET 0x0e5c 4549#define PRV_BASEADDR_E_LENGTH 4 4550#define PRV_BASEADDR_E_OFFSET 0x0 4551#define PRV_BASEADDR_NR_E 1 4552 4553#define IP4_ADDR 4554#define PRV_BASEADDR_IP4_ADDR_BOFFSET 0 4555#define PRV_BASEADDR_IP4_ADDR_BLEN 20 4556#define PRV_BASEADDR_IP4_ADDR_FLAG HSL_RW 4557 4558 4559 4560 4561#define PRVIP_CTL 4562#define PRVIP_CTL_OFFSET 0x0418 4563#define PRVIP_CTL_E_LENGTH 4 4564#define PRVIP_CTL_E_OFFSET 0x0 4565#define PRVIP_CTL_NR_E 1 4566 4567#define BASEADDR_SEL 4568#define PRVIP_CTL_BASEADDR_SEL_BOFFSET 28 4569#define PRVIP_CTL_BASEADDR_SEL_BLEN 1 4570#define PRVIP_CTL_BASEADDR_SEL_FLAG HSL_RW 4571 4572#define IP4_BASEADDR 4573#define PRVIP_CTL_IP4_BASEADDR_BOFFSET 0 4574#define PRVIP_CTL_IP4_BASEADDR_BLEN 20 4575#define PRVIP_CTL_IP4_BASEADDR_FLAG HSL_RW 4576 4577 4578#define OFFLOAD_PRVIP_CTL 4579#define OFFLOAD_PRVIP_CTL_OFFSET 0x0e5c 4580#define OFFLOAD_PRVIP_CTL_E_LENGTH 4 4581#define OFFLOAD_PRVIP_CTL_E_OFFSET 0x0 4582#define OFFLOAD_PRVIP_CTL_NR_E 1 4583 4584#define IP4_BASEADDR 4585#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BOFFSET 0 4586#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BLEN 20 4587#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_FLAG HSL_RW 4588 4589 4590 4591 4592#define PUB_ADDR0 4593#define PUB_ADDR0_OFFSET 0x5aa00 4594#define PUB_ADDR0_E_LENGTH 4 4595#define PUB_ADDR0_E_OFFSET 0x0 4596#define PUB_ADDR0_NR_E 1 4597 4598#define IP4_ADDR 4599#define PUB_ADDR0_IP4_ADDR_BOFFSET 0 4600#define PUB_ADDR0_IP4_ADDR_BLEN 32 4601#define PUB_ADDR0_IP4_ADDR_FLAG HSL_RW 4602 4603 4604#define PUB_ADDR1 4605#define PUB_ADDR1_OFFSET 0x5aa04 4606#define PUB_ADDR1_E_LENGTH 4 4607#define PUB_ADDR1_E_OFFSET 0x0 4608#define PUB_ADDR1_NR_E 1 4609 4610#define ADDR_VALID 4611#define PUB_ADDR1_ADDR_VALID_BOFFSET 0 4612#define PUB_ADDR1_ADDR_VALID_BLEN 1 4613#define PUB_ADDR1_ADDR_VALID_FLAG HSL_RW 4614 4615 4616 4617 4618#define INTF_ADDR_ENTRY0 4619#define INTF_ADDR_ENTRY0_OFFSET 0x5aa00 4620#define INTF_ADDR_ENTRY0_E_LENGTH 4 4621#define INTF_ADDR_ENTRY0_E_OFFSET 0x0 4622#define INTF_ADDR_ENTRY0_NR_E 8 4623 4624#define MAC_ADDR2 4625#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET 24 4626#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN 8 4627#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG HSL_RW 4628 4629#define MAC_ADDR3 4630#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET 16 4631#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN 8 4632#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG HSL_RW 4633 4634#define MAC_ADDR4 4635#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET 8 4636#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN 8 4637#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG HSL_RW 4638 4639#define MAC_ADDR5 4640#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET 0 4641#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN 8 4642#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG HSL_RW 4643 4644 4645#define INTF_ADDR_ENTRY1 4646#define INTF_ADDR_ENTRY1_OFFSET 0x5aa04 4647#define INTF_ADDR_ENTRY1_E_LENGTH 4 4648#define INTF_ADDR_ENTRY1_E_OFFSET 0x0 4649#define INTF_ADDR_ENTRY1_NR_E 8 4650 4651#define VID_HIGH0 4652#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET 28 4653#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN 4 4654#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG HSL_RW 4655 4656#define VID_LOW 4657#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET 16 4658#define INTF_ADDR_ENTRY1_VID_LOW_BLEN 12 4659#define INTF_ADDR_ENTRY1_VID_LOW_FLAG HSL_RW 4660 4661#define MAC_ADDR0 4662#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET 8 4663#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN 8 4664#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG HSL_RW 4665 4666#define MAC_ADDR1 4667#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET 0 4668#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN 8 4669#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG HSL_RW 4670 4671 4672#define INTF_ADDR_ENTRY2 4673#define INTF_ADDR_ENTRY2_OFFSET 0x5aa08 4674#define INTF_ADDR_ENTRY2_E_LENGTH 4 4675#define INTF_ADDR_ENTRY2_E_OFFSET 0x0 4676#define INTF_ADDR_ENTRY2_NR_E 8 4677 4678#define IP6_ROUTE 4679#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET 9 4680#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN 1 4681#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG HSL_RW 4682 4683#define IP4_ROUTE 4684#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET 8 4685#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN 1 4686#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG HSL_RW 4687 4688#define VID_HIGH1 4689#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET 0 4690#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN 8 4691#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG HSL_RW 4692 4693 4694 4695 4696 /* Port Shaper Register0 */ 4697#define EG_SHAPER0 4698#define EG_SHAPER0_OFFSET 0x0890 4699#define EG_SHAPER0_E_LENGTH 4 4700#define EG_SHAPER0_E_OFFSET 0x0020 4701#define EG_SHAPER0_NR_E 7 4702 4703#define EG_Q1_CIR 4704#define EG_SHAPER0_EG_Q1_CIR_BOFFSET 16 4705#define EG_SHAPER0_EG_Q1_CIR_BLEN 15 4706#define EG_SHAPER0_EG_Q1_CIR_FLAG HSL_RW 4707 4708#define EG_Q0_CIR 4709#define EG_SHAPER0_EG_Q0_CIR_BOFFSET 0 4710#define EG_SHAPER0_EG_Q0_CIR_BLEN 15 4711#define EG_SHAPER0_EG_Q0_CIR_FLAG HSL_RW 4712 4713 4714 /* Port Shaper Register1 */ 4715#define EG_SHAPER1 4716#define EG_SHAPER1_OFFSET 0x0894 4717#define EG_SHAPER1_E_LENGTH 4 4718#define EG_SHAPER1_E_OFFSET 0x0020 4719#define EG_SHAPER1_NR_E 7 4720 4721#define EG_Q3_CIR 4722#define EG_SHAPER1_EG_Q3_CIR_BOFFSET 16 4723#define EG_SHAPER1_EG_Q3_CIR_BLEN 15 4724#define EG_SHAPER1_EG_Q3_CIR_FLAG HSL_RW 4725 4726#define EG_Q2_CIR 4727#define EG_SHAPER1_EG_Q2_CIR_BOFFSET 0 4728#define EG_SHAPER1_EG_Q2_CIR_BLEN 15 4729#define EG_SHAPER1_EG_Q2_CIR_FLAG HSL_RW 4730 4731 4732 /* Port Shaper Register2 */ 4733#define EG_SHAPER2 4734#define EG_SHAPER2_OFFSET 0x0898 4735#define EG_SHAPER2_E_LENGTH 4 4736#define EG_SHAPER2_E_OFFSET 0x0020 4737#define EG_SHAPER2_NR_E 7 4738 4739#define EG_Q5_CIR 4740#define EG_SHAPER2_EG_Q5_CIR_BOFFSET 16 4741#define EG_SHAPER2_EG_Q5_CIR_BLEN 15 4742#define EG_SHAPER2_EG_Q5_CIR_FLAG HSL_RW 4743 4744#define EG_Q4_CIR 4745#define EG_SHAPER2_EG_Q4_CIR_BOFFSET 0 4746#define EG_SHAPER2_EG_Q4_CIR_BLEN 15 4747#define EG_SHAPER2_EG_Q4_CIR_FLAG HSL_RW 4748 4749 4750 /* Port Shaper Register3 */ 4751#define EG_SHAPER3 4752#define EG_SHAPER3_OFFSET 0x089c 4753#define EG_SHAPER3_E_LENGTH 4 4754#define EG_SHAPER3_E_OFFSET 0x0020 4755#define EG_SHAPER3_NR_E 7 4756 4757#define EG_Q1_EIR 4758#define EG_SHAPER3_EG_Q1_EIR_BOFFSET 16 4759#define EG_SHAPER3_EG_Q1_EIR_BLEN 15 4760#define EG_SHAPER3_EG_Q1_EIR_FLAG HSL_RW 4761 4762#define EG_Q0_EIR 4763#define EG_SHAPER3_EG_Q0_EIR_BOFFSET 0 4764#define EG_SHAPER3_EG_Q0_EIR_BLEN 15 4765#define EG_SHAPER3_EG_Q0_EIR_FLAG HSL_RW 4766 4767 4768 /* Port Shaper Register4 */ 4769#define EG_SHAPER4 4770#define EG_SHAPER4_OFFSET 0x08a0 4771#define EG_SHAPER4_E_LENGTH 4 4772#define EG_SHAPER4_E_OFFSET 0x0020 4773#define EG_SHAPER4_NR_E 7 4774 4775#define EG_Q3_EIR 4776#define EG_SHAPER4_EG_Q3_EIR_BOFFSET 16 4777#define EG_SHAPER4_EG_Q3_EIR_BLEN 15 4778#define EG_SHAPER4_EG_Q3_EIR_FLAG HSL_RW 4779 4780#define EG_Q2_EIR 4781#define EG_SHAPER4_EG_Q2_EIR_BOFFSET 0 4782#define EG_SHAPER4_EG_Q2_EIR_BLEN 15 4783#define EG_SHAPER4_EG_Q2_EIR_FLAG HSL_RW 4784 4785 4786 /* Port Shaper Register5 */ 4787#define EG_SHAPER5 4788#define EG_SHAPER5_OFFSET 0x08a4 4789#define EG_SHAPER5_E_LENGTH 4 4790#define EG_SHAPER5_E_OFFSET 0x0020 4791#define EG_SHAPER5_NR_E 7 4792 4793#define EG_Q5_EIR 4794#define EG_SHAPER5_EG_Q5_EIR_BOFFSET 16 4795#define EG_SHAPER5_EG_Q5_EIR_BLEN 15 4796#define EG_SHAPER5_EG_Q5_EIR_FLAG HSL_RW 4797 4798#define EG_Q4_EIR 4799#define EG_SHAPER5_EG_Q4_EIR_BOFFSET 0 4800#define EG_SHAPER5_EG_Q4_EIR_BLEN 15 4801#define EG_SHAPER5_EG_Q4_EIR_FLAG HSL_RW 4802 4803 4804 /* Port Shaper Register6 */ 4805#define EG_SHAPER6 4806#define EG_SHAPER6_OFFSET 0x08a8 4807#define EG_SHAPER6_E_LENGTH 4 4808#define EG_SHAPER6_E_OFFSET 0x0020 4809#define EG_SHAPER6_NR_E 7 4810 4811#define EG_Q3_CBS 4812#define EG_SHAPER6_EG_Q3_CBS_BOFFSET 28 4813#define EG_SHAPER6_EG_Q3_CBS_BLEN 3 4814#define EG_SHAPER6_EG_Q3_CBS_FLAG HSL_RW 4815 4816#define EG_Q3_EBS 4817#define EG_SHAPER6_EG_Q3_EBS_BOFFSET 24 4818#define EG_SHAPER6_EG_Q3_EBS_BLEN 3 4819#define EG_SHAPER6_EG_Q3_EBS_FLAG HSL_RW 4820 4821#define EG_Q2_CBS 4822#define EG_SHAPER6_EG_Q2_CBS_BOFFSET 20 4823#define EG_SHAPER6_EG_Q2_CBS_BLEN 3 4824#define EG_SHAPER6_EG_Q2_CBS_FLAG HSL_RW 4825 4826#define EG_Q2_EBS 4827#define EG_SHAPER6_EG_Q2_EBS_BOFFSET 16 4828#define EG_SHAPER6_EG_Q2_EBS_BLEN 3 4829#define EG_SHAPER6_EG_Q2_EBS_FLAG HSL_RW 4830 4831#define EG_Q1_CBS 4832#define EG_SHAPER6_EG_Q1_CBS_BOFFSET 12 4833#define EG_SHAPER6_EG_Q1_CBS_BLEN 3 4834#define EG_SHAPER6_EG_Q1_CBS_FLAG HSL_RW 4835 4836#define EG_Q1_EBS 4837#define EG_SHAPER6_EG_Q1_EBS_BOFFSET 8 4838#define EG_SHAPER6_EG_Q1_EBS_BLEN 3 4839#define EG_SHAPER6_EG_Q1_EBS_FLAG HSL_RW 4840 4841#define EG_Q0_CBS 4842#define EG_SHAPER6_EG_Q0_CBS_BOFFSET 4 4843#define EG_SHAPER6_EG_Q0_CBS_BLEN 3 4844#define EG_SHAPER6_EG_Q0_CBS_FLAG HSL_RW 4845 4846#define EG_Q0_EBS 4847#define EG_SHAPER6_EG_Q0_EBS_BOFFSET 0 4848#define EG_SHAPER6_EG_Q0_EBS_BLEN 3 4849#define EG_SHAPER6_EG_Q0_EBS_FLAG HSL_RW 4850 4851 4852 /* Port Shaper Register7 */ 4853#define EG_SHAPER7 4854#define EG_SHAPER7_OFFSET 0x08ac 4855#define EG_SHAPER7_E_LENGTH 4 4856#define EG_SHAPER7_E_OFFSET 0x0020 4857#define EG_SHAPER7_NR_E 7 4858 4859#define EG_Q5_CBS 4860#define EG_SHAPER7_EG_Q5_CBS_BOFFSET 28 4861#define EG_SHAPER7_EG_Q5_CBS_BLEN 3 4862#define EG_SHAPER7_EG_Q5_CBS_FLAG HSL_RW 4863 4864#define EG_Q5_EBS 4865#define EG_SHAPER7_EG_Q5_EBS_BOFFSET 24 4866#define EG_SHAPER7_EG_Q5_EBS_BLEN 3 4867#define EG_SHAPER7_EG_Q5_EBS_FLAG HSL_RW 4868 4869#define EG_Q4_CBS 4870#define EG_SHAPER7_EG_Q4_CBS_BOFFSET 20 4871#define EG_SHAPER7_EG_Q4_CBS_BLEN 3 4872#define EG_SHAPER7_EG_Q4_CBS_FLAG HSL_RW 4873 4874#define EG_Q4_EBS 4875#define EG_SHAPER7_EG_Q4_EBS_BOFFSET 16 4876#define EG_SHAPER7_EG_Q4_EBS_BLEN 3 4877#define EG_SHAPER7_EG_Q4_EBS_FLAG HSL_RW 4878 4879#define EG_Q5_UNIT 4880#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET 13 4881#define EG_SHAPER7_EG_Q5_UNIT_BLEN 1 4882#define EG_SHAPER7_EG_Q5_UNIT_FLAG HSL_RW 4883 4884#define EG_Q4_UNIT 4885#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET 12 4886#define EG_SHAPER7_EG_Q4_UNIT_BLEN 1 4887#define EG_SHAPER7_EG_Q4_UNIT_FLAG HSL_RW 4888 4889#define EG_Q3_UNIT 4890#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET 11 4891#define EG_SHAPER7_EG_Q3_UNIT_BLEN 1 4892#define EG_SHAPER7_EG_Q3_UNIT_FLAG HSL_RW 4893 4894#define EG_Q2_UNIT 4895#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET 10 4896#define EG_SHAPER7_EG_Q2_UNIT_BLEN 1 4897#define EG_SHAPER7_EG_Q2_UNIT_FLAG HSL_RW 4898 4899#define EG_Q1_UNIT 4900#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET 9 4901#define EG_SHAPER7_EG_Q1_UNIT_BLEN 1 4902#define EG_SHAPER7_EG_Q1_UNIT_FLAG HSL_RW 4903 4904#define EG_Q0_UNIT 4905#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET 8 4906#define EG_SHAPER7_EG_Q0_UNIT_BLEN 1 4907#define EG_SHAPER7_EG_Q0_UNIT_FLAG HSL_RW 4908 4909#define EG_PT 4910#define EG_SHAPER7_EG_PT_BOFFSET 3 4911#define EG_SHAPER7_EG_PT_BLEN 1 4912#define EG_SHAPER7_EG_PT_FLAG HSL_RW 4913 4914#define EG_TS 4915#define EG_SHAPER7_EG_TS_BOFFSET 0 4916#define EG_SHAPER7_EG_TS_BLEN 3 4917#define EG_SHAPER7_EG_TS_FLAG HSL_RW 4918 4919 4920 4921 /* ACL Policer Register0 */ 4922#define ACL_POLICER0 4923#define ACL_POLICER0_OFFSET 0x0a00 4924#define ACL_POLICER0_E_LENGTH 4 4925#define ACL_POLICER0_E_OFFSET 0x0008 4926#define ACL_POLICER0_NR_E 32 4927 4928#define ACL_CBS 4929#define ACL_POLICER0_ACL_CBS_BOFFSET 15 4930#define ACL_POLICER0_ACL_CBS_BLEN 3 4931#define ACL_POLICER0_ACL_CBS_FLAG HSL_RW 4932 4933#define ACL_CIR 4934#define ACL_POLICER0_ACL_CIR_BOFFSET 0 4935#define ACL_POLICER0_ACL_CIR_BLEN 15 4936#define ACL_POLICER0_ACL_CIR_FLAG HSL_RW 4937 4938 4939 /* ACL Policer Register1 */ 4940#define ACL_POLICER1 4941#define ACL_POLICER1_OFFSET 0x0a04 4942#define ACL_POLICER1_E_LENGTH 4 4943#define ACL_POLICER1_E_OFFSET 0x0008 4944#define ACL_POLICER1_NR_E 32 4945 4946#define ACL_BORROW 4947#define ACL_POLICER1_ACL_BORROW_BOFFSET 23 4948#define ACL_POLICER1_ACL_BORROW_BLEN 1 4949#define ACL_POLICER1_ACL_BORROW_FLAG HSL_RW 4950 4951#define ACL_UNIT 4952#define ACL_POLICER1_ACL_UNIT_BOFFSET 22 4953#define ACL_POLICER1_ACL_UNIT_BLEN 1 4954#define ACL_POLICER1_ACL_UNIT_FLAG HSL_RW 4955 4956#define ACL_CF 4957#define ACL_POLICER1_ACL_CF_BOFFSET 21 4958#define ACL_POLICER1_ACL_CF_BLEN 1 4959#define ACL_POLICER1_ACL_CF_FLAG HSL_RW 4960 4961#define ACL_CM 4962#define ACL_POLICER1_ACL_CM_BOFFSET 20 4963#define ACL_POLICER1_ACL_CM_BLEN 1 4964#define ACL_POLICER1_ACL_CM_FLAG HSL_RW 4965 4966#define ACL_TS 4967#define ACL_POLICER1_ACL_TS_BOFFSET 18 4968#define ACL_POLICER1_ACL_TS_BLEN 2 4969#define ACL_POLICER1_ACL_TS_FLAG HSL_RW 4970 4971#define ACL_EBS 4972#define ACL_POLICER1_ACL_EBS_BOFFSET 15 4973#define ACL_POLICER1_ACL_EBS_BLEN 3 4974#define ACL_POLICER1_ACL_EBS_FLAG HSL_RW 4975 4976#define ACL_EIR 4977#define ACL_POLICER1_ACL_EIR_BOFFSET 0 4978#define ACL_POLICER1_ACL_EIR_BLEN 15 4979#define ACL_POLICER1_ACL_EIR_FLAG HSL_RW 4980 4981 4982 /* ACL Counter Register0 */ 4983#define ACL_COUNTER0 4984#define ACL_COUNTER0_OFFSET 0x1c000 4985#define ACL_COUNTER0_E_LENGTH 4 4986#define ACL_COUNTER0_E_OFFSET 0x0008 4987#define ACL_COUNTER0_NR_E 32 4988 4989 /* ACL Counter Register1 */ 4990#define ACL_COUNTER1 4991#define ACL_COUNTER1_OFFSET 0x1c004 4992#define ACL_COUNTER1_E_LENGTH 4 4993#define ACL_COUNTER1_E_OFFSET 0x0008 4994#define ACL_COUNTER1_NR_E 32 4995 4996 4997 4998 4999 /* INGRESS Policer Register0 */ 5000#define INGRESS_POLICER0 5001#define INGRESS_POLICER0_OFFSET 0x0b00 5002#define INGRESS_POLICER0_E_LENGTH 4 5003#define INGRESS_POLICER0_E_OFFSET 0x0010 5004#define INGRESS_POLICER0_NR_E 7 5005 5006#define ADD_RATE_BYTE 5007#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24 5008#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8 5009#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW 5010 5011#define C_ING_TS 5012#define INGRESS_POLICER0_C_ING_TS_BOFFSET 22 5013#define INGRESS_POLICER0_C_ING_TS_BLEN 2 5014#define INGRESS_POLICER0_C_ING_TS_FLAG HSL_RW 5015 5016#define RATE_MODE 5017#define INGRESS_POLICER0_RATE_MODE_BOFFSET 20 5018#define INGRESS_POLICER0_RATE_MODE_BLEN 1 5019#define INGRESS_POLICER0_RATE_MODE_FLAG HSL_RW 5020 5021#define INGRESS_CBS 5022#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET 15 5023#define INGRESS_POLICER0_INGRESS_CBS_BLEN 3 5024#define INGRESS_POLICER0_INGRESS_CBS_FLAG HSL_RW 5025 5026#define INGRESS_CIR 5027#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET 0 5028#define INGRESS_POLICER0_INGRESS_CIR_BLEN 15 5029#define INGRESS_POLICER0_INGRESS_CIR_FLAG HSL_RW 5030 5031 5032 /* INGRESS Policer Register1 */ 5033#define INGRESS_POLICER1 5034#define INGRESS_POLICER1_OFFSET 0x0b04 5035#define INGRESS_POLICER1_E_LENGTH 4 5036#define INGRESS_POLICER1_E_OFFSET 0x0010 5037#define INGRESS_POLICER1_NR_E 7 5038 5039#define INGRESS_BORROW 5040#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET 23 5041#define INGRESS_POLICER1_INGRESS_BORROW_BLEN 1 5042#define INGRESS_POLICER1_INGRESS_BORROW_FLAG HSL_RW 5043 5044#define INGRESS_UNIT 5045#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET 22 5046#define INGRESS_POLICER1_INGRESS_UNIT_BLEN 1 5047#define INGRESS_POLICER1_INGRESS_UNIT_FLAG HSL_RW 5048 5049#define INGRESS_CF 5050#define INGRESS_POLICER1_INGRESS_CF_BOFFSET 21 5051#define INGRESS_POLICER1_INGRESS_CF_BLEN 1 5052#define INGRESS_POLICER1_INGRESS_CF_FLAG HSL_RW 5053 5054#define INGRESS_CM 5055#define INGRESS_POLICER1_INGRESS_CM_BOFFSET 20 5056#define INGRESS_POLICER1_INGRESS_CM_BLEN 1 5057#define INGRESS_POLICER1_INGRESS_CM_FLAG HSL_RW 5058 5059#define E_ING_TS 5060#define INGRESS_POLICER1_E_ING_TS_BOFFSET 18 5061#define INGRESS_POLICER1_E_ING_TS_BLEN 2 5062#define INGRESS_POLICER1_E_ING_TS_FLAG HSL_RW 5063 5064#define INGRESS_EBS 5065#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET 15 5066#define INGRESS_POLICER1_INGRESS_EBS_BLEN 3 5067#define INGRESS_POLICER1_INGRESS_EBS_FLAG HSL_RW 5068 5069#define INGRESS_EIR 5070#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET 0 5071#define INGRESS_POLICER1_INGRESS_EIR_BLEN 15 5072#define INGRESS_POLICER1_INGRESS_EIR_FLAG HSL_RW 5073 5074 5075 /* INGRESS Policer Register2 */ 5076#define INGRESS_POLICER2 5077#define INGRESS_POLICER2_OFFSET 0x0b08 5078#define INGRESS_POLICER2_E_LENGTH 4 5079#define INGRESS_POLICER2_E_OFFSET 0x0010 5080#define INGRESS_POLICER2_NR_E 7 5081 5082#define C_MUL 5083#define INGRESS_POLICER2_C_MUL_BOFFSET 15 5084#define INGRESS_POLICER2_C_MUL_BLEN 1 5085#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW 5086 5087#define C_UNI 5088#define INGRESS_POLICER2_C_UNI_BOFFSET 14 5089#define INGRESS_POLICER2_C_UNI_BLEN 1 5090#define INGRESS_POLICER2_C_UNI_FLAG HSL_RW 5091 5092#define C_UNK_MUL 5093#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET 13 5094#define INGRESS_POLICER2_C_UNK_MUL_BLEN 1 5095#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW 5096 5097#define C_UNK_UNI 5098#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET 12 5099#define INGRESS_POLICER2_C_UNK_UNI_BLEN 1 5100#define INGRESS_POLICER2_C_UNK_UNI_FLAG HSL_RW 5101 5102#define C_BROAD 5103#define INGRESS_POLICER2_C_BROAD_BOFFSET 11 5104#define INGRESS_POLICER2_C_BROAD_BLEN 1 5105#define INGRESS_POLICER2_C_BROAD_FLAG HSL_RW 5106 5107#define C_MANAGE 5108#define INGRESS_POLICER2_C_MANAGC_BOFFSET 10 5109#define INGRESS_POLICER2_C_MANAGC_BLEN 1 5110#define INGRESS_POLICER2_C_MANAGC_FLAG HSL_RW 5111 5112#define C_TCP 5113#define INGRESS_POLICER2_C_TCP_BOFFSET 9 5114#define INGRESS_POLICER2_C_TCP_BLEN 1 5115#define INGRESS_POLICER2_C_TCP_FLAG HSL_RW 5116 5117#define C_MIRR 5118#define INGRESS_POLICER2_C_MIRR_BOFFSET 8 5119#define INGRESS_POLICER2_C_MIRR_BLEN 1 5120#define INGRESS_POLICER2_C_MIRR_FLAG HSL_RW 5121 5122#define E_MUL 5123#define INGRESS_POLICER2_E_MUL_BOFFSET 7 5124#define INGRESS_POLICER2_E_MUL_BLEN 1 5125#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW 5126 5127#define E_UNI 5128#define INGRESS_POLICER2_E_UNI_BOFFSET 6 5129#define INGRESS_POLICER2_E_UNI_BLEN 1 5130#define INGRESS_POLICER2_E_UNI_FLAG HSL_RW 5131 5132#define E_UNK_MUL 5133#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET 5 5134#define INGRESS_POLICER2_E_UNK_MUL_BLEN 1 5135#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW 5136 5137#define E_UNK_UNI 5138#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET 4 5139#define INGRESS_POLICER2_E_UNK_UNI_BLEN 1 5140#define INGRESS_POLICER2_E_UNK_UNI_FLAG HSL_RW 5141 5142#define E_BROAD 5143#define INGRESS_POLICER2_E_BROAD_BOFFSET 3 5144#define INGRESS_POLICER2_E_BROAD_BLEN 1 5145#define INGRESS_POLICER2_E_BROAD_FLAG HSL_RW 5146 5147#define E_MANAGE 5148#define INGRESS_POLICER2_E_MANAGE_BOFFSET 2 5149#define INGRESS_POLICER2_E_MANAGE_BLEN 1 5150#define INGRESS_POLICER2_E_MANAGE_FLAG HSL_RW 5151 5152#define E_TCP 5153#define INGRESS_POLICER2_E_TCP_BOFFSET 1 5154#define INGRESS_POLICER2_E_TCP_BLEN 1 5155#define INGRESS_POLICER2_E_TCP_FLAG HSL_RW 5156 5157#define E_MIRR 5158#define INGRESS_POLICER2_E_MIRR_BOFFSET 0 5159#define INGRESS_POLICER2_E_MIRR_BLEN 1 5160#define INGRESS_POLICER2_E_MIRR_FLAG HSL_RW 5161 5162 5163 5164 5165 /* Port Rate Limit2 Register */ 5166#define WRR_CTRL 5167#define WRR_CTRL_OFFSET 0x0830 5168#define WRR_CTRL_E_LENGTH 4 5169#define WRR_CTRL_E_OFFSET 0x0004 5170#define WRR_CTRL_NR_E 7 5171 5172#define SCH_MODE 5173#define WRR_CTRL_SCH_MODE_BOFFSET 30 5174#define WRR_CTRL_SCH_MODE_BLEN 2 5175#define WRR_CTRL_SCH_MODE_FLAG HSL_RW 5176 5177#define Q5_W 5178#define WRR_CTRL_Q5_W_BOFFSET 25 5179#define WRR_CTRL_Q5_W_BLEN 5 5180#define WRR_CTRL_Q5_W_FLAG HSL_RW 5181 5182#define Q4_W 5183#define WRR_CTRL_Q4_W_BOFFSET 20 5184#define WRR_CTRL_Q4_W_BLEN 5 5185#define WRR_CTRL_Q4_W_FLAG HSL_RW 5186 5187#define Q3_W 5188#define WRR_CTRL_Q3_W_BOFFSET 15 5189#define WRR_CTRL_Q3_W_BLEN 5 5190#define WRR_CTRL_Q3_W_FLAG HSL_RW 5191 5192#define Q2_W 5193#define WRR_CTRL_Q2_W_BOFFSET 10 5194#define WRR_CTRL_Q2_W_BLEN 5 5195#define WRR_CTRL_Q2_W_FLAG HSL_RW 5196 5197#define Q1_W 5198#define WRR_CTRL_Q1_W_BOFFSET 5 5199#define WRR_CTRL_Q1_W_BLEN 5 5200#define WRR_CTRL_Q1_W_FLAG HSL_RW 5201 5202#define Q0_W 5203#define WRR_CTRL_Q0_W_BOFFSET 0 5204#define WRR_CTRL_Q0_W_BLEN 5 5205#define WRR_CTRL_Q0_W_FLAG HSL_RW 5206 5207 5208 5209 5210 5211#ifdef __cplusplus 5212} 5213#endif /* __cplusplus */ 5214#endif /* _ISIS_REG_H_ */ 5215 5216