1/* 2 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 * Permission to use, copy, modify, and/or distribute this software for 4 * any purpose with or without fee is hereby granted, provided that the 5 * above copyright notice and this permission notice appear in all copies. 6 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 7 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 10 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 11 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 12 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 13 */ 14 15 16 17#ifndef _DESS_REG_H_ 18#define _DESS_REG_H_ 19 20#ifdef __cplusplus 21extern "C" { 22#endif /* __cplusplus */ 23 24#define DESS_DEVICE_ID 0x14 /* TBD */ 25 26#define MAX_ENTRY_LEN 128 27 28#define HSL_RW 1 29#define HSL_RO 0 30 31 32 /* DESS Mask Control Register */ 33#define MASK_CTL 34#define MASK_CTL_ID 0 35#define MASK_CTL_OFFSET 0x0000 36#define MASK_CTL_E_LENGTH 4 37#define MASK_CTL_E_OFFSET 0 38#define MASK_CTL_NR_E 1 39 40#define DEVICE_ID 41#define MASK_CTL_DEVICE_ID_BOFFSET 8 42#define MASK_CTL_DEVICE_ID_BLEN 8 43#define MASK_CTL_DEVICE_ID_FLAG HSL_RO 44 45#define REV_ID 46#define MASK_CTL_REV_ID_BOFFSET 0 47#define MASK_CTL_REV_ID_BLEN 8 48#define MASK_CTL_REV_ID_FLAG HSL_RO 49 50 51/* RGMII Control Register */ 52#define RGMII_CTRL 53#define RGMII_CTRL_ID 0 54#define RGMII_CTRL_OFFSET 0x0004 55#define RGMII_CTRL_E_LENGTH 4 56#define RGMII_CTRL_E_OFFSET 0 57#define RGMII_CTRL_NR_E 1 58 59#define RMII1_MASTER_EN 60#define RGMII_CTRL_RMII1_MASTER_EN_BOFFSET 25 61#define RGMII_CTRL_RMII1_MASTER_EN_BLEN 1 62#define RGMII_CTRL_RMII1_MASTER_EN_FLAG HSL_RW 63 64#define RMII0_MASTER_EN 65#define RGMII_CTRL_RMII0_MASTER_EN_BOFFSET 24 66#define RGMII_CTRL_RMII0_MASTER_EN_BLEN 1 67#define RGMII_CTRL_RMII0_MASTER_EN_FLAG HSL_RW 68 69 70/* Global Interrupt Status Register1 */ 71#define GBL_INT_STATUS1 72#define GBL_INT_STATUS1_ID 1 73#define GBL_INT_STATUS1_OFFSET 0x0024 74#define GBL_INT_STATUS1_E_LENGTH 4 75#define GBL_INT_STATUS1_E_OFFSET 0 76#define GBL_INT_STATUS1_NR_E 1 77 78#define LINK_CHG_INT_S 79#define GBL_INT_STATUS1_LINK_CHG_INT_S_BOFFSET 1 80#define GBL_INT_STATUS1_LINK_CHG_INT_S_BLEN 7 81#define GBL_INT_STATUS1_LINK_CHG_INT_S_FLAG HSL_RW 82 83#define PHY_INT_S 84#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET 15 85#define GBL_INT_STATUS1_PHY_INT_S_BLEN 1 86#define GBL_INT_STATUS1_PHY_INT_S_FLAG HSL_RO 87 88 89 /* Global Interrupt Mask Register1 */ 90#define GBL_INT_MASK1 91#define GBL_INT_MASK1_ID 1 92#define GBL_INT_MASK1_OFFSET 0x002c 93#define GBL_INT_MASK1_E_LENGTH 4 94#define GBL_INT_MASK1_E_OFFSET 0 95#define GBL_INT_MASK1_NR_E 1 96 97#define LINK_CHG_INT_M 98#define GBL_INT_MASK1_LINK_CHG_INT_M_BOFFSET 1 99#define GBL_INT_MASK1_LINK_CHG_INT_M_BLEN 7 100#define GBL_INT_MASK1_LINK_CHG_INT_M_FLAG HSL_RW 101 102#define PHY_INT_M 103#define GBL_INT_MASK1_PHY_INT_M_BOFFSET 15 104#define GBL_INT_MASK1_PHY_INT_M_BLEN 1 105#define GBL_INT_MASK1_PHY_INT_M_FLAG HSL_RO 106 107 108 109 110 /* Module Enable Register */ 111#define MOD_ENABLE 112#define MOD_ENABLE_OFFSET 0x0030 113#define MOD_ENABLE_E_LENGTH 4 114#define MOD_ENABLE_E_OFFSET 0 115#define MOD_ENABLE_NR_E 1 116 117#define L3_EN 118#define MOD_ENABLE_L3_EN_BOFFSET 2 119#define MOD_ENABLE_L3_EN_BLEN 1 120#define MOD_ENABLE_L3_EN_FLAG HSL_RW 121 122#define ACL_EN 123#define MOD_ENABLE_ACL_EN_BOFFSET 1 124#define MOD_ENABLE_ACL_EN_BLEN 1 125#define MOD_ENABLE_ACL_EN_FLAG HSL_RW 126 127#define MIB_EN 128#define MOD_ENABLE_MIB_EN_BOFFSET 0 129#define MOD_ENABLE_MIB_EN_BLEN 1 130#define MOD_ENABLE_MIB_EN_FLAG HSL_RW 131 132 133 134 135 /* MIB Function Register */ 136#define MIB_FUNC 137#define MIB_FUNC_OFFSET 0x0034 138#define MIB_FUNC_E_LENGTH 4 139#define MIB_FUNC_E_OFFSET 0 140#define MIB_FUNC_NR_E 1 141 142#define MIB_FUN 143#define MIB_FUNC_MIB_FUN_BOFFSET 24 144#define MIB_FUNC_MIB_FUN_BLEN 3 145#define MIB_FUNC_MIB_FUN_FLAG HSL_RW 146 147#define MIB_FLUSH_PORT 148#define MIB_FUNC_MIB_FLUSH_PORT_BOFFSET 21 149#define MIB_FUNC_MIB_FLUSH_PORT_BLEN 3 150#define MIB_FUNC_MIB_FLUSH_PORT_FLAG HSL_RW 151 152#define MIB_CPU_KEEP 153#define MIB_FUNC_MIB_CPU_KEEP_BOFFSET 20 154#define MIB_FUNC_MIB_CPU_KEEP_BLEN 1 155#define MIB_FUNC_MIB_CPU_KEEP_FLAG HSL_RW 156 157#define MIB_BUSY 158#define MIB_FUNC_MIB_BUSY_BOFFSET 17 159#define MIB_FUNC_MIB_BUSY_BLEN 1 160#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW 161 162#define MIB_AT_HALF_EN 163#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 164#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 165#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW 166 167#define MIB_TIMER 168#define MIB_FUNC_MIB_TIMER_BOFFSET 0 169#define MIB_FUNC_MIB_TIMER_BLEN 16 170#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW 171 172 173 174 175 /* Service tag Register */ 176#define SERVICE_TAG 177#define SERVICE_TAG_OFFSET 0x0048 178#define SERVICE_TAG_E_LENGTH 4 179#define SERVICE_TAG_E_OFFSET 0 180#define SERVICE_TAG_NR_E 1 181 182#define STAG_MODE 183#define SERVICE_TAG_STAG_MODE_BOFFSET 17 184#define SERVICE_TAG_STAG_MODE_BLEN 1 185#define SERVICE_TAG_STAG_MODE_FLAG HSL_RW 186 187#define TAG_VALUE 188#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 189#define SERVICE_TAG_TAG_VALUE_BLEN 16 190#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW 191 192 193 194 195 /* Global MAC Address Register */ 196#define GLOBAL_MAC_ADDR0 197#define GLOBAL_MAC_ADDR0_OFFSET 0x0060 198#define GLOBAL_MAC_ADDR0_E_LENGTH 4 199#define GLOBAL_MAC_ADDR0_E_OFFSET 0 200#define GLOBAL_MAC_ADDR0_NR_E 1 201 202#define GLB_BYTE4 203#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 204#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 205#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW 206 207#define GLB_BYTE5 208#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 209#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 210#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW 211 212#define GLOBAL_MAC_ADDR1 213#define GLOBAL_MAC_ADDR1_ID 4 214#define GLOBAL_MAC_ADDR1_OFFSET 0x0064 215#define GLOBAL_MAC_ADDR1_E_LENGTH 4 216#define GLOBAL_MAC_ADDR1_E_OFFSET 0 217#define GLOBAL_MAC_ADDR1_NR_E 1 218 219#define GLB_BYTE0 220#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 221#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 222#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW 223 224#define GLB_BYTE1 225#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 226#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 227#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW 228 229#define GLB_BYTE2 230#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 231#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 232#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW 233 234#define GLB_BYTE3 235#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 236#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 237#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW 238 239 240 241 242 /* Max Size Register */ 243#define MAX_SIZE 244#define MAX_SIZE_OFFSET 0x0078 245#define MAX_SIZE_E_LENGTH 4 246#define MAX_SIZE_E_OFFSET 0 247#define MAX_SIZE_NR_E 1 248 249#define CRC_RESERVE 250#define MAX_SIZE_CRC_RESERVE_BOFFSET 16 251#define MAX_SIZE_CRC_RESERVE_BLEN 1 252#define MAX_SIZE_CRC_RESERVE_FLAG HSL_RW 253 254#define MAX_FRAME_SIZE 255#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET 0 256#define MAX_SIZE_MAX_FRAME_SIZE_BLEN 14 257#define MAX_SIZE_MAX_FRAME_SIZE_FLAG HSL_RW 258 259 260 261 262 263 264 265 266 267 268 269 270 /* Port Status Register */ 271#define PORT_STATUS 272#define PORT_STATUS_OFFSET 0x007c 273#define PORT_STATUS_E_LENGTH 4 274#define PORT_STATUS_E_OFFSET 0x0004 275#define PORT_STATUS_NR_E 7 276 277#define FLOW_LINK_EN 278#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 279#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 280#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW 281 282#define AUTO_RX_FLOW 283#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET 11 284#define PORT_STATUS_AUTO_RX_FLOW_BLEN 1 285#define PORT_STATUS_AUTO_RX_FLOW_FLAG HSL_RO 286 287#define AUTO_TX_FLOW 288#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET 10 289#define PORT_STATUS_AUTO_TX_FLOW_BLEN 1 290#define PORT_STATUS_AUTO_TX_FLOW_FLAG HSL_RO 291 292#define LINK_EN 293#define PORT_STATUS_LINK_EN_BOFFSET 9 294#define PORT_STATUS_LINK_EN_BLEN 1 295#define PORT_STATUS_LINK_EN_FLAG HSL_RW 296 297#define LINK 298#define PORT_STATUS_LINK_BOFFSET 8 299#define PORT_STATUS_LINK_BLEN 1 300#define PORT_STATUS_LINK_FLAG HSL_RO 301 302#define TX_HALF_FLOW_EN 303#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 304#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 305#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW 306 307#define DUPLEX_MODE 308#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 309#define PORT_STATUS_DUPLEX_MODE_BLEN 1 310#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW 311 312#define RX_FLOW_EN 313#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 314#define PORT_STATUS_RX_FLOW_EN_BLEN 1 315#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW 316 317#define TX_FLOW_EN 318#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 319#define PORT_STATUS_TX_FLOW_EN_BLEN 1 320#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW 321 322#define RXMAC_EN 323#define PORT_STATUS_RXMAC_EN_BOFFSET 3 324#define PORT_STATUS_RXMAC_EN_BLEN 1 325#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW 326 327#define TXMAC_EN 328#define PORT_STATUS_TXMAC_EN_BOFFSET 2 329#define PORT_STATUS_TXMAC_EN_BLEN 1 330#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW 331 332#define SPEED_MODE 333#define PORT_STATUS_SPEED_MODE_BOFFSET 0 334#define PORT_STATUS_SPEED_MODE_BLEN 2 335#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW 336 337 338 339 340 /* Header Ctl Register */ 341#define HEADER_CTL 342#define HEADER_CTL_OFFSET 0x0098 343#define HEADER_CTL_E_LENGTH 4 344#define HEADER_CTL_E_OFFSET 0x0004 345#define HEADER_CTL_NR_E 1 346 347#define TYPE_LEN 348#define HEADER_CTL_TYPE_LEN_BOFFSET 16 349#define HEADER_CTL_TYPE_LEN_BLEN 1 350#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW 351 352#define TYPE_VAL 353#define HEADER_CTL_TYPE_VAL_BOFFSET 0 354#define HEADER_CTL_TYPE_VAL_BLEN 16 355#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW 356 357 358 359 360 /* Port Header Ctl Register */ 361#define PORT_HDR_CTL 362#define PORT_HDR_CTL_OFFSET 0x009c 363#define PORT_HDR_CTL_E_LENGTH 4 364#define PORT_HDR_CTL_E_OFFSET 0x0004 365#define PORT_HDR_CTL_NR_E 7 366 367#define IPG_DEC_EN 368#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET 5 369#define PORT_HDR_CTL_IPG_DEC_EN_BLEN 1 370#define PORT_HDR_CTL_IPG_DEC_EN_FLAG HSL_RW 371 372#define LOOPBACK_EN 373#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET 4 374#define PORT_HDR_CTL_LOOPBACK_EN_BLEN 1 375#define PORT_HDR_CTL_LOOPBACK_EN_FLAG HSL_RW 376 377#define RXHDR_MODE 378#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2 379#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2 380#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW 381 382#define TXHDR_MODE 383#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0 384#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2 385#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW 386 387 388 389 390 /* EEE control Register */ 391#define EEE_CTL 392#define EEE_CTL_OFFSET 0x0100 393#define EEE_CTL_E_LENGTH 4 394#define EEE_CTL_E_OFFSET 0 395#define EEE_CTL_NR_E 1 396 397#define LPI_STATE_REMAP_EN_5 398#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET 13 399#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN 1 400#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG HSL_RW 401 402#define LPI_EN_5 403#define EEE_CTL_LPI_EN_5_BOFFSET 12 404#define EEE_CTL_LPI_EN_5_BLEN 1 405#define EEE_CTL_LPI_EN_5_FLAG HSL_RW 406 407#define LPI_STATE_REMAP_EN_4 408#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET 11 409#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN 1 410#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG HSL_RW 411 412#define LPI_EN_4 413#define EEE_CTL_LPI_EN_4_BOFFSET 10 414#define EEE_CTL_LPI_EN_4_BLEN 1 415#define EEE_CTL_LPI_EN_4_FLAG HSL_RW 416 417#define LPI_STATE_REMAP_EN_3 418#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET 9 419#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN 1 420#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG HSL_RW 421 422#define LPI_EN_3 423#define EEE_CTL_LPI_EN_3_BOFFSET 8 424#define EEE_CTL_LPI_EN_3_BLEN 1 425#define EEE_CTL_LPI_EN_3_FLAG HSL_RW 426 427#define LPI_STATE_REMAP_EN_2 428#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET 7 429#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN 1 430#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG HSL_RW 431 432#define LPI_EN_2 433#define EEE_CTL_LPI_EN_2_BOFFSET 6 434#define EEE_CTL_LPI_EN_2_BLEN 1 435#define EEE_CTL_LPI_EN_2_FLAG HSL_RW 436 437#define LPI_STATE_REMAP_EN_1 438#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET 5 439#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN 1 440#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG HSL_RW 441 442#define LPI_EN_1 443#define EEE_CTL_LPI_EN_1_BOFFSET 4 444#define EEE_CTL_LPI_EN_1_BLEN 1 445#define EEE_CTL_LPI_EN_1_FLAG HSL_RW 446 447 448 449 450 /* Frame Ack Ctl0 Register */ 451#define FRAME_ACK_CTL0 452#define FRAME_ACK_CTL0_OFFSET 0x0210 453#define FRAME_ACK_CTL0_E_LENGTH 4 454#define FRAME_ACK_CTL0_E_OFFSET 0 455#define FRAME_ACK_CTL0_NR_E 1 456 457#define ARP_REQ_EN 458#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET 6 459#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN 1 460#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG HSL_RW 461 462#define ARP_REP_EN 463#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET 5 464#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN 1 465#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG HSL_RW 466 467#define DHCP_EN 468#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET 4 469#define FRAME_ACK_CTL0_DHCP_EN_BLEN 1 470#define FRAME_ACK_CTL0_DHCP_EN_FLAG HSL_RW 471 472#define EAPOL_EN 473#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET 3 474#define FRAME_ACK_CTL0_EAPOL_EN_BLEN 1 475#define FRAME_ACK_CTL0_EAPOL_EN_FLAG HSL_RW 476 477#define LEAVE_EN 478#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET 2 479#define FRAME_ACK_CTL0_LEAVE_EN_BLEN 1 480#define FRAME_ACK_CTL0_LEAVE_EN_FLAG HSL_RW 481 482#define JOIN_EN 483#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET 1 484#define FRAME_ACK_CTL0_JOIN_EN_BLEN 1 485#define FRAME_ACK_CTL0_JOIN_EN_FLAG HSL_RW 486 487#define IGMP_MLD_EN 488#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET 0 489#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN 1 490#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG HSL_RW 491 492 493 494 495 /* Frame Ack Ctl1 Register */ 496#define FRAME_ACK_CTL1 497#define FRAME_ACK_CTL1_OFFSET 0x0214 498#define FRAME_ACK_CTL1_E_LENGTH 4 499#define FRAME_ACK_CTL1_E_OFFSET 0 500#define FRAME_ACK_CTL1_NR_E 1 501 502#define LLDP_EN 503#define FRAME_ACK_CTL1_LLDP_EN_BOFFSET 26 504#define FRAME_ACK_CTL1_LLDP_EN_BLEN 1 505#define FRAME_ACK_CTL1_LLDP_EN_FLAG HSL_RW 506 507 508#define PPPOE_EN 509#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET 25 510#define FRAME_ACK_CTL1_PPPOE_EN_BLEN 1 511#define FRAME_ACK_CTL1_PPPOE_EN_FLAG HSL_RW 512 513#define IGMP_V3_EN 514#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET 24 515#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN 1 516#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG HSL_RW 517 518 519 520 521 /* Window Rule Ctl0 Register */ 522#define WIN_RULE_CTL0 523#define WIN_RULE_CTL0_OFFSET 0x0218 524#define WIN_RULE_CTL0_E_LENGTH 4 525#define WIN_RULE_CTL0_E_OFFSET 0x4 526#define WIN_RULE_CTL0_NR_E 7 527 528#define L4_LENGTH 529#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET 24 530#define WIN_RULE_CTL0_L4_LENGTH_BLEN 4 531#define WIN_RULE_CTL0_L4_LENGTH_FLAG HSL_RW 532 533#define L3_LENGTH 534#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET 20 535#define WIN_RULE_CTL0_L3_LENGTH_BLEN 4 536#define WIN_RULE_CTL0_L3_LENGTH_FLAG HSL_RW 537 538#define L2_LENGTH 539#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET 16 540#define WIN_RULE_CTL0_L2_LENGTH_BLEN 4 541#define WIN_RULE_CTL0_L2_LENGTH_FLAG HSL_RW 542 543#define L4_OFFSET 544#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET 10 545#define WIN_RULE_CTL0_L4_OFFSET_BLEN 5 546#define WIN_RULE_CTL0_L4_OFFSET_FLAG HSL_RW 547 548#define L3_OFFSET 549#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET 5 550#define WIN_RULE_CTL0_L3_OFFSET_BLEN 5 551#define WIN_RULE_CTL0_L3_OFFSET_FLAG HSL_RW 552 553#define L2_OFFSET 554#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET 0 555#define WIN_RULE_CTL0_L2_OFFSET_BLEN 5 556#define WIN_RULE_CTL0_L2_OFFSET_FLAG HSL_RW 557 558 559 560 561 /* Window Rule Ctl1 Register */ 562#define WIN_RULE_CTL1 563#define WIN_RULE_CTL1_OFFSET 0x0234 564#define WIN_RULE_CTL1_E_LENGTH 4 565#define WIN_RULE_CTL1_E_OFFSET 0x4 566#define WIN_RULE_CTL1_NR_E 7 567 568#define L3P_LENGTH 569#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET 20 570#define WIN_RULE_CTL1_L3P_LENGTH_BLEN 4 571#define WIN_RULE_CTL1_L3P_LENGTH_FLAG HSL_RW 572 573#define L2S_LENGTH 574#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET 16 575#define WIN_RULE_CTL1_L2S_LENGTH_BLEN 4 576#define WIN_RULE_CTL1_L2S_LENGTH_FLAG HSL_RW 577 578#define L3P_OFFSET 579#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET 5 580#define WIN_RULE_CTL1_L3P_OFFSET_BLEN 5 581#define WIN_RULE_CTL1_L3P_OFFSET_FLAG HSL_RW 582 583#define L2S_OFFSET 584#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET 0 585#define WIN_RULE_CTL1_L2S_OFFSET_BLEN 5 586#define WIN_RULE_CTL1_L2S_OFFSET_FLAG HSL_RW 587 588 589 590 591 /* Trunk Hash Mode Register */ 592#define TRUNK_HASH_MODE 593#define TRUNK_HASH_MODE_OFFSET 0x0270 594#define TRUNK_HASH_MODE_E_LENGTH 4 595#define TRUNK_HASH_MODE_E_OFFSET 0x4 596#define TRUNK_HASH_MODE_NR_E 1 597 598#define DIP_EN 599#define TRUNK_HASH_MODE_DIP_EN_BOFFSET 3 600#define TRUNK_HASH_MODE_DIP_EN_BLEN 1 601#define TRUNK_HASH_MODE_DIP_EN_FLAG HSL_RW 602 603#define SIP_EN 604#define TRUNK_HASH_MODE_SIP_EN_BOFFSET 2 605#define TRUNK_HASH_MODE_SIP_EN_BLEN 1 606#define TRUNK_HASH_MODE_SIP_EN_FLAG HSL_RW 607 608#define SA_EN 609#define TRUNK_HASH_MODE_SA_EN_BOFFSET 1 610#define TRUNK_HASH_MODE_SA_EN_BLEN 1 611#define TRUNK_HASH_MODE_SA_EN_FLAG HSL_RW 612 613#define DA_EN 614#define TRUNK_HASH_MODE_DA_EN_BOFFSET 0 615#define TRUNK_HASH_MODE_DA_EN_BLEN 1 616#define TRUNK_HASH_MODE_DA_EN_FLAG HSL_RW 617 618 619 620 621 /* Vlan Table Function0 Register */ 622#define VLAN_TABLE_FUNC0 623#define VLAN_TABLE_FUNC0_OFFSET 0x0610 624#define VLAN_TABLE_FUNC0_E_LENGTH 4 625#define VLAN_TABLE_FUNC0_E_OFFSET 0 626#define VLAN_TABLE_FUNC0_NR_E 1 627 628#define VT_VALID 629#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET 20 630#define VLAN_TABLE_FUNC0_VT_VALID_BLEN 1 631#define VLAN_TABLE_FUNC0_VT_VALID_FLAG HSL_RW 632 633#define IVL_EN 634#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET 19 635#define VLAN_TABLE_FUNC0_IVL_EN_BLEN 1 636#define VLAN_TABLE_FUNC0_IVL_EN_FLAG HSL_RW 637 638#define LEARN_DIS 639#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET 18 640#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN 1 641#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG HSL_RW 642 643#define VID_MEM 644#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET 4 645#define VLAN_TABLE_FUNC0_VID_MEM_BLEN 14 646#define VLAN_TABLE_FUNC0_VID_MEM_FLAG HSL_RW 647 648#define VT_PRI_EN 649#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 3 650#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 651#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW 652 653#define VT_PRI 654#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 0 655#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 656#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW 657 658 /* Vlan Table Function1 Register */ 659#define VLAN_TABLE_FUNC1 660#define VLAN_TABLE_FUNC1_OFFSET 0x0614 661#define VLAN_TABLE_FUNC1_E_LENGTH 4 662#define VLAN_TABLE_FUNC1_E_OFFSET 0 663#define VLAN_TABLE_FUNC1_NR_E 1 664 665#define VT_BUSY 666#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET 31 667#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN 1 668#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG HSL_RW 669 670#define VLAN_ID 671#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET 16 672#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN 12 673#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG HSL_RW 674 675#define VT_PORT_NUM 676#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET 8 677#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN 4 678#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG HSL_RW 679 680#define VT_FULL_VIO 681#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET 4 682#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN 1 683#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG HSL_RW 684 685#define VT_FUNC 686#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET 0 687#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN 3 688#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG HSL_RW 689 690 691 692 693 /* Address Table Function0 Register */ 694#define ADDR_TABLE_FUNC0 695#define ADDR_TABLE_FUNC0_OFFSET 0x0600 696#define ADDR_TABLE_FUNC0_E_LENGTH 4 697#define ADDR_TABLE_FUNC0_E_OFFSET 0 698#define ADDR_TABLE_FUNC0_NR_E 1 699 700 701#define AT_ADDR_BYTE2 702#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24 703#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN 8 704#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG HSL_RW 705 706#define AT_ADDR_BYTE3 707#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16 708#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN 8 709#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG HSL_RW 710 711#define AT_ADDR_BYTE4 712#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8 713#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 714#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW 715 716#define AT_ADDR_BYTE5 717#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0 718#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 719#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW 720 721 /* Address Table Function1 Register */ 722#define ADDR_TABLE_FUNC1 723#define ADDR_TABLE_FUNC1_OFFSET 0x0604 724#define ADDR_TABLE_FUNC1_E_LENGTH 4 725#define ADDR_TABLE_FUNC1_E_OFFSET 0 726#define ADDR_TABLE_FUNC1_NR_E 1 727 728#define SA_DROP_EN 729#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET 30 730#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN 1 731#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG HSL_RW 732 733#define MIRROR_EN 734#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET 29 735#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN 1 736#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG HSL_RW 737 738#define AT_PRI_EN 739#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET 28 740#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN 1 741#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG HSL_RW 742 743#define AT_SVL_EN 744#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET 27 745#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN 1 746#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG HSL_RW 747 748#define AT_PRI 749#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET 24 750#define ADDR_TABLE_FUNC1_AT_PRI_BLEN 3 751#define ADDR_TABLE_FUNC1_AT_PRI_FLAG HSL_RW 752 753#define CROSS_PT 754#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET 23 755#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN 1 756#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG HSL_RW 757 758#define DES_PORT 759#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET 16 760#define ADDR_TABLE_FUNC1_DES_PORT_BLEN 7 761#define ADDR_TABLE_FUNC1_DES_PORT_FLAG HSL_RW 762 763#define AT_ADDR_BYTE0 764#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8 765#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 766#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW 767 768#define AT_ADDR_BYTE1 769#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0 770#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 771#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW 772 773 /* Address Table Function2 Register */ 774#define ADDR_TABLE_FUNC2 775#define ADDR_TABLE_FUNC2_OFFSET 0x0608 776#define ADDR_TABLE_FUNC2_E_LENGTH 4 777#define ADDR_TABLE_FUNC2_E_OFFSET 0 778#define ADDR_TABLE_FUNC2_NR_E 1 779 780 781#define LOAD_BALANCE_EN 782#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_BOFFSET 23 783#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_BLEN 1 784#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_FLAG HSL_RW 785 786#define LOAD_BALANCE 787#define ADDR_TABLE_FUNC2_LOAD_BALANCE_BOFFSET 21 788#define ADDR_TABLE_FUNC2_LOAD_BALANCE_BLEN 2 789#define ADDR_TABLE_FUNC2_LOAD_BALANCE_FLAG HSL_RW 790 791#define WL_EN 792#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET 20 793#define ADDR_TABLE_FUNC2_WL_EN_BLEN 1 794#define ADDR_TABLE_FUNC2_WL_EN_FLAG HSL_RW 795 796#define AT_VID 797#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET 8 798#define ADDR_TABLE_FUNC2_AT_VID_BLEN 12 799#define ADDR_TABLE_FUNC2_AT_VID_FLAG HSL_RW 800 801#define SHORT_LOOP 802#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET 7 803#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN 1 804#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG HSL_RW 805 806#define COPY_TO_CPU 807#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 6 808#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 809#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW 810 811#define REDRCT_TO_CPU 812#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5 813#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 814#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW 815 816#define LEAKY_EN 817#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 4 818#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 819#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW 820 821#define AT_STATUS 822#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 0 823#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 824#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW 825 826 /* Address Table Function3 Register */ 827#define ADDR_TABLE_FUNC3 828#define ADDR_TABLE_FUNC3_OFFSET 0x060c 829#define ADDR_TABLE_FUNC3_E_LENGTH 4 830#define ADDR_TABLE_FUNC3_E_OFFSET 0 831#define ADDR_TABLE_FUNC3_NR_E 1 832 833#define AT_BUSY 834#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET 31 835#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN 1 836#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG HSL_RW 837 838#define NEW_PORT_NUM 839#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET 22 840#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN 3 841#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG HSL_RW 842 843#define AT_INDEX 844#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET 16 845#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN 5 846#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG HSL_RW 847 848#define AT_VID_EN 849#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET 15 850#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN 1 851#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG HSL_RW 852 853#define AT_PORT_EN 854#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET 14 855#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN 1 856#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG HSL_RW 857 858#define AT_MULTI_EN 859#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET 13 860#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN 1 861#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG HSL_RW 862 863#define AT_FULL_VIO 864#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET 12 865#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN 1 866#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG HSL_RW 867 868#define AT_PORT_NUM 869#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET 8 870#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN 4 871#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG HSL_RW 872 873#define FLUSH_ST_EN 874#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET 4 875#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN 1 876#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG HSL_RW 877 878#define AT_FUNC 879#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET 0 880#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN 4 881#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG HSL_RW 882 883 884 885 886 /* Reserve Address Table0 Register */ 887#define RESV_ADDR_TBL0 888#define RESV_ADDR_TBL0_OFFSET 0x3c000 889#define RESV_ADDR_TBL0_E_LENGTH 4 890#define RESV_ADDR_TBL0_E_OFFSET 0 891#define RESV_ADDR_TBL0_NR_E 1 892 893#define RESV_ADDR_BYTE2 894#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24 895#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN 8 896#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG HSL_RW 897 898#define RESV_ADDR_BYTE3 899#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16 900#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN 8 901#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG HSL_RW 902 903#define RESV_ADDR_BYTE4 904#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8 905#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN 8 906#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG HSL_RW 907 908#define RESV_ADDR_BYTE5 909#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0 910#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN 8 911#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG HSL_RW 912 913 /* Reserve Address Table1 Register */ 914#define RESV_ADDR_TBL1 915#define RESV_ADDR_TBL1_OFFSET 0x3c004 916#define RESV_ADDR_TBL1_E_LENGTH 4 917#define RESV_ADDR_TBL1_E_OFFSET 0 918#define RESV_ADDR_TBL1_NR_E 1 919 920#define RESV_COPY_TO_CPU 921#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET 31 922#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN 1 923#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG HSL_RW 924 925#define RESV_REDRCT_TO_CPU 926#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30 927#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN 1 928#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG HSL_RW 929 930#define RESV_LEAKY_EN 931#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET 29 932#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN 1 933#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG HSL_RW 934 935#define RESV_MIRROR_EN 936#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET 28 937#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN 1 938#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG HSL_RW 939 940#define RESV_PRI_EN 941#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET 27 942#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN 1 943#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG HSL_RW 944 945#define RESV_PRI 946#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET 24 947#define RESV_ADDR_TBL1_RESV_PRI_BLEN 3 948#define RESV_ADDR_TBL1_RESV_PRI_FLAG HSL_RW 949 950#define RESV_CROSS_PT 951#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET 23 952#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN 1 953#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG HSL_RW 954 955#define RESV_DES_PORT 956#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET 16 957#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN 7 958#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG HSL_RW 959 960#define RESV_ADDR_BYTE0 961#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8 962#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN 8 963#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG HSL_RW 964 965#define RESV_ADDR_BYTE1 966#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0 967#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN 8 968#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG HSL_RW 969 970 /* Reserve Address Table2 Register */ 971#define RESV_ADDR_TBL2 972#define RESV_ADDR_TBL2_OFFSET 0x3c008 973#define RESV_ADDR_TBL2_E_LENGTH 4 974#define RESV_ADDR_TBL2_E_OFFSET 0 975#define RESV_ADDR_TBL2_NR_E 1 976 977#define RESV_STATUS 978#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET 0 979#define RESV_ADDR_TBL2_RESV_STATUS_BLEN 1 980#define RESV_ADDR_TBL2_RESV_STATUS_FLAG HSL_RW 981 982 983 984 985 /* Address Table Control Register */ 986#define ADDR_TABLE_CTL 987#define ADDR_TABLE_CTL_OFFSET 0x0618 988#define ADDR_TABLE_CTL_E_LENGTH 4 989#define ADDR_TABLE_CTL_E_OFFSET 0 990#define ADDR_TABLE_CTL_NR_E 1 991 992#define ARL_INI_EN 993#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 31 994#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 995#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW 996 997#define LEARN_CHANGE_EN 998#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 30 999#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 1000#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW 1001 1002#define IGMP_JOIN_LEAKY 1003#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET 29 1004#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN 1 1005#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW 1006 1007#define IGMP_CREAT_EN 1008#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET 28 1009#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN 1 1010#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG HSL_RW 1011 1012#define IGMP_PRI_EN 1013#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET 27 1014#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN 1 1015#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG HSL_RW 1016 1017#define IGMP_PRI 1018#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET 24 1019#define ADDR_TABLE_CTL_IGMP_PRI_BLEN 3 1020#define ADDR_TABLE_CTL_IGMP_PRI_FLAG HSL_RW 1021 1022#define IGMP_JOIN_STATIC 1023#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET 20 1024#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN 4 1025#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW 1026 1027#define AGE_EN 1028#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 19 1029#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 1030#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW 1031 1032#define LOOP_CHECK_TIMER 1033#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET 16 1034#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN 3 1035#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG HSL_RW 1036 1037#define AGE_TIME 1038#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 1039#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 1040#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW 1041 1042 1043 1044 1045 /* Global Forward Control0 Register */ 1046#define FORWARD_CTL0 1047#define FORWARD_CTL0_OFFSET 0x0620 1048#define FORWARD_CTL0_E_LENGTH 4 1049#define FORWARD_CTL0_E_OFFSET 0 1050#define FORWARD_CTL0_NR_E 1 1051 1052#define ARP_CMD 1053#define FORWARD_CTL0_ARP_CMD_BOFFSET 26 1054#define FORWARD_CTL0_ARP_CMD_BLEN 2 1055#define FORWARD_CTL0_ARP_CMD_FLAG HSL_RW 1056 1057#define IP_NOT_FOUND 1058#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET 24 1059#define FORWARD_CTL0_IP_NOT_FOUND_BLEN 2 1060#define FORWARD_CTL0_IP_NOT_FOUND_FLAG HSL_RW 1061 1062#define ARP_NOT_FOUND 1063#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET 22 1064#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN 2 1065#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG HSL_RW 1066 1067#define HASH_MODE 1068#define FORWARD_CTL0_HASH_MODE_BOFFSET 20 1069#define FORWARD_CTL0_HASH_MODE_BLEN 2 1070#define FORWARD_CTL0_HASH_MODE_FLAG HSL_RW 1071 1072#define NAT_NOT_FOUND_DROP 1073#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET 17 1074#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN 1 1075#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG HSL_RW 1076 1077#define SP_NOT_FOUND_DROP 1078#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET 16 1079#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN 1 1080#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG HSL_RW 1081 1082#define IGMP_LEAVE_DROP 1083#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET 14 1084#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN 1 1085#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG HSL_RW 1086 1087#define ARL_UNI_LEAKY 1088#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET 13 1089#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN 1 1090#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG HSL_RW 1091 1092#define ARL_MUL_LEAKY 1093#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET 12 1094#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN 1 1095#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG HSL_RW 1096 1097#define MANAGE_VID_VIO_DROP_EN 1098#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11 1099#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN 1 1100#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW 1101 1102#define CPU_PORT_EN 1103#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET 10 1104#define FORWARD_CTL0_CPU_PORT_EN_BLEN 1 1105#define FORWARD_CTL0_CPU_PORT_EN_FLAG HSL_RW 1106 1107#define PPPOE_RDT_EN 1108#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET 8 1109#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN 1 1110#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG HSL_RW 1111 1112#define MIRROR_PORT_NUM 1113#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET 4 1114#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN 4 1115#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG HSL_RW 1116 1117#define IGMP_COPY_EN 1118#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET 3 1119#define FORWARD_CTL0_IGMP_COPY_EN_BLEN 1 1120#define FORWARD_CTL0_IGMP_COPY_EN_FLAG HSL_RW 1121 1122#define RIP_CPY_EN 1123#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET 2 1124#define FORWARD_CTL0_RIP_CPY_EN_BLEN 1 1125#define FORWARD_CTL0_RIP_CPY_EN_FLAG HSL_RW 1126 1127#define EAPOL_CMD 1128#define FORWARD_CTL0_EAPOL_CMD_BOFFSET 0 1129#define FORWARD_CTL0_EAPOL_CMD_BLEN 1 1130#define FORWARD_CTL0_EAPOL_CMD_FLAG HSL_RW 1131 1132 /* Global Forward Control1 Register */ 1133#define FORWARD_CTL1 1134#define FORWARD_CTL1_OFFSET 0x0624 1135#define FORWARD_CTL1_E_LENGTH 4 1136#define FORWARD_CTL1_E_OFFSET 0 1137#define FORWARD_CTL1_NR_E 1 1138 1139#define IGMP_DP 1140#define FORWARD_CTL1_IGMP_DP_BOFFSET 24 1141#define FORWARD_CTL1_IGMP_DP_BLEN 7 1142#define FORWARD_CTL1_IGMP_DP_FLAG HSL_RW 1143 1144#define BC_FLOOD_DP 1145#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16 1146#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7 1147#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW 1148 1149#define MUL_FLOOD_DP 1150#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET 8 1151#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN 7 1152#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG HSL_RW 1153 1154#define UNI_FLOOD_DP 1155#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET 0 1156#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN 7 1157#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG HSL_RW 1158 1159 1160 1161 1162 /* Global Learn Limit Ctl Register */ 1163#define GLOBAL_LEARN_LIMIT_CTL 1164#define GLOBAL_LEARN_LIMIT_CTL_OFFSET 0x0628 1165#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH 4 1166#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET 0 1167#define GLOBAL_LEARN_LIMIT_CTL_NR_E 1 1168 1169#define GOL_SA_LEARN_LIMIT_EN 1170#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET 12 1171#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN 1 1172#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG HSL_RW 1173 1174#define GOL_SA_LEARN_LIMIT_DROP_EN 1175#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 13 1176#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 1177#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW 1178 1179#define GOL_SA_LEARN_CNT 1180#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET 0 1181#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN 12 1182#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG HSL_RW 1183 1184 1185 1186 1187 /* DSCP To Priority Register */ 1188#define DSCP_TO_PRI 1189#define DSCP_TO_PRI_OFFSET 0x0630 1190#define DSCP_TO_PRI_E_LENGTH 4 1191#define DSCP_TO_PRI_E_OFFSET 0x0004 1192#define DSCP_TO_PRI_NR_E 8 1193 1194 1195 1196 1197 /* UP To Priority Register */ 1198#define UP_TO_PRI 1199#define UP_TO_PRI_OFFSET 0x0650 1200#define UP_TO_PRI_E_LENGTH 4 1201#define UP_TO_PRI_E_OFFSET 0x0004 1202#define UP_TO_PRI_NR_E 1 1203 1204 1205 1206 1207 /* WAN DSCP To Priority Register */ 1208#define DSCP_TO_EHPRI 1209#define DSCP_TO_EHPRI_OFFSET 0x0730 1210#define DSCP_TO_EHPRI_E_LENGTH 4 1211#define DSCP_TO_EHPRI_E_OFFSET 0x0004 1212#define DSCP_TO_EHPRI_NR_E 8 1213 1214 1215 1216 1217 /* WAN UP To Priority Register */ 1218#define UP_TO_EHPRI 1219#define UP_TO_EHPRI_OFFSET 0x0750 1220#define UP_TO_EHPRI_E_LENGTH 4 1221#define UP_TO_EHPRI_E_OFFSET 0x0004 1222#define UP_TO_EHPRI_NR_E 1 1223 1224 1225 1226 1227 /* Port Lookup control Register */ 1228#define PORT_LOOKUP_CTL 1229#define PORT_LOOKUP_CTL_OFFSET 0x0660 1230#define PORT_LOOKUP_CTL_E_LENGTH 4 1231#define PORT_LOOKUP_CTL_E_OFFSET 0x000c 1232#define PORT_LOOKUP_CTL_NR_E 7 1233 1234#define MULTI_DROP_EN 1235#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET 31 1236#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN 1 1237#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG HSL_RW 1238 1239#define UNI_LEAKY_EN 1240#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET 28 1241#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN 1 1242#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG HSL_RW 1243 1244#define MUL_LEAKY_EN 1245#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET 27 1246#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN 1 1247#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG HSL_RW 1248 1249#define ARP_LEAKY_EN 1250#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET 26 1251#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN 1 1252#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG HSL_RW 1253 1254#define ING_MIRROR_EN 1255#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET 25 1256#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN 1 1257#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG HSL_RW 1258 1259#define PORT_LOOP_BACK 1260#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET 21 1261#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN 1 1262#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG HSL_RW 1263 1264#define LEARN_EN 1265#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET 20 1266#define PORT_LOOKUP_CTL_LEARN_EN_BLEN 1 1267#define PORT_LOOKUP_CTL_LEARN_EN_FLAG HSL_RW 1268 1269#define PORT_STATE 1270#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET 16 1271#define PORT_LOOKUP_CTL_PORT_STATE_BLEN 3 1272#define PORT_LOOKUP_CTL_PORT_STATE_FLAG HSL_RW 1273 1274#define FORCE_PVLAN 1275#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET 10 1276#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN 1 1277#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG HSL_RW 1278 1279#define DOT1Q_MODE 1280#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET 8 1281#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN 2 1282#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG HSL_RW 1283 1284#define PORT_VID_MEM 1285#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET 0 1286#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN 7 1287#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG HSL_RW 1288 1289 1290 1291 1292 /* Priority Control Register */ 1293#define PRI_CTL 1294#define PRI_CTL_OFFSET 0x0664 1295#define PRI_CTL_E_LENGTH 4 1296#define PRI_CTL_E_OFFSET 0x000c 1297#define PRI_CTL_NR_E 7 1298 1299#define EG_MAC_BASE_VLAN_EN 1300#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET 20 1301#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN 1 1302#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG HSL_RW 1303 1304#define FLOW_PRI_EN 1305#define PRI_CTL_FLOW_PRI_EN_BOFFSET 19 1306#define PRI_CTL_FLOW_PRI_EN_BLEN 1 1307#define PRI_CTL_FLOW_PRI_EN_FLAG HSL_RW 1308 1309#define DA_PRI_EN 1310#define PRI_CTL_DA_PRI_EN_BOFFSET 18 1311#define PRI_CTL_DA_PRI_EN_BLEN 1 1312#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW 1313 1314#define VLAN_PRI_EN 1315#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 1316#define PRI_CTL_VLAN_PRI_EN_BLEN 1 1317#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW 1318 1319#define IP_PRI_EN 1320#define PRI_CTL_IP_PRI_EN_BOFFSET 16 1321#define PRI_CTL_IP_PRI_EN_BLEN 1 1322#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW 1323 1324#define FLOW_PRI_SEL 1325#define PRI_CTL_FLOW_PRI_SEL_BOFFSET 8 1326#define PRI_CTL_FLOW_PRI_SEL_BLEN 2 1327#define PRI_CTL_FLOW_PRI_SEL_FLAG HSL_RW 1328 1329#define DA_PRI_SEL 1330#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 1331#define PRI_CTL_DA_PRI_SEL_BLEN 2 1332#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW 1333 1334#define VLAN_PRI_SEL 1335#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 1336#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 1337#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW 1338 1339#define IP_PRI_SEL 1340#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 1341#define PRI_CTL_IP_PRI_SEL_BLEN 2 1342#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW 1343 1344 1345 1346 /* Port Learn Limit Ctl Register */ 1347#define PORT_LEARN_LIMIT_CTL 1348#define PORT_LEARN_LIMIT_CTL_OFFSET 0x0668 1349#define PORT_LEARN_LIMIT_CTL_E_LENGTH 4 1350#define PORT_LEARN_LIMIT_CTL_E_OFFSET 0x000c 1351#define PORT_LEARN_LIMIT_CTL_NR_E 7 1352 1353#define IGMP_JOIN_LIMIT_DROP_EN 1354#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET 29 1355#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN 1 1356#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG HSL_RW 1357 1358#define SA_LEARN_LIMIT_DROP_EN 1359#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 28 1360#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 1361#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW 1362 1363#define IGMP_JOIN_LIMIT_EN 1364#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET 27 1365#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN 1 1366#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG HSL_RW 1367 1368#define IGMP_JOIN_CNT 1369#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET 16 1370#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN 11 1371#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG HSL_RW 1372 1373#define SA_LEARN_STATUS 1374#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET 12 1375#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN 4 1376#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG HSL_RW 1377 1378#define SA_LEARN_LIMIT_EN 1379#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET 11 1380#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN 1 1381#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG HSL_RW 1382 1383#define SA_LEARN_CNT 1384#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET 0 1385#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN 11 1386#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG HSL_RW 1387 1388 1389 1390 /* Global Trunk Ctl0 Register */ 1391#define GOL_TRUNK_CTL0 1392#define GOL_TRUNK_CTL0_OFFSET 0x0700 1393#define GOL_TRUNK_CTL0_E_LENGTH 4 1394#define GOL_TRUNK_CTL0_E_OFFSET 0x4 1395#define GOL_TRUNK_CTL0_NR_E 1 1396 1397 1398 /* Global Trunk Ctl1 Register */ 1399#define GOL_TRUNK_CTL1 1400#define GOL_TRUNK_CTL1_OFFSET 0x0704 1401#define GOL_TRUNK_CTL1_E_LENGTH 4 1402#define GOL_TRUNK_CTL1_E_OFFSET 0x4 1403#define GOL_TRUNK_CTL1_NR_E 2 1404 1405 1406 /* ACL Forward source filter Register */ 1407#define ACL_FWD_SRC_FILTER_CTL0 1408#define ACL_FWD_SRC_FILTER_CTL0_OFFSET 0x0710 1409#define ACL_FWD_SRC_FILTER_CTL0_E_LENGTH 4 1410#define ACL_FWD_SRC_FILTER_CTL0_E_OFFSET 0x4 1411#define ACL_FWD_SRC_FILTER_CTL0_NR_E 3 1412 1413 1414 /* VLAN translation register */ 1415#define VLAN_TRANS 1416#define VLAN_TRANS_OFFSET 0x0418 1417#define VLAN_TRANS_E_LENGTH 4 1418#define VLAN_TRANS_E_OFFSET 0 1419#define VLAN_TRANS_NR_E 7 1420 1421#define EG_FLTR_BYPASS_EN 1422#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BOFFSET 1 1423#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BLEN 1 1424#define VLAN_TRANS_EG_FLTR_BYPASS_EN_FLAG HSL_RW 1425 1426#define NET_ISO 1427#define VLAN_TRANS_NET_ISO_BOFFSET 0 1428#define VLAN_TRANS_NET_ISO_BLEN 1 1429#define VLAN_TRANS_NET_ISO_FLAG HSL_RW 1430 1431 1432 /* Port vlan0 Register */ 1433#define PORT_VLAN0 1434#define PORT_VLAN0_OFFSET 0x0420 1435#define PORT_VLAN0_E_LENGTH 4 1436#define PORT_VLAN0_E_OFFSET 0x0008 1437#define PORT_VLAN0_NR_E 7 1438 1439#define ING_CPRI 1440#define PORT_VLAN0_ING_CPRI_BOFFSET 29 1441#define PORT_VLAN0_ING_CPRI_BLEN 3 1442#define PORT_VLAN0_ING_CPRI_FLAG HSL_RW 1443 1444#define ING_FORCE_CPRI 1445#define PORT_VLAN0_ING_FORCE_CPRI_BOFFSET 28 1446#define PORT_VLAN0_ING_FORCE_CPRI_BLEN 1 1447#define PORT_VLAN0_ING_FORCE_CPRI_FLAG HSL_RW 1448 1449#define DEF_CVID 1450#define PORT_VLAN0_DEF_CVID_BOFFSET 16 1451#define PORT_VLAN0_DEF_CVID_BLEN 12 1452#define PORT_VLAN0_DEF_CVID_FLAG HSL_RW 1453 1454#define ING_SPRI 1455#define PORT_VLAN0_ING_SPRI_BOFFSET 13 1456#define PORT_VLAN0_ING_SPRI_BLEN 3 1457#define PORT_VLAN0_ING_SPRI_FLAG HSL_RW 1458 1459#define ING_FORCE_SPRI 1460#define PORT_VLAN0_ING_FORCE_SPRI_BOFFSET 12 1461#define PORT_VLAN0_ING_FORCE_SPRI_BLEN 1 1462#define PORT_VLAN0_ING_FORCE_SPRI_FLAG HSL_RW 1463 1464#define DEF_SVID 1465#define PORT_VLAN0_DEF_SVID_BOFFSET 0 1466#define PORT_VLAN0_DEF_SVID_BLEN 12 1467#define PORT_VLAN0_DEF_SVID_FLAG HSL_RW 1468 1469 /* Port vlan1 Register */ 1470#define PORT_VLAN1 1471#define PORT_VLAN1_OFFSET 0x0424 1472#define PORT_VLAN1_E_LENGTH 4 1473#define PORT_VLAN1_E_OFFSET 0x0008 1474#define PORT_VLAN1_NR_E 7 1475 1476#define VRF_ID 1477#define PORT_VLAN1_VRF_ID_BOFFSET 15 1478#define PORT_VLAN1_VRF_ID_BLEN 3 1479#define PORT_VLAN1_VRF_ID_FLAG HSL_RW 1480 1481#define EG_VLAN_MODE 1482#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET 12 1483#define PORT_VLAN1_EG_VLAN_MODE_BLEN 2 1484#define PORT_VLAN1_EG_VLAN_MODE_FLAG HSL_RW 1485 1486#define VLAN_DIS 1487#define PORT_VLAN1_VLAN_DIS_BOFFSET 11 1488#define PORT_VLAN1_VLAN_DIS_BLEN 1 1489#define PORT_VLAN1_VLAN_DIS_FLAG HSL_RW 1490 1491#define SP_CHECK_EN 1492#define PORT_VLAN1_SP_CHECK_EN_BOFFSET 10 1493#define PORT_VLAN1_SP_CHECK_EN_BLEN 1 1494#define PORT_VLAN1_SP_CHECK_EN_FLAG HSL_RW 1495 1496#define COREP_EN 1497#define PORT_VLAN1_COREP_EN_BOFFSET 9 1498#define PORT_VLAN1_COREP_EN_BLEN 1 1499#define PORT_VLAN1_COREP_EN_FLAG HSL_RW 1500 1501#define FORCE_DEF_VID 1502#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET 8 1503#define PORT_VLAN1_FORCE_DEF_VID_BLEN 1 1504#define PORT_VLAN1_FORCE_DEF_VID_FLAG HSL_RW 1505 1506#define TLS_EN 1507#define PORT_VLAN1_TLS_EN_BOFFSET 7 1508#define PORT_VLAN1_TLS_EN_BLEN 1 1509#define PORT_VLAN1_TLS_EN_FLAG HSL_RW 1510 1511#define PROPAGATION_EN 1512#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6 1513#define PORT_VLAN1_PROPAGATION_EN_BLEN 1 1514#define PORT_VLAN1_PROPAGATION_EN_FLAG HSL_RW 1515 1516#define CLONE 1517#define PORT_VLAN1_CLONE_BOFFSET 5 1518#define PORT_VLAN1_CLONE_BLEN 1 1519#define PORT_VLAN1_CLONE_FLAG HSL_RW 1520 1521#define PRI_PROPAGATION 1522#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET 4 1523#define PORT_VLAN1_PRI_PROPAGATION_BLEN 1 1524#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW 1525 1526#define IN_VLAN_MODE 1527#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET 2 1528#define PORT_VLAN1_IN_VLAN_MODE_BLEN 2 1529#define PORT_VLAN1_IN_VLAN_MODE_FLAG HSL_RW 1530 1531 1532 /* Route Default VID Register */ 1533#define ROUTER_DEFV 1534#define ROUTER_DEFV_OFFSET 0x0c70 1535#define ROUTER_DEFV_E_LENGTH 4 1536#define ROUTER_DEFV_E_OFFSET 0x0004 1537#define ROUTER_DEFV_NR_E 4 1538 1539 1540 /* Route Egress VLAN Mode Register */ 1541#define ROUTER_EG 1542#define ROUTER_EG_OFFSET 0x0c80 1543#define ROUTER_EG_E_LENGTH 4 1544#define ROUTER_EG_E_OFFSET 0x0004 1545#define ROUTER_EG_NR_E 1 1546 1547/* port flow control threshold Register */ 1548#define PORT_FLOC_CTRL_THRESH 1549#define PORT_FLOC_CTRL_THRESH_OFFSET 0x9b0 1550#define PORT_FLOC_CTRL_THRESH_E_LENGTH 4 1551#define PORT_FLOC_CTRL_THRESH_E_OFFSET 0x0004 1552#define PORT_FLOC_CTRL_THRESH_NR_E 7 1553 1554 1555 /* LED control Register */ 1556#define LED_CTRL "ledctrl" 1557#define LED_CTRL_ID 25 1558#define LED_CTRL_OFFSET 0x0050 1559#define LED_CTRL_E_LENGTH 4 1560#define LED_CTRL_E_OFFSET 0 1561#define LED_CTRL_NR_E 3 1562 1563#define PATTERN_EN "lctrl_pen" 1564#define LED_CTRL_PATTERN_EN_BOFFSET 14 1565#define LED_CTRL_PATTERN_EN_BLEN 2 1566#define LED_CTRL_PATTERN_EN_FLAG HSL_RW 1567 1568#define FULL_LIGHT_EN "lctrl_fen" 1569#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 1570#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 1571#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW 1572 1573#define HALF_LIGHT_EN "lctrl_hen" 1574#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 1575#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 1576#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW 1577 1578#define POWERON_LIGHT_EN "lctrl_poen" 1579#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 1580#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 1581#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW 1582 1583#define GE_LIGHT_EN "lctrl_geen" 1584#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 1585#define LED_CTRL_GE_LIGHT_EN_BLEN 1 1586#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW 1587 1588#define FE_LIGHT_EN "lctrl_feen" 1589#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 1590#define LED_CTRL_FE_LIGHT_EN_BLEN 1 1591#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW 1592 1593#define ETH_LIGHT_EN "lctrl_ethen" 1594#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 1595#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 1596#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW 1597 1598#define COL_BLINK_EN "lctrl_cen" 1599#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 1600#define LED_CTRL_COL_BLINK_EN_BLEN 1 1601#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW 1602 1603#define RX_BLINK_EN "lctrl_rxen" 1604#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 1605#define LED_CTRL_RX_BLINK_EN_BLEN 1 1606#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW 1607 1608#define TX_BLINK_EN "lctrl_txen" 1609#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 1610#define LED_CTRL_TX_BLINK_EN_BLEN 1 1611#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW 1612 1613#define LINKUP_OVER_EN "lctrl_loen" 1614#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 1615#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 1616#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW 1617 1618#define BLINK_FREQ "lctrl_bfreq" 1619#define LED_CTRL_BLINK_FREQ_BOFFSET 0 1620#define LED_CTRL_BLINK_FREQ_BLEN 2 1621#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW 1622 1623 /* LED control Register */ 1624#define LED_PATTERN "ledpatten" 1625#define LED_PATTERN_ID 25 1626#define LED_PATTERN_OFFSET 0x005c 1627#define LED_PATTERN_E_LENGTH 4 1628#define LED_PATTERN_E_OFFSET 0 1629#define LED_PATTERN_NR_E 1 1630 1631 1632#define P3L2_MODE 1633#define LED_PATTERN_P3L2_MODE_BOFFSET 24 1634#define LED_PATTERN_P3L2_MODE_BLEN 2 1635#define LED_PATTERN_P3L2_MODE_FLAG HSL_RW 1636 1637#define P3L1_MODE 1638#define LED_PATTERN_P3L1_MODE_BOFFSET 22 1639#define LED_PATTERN_P3L1_MODE_BLEN 2 1640#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW 1641 1642#define P3L0_MODE 1643#define LED_PATTERN_P3L0_MODE_BOFFSET 20 1644#define LED_PATTERN_P3L0_MODE_BLEN 2 1645#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW 1646 1647#define P2L2_MODE 1648#define LED_PATTERN_P2L2_MODE_BOFFSET 18 1649#define LED_PATTERN_P2L2_MODE_BLEN 2 1650#define LED_PATTERN_P2L2_MODE_FLAG HSL_RW 1651 1652#define P2L1_MODE 1653#define LED_PATTERN_P2L1_MODE_BOFFSET 16 1654#define LED_PATTERN_P2L1_MODE_BLEN 2 1655#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW 1656 1657#define P2L0_MODE 1658#define LED_PATTERN_P2L0_MODE_BOFFSET 14 1659#define LED_PATTERN_P2L0_MODE_BLEN 2 1660#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW 1661 1662#define P1L2_MODE 1663#define LED_PATTERN_P1L2_MODE_BOFFSET 12 1664#define LED_PATTERN_P1L2_MODE_BLEN 2 1665#define LED_PATTERN_P1L2_MODE_FLAG HSL_RW 1666 1667#define P1L1_MODE 1668#define LED_PATTERN_P1L1_MODE_BOFFSET 10 1669#define LED_PATTERN_P1L1_MODE_BLEN 2 1670#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW 1671 1672#define P1L0_MODE 1673#define LED_PATTERN_P1L0_MODE_BOFFSET 8 1674#define LED_PATTERN_P1L0_MODE_BLEN 2 1675#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW 1676 1677 1678 1679 1680 /* Pri To Queue Register */ 1681#define PRI_TO_QUEUE 1682#define PRI_TO_QUEUE_OFFSET 0x0814 1683#define PRI_TO_QUEUE_E_LENGTH 4 1684#define PRI_TO_QUEUE_E_OFFSET 0x0004 1685#define PRI_TO_QUEUE_NR_E 1 1686 1687 1688 1689 1690 /* Pri To EhQueue Register */ 1691#define PRI_TO_EHQUEUE 1692#define PRI_TO_EHQUEUE_OFFSET 0x0810 1693#define PRI_TO_EHQUEUE_E_LENGTH 4 1694#define PRI_TO_EHQUEUE_E_OFFSET 0x0004 1695#define PRI_TO_EHQUEUE_NR_E 1 1696 1697 1698 1699 1700 /*Global Flow Control Register*/ 1701#define QM_CTRL_REG 1702#define QM_CTRL_REG_OFFSET 0X0808 1703#define QM_CTRL_REG_E_LENGTH 4 1704#define QM_CTRL_REG_E_OFFSET 0x0004 1705#define QM_CTRL_REG_NR_E 1 1706 1707#define GOL_FLOW_EN 1708#define QM_CTRL_REG_GOL_FLOW_EN_BOFFSET 16 1709#define QM_CTRL_REG_GOL_FLOW_EN_BLEN 7 1710#define QM_CTRL_REG_GOL_FLOW_EN_FLAG HSL_RW 1711 1712#define QM_FUNC_TEST 1713#define QM_CTRL_REG_QM_FUNC_TEST_BOFFSET 10 1714#define QM_CTRL_REG_QM_FUNC_TEST_BLEN 1 1715#define QM_CTRL_REG_QM_FUNC_TEST_FLAG HSL_RW 1716 1717#define RATE_DROP_EN 1718#define QM_CTRL_REG_RATE_DROP_EN_BOFFSET 7 1719#define QM_CTRL_REG_RATE_DROP_EN_BLEN 1 1720#define QM_CTRL_REG_RATE_DROP_EN_FLAG HSL_RW 1721 1722#define FLOW_DROP_EN 1723#define QM_CTRL_REG_FLOW_DROP_EN_BOFFSET 6 1724#define QM_CTRL_REG_FLOW_DROP_EN_BLEN 1 1725#define QM_CTRL_REG_FLOW_DROP_EN_FLAG HSL_RW 1726 1727#define FLOW_DROP_CNT 1728#define QM_CTRL_REG_FLOW_DROP_CNT_BOFFSET 0 1729#define QM_CTRL_REG_FLOW_DROP_CNT_BLEN 6 1730#define QM_CTRL_REG_FLOW_DROP_CNT_FLAG HSL_RW 1731 1732 1733 1734 1735 /* Port HOL CTL0 Register */ 1736#define PORT_HOL_CTL0 1737#define PORT_HOL_CTL0_OFFSET 0x0970 1738#define PORT_HOL_CTL0_E_LENGTH 4 1739#define PORT_HOL_CTL0_E_OFFSET 0x0008 1740#define PORT_HOL_CTL0_NR_E 7 1741 1742#define PORT_DESC_NR 1743#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24 1744#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 6 1745#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW 1746 1747#define QUEUE5_DESC_NR 1748#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET 20 1749#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN 4 1750#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG HSL_RW 1751 1752#define QUEUE4_DESC_NR 1753#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET 16 1754#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN 4 1755#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG HSL_RW 1756 1757#define QUEUE3_DESC_NR 1758#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET 12 1759#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN 4 1760#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG HSL_RW 1761 1762#define QUEUE2_DESC_NR 1763#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET 8 1764#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN 4 1765#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG HSL_RW 1766 1767#define QUEUE1_DESC_NR 1768#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET 4 1769#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN 4 1770#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG HSL_RW 1771 1772#define QUEUE0_DESC_NR 1773#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET 0 1774#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN 4 1775#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG HSL_RW 1776 1777 /* Port HOL CTL1 Register */ 1778#define PORT_HOL_CTL1 1779#define PORT_HOL_CTL1_OFFSET 0x0974 1780#define PORT_HOL_CTL1_E_LENGTH 4 1781#define PORT_HOL_CTL1_E_OFFSET 0x0008 1782#define PORT_HOL_CTL1_NR_E 7 1783 1784#define EG_MIRROR_EN 1785#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET 16 1786#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN 1 1787#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG HSL_RW 1788 1789#define PORT_RED_EN 1790#define PORT_HOL_CTL1_PORT_RED_EN_BOFFSET 8 1791#define PORT_HOL_CTL1_PORT_RED_EN_BLEN 1 1792#define PORT_HOL_CTL1_PORT_RED_EN_FLAG HSL_RW 1793 1794#define PORT_DESC_EN 1795#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET 7 1796#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN 1 1797#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG HSL_RW 1798 1799#define QUEUE_DESC_EN 1800#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET 6 1801#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN 1 1802#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG HSL_RW 1803 1804#define PORT_IN_DESC_EN 1805#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0 1806#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 4 1807#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW 1808 1809 1810 /* PKT edit control register */ 1811#define PKT_CTRL 1812#define PKT_CTRL_OFFSET 0x0c00 1813#define PKT_CTRL_E_LENGTH 4 1814#define PKT_CTRL_E_OFFSET 0 1815#define PKT_CTRL_NR_E 7 1816 1817#define CPU_VID_EN 1818#define PKT_CTRL_CPU_VID_EN_BOFFSET 1 1819#define PKT_CTRL_CPU_VID_EN_BLEN 1 1820#define PKT_CTRL_CPU_VID_EN_FLAG HSL_RW 1821 1822 1823#define RTD_PPPOE_EN 1824#define PKT_CTRL_RTD_PPPOE_EN_BOFFSET 0 1825#define PKT_CTRL_RTD_PPPOE_EN_BLEN 1 1826#define PKT_CTRL_RTD_PPPOE_EN_FLAG HSL_RW 1827 1828 1829 1830 1831 /* mib memory info */ 1832#define MIB_RXBROAD 1833#define MIB_RXBROAD_OFFSET 0x01000 1834#define MIB_RXBROAD_E_LENGTH 4 1835#define MIB_RXBROAD_E_OFFSET 0x100 1836#define MIB_RXBROAD_NR_E 7 1837 1838#define MIB_RXPAUSE 1839#define MIB_RXPAUSE_OFFSET 0x01004 1840#define MIB_RXPAUSE_E_LENGTH 4 1841#define MIB_RXPAUSE_E_OFFSET 0x100 1842#define MIB_RXPAUSE_NR_E 7 1843 1844#define MIB_RXMULTI 1845#define MIB_RXMULTI_OFFSET 0x01008 1846#define MIB_RXMULTI_E_LENGTH 4 1847#define MIB_RXMULTI_E_OFFSET 0x100 1848#define MIB_RXMULTI_NR_E 7 1849 1850#define MIB_RXFCSERR 1851#define MIB_RXFCSERR_OFFSET 0x0100c 1852#define MIB_RXFCSERR_E_LENGTH 4 1853#define MIB_RXFCSERR_E_OFFSET 0x100 1854#define MIB_RXFCSERR_NR_E 7 1855 1856#define MIB_RXALLIGNERR 1857#define MIB_RXALLIGNERR_OFFSET 0x01010 1858#define MIB_RXALLIGNERR_E_LENGTH 4 1859#define MIB_RXALLIGNERR_E_OFFSET 0x100 1860#define MIB_RXALLIGNERR_NR_E 7 1861 1862#define MIB_RXRUNT 1863#define MIB_RXRUNT_OFFSET 0x01014 1864#define MIB_RXRUNT_E_LENGTH 4 1865#define MIB_RXRUNT_E_OFFSET 0x100 1866#define MIB_RXRUNT_NR_E 7 1867 1868#define MIB_RXFRAGMENT 1869#define MIB_RXFRAGMENT_OFFSET 0x01018 1870#define MIB_RXFRAGMENT_E_LENGTH 4 1871#define MIB_RXFRAGMENT_E_OFFSET 0x100 1872#define MIB_RXFRAGMENT_NR_E 7 1873 1874#define MIB_RX64BYTE 1875#define MIB_RX64BYTE_OFFSET 0x0101c 1876#define MIB_RX64BYTE_E_LENGTH 4 1877#define MIB_RX64BYTE_E_OFFSET 0x100 1878#define MIB_RX64BYTE_NR_E 7 1879 1880#define MIB_RX128BYTE 1881#define MIB_RX128BYTE_OFFSET 0x01020 1882#define MIB_RX128BYTE_E_LENGTH 4 1883#define MIB_RX128BYTE_E_OFFSET 0x100 1884#define MIB_RX128BYTE_NR_E 7 1885 1886#define MIB_RX256BYTE 1887#define MIB_RX256BYTE_OFFSET 0x01024 1888#define MIB_RX256BYTE_E_LENGTH 4 1889#define MIB_RX256BYTE_E_OFFSET 0x100 1890#define MIB_RX256BYTE_NR_E 7 1891 1892#define MIB_RX512BYTE 1893#define MIB_RX512BYTE_OFFSET 0x01028 1894#define MIB_RX512BYTE_E_LENGTH 4 1895#define MIB_RX512BYTE_E_OFFSET 0x100 1896#define MIB_RX512BYTE_NR_E 7 1897 1898#define MIB_RX1024BYTE 1899#define MIB_RX1024BYTE_OFFSET 0x0102c 1900#define MIB_RX1024BYTE_E_LENGTH 4 1901#define MIB_RX1024BYTE_E_OFFSET 0x100 1902#define MIB_RX1024BYTE_NR_E 7 1903 1904#define MIB_RX1518BYTE 1905#define MIB_RX1518BYTE_OFFSET 0x01030 1906#define MIB_RX1518BYTE_E_LENGTH 4 1907#define MIB_RX1518BYTE_E_OFFSET 0x100 1908#define MIB_RX1518BYTE_NR_E 7 1909 1910#define MIB_RXMAXBYTE 1911#define MIB_RXMAXBYTE_OFFSET 0x01034 1912#define MIB_RXMAXBYTE_E_LENGTH 4 1913#define MIB_RXMAXBYTE_E_OFFSET 0x100 1914#define MIB_RXMAXBYTE_NR_E 7 1915 1916#define MIB_RXTOOLONG 1917#define MIB_RXTOOLONG_OFFSET 0x01038 1918#define MIB_RXTOOLONG_E_LENGTH 4 1919#define MIB_RXTOOLONG_E_OFFSET 0x100 1920#define MIB_RXTOOLONG_NR_E 7 1921 1922#define MIB_RXGOODBYTE_LO 1923#define MIB_RXGOODBYTE_LO_OFFSET 0x0103c 1924#define MIB_RXGOODBYTE_LO_E_LENGTH 4 1925#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 1926#define MIB_RXGOODBYTE_LO_NR_E 7 1927 1928#define MIB_RXGOODBYTE_HI 1929#define MIB_RXGOODBYTE_HI_OFFSET 0x01040 1930#define MIB_RXGOODBYTE_HI_E_LENGTH 4 1931#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 1932#define MIB_RXGOODBYTE_HI_NR_E 7 1933 1934#define MIB_RXBADBYTE_LO 1935#define MIB_RXBADBYTE_LO_OFFSET 0x01044 1936#define MIB_RXBADBYTE_LO_E_LENGTH 4 1937#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 1938#define MIB_RXBADBYTE_LO_NR_E 7 1939 1940#define MIB_RXBADBYTE_HI 1941#define MIB_RXBADBYTE_HI_OFFSET 0x01048 1942#define MIB_RXBADBYTE_HI_E_LENGTH 4 1943#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 1944#define MIB_RXBADBYTE_HI_NR_E 7 1945 1946#define MIB_RXOVERFLOW 1947#define MIB_RXOVERFLOW_OFFSET 0x0104c 1948#define MIB_RXOVERFLOW_E_LENGTH 4 1949#define MIB_RXOVERFLOW_E_OFFSET 0x100 1950#define MIB_RXOVERFLOW_NR_E 7 1951 1952#define MIB_FILTERED 1953#define MIB_FILTERED_OFFSET 0x01050 1954#define MIB_FILTERED_E_LENGTH 4 1955#define MIB_FILTERED_E_OFFSET 0x100 1956#define MIB_FILTERED_NR_E 7 1957 1958#define MIB_TXBROAD 1959#define MIB_TXBROAD_OFFSET 0x01054 1960#define MIB_TXBROAD_E_LENGTH 4 1961#define MIB_TXBROAD_E_OFFSET 0x100 1962#define MIB_TXBROAD_NR_E 7 1963 1964#define MIB_TXPAUSE 1965#define MIB_TXPAUSE_OFFSET 0x01058 1966#define MIB_TXPAUSE_E_LENGTH 4 1967#define MIB_TXPAUSE_E_OFFSET 0x100 1968#define MIB_TXPAUSE_NR_E 7 1969 1970#define MIB_TXMULTI 1971#define MIB_TXMULTI_OFFSET 0x0105c 1972#define MIB_TXMULTI_E_LENGTH 4 1973#define MIB_TXMULTI_E_OFFSET 0x100 1974#define MIB_TXMULTI_NR_E 7 1975 1976#define MIB_TXUNDERRUN 1977#define MIB_TXUNDERRUN_OFFSET 0x01060 1978#define MIB_TXUNDERRUN_E_LENGTH 4 1979#define MIB_TXUNDERRUN_E_OFFSET 0x100 1980#define MIB_TXUNDERRUN_NR_E 7 1981 1982#define MIB_TX64BYTE 1983#define MIB_TX64BYTE_OFFSET 0x01064 1984#define MIB_TX64BYTE_E_LENGTH 4 1985#define MIB_TX64BYTE_E_OFFSET 0x100 1986#define MIB_TX64BYTE_NR_E 7 1987 1988#define MIB_TX128BYTE 1989#define MIB_TX128BYTE_OFFSET 0x01068 1990#define MIB_TX128BYTE_E_LENGTH 4 1991#define MIB_TX128BYTE_E_OFFSET 0x100 1992#define MIB_TX128BYTE_NR_E 7 1993 1994#define MIB_TX256BYTE 1995#define MIB_TX256BYTE_OFFSET 0x0106c 1996#define MIB_TX256BYTE_E_LENGTH 4 1997#define MIB_TX256BYTE_E_OFFSET 0x100 1998#define MIB_TX256BYTE_NR_E 7 1999 2000#define MIB_TX512BYTE 2001#define MIB_TX512BYTE_OFFSET 0x01070 2002#define MIB_TX512BYTE_E_LENGTH 4 2003#define MIB_TX512BYTE_E_OFFSET 0x100 2004#define MIB_TX512BYTE_NR_E 7 2005 2006#define MIB_TX1024BYTE 2007#define MIB_TX1024BYTE_OFFSET 0x01074 2008#define MIB_TX1024BYTE_E_LENGTH 4 2009#define MIB_TX1024BYTE_E_OFFSET 0x100 2010#define MIB_TX1024BYTE_NR_E 7 2011 2012#define MIB_TX1518BYTE 2013#define MIB_TX1518BYTE_OFFSET 0x01078 2014#define MIB_TX1518BYTE_E_LENGTH 4 2015#define MIB_TX1518BYTE_E_OFFSET 0x100 2016#define MIB_TX1518BYTE_NR_E 7 2017 2018#define MIB_TXMAXBYTE 2019#define MIB_TXMAXBYTE_OFFSET 0x0107c 2020#define MIB_TXMAXBYTE_E_LENGTH 4 2021#define MIB_TXMAXBYTE_E_OFFSET 0x100 2022#define MIB_TXMAXBYTE_NR_E 7 2023 2024#define MIB_TXOVERSIZE 2025#define MIB_TXOVERSIZE_OFFSET 0x01080 2026#define MIB_TXOVERSIZE_E_LENGTH 4 2027#define MIB_TXOVERSIZE_E_OFFSET 0x100 2028#define MIB_TXOVERSIZE_NR_E 7 2029 2030#define MIB_TXBYTE_LO 2031#define MIB_TXBYTE_LO_OFFSET 0x01084 2032#define MIB_TXBYTE_LO_E_LENGTH 4 2033#define MIB_TXBYTE_LO_E_OFFSET 0x100 2034#define MIB_TXBYTE_LO_NR_E 7 2035 2036#define MIB_TXBYTE_HI 2037#define MIB_TXBYTE_HI_OFFSET 0x01088 2038#define MIB_TXBYTE_HI_E_LENGTH 4 2039#define MIB_TXBYTE_HI_E_OFFSET 0x100 2040#define MIB_TXBYTE_HI_NR_E 7 2041 2042#define MIB_TXCOLLISION 2043#define MIB_TXCOLLISION_OFFSET 0x0108c 2044#define MIB_TXCOLLISION_E_LENGTH 4 2045#define MIB_TXCOLLISION_E_OFFSET 0x100 2046#define MIB_TXCOLLISION_NR_E 7 2047 2048#define MIB_TXABORTCOL 2049#define MIB_TXABORTCOL_OFFSET 0x01090 2050#define MIB_TXABORTCOL_E_LENGTH 4 2051#define MIB_TXABORTCOL_E_OFFSET 0x100 2052#define MIB_TXABORTCOL_NR_E 7 2053 2054#define MIB_TXMULTICOL 2055#define MIB_TXMULTICOL_OFFSET 0x01094 2056#define MIB_TXMULTICOL_E_LENGTH 4 2057#define MIB_TXMULTICOL_E_OFFSET 0x100 2058#define MIB_TXMULTICOL_NR_E 7 2059 2060#define MIB_TXSINGALCOL 2061#define MIB_TXSINGALCOL_OFFSET 0x01098 2062#define MIB_TXSINGALCOL_E_LENGTH 4 2063#define MIB_TXSINGALCOL_E_OFFSET 0x100 2064#define MIB_TXSINGALCOL_NR_E 7 2065 2066#define MIB_TXEXCDEFER 2067#define MIB_TXEXCDEFER_OFFSET 0x0109c 2068#define MIB_TXEXCDEFER_E_LENGTH 4 2069#define MIB_TXEXCDEFER_E_OFFSET 0x100 2070#define MIB_TXEXCDEFER_NR_E 7 2071 2072#define MIB_TXDEFER 2073#define MIB_TXDEFER_OFFSET 0x010a0 2074#define MIB_TXDEFER_E_LENGTH 4 2075#define MIB_TXDEFER_E_OFFSET 0x100 2076#define MIB_TXDEFER_NR_E 7 2077 2078#define MIB_TXLATECOL 2079#define MIB_TXLATECOL_OFFSET 0x010a4 2080#define MIB_TXLATECOL_E_LENGTH 4 2081#define MIB_TXLATECOL_E_OFFSET 0x100 2082#define MIB_TXLATECOL_NR_E 7 2083 2084#define MIB_RXUNICAST 2085#define MIB_RXUNICAST_OFFSET 0x010a8 2086#define MIB_RXUNICAST_E_LENGTH 4 2087#define MIB_RXUNICAST_E_OFFSET 0x100 2088#define MIB_RXUNICAST_NR_E 7 2089 2090#define MIB_TXUNICAST 2091#define MIB_TXUNICAST_OFFSET 0x010ac 2092#define MIB_TXUNICAST_E_LENGTH 4 2093#define MIB_TXUNICAST_E_OFFSET 0x100 2094#define MIB_TXUNICAST_NR_E 7 2095 2096 /* ACL Action Register */ 2097#define ACL_RSLT0 10 2098#define ACL_RSLT0_OFFSET 0x5a000 2099#define ACL_RSLT0_E_LENGTH 4 2100#define ACL_RSLT0_E_OFFSET 0x10 2101#define ACL_RSLT0_NR_E 96 2102 2103#define CTAGPRI 2104#define ACL_RSLT0_CTAGPRI_BOFFSET 29 2105#define ACL_RSLT0_CTAGPRI_BLEN 3 2106#define ACL_RSLT0_CTAGPRI_FLAG HSL_RW 2107 2108#define CTAGCFI 2109#define ACL_RSLT0_CTAGCFI_BOFFSET 28 2110#define ACL_RSLT0_CTAGCFI_BLEN 1 2111#define ACL_RSLT0_CTAGCFI_FLAG HSL_RW 2112 2113#define CTAGVID 2114#define ACL_RSLT0_CTAGVID_BOFFSET 16 2115#define ACL_RSLT0_CTAGVID_BLEN 12 2116#define ACL_RSLT0_CTAGVID_FLAG HSL_RW 2117 2118#define STAGPRI 2119#define ACL_RSLT0_STAGPRI_BOFFSET 13 2120#define ACL_RSLT0_STAGPRI_BLEN 3 2121#define ACL_RSLT0_STAGPRI_FLAG HSL_RW 2122 2123#define STAGDEI 2124#define ACL_RSLT0_STAGDEI_BOFFSET 12 2125#define ACL_RSLT0_STAGDEI_BLEN 1 2126#define ACL_RSLT0_STAGDEI_FLAG HSL_RW 2127 2128#define STAGVID 2129#define ACL_RSLT0_STAGVID_BOFFSET 0 2130#define ACL_RSLT0_STAGVID_BLEN 12 2131#define ACL_RSLT0_STAGVID_FLAG HSL_RW 2132 2133 2134#define ACL_RSLT1 11 2135#define ACL_RSLT1_OFFSET 0x5a004 2136#define ACL_RSLT1_E_LENGTH 4 2137#define ACL_RSLT1_E_OFFSET 0x10 2138#define ACL_RSLT1_NR_E 96 2139 2140#define DES_PORT0 2141#define ACL_RSLT1_DES_PORT0_BOFFSET 29 2142#define ACL_RSLT1_DES_PORT0_BLEN 3 2143#define ACL_RSLT1_DES_PORT0_FLAG HSL_RW 2144 2145#define PRI_QU_EN 2146#define ACL_RSLT1_PRI_QU_EN_BOFFSET 28 2147#define ACL_RSLT1_PRI_QU_EN_BLEN 1 2148#define ACL_RSLT1_PRI_QU_EN_FLAG HSL_RW 2149 2150#define PRI_QU 2151#define ACL_RSLT1_PRI_QU_BOFFSET 25 2152#define ACL_RSLT1_PRI_QU_BLEN 3 2153#define ACL_RSLT1_PRI_QU_FLAG HSL_RW 2154 2155#define WCMP_EN 2156#define ACL_RSLT1_WCMP_EN_BOFFSET 24 2157#define ACL_RSLT1_WCMP_EN_BLEN 1 2158#define ACL_RSLT1_WCMP_EN_FLAG HSL_RW 2159 2160#define ARP_PTR 2161#define ACL_RSLT1_ARP_PTR_BOFFSET 17 2162#define ACL_RSLT1_ARP_PTR_BLEN 7 2163#define ACL_RSLT1_ARP_PTR_FLAG HSL_RW 2164 2165#define ARP_PTR_EN 2166#define ACL_RSLT1_ARP_PTR_EN_BOFFSET 16 2167#define ACL_RSLT1_ARP_PTR_EN_BLEN 1 2168#define ACL_RSLT1_ARP_PTR_EN_FLAG HSL_RW 2169 2170#define FORCE_L3_MODE 2171#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET 14 2172#define ACL_RSLT1_FORCE_L3_MODE_BLEN 2 2173#define ACL_RSLT1_FORCE_L3_MODE_FLAG HSL_RW 2174 2175#define LOOK_VID_CHG 2176#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET 13 2177#define ACL_RSLT1_LOOK_VID_CHG_BLEN 1 2178#define ACL_RSLT1_LOOK_VID_CHG_FLAG HSL_RW 2179 2180#define TRANS_CVID_CHG 2181#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET 12 2182#define ACL_RSLT1_TRANS_CVID_CHG_BLEN 1 2183#define ACL_RSLT1_TRANS_CVID_CHG_FLAG HSL_RW 2184 2185#define TRANS_SVID_CHG 2186#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET 11 2187#define ACL_RSLT1_TRANS_SVID_CHG_BLEN 1 2188#define ACL_RSLT1_TRANS_SVID_CHG_FLAG HSL_RW 2189 2190#define CTAG_CFI_CHG 2191#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET 10 2192#define ACL_RSLT1_CTAG_CFI_CHG_BLEN 1 2193#define ACL_RSLT1_CTAG_CFI_CHG_FLAG HSL_RW 2194 2195#define CTAG_PRI_REMAP 2196#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET 9 2197#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN 1 2198#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG HSL_RW 2199 2200#define STAG_DEI_CHG 2201#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET 8 2202#define ACL_RSLT1_STAG_DEI_CHG_BLEN 1 2203#define ACL_RSLT1_STAG_DEI_CHG_FLAG HSL_RW 2204 2205#define STAG_PRI_REMAP 2206#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET 7 2207#define ACL_RSLT1_STAG_PRI_REMAP_BLEN 1 2208#define ACL_RSLT1_STAG_PRI_REMAP_FLAG HSL_RW 2209 2210#define DSCP_REMAP 2211#define ACL_RSLT1_DSCP_REMAP_BOFFSET 6 2212#define ACL_RSLT1_DSCP_REMAP_BLEN 1 2213#define ACL_RSLT1_DSCP_REMAP_FLAG HSL_RW 2214 2215#define DSCPV 2216#define ACL_RSLT1_DSCPV_BOFFSET 0 2217#define ACL_RSLT1_DSCPV_BLEN 6 2218#define ACL_RSLT1_DSCPV_FLAG HSL_RW 2219 2220#define ACL_RSLT2 12 2221#define ACL_RSLT2_OFFSET 0x5a008 2222#define ACL_RSLT2_E_LENGTH 4 2223#define ACL_RSLT2_E_OFFSET 0x10 2224#define ACL_RSLT2_NR_E 96 2225 2226#define TRIGGER_INTR 2227#define ACL_RSLT2_TRIGGER_INTR_BOFFSET 16 2228#define ACL_RSLT2_TRIGGER_INTR_BLEN 1 2229#define ACL_RSLT2_TRIGGER_INTR_FLAG HSL_RW 2230 2231#define EG_BYPASS 2232#define ACL_RSLT2_EG_BYPASS_BOFFSET 15 2233#define ACL_RSLT2_EG_BYPASS_BLEN 1 2234#define ACL_RSLT2_EG_BYPASS_FLAG HSL_RW 2235 2236#define POLICER_EN 2237#define ACL_RSLT2_POLICER_EN_BOFFSET 14 2238#define ACL_RSLT2_POLICER_EN_BLEN 1 2239#define ACL_RSLT2_POLICER_EN_FLAG HSL_RW 2240 2241#define POLICER_PTR 2242#define ACL_RSLT2_POLICER_PTR_BOFFSET 9 2243#define ACL_RSLT2_POLICER_PTR_BLEN 5 2244#define ACL_RSLT2_POLICER_PTR_FLAG HSL_RW 2245 2246#define FWD_CMD 2247#define ACL_RSLT2_FWD_CMD_BOFFSET 6 2248#define ACL_RSLT2_FWD_CMD_BLEN 3 2249#define ACL_RSLT2_FWD_CMD_FLAG HSL_RW 2250 2251#define MIRR_EN 2252#define ACL_RSLT2_MIRR_EN_BOFFSET 5 2253#define ACL_RSLT2_MIRR_EN_BLEN 1 2254#define ACL_RSLT2_MIRR_EN_FLAG HSL_RW 2255 2256#define DES_PORT_EN 2257#define ACL_RSLT2_DES_PORT_EN_BOFFSET 4 2258#define ACL_RSLT2_DES_PORT_EN_BLEN 1 2259#define ACL_RSLT2_DES_PORT_EN_FLAG HSL_RW 2260 2261#define DES_PORT1 2262#define ACL_RSLT2_DES_PORT1_BOFFSET 0 2263#define ACL_RSLT2_DES_PORT1_BLEN 4 2264#define ACL_RSLT2_DES_PORT1_FLAG HSL_RW 2265 2266 2267 2268 2269 /* MAC Type Rule Field Define */ 2270#define MAC_RUL_V0 0 2271#define MAC_RUL_V0_OFFSET 0x58000 2272#define MAC_RUL_V0_E_LENGTH 4 2273#define MAC_RUL_V0_E_OFFSET 0x20 2274#define MAC_RUL_V0_NR_E 96 2275 2276#define DAV_BYTE2 2277#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24 2278#define MAC_RUL_V0_DAV_BYTE2_BLEN 8 2279#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW 2280 2281#define DAV_BYTE3 2282#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16 2283#define MAC_RUL_V0_DAV_BYTE3_BLEN 8 2284#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW 2285 2286#define DAV_BYTE4 2287#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8 2288#define MAC_RUL_V0_DAV_BYTE4_BLEN 8 2289#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW 2290 2291#define DAV_BYTE5 2292#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0 2293#define MAC_RUL_V0_DAV_BYTE5_BLEN 8 2294#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW 2295 2296 2297#define MAC_RUL_V1 1 2298#define MAC_RUL_V1_OFFSET 0x58004 2299#define MAC_RUL_V1_E_LENGTH 4 2300#define MAC_RUL_V1_E_OFFSET 0x20 2301#define MAC_RUL_V1_NR_E 96 2302 2303#define SAV_BYTE4 2304#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24 2305#define MAC_RUL_V1_SAV_BYTE4_BLEN 8 2306#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW 2307 2308#define SAV_BYTE5 2309#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16 2310#define MAC_RUL_V1_SAV_BYTE5_BLEN 8 2311#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW 2312 2313#define DAV_BYTE0 2314#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8 2315#define MAC_RUL_V1_DAV_BYTE0_BLEN 8 2316#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW 2317 2318#define DAV_BYTE1 2319#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0 2320#define MAC_RUL_V1_DAV_BYTE1_BLEN 8 2321#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW 2322 2323 2324#define MAC_RUL_V2 2 2325#define MAC_RUL_V2_OFFSET 0x58008 2326#define MAC_RUL_V2_E_LENGTH 4 2327#define MAC_RUL_V2_E_OFFSET 0x20 2328#define MAC_RUL_V2_NR_E 96 2329 2330#define SAV_BYTE0 2331#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24 2332#define MAC_RUL_V2_SAV_BYTE0_BLEN 8 2333#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW 2334 2335#define SAV_BYTE1 2336#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16 2337#define MAC_RUL_V2_SAV_BYTE1_BLEN 8 2338#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW 2339 2340#define SAV_BYTE2 2341#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8 2342#define MAC_RUL_V2_SAV_BYTE2_BLEN 8 2343#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW 2344 2345#define SAV_BYTE3 2346#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0 2347#define MAC_RUL_V2_SAV_BYTE3_BLEN 8 2348#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW 2349 2350 2351#define MAC_RUL_V3 3 2352#define MAC_RUL_V3_ID 13 2353#define MAC_RUL_V3_OFFSET 0x5800c 2354#define MAC_RUL_V3_E_LENGTH 4 2355#define MAC_RUL_V3_E_OFFSET 0x20 2356#define MAC_RUL_V3_NR_E 96 2357 2358#define ETHTYPV 2359#define MAC_RUL_V3_ETHTYPV_BOFFSET 16 2360#define MAC_RUL_V3_ETHTYPV_BLEN 16 2361#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW 2362 2363#define VLANPRIV 2364#define MAC_RUL_V3_VLANPRIV_BOFFSET 13 2365#define MAC_RUL_V3_VLANPRIV_BLEN 3 2366#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW 2367 2368#define VLANCFIV 2369#define MAC_RUL_V3_VLANCFIV_BOFFSET 12 2370#define MAC_RUL_V3_VLANCFIV_BLEN 1 2371#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW 2372 2373#define VLANIDV 2374#define MAC_RUL_V3_VLANIDV_BOFFSET 0 2375#define MAC_RUL_V3_VLANIDV_BLEN 12 2376#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW 2377 2378 2379#define MAC_RUL_V4 4 2380#define MAC_RUL_V4_OFFSET 0x58010 2381#define MAC_RUL_V4_E_LENGTH 4 2382#define MAC_RUL_V4_E_OFFSET 0x20 2383#define MAC_RUL_V4_NR_E 96 2384 2385#define RULE_INV 2386#define MAC_RUL_V4_RULE_INV_BOFFSET 7 2387#define MAC_RUL_V4_RULE_INV_BLEN 1 2388#define MAC_RUL_V4_RULE_INV_FLAG HSL_RW 2389 2390#define SRC_PT 2391#define MAC_RUL_V4_SRC_PT_BOFFSET 0 2392#define MAC_RUL_V4_SRC_PT_BLEN 7 2393#define MAC_RUL_V4_SRC_PT_FLAG HSL_RW 2394 2395 2396#define MAC_RUL_M0 5 2397#define MAC_RUL_M0_OFFSET 0x59000 2398#define MAC_RUL_M0_E_LENGTH 4 2399#define MAC_RUL_M0_E_OFFSET 0x20 2400#define MAC_RUL_M0_NR_E 96 2401 2402#define DAM_BYTE2 2403#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24 2404#define MAC_RUL_M0_DAM_BYTE2_BLEN 8 2405#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW 2406 2407#define DAM_BYTE3 2408#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16 2409#define MAC_RUL_M0_DAM_BYTE3_BLEN 8 2410#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW 2411 2412#define DAM_BYTE4 2413#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8 2414#define MAC_RUL_M0_DAM_BYTE4_BLEN 8 2415#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW 2416 2417#define DAM_BYTE5 2418#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0 2419#define MAC_RUL_M0_DAM_BYTE5_BLEN 8 2420#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW 2421 2422 2423#define MAC_RUL_M1 6 2424#define MAC_RUL_M1_OFFSET 0x59004 2425#define MAC_RUL_M1_E_LENGTH 4 2426#define MAC_RUL_M1_E_OFFSET 0x20 2427#define MAC_RUL_M1_NR_E 96 2428 2429#define SAM_BYTE4 2430#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24 2431#define MAC_RUL_M1_SAM_BYTE4_BLEN 8 2432#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW 2433 2434#define SAM_BYTE5 2435#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16 2436#define MAC_RUL_M1_SAM_BYTE5_BLEN 8 2437#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW 2438 2439#define DAM_BYTE0 2440#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8 2441#define MAC_RUL_M1_DAM_BYTE0_BLEN 8 2442#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW 2443 2444#define DAM_BYTE1 2445#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0 2446#define MAC_RUL_M1_DAM_BYTE1_BLEN 8 2447#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW 2448 2449 2450#define MAC_RUL_M2 7 2451#define MAC_RUL_M2_OFFSET 0x59008 2452#define MAC_RUL_M2_E_LENGTH 4 2453#define MAC_RUL_M2_E_OFFSET 0x20 2454#define MAC_RUL_M2_NR_E 96 2455 2456#define SAM_BYTE0 2457#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24 2458#define MAC_RUL_M2_SAM_BYTE0_BLEN 8 2459#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW 2460 2461#define SAM_BYTE1 2462#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16 2463#define MAC_RUL_M2_SAM_BYTE1_BLEN 8 2464#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW 2465 2466#define SAM_BYTE2 2467#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8 2468#define MAC_RUL_M2_SAM_BYTE2_BLEN 8 2469#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW 2470 2471#define SAM_BYTE3 2472#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0 2473#define MAC_RUL_M2_SAM_BYTE3_BLEN 8 2474#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW 2475 2476 2477#define MAC_RUL_M3 8 2478#define MAC_RUL_M3_OFFSET 0x5900c 2479#define MAC_RUL_M3_E_LENGTH 4 2480#define MAC_RUL_M3_E_OFFSET 0x20 2481#define MAC_RUL_M3_NR_E 96 2482 2483#define ETHTYPM 2484#define MAC_RUL_M3_ETHTYPM_BOFFSET 16 2485#define MAC_RUL_M3_ETHTYPM_BLEN 16 2486#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW 2487 2488#define VLANPRIM 2489#define MAC_RUL_M3_VLANPRIM_BOFFSET 13 2490#define MAC_RUL_M3_VLANPRIM_BLEN 3 2491#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW 2492 2493#define VLANCFIM 2494#define MAC_RUL_M3_VLANCFIM_BOFFSET 12 2495#define MAC_RUL_M3_VLANCFIM_BLEN 1 2496#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW 2497 2498#define VLANIDM 2499#define MAC_RUL_M3_VLANIDM_BOFFSET 0 2500#define MAC_RUL_M3_VLANIDM_BLEN 12 2501#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW 2502 2503 2504#define MAC_RUL_M4 9 2505#define MAC_RUL_M4_OFFSET 0x59010 2506#define MAC_RUL_M4_E_LENGTH 4 2507#define MAC_RUL_M4_E_OFFSET 0x20 2508#define MAC_RUL_M4_NR_E 96 2509 2510#define RULE_VALID 2511#define MAC_RUL_M4_RULE_VALID_BOFFSET 6 2512#define MAC_RUL_M4_RULE_VALID_BLEN 2 2513#define MAC_RUL_M4_RULE_VALID_FLAG HSL_RW 2514 2515#define TAGGEDM 2516#define MAC_RUL_M4_TAGGEDM_BOFFSET 5 2517#define MAC_RUL_M4_TAGGEDM_BLEN 1 2518#define MAC_RUL_M4_TAGGEDM_FLAG HSL_RW 2519 2520#define TAGGEDV 2521#define MAC_RUL_M4_TAGGEDV_BOFFSET 4 2522#define MAC_RUL_M4_TAGGEDV_BLEN 1 2523#define MAC_RUL_M4_TAGGEDV_FLAG HSL_RW 2524 2525#define VIDMSK 2526#define MAC_RUL_M4_VIDMSK_BOFFSET 3 2527#define MAC_RUL_M4_VIDMSK_BLEN 1 2528#define MAC_RUL_M4_VIDMSK_FLAG HSL_RW 2529 2530#define RULE_TYP 2531#define MAC_RUL_M4_RULE_TYP_BOFFSET 0 2532#define MAC_RUL_M4_RULE_TYP_BLEN 3 2533#define MAC_RUL_M4_RULE_TYP_FLAG HSL_RW 2534 2535 2536 2537 2538 /* IP4 Type Rule Field Define */ 2539#define IP4_RUL_V0 0 2540#define IP4_RUL_V0_OFFSET 0x58000 2541#define IP4_RUL_V0_E_LENGTH 4 2542#define IP4_RUL_V0_E_OFFSET 0x20 2543#define IP4_RUL_V0_NR_E 96 2544 2545#define DIPV 2546#define IP4_RUL_V0_DIPV_BOFFSET 0 2547#define IP4_RUL_V0_DIPV_BLEN 32 2548#define IP4_RUL_V0_DIPV_FLAG HSL_RW 2549 2550 2551#define IP4_RUL_V1 1 2552#define IP4_RUL_V1_OFFSET 0x58004 2553#define IP4_RUL_V1_E_LENGTH 4 2554#define IP4_RUL_V1_E_OFFSET 0x20 2555#define IP4_RUL_V1_NR_E 96 2556 2557#define SIPV 2558#define IP4_RUL_V1_SIPV_BOFFSET 0 2559#define IP4_RUL_V1_SIPV_BLEN 32 2560#define IP4_RUL_V1_SIPV_FLAG HSL_RW 2561 2562 2563#define IP4_RUL_V2 2 2564#define IP4_RUL_V2_OFFSET 0x58008 2565#define IP4_RUL_V2_E_LENGTH 4 2566#define IP4_RUL_V2_E_OFFSET 0x20 2567#define IP4_RUL_V2_NR_E 96 2568 2569#define IP4PROTV 2570#define IP4_RUL_V2_IP4PROTV_BOFFSET 0 2571#define IP4_RUL_V2_IP4PROTV_BLEN 8 2572#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW 2573 2574#define IP4DSCPV 2575#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8 2576#define IP4_RUL_V2_IP4DSCPV_BLEN 8 2577#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW 2578 2579#define IP4DPORTV 2580#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16 2581#define IP4_RUL_V2_IP4DPORTV_BLEN 16 2582#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW 2583 2584 2585#define IP4_RUL_V3 3 2586#define IP4_RUL_V3_OFFSET 0x5800c 2587#define IP4_RUL_V3_E_LENGTH 4 2588#define IP4_RUL_V3_E_OFFSET 0x20 2589#define IP4_RUL_V3_NR_E 96 2590 2591#define IP4TCPFLAGV 2592#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET 24 2593#define IP4_RUL_V3_IP4TCPFLAGV_BLEN 6 2594#define IP4_RUL_V3_IP4TCPFLAGV_FLAG HSL_RW 2595 2596#define IP4DHCPV 2597#define IP4_RUL_V3_IP4DHCPV_BOFFSET 22 2598#define IP4_RUL_V3_IP4DHCPV_BLEN 1 2599#define IP4_RUL_V3_IP4DHCPV_FLAG HSL_RW 2600 2601#define IP4RIPV 2602#define IP4_RUL_V3_IP4RIPV_BOFFSET 21 2603#define IP4_RUL_V3_IP4RIPV_BLEN 1 2604#define IP4_RUL_V3_IP4RIPV_FLAG HSL_RW 2605 2606#define ICMP_EN 2607#define IP4_RUL_V3_ICMP_EN_BOFFSET 20 2608#define IP4_RUL_V3_ICMP_EN_BLEN 1 2609#define IP4_RUL_V3_ICMP_EN_FLAG HSL_RW 2610 2611#define IP4SPORTV 2612#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0 2613#define IP4_RUL_V3_IP4SPORTV_BLEN 16 2614#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW 2615 2616#define IP4ICMPTYPV 2617#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET 8 2618#define IP4_RUL_V3_IP4ICMPTYPV_BLEN 8 2619#define IP4_RUL_V3_IP4ICMPTYPV_FLAG HSL_RW 2620 2621#define IP4ICMPCODEV 2622#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET 0 2623#define IP4_RUL_V3_IP4ICMPCODEV_BLEN 8 2624#define IP4_RUL_V3_IP4ICMPCODEV_FLAG HSL_RW 2625 2626 2627#define IP4_RUL_V4 4 2628#define IP4_RUL_V4_OFFSET 0x58010 2629#define IP4_RUL_V4_E_LENGTH 4 2630#define IP4_RUL_V4_E_OFFSET 0x20 2631#define IP4_RUL_V4_NR_E 96 2632 2633 2634#define IP4_RUL_M0 5 2635#define IP4_RUL_M0_OFFSET 0x59000 2636#define IP4_RUL_M0_E_LENGTH 4 2637#define IP4_RUL_M0_E_OFFSET 0x20 2638#define IP4_RUL_M0_NR_E 96 2639 2640#define DIPM 2641#define IP4_RUL_M0_DIPM_BOFFSET 0 2642#define IP4_RUL_M0_DIPM_BLEN 32 2643#define IP4_RUL_M0_DIPM_FLAG HSL_RW 2644 2645 2646#define IP4_RUL_M1 6 2647#define IP4_RUL_M1_OFFSET 0x59004 2648#define IP4_RUL_M1_E_LENGTH 4 2649#define IP4_RUL_M1_E_OFFSET 0x20 2650#define IP4_RUL_M1_NR_E 96 2651 2652#define SIPM 2653#define IP4_RUL_M1_SIPM_BOFFSET 0 2654#define IP4_RUL_M1_SIPM_BLEN 32 2655#define IP4_RUL_M1_SIPM_FLAG HSL_RW 2656 2657 2658#define IP4_RUL_M2 7 2659#define IP4_RUL_M2_OFFSET 0x59008 2660#define IP4_RUL_M2_E_LENGTH 4 2661#define IP4_RUL_M2_E_OFFSET 0x20 2662#define IP4_RUL_M2_NR_E 96 2663 2664#define IP4PROTM 2665#define IP4_RUL_M2_IP4PROTM_BOFFSET 0 2666#define IP4_RUL_M2_IP4PROTM_BLEN 8 2667#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW 2668 2669#define IP4DSCPM 2670#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8 2671#define IP4_RUL_M2_IP4DSCPM_BLEN 8 2672#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW 2673 2674#define IP4DPORTM 2675#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16 2676#define IP4_RUL_M2_IP4DPORTM_BLEN 16 2677#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW 2678 2679 2680#define IP4_RUL_M3 8 2681#define IP4_RUL_M3_OFFSET 0x5900c 2682#define IP4_RUL_M3_E_LENGTH 4 2683#define IP4_RUL_M3_E_OFFSET 0x20 2684#define IP4_RUL_M3_NR_E 96 2685 2686#define IP4TCPFLAGM 2687#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET 24 2688#define IP4_RUL_M3_IP4TCPFLAGM_BLEN 6 2689#define IP4_RUL_M3_IP4TCPFLAGM_FLAG HSL_RW 2690 2691#define IP4DHCPM 2692#define IP4_RUL_M3_IP4DHCPM_BOFFSET 22 2693#define IP4_RUL_M3_IP4DHCPM_BLEN 1 2694#define IP4_RUL_M3_IP4DHCPM_FLAG HSL_RW 2695 2696#define IP4RIPM 2697#define IP4_RUL_M3_IP4RIPM_BOFFSET 21 2698#define IP4_RUL_M3_IP4RIPM_BLEN 1 2699#define IP4_RUL_M3_IP4RIPM_FLAG HSL_RW 2700 2701#define IP4DPORTM_EN 2702#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17 2703#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1 2704#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW 2705 2706#define IP4SPORTM_EN 2707#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16 2708#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1 2709#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW 2710 2711#define IP4SPORTM 2712#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0 2713#define IP4_RUL_M3_IP4SPORTM_BLEN 16 2714#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW 2715 2716#define IP4ICMPTYPM 2717#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET 8 2718#define IP4_RUL_M3_IP4ICMPTYPM_BLEN 8 2719#define IP4_RUL_M3_IP4ICMPTYPM_FLAG HSL_RW 2720 2721#define IP4ICMPCODEM 2722#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET 0 2723#define IP4_RUL_M3_IP4ICMPCODEM_BLEN 8 2724#define IP4_RUL_M3_IP4ICMPCODEM_FLAG HSL_RW 2725 2726 2727#define IP4_RUL_M4 9 2728#define IP4_RUL_M4_OFFSET 0x59010 2729#define IP4_RUL_M4_E_LENGTH 4 2730#define IP4_RUL_M4_E_OFFSET 0x20 2731#define IP4_RUL_M4_NR_E 32 2732 2733 2734 2735 2736 /* IP6 Type1 Rule Field Define */ 2737#define IP6_RUL1_V0 0 2738#define IP6_RUL1_V0_OFFSET 0x58000 2739#define IP6_RUL1_V0_E_LENGTH 4 2740#define IP6_RUL1_V0_E_OFFSET 0x20 2741#define IP6_RUL1_V0_NR_E 96 2742 2743#define IP6_DIPV0 2744#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0 2745#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32 2746#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW 2747 2748 2749#define IP6_RUL1_V1 1 2750#define IP6_RUL1_V1_OFFSET 0x58004 2751#define IP6_RUL1_V1_E_LENGTH 4 2752#define IP6_RUL1_V1_E_OFFSET 0x20 2753#define IP6_RUL1_V1_NR_E 96 2754 2755#define IP6_DIPV1 2756#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0 2757#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32 2758#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW 2759 2760 2761#define IP6_RUL1_V2 2 2762#define IP6_RUL1_V2_OFFSET 0x58008 2763#define IP6_RUL1_V2_E_LENGTH 4 2764#define IP6_RUL1_V2_E_OFFSET 0x20 2765#define IP6_RUL1_V2_NR_E 96 2766 2767#define IP6_DIPV2 2768#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0 2769#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32 2770#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW 2771 2772 2773#define IP6_RUL1_V3 3 2774#define IP6_RUL1_V3_OFFSET 0x5800c 2775#define IP6_RUL1_V3_E_LENGTH 4 2776#define IP6_RUL1_V3_E_OFFSET 0x20 2777#define IP6_RUL1_V3_NR_E 96 2778 2779#define IP6_DIPV3 2780#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0 2781#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32 2782#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW 2783 2784 2785#define IP6_RUL1_V4 4 2786#define IP6_RUL1_V4_OFFSET 0x58010 2787#define IP6_RUL1_V4_E_LENGTH 4 2788#define IP6_RUL1_V4_E_OFFSET 0x20 2789#define IP6_RUL1_V4_NR_E 96 2790 2791 2792#define IP6_RUL1_M0 5 2793#define IP6_RUL1_M0_OFFSET 0x59000 2794#define IP6_RUL1_M0_E_LENGTH 4 2795#define IP6_RUL1_M0_E_OFFSET 0x20 2796#define IP6_RUL1_M0_NR_E 96 2797 2798#define IP6_DIPM0 2799#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0 2800#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32 2801#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW 2802 2803 2804#define IP6_RUL1_M1 6 2805#define IP6_RUL1_M1_OFFSET 0x59004 2806#define IP6_RUL1_M1_E_LENGTH 4 2807#define IP6_RUL1_M1_E_OFFSET 0x20 2808#define IP6_RUL1_M1_NR_E 96 2809 2810#define IP6_DIPM1 2811#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0 2812#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32 2813#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW 2814 2815 2816#define IP6_RUL1_M2 7 2817#define IP6_RUL1_M2_OFFSET 0x59008 2818#define IP6_RUL1_M2_E_LENGTH 4 2819#define IP6_RUL1_M2_E_OFFSET 0x20 2820#define IP6_RUL1_M2_NR_E 96 2821 2822#define IP6_DIPM2 2823#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0 2824#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32 2825#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW 2826 2827 2828#define IP6_RUL1_M3 8 2829#define IP6_RUL1_M3_OFFSET 0x5900c 2830#define IP6_RUL1_M3_E_LENGTH 4 2831#define IP6_RUL1_M3_E_OFFSET 0x20 2832#define IP6_RUL1_M3_NR_E 96 2833 2834#define IP6_DIPM3 2835#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0 2836#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32 2837#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW 2838 2839 2840#define IP6_RUL1_M4 9 2841#define IP6_RUL1_M4_OFFSET 0x59010 2842#define IP6_RUL1_M4_E_LENGTH 4 2843#define IP6_RUL1_M4_E_OFFSET 0x20 2844#define IP6_RUL1_M4_NR_E 96 2845 2846 2847 2848 2849 /* IP6 Type2 Rule Field Define */ 2850#define IP6_RUL2_V0 0 2851#define IP6_RUL2_V0_OFFSET 0x58000 2852#define IP6_RUL2_V0_E_LENGTH 4 2853#define IP6_RUL2_V0_E_OFFSET 0x20 2854#define IP6_RUL2_V0_NR_E 96 2855 2856#define IP6_SIPV0 2857#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0 2858#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32 2859#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW 2860 2861 2862#define IP6_RUL2_V1 1 2863#define IP6_RUL2_V1_OFFSET 0x58004 2864#define IP6_RUL2_V1_E_LENGTH 4 2865#define IP6_RUL2_V1_E_OFFSET 0x20 2866#define IP6_RUL2_V1_NR_E 96 2867 2868#define IP6_SIPV1 2869#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0 2870#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32 2871#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW 2872 2873 2874#define IP6_RUL2_V2 2 2875#define IP6_RUL2_V2_OFFSET 0x58008 2876#define IP6_RUL2_V2_E_LENGTH 4 2877#define IP6_RUL2_V2_E_OFFSET 0x20 2878#define IP6_RUL2_V2_NR_E 96 2879 2880#define IP6_SIPV2 2881#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0 2882#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32 2883#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW 2884 2885 2886#define IP6_RUL2_V3 3 2887#define IP6_RUL2_V3_OFFSET 0x5800c 2888#define IP6_RUL2_V3_E_LENGTH 4 2889#define IP6_RUL2_V3_E_OFFSET 0x20 2890#define IP6_RUL2_V3_NR_E 96 2891 2892#define IP6_SIPV3 2893#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0 2894#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32 2895#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW 2896 2897 2898#define IP6_RUL2_V4 4 2899#define IP6_RUL2_V4_OFFSET 0x58010 2900#define IP6_RUL2_V4_E_LENGTH 4 2901#define IP6_RUL2_V4_E_OFFSET 0x20 2902#define IP6_RUL2_V4_NR_E 96 2903 2904 2905#define IP6_RUL2_M0 5 2906#define IP6_RUL2_M0_OFFSET 0x59000 2907#define IP6_RUL2_M0_E_LENGTH 4 2908#define IP6_RUL2_M0_E_OFFSET 0x20 2909#define IP6_RUL2_M0_NR_E 96 2910 2911#define IP6_SIPM0 2912#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0 2913#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32 2914#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW 2915 2916 2917#define IP6_RUL2_M1 6 2918#define IP6_RUL2_M1_OFFSET 0x59004 2919#define IP6_RUL2_M1_E_LENGTH 4 2920#define IP6_RUL2_M1_E_OFFSET 0x20 2921#define IP6_RUL2_M1_NR_E 96 2922 2923#define IP6_SIPM1 2924#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0 2925#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32 2926#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW 2927 2928 2929#define IP6_RUL2_M2 7 2930#define IP6_RUL2_M2_OFFSET 0x59008 2931#define IP6_RUL2_M2_E_LENGTH 4 2932#define IP6_RUL2_M2_E_OFFSET 0x20 2933#define IP6_RUL2_M2_NR_E 96 2934 2935#define IP6_SIPM2 2936#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0 2937#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32 2938#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW 2939 2940 2941#define IP6_RUL2_M3 8 2942#define IP6_RUL2_M3_OFFSET 0x5900c 2943#define IP6_RUL2_M3_E_LENGTH 4 2944#define IP6_RUL2_M3_E_OFFSET 0x20 2945#define IP6_RUL2_M3_NR_E 96 2946 2947#define IP6_SIPM3 2948#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0 2949#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32 2950#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW 2951 2952 2953#define IP6_RUL2_M4 9 2954#define IP6_RUL2_M4_OFFSET 0x59010 2955#define IP6_RUL2_M4_E_LENGTH 4 2956#define IP6_RUL2_M4_E_OFFSET 0x20 2957#define IP6_RUL2_M4_NR_E 96 2958 2959 2960 2961 2962 /* IP6 Type3 Rule Field Define */ 2963#define IP6_RUL3_V0 0 2964#define IP6_RUL3_V0_OFFSET 0x58000 2965#define IP6_RUL3_V0_E_LENGTH 4 2966#define IP6_RUL3_V0_E_OFFSET 0x20 2967#define IP6_RUL3_V0_NR_E 96 2968 2969#define IP6PROTV 2970#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0 2971#define IP6_RUL3_V0_IP6PROTV_BLEN 8 2972#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW 2973 2974#define IP6DSCPV 2975#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8 2976#define IP6_RUL3_V0_IP6DSCPV_BLEN 8 2977#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW 2978 2979 2980#define IP6_RUL3_V1 1 2981#define IP6_RUL3_V1_OFFSET 0x58004 2982#define IP6_RUL3_V1_E_LENGTH 4 2983#define IP6_RUL3_V1_E_OFFSET 0x20 2984#define IP6_RUL3_V1_NR_E 96 2985 2986#define IP6LABEL1V 2987#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16 2988#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16 2989#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW 2990 2991 2992#define IP6_RUL3_V2 2 2993#define IP6_RUL3_V2_OFFSET 0x58008 2994#define IP6_RUL3_V2_E_LENGTH 4 2995#define IP6_RUL3_V2_E_OFFSET 0x20 2996#define IP6_RUL3_V2_NR_E 96 2997 2998#define IP6LABEL2V 2999#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0 3000#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4 3001#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW 3002 3003#define IP6DPORTV 3004#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16 3005#define IP6_RUL3_V2_IP6DPORTV_BLEN 16 3006#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW 3007 3008 3009#define IP6_RUL3_V3 3 3010#define IP6_RUL3_V3_OFFSET 0x5800c 3011#define IP6_RUL3_V3_E_LENGTH 4 3012#define IP6_RUL3_V3_E_OFFSET 0x20 3013#define IP6_RUL3_V3_NR_E 96 3014 3015#define IP6TCPFLAGV 3016#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET 24 3017#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN 6 3018#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG HSL_RW 3019 3020#define IP6FWDTYPV 3021#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET 23 3022#define IP6_RUL3_V3_IP6FWDTYPV_BLEN 1 3023#define IP6_RUL3_V3_IP6FWDTYPV_FLAG HSL_RW 3024 3025#define IP6DHCPV 3026#define IP6_RUL3_V3_IP6DHCPV_BOFFSET 22 3027#define IP6_RUL3_V3_IP6DHCPV_BLEN 1 3028#define IP6_RUL3_V3_IP6DHCPV_FLAG HSL_RW 3029 3030#define ICMP6_EN 3031#define IP6_RUL3_V3_ICMP6_EN_BOFFSET 20 3032#define IP6_RUL3_V3_ICMP6_EN_BLEN 1 3033#define IP6_RUL3_V3_ICMP6_EN_FLAG HSL_RW 3034 3035#define IP6SPORTV 3036#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0 3037#define IP6_RUL3_V3_IP6SPORTV_BLEN 16 3038#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW 3039 3040#define IP6ICMPTYPV 3041#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET 8 3042#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN 8 3043#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG HSL_RW 3044 3045#define IP6ICMPCODEV 3046#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET 0 3047#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN 8 3048#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG HSL_RW 3049 3050 3051#define IP6_RUL3_V4 4 3052#define IP6_RUL3_V4_OFFSET 0x58010 3053#define IP6_RUL3_V4_E_LENGTH 4 3054#define IP6_RUL3_V4_E_OFFSET 0x20 3055#define IP6_RUL3_V4_NR_E 96 3056 3057 3058#define IP6_RUL3_M0 5 3059#define IP6_RUL3_M0_OFFSET 0x59000 3060#define IP6_RUL3_M0_E_LENGTH 4 3061#define IP6_RUL3_M0_E_OFFSET 0x20 3062#define IP6_RUL3_M0_NR_E 96 3063 3064#define IP6PROTM 3065#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0 3066#define IP6_RUL3_M0_IP6PROTM_BLEN 8 3067#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW 3068 3069#define IP6DSCPM 3070#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8 3071#define IP6_RUL3_M0_IP6DSCPM_BLEN 8 3072#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW 3073 3074 3075#define IP6_RUL3_M1 6 3076#define IP6_RUL3_M1_OFFSET 0x59004 3077#define IP6_RUL3_M1_E_LENGTH 4 3078#define IP6_RUL3_M1_E_OFFSET 0x20 3079#define IP6_RUL3_M1_NR_E 96 3080 3081#define IP6LABEL1M 3082#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16 3083#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16 3084#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW 3085 3086 3087#define IP6_RUL3_M2 7 3088#define IP6_RUL3_M2_OFFSET 0x59008 3089#define IP6_RUL3_M2_E_LENGTH 4 3090#define IP6_RUL3_M2_E_OFFSET 0x20 3091#define IP6_RUL3_M2_NR_E 96 3092 3093#define IP6LABEL2M 3094#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0 3095#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4 3096#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW 3097 3098#define IP6DPORTM 3099#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16 3100#define IP6_RUL3_M2_IP6DPORTM_BLEN 16 3101#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW 3102 3103 3104#define IP6_RUL3_M3 8 3105#define IP6_RUL3_M3_OFFSET 0x5900c 3106#define IP6_RUL3_M3_E_LENGTH 4 3107#define IP6_RUL3_M3_E_OFFSET 0x20 3108#define IP6_RUL3_M3_NR_E 96 3109 3110#define IP6TCPFLAGM 3111#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET 24 3112#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN 6 3113#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG HSL_RW 3114 3115#define IP6RWDTYPM 3116#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET 23 3117#define IP6_RUL3_M3_IP6RWDTYPV_BLEN 1 3118#define IP6_RUL3_M3_IP6RWDTYPV_FLAG HSL_RW 3119 3120#define IP6DHCPM 3121#define IP6_RUL3_M3_IP6DHCPM_BOFFSET 22 3122#define IP6_RUL3_M3_IP6DHCPM_BLEN 1 3123#define IP6_RUL3_M3_IP6DHCPM_FLAG HSL_RW 3124 3125#define IP6DPORTM_EN 3126#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17 3127#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1 3128#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW 3129 3130#define IP6SPORTM_EN 3131#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16 3132#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1 3133#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW 3134 3135#define IP6SPORTM 3136#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0 3137#define IP6_RUL3_M3_IP6SPORTM_BLEN 16 3138#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW 3139 3140#define IP6ICMPTYPM 3141#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET 8 3142#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN 8 3143#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG HSL_RW 3144 3145#define IP6ICMPCODEM 3146#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET 0 3147#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN 8 3148#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG HSL_RW 3149 3150 3151#define IP6_RUL3_M4 9 3152#define IP6_RUL3_M4_OFFSET 0x59010 3153#define IP6_RUL3_M4_E_LENGTH 4 3154#define IP6_RUL3_M4_E_OFFSET 0x20 3155#define IP6_RUL3_M4_NR_E 96 3156 3157 3158 3159 3160 /* Enhanced MAC Type Rule Field Define */ 3161#define EHMAC_RUL_V0 0 3162#define EHMAC_RUL_V0_OFFSET 0x58000 3163#define EHMAC_RUL_V0_E_LENGTH 4 3164#define EHMAC_RUL_V0_E_OFFSET 0x20 3165#define EHMAC_RUL_V0_NR_E 96 3166 3167#define DAV_BYTE2 3168#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET 24 3169#define EHMAC_RUL_V0_DAV_BYTE2_BLEN 8 3170#define EHMAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW 3171 3172#define DAV_BYTE3 3173#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET 16 3174#define EHMAC_RUL_V0_DAV_BYTE3_BLEN 8 3175#define EHMAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW 3176 3177#define DAV_BYTE4 3178#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET 8 3179#define EHMAC_RUL_V0_DAV_BYTE4_BLEN 8 3180#define EHMAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW 3181 3182#define DAV_BYTE5 3183#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET 0 3184#define EHMAC_RUL_V0_DAV_BYTE5_BLEN 8 3185#define EHMAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW 3186 3187 3188#define EHMAC_RUL_V1 1 3189#define EHMAC_RUL_V1_OFFSET 0x58004 3190#define EHMAC_RUL_V1_E_LENGTH 4 3191#define EHMAC_RUL_V1_E_OFFSET 0x20 3192#define EHMAC_RUL_V1_NR_E 96 3193 3194#define SAV_BYTE4 3195#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET 24 3196#define EHMAC_RUL_V1_SAV_BYTE4_BLEN 8 3197#define EHMAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW 3198 3199#define SAV_BYTE5 3200#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET 16 3201#define EHMAC_RUL_V1_SAV_BYTE5_BLEN 8 3202#define EHMAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW 3203 3204#define DAV_BYTE0 3205#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET 8 3206#define EHMAC_RUL_V1_DAV_BYTE0_BLEN 8 3207#define EHMAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW 3208 3209#define DAV_BYTE1 3210#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET 0 3211#define EHMAC_RUL_V1_DAV_BYTE1_BLEN 8 3212#define EHMAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW 3213 3214 3215#define EHMAC_RUL_V2 2 3216#define EHMAC_RUL_V2_OFFSET 0x58008 3217#define EHMAC_RUL_V2_E_LENGTH 4 3218#define EHMAC_RUL_V2_E_OFFSET 0x20 3219#define EHMAC_RUL_V2_NR_E 96 3220 3221#define CTAG_VIDLV 3222#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET 24 3223#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN 8 3224#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG HSL_RW 3225 3226#define STAG_PRIV 3227#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET 21 3228#define EHMAC_RUL_V2_STAG_PRIV_BLEN 3 3229#define EHMAC_RUL_V2_STAG_PRIV_FLAG HSL_RW 3230 3231#define STAG_DEIV 3232#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET 20 3233#define EHMAC_RUL_V2_STAG_DEIV_BLEN 1 3234#define EHMAC_RUL_V2_STAG_DEIV_FLAG HSL_RW 3235 3236#define STAG_VIDV 3237#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET 8 3238#define EHMAC_RUL_V2_STAG_VIDV_BLEN 12 3239#define EHMAC_RUL_V2_STAG_VIDV_FLAG HSL_RW 3240 3241#define SAV_BYTE3 3242#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET 0 3243#define EHMAC_RUL_V2_SAV_BYTE3_BLEN 8 3244#define EHMAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW 3245 3246 3247#define EHMAC_RUL_V3 3 3248#define EHMAC_RUL_V3_ID 13 3249#define EHMAC_RUL_V3_OFFSET 0x5800c 3250#define EHMAC_RUL_V3_E_LENGTH 4 3251#define EHMAC_RUL_V3_E_OFFSET 0x20 3252#define EHMAC_RUL_V3_NR_E 96 3253 3254#define STAGGEDM 3255#define EHMAC_RUL_V3_STAGGEDM_BOFFSET 31 3256#define EHMAC_RUL_V3_STAGGEDM_BLEN 1 3257#define EHMAC_RUL_V3_STAGGEDM_FLAG HSL_RW 3258 3259#define STAGGEDV 3260#define EHMAC_RUL_V3_STAGGEDV_BOFFSET 30 3261#define EHMAC_RUL_V3_STAGGEDV_BLEN 1 3262#define EHMAC_RUL_V3_STAGGEDV_FLAG HSL_RW 3263 3264#define DA_EN 3265#define EHMAC_RUL_V3_DA_EN_BOFFSET 25 3266#define EHMAC_RUL_V3_DA_EN_BLEN 1 3267#define EHMAC_RUL_V3_DA_EN_FLAG HSL_RW 3268 3269#define SVIDMSK 3270#define EHMAC_RUL_V3_SVIDMSK_BOFFSET 24 3271#define EHMAC_RUL_V3_SVIDMSK_BLEN 1 3272#define EHMAC_RUL_V3_SVIDMSK_FLAG HSL_RW 3273 3274#define ETHTYPV 3275#define EHMAC_RUL_V3_ETHTYPV_BOFFSET 8 3276#define EHMAC_RUL_V3_ETHTYPV_BLEN 16 3277#define EHMAC_RUL_V3_ETHTYPV_FLAG HSL_RW 3278 3279#define CTAG_PRIV 3280#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET 5 3281#define EHMAC_RUL_V3_CTAG_PRIV_BLEN 3 3282#define EHMAC_RUL_V3_CTAG_PRIV_FLAG HSL_RW 3283 3284#define CTAG_CFIV 3285#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET 4 3286#define EHMAC_RUL_V3_CTAG_CFIV_BLEN 1 3287#define EHMAC_RUL_V3_CTAG_CFIV_FLAG HSL_RW 3288 3289#define CTAG_VIDHV 3290#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET 0 3291#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN 4 3292#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG HSL_RW 3293 3294 3295#define EHMAC_RUL_V4 4 3296#define EHMAC_RUL_V4_OFFSET 0x58010 3297#define EHMAC_RUL_V4_E_LENGTH 4 3298#define EHMAC_RUL_V4_E_OFFSET 0x20 3299#define EHMAC_RUL_V4_NR_E 96 3300 3301 3302#define EHMAC_RUL_M0 5 3303#define EHMAC_RUL_M0_OFFSET 0x59000 3304#define EHMAC_RUL_M0_E_LENGTH 4 3305#define EHMAC_RUL_M0_E_OFFSET 0x20 3306#define EHMAC_RUL_M0_NR_E 96 3307 3308#define DAM_BYTE2 3309#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET 24 3310#define EHMAC_RUL_M0_DAM_BYTE2_BLEN 8 3311#define EHMAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW 3312 3313#define DAM_BYTE3 3314#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET 16 3315#define EHMAC_RUL_M0_DAM_BYTE3_BLEN 8 3316#define EHMAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW 3317 3318#define DAM_BYTE4 3319#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET 8 3320#define EHMAC_RUL_M0_DAM_BYTE4_BLEN 8 3321#define EHMAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW 3322 3323#define DAM_BYTE5 3324#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET 0 3325#define EHMAC_RUL_M0_DAM_BYTE5_BLEN 8 3326#define EHMAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW 3327 3328 3329#define EHMAC_RUL_M1 6 3330#define EHMAC_RUL_M1_OFFSET 0x59004 3331#define EHMAC_RUL_M1_E_LENGTH 4 3332#define EHMAC_RUL_M1_E_OFFSET 0x20 3333#define EHMAC_RUL_M1_NR_E 96 3334 3335#define SAM_BYTE4 3336#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET 24 3337#define EHMAC_RUL_M1_SAM_BYTE4_BLEN 8 3338#define EHMAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW 3339 3340#define SAM_BYTE5 3341#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET 16 3342#define EHMAC_RUL_M1_SAM_BYTE5_BLEN 8 3343#define EHMAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW 3344 3345#define DAM_BYTE0 3346#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET 8 3347#define EHMAC_RUL_M1_DAM_BYTE0_BLEN 8 3348#define EHMAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW 3349 3350#define DAM_BYTE1 3351#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET 0 3352#define EHMAC_RUL_M1_DAM_BYTE1_BLEN 8 3353#define EHMAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW 3354 3355 3356#define EHMAC_RUL_M2 7 3357#define EHMAC_RUL_M2_OFFSET 0x59008 3358#define EHMAC_RUL_M2_E_LENGTH 4 3359#define EHMAC_RUL_M2_E_OFFSET 0x20 3360#define EHMAC_RUL_M2_NR_E 96 3361 3362#define CTAG_VIDLM 3363#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET 24 3364#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN 8 3365#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG HSL_RW 3366 3367#define STAG_PRIM 3368#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET 21 3369#define EHMAC_RUL_M2_STAG_PRIM_BLEN 3 3370#define EHMAC_RUL_M2_STAG_PRIM_FLAG HSL_RW 3371 3372#define STAG_DEIM 3373#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET 20 3374#define EHMAC_RUL_M2_STAG_DEIM_BLEN 1 3375#define EHMAC_RUL_M2_STAG_DEIM_FLAG HSL_RW 3376 3377#define STAG_VIDM 3378#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET 8 3379#define EHMAC_RUL_M2_STAG_VIDM_BLEN 12 3380#define EHMAC_RUL_M2_STAG_VIDM_FLAG HSL_RW 3381 3382#define SAM_BYTE3 3383#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET 0 3384#define EHMAC_RUL_M2_SAM_BYTE3_BLEN 8 3385#define EHMAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW 3386 3387 3388#define EHMAC_RUL_M3 8 3389#define EHMAC_RUL_M3_OFFSET 0x5900c 3390#define EHMAC_RUL_M3_E_LENGTH 4 3391#define EHMAC_RUL_M3_E_OFFSET 0x20 3392#define EHMAC_RUL_M3_NR_E 96 3393 3394#define ETHTYPM 3395#define EHMAC_RUL_M3_ETHTYPM_BOFFSET 8 3396#define EHMAC_RUL_M3_ETHTYPM_BLEN 16 3397#define EHMAC_RUL_M3_ETHTYPM_FLAG HSL_RW 3398 3399#define CTAG_PRIM 3400#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET 5 3401#define EHMAC_RUL_M3_CTAG_PRIM_BLEN 3 3402#define EHMAC_RUL_M3_CTAG_PRIM_FLAG HSL_RW 3403 3404#define CTAG_CFIM 3405#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET 4 3406#define EHMAC_RUL_M3_CTAG_CFIM_BLEN 1 3407#define EHMAC_RUL_M3_CTAG_CFIM_FLAG HSL_RW 3408 3409#define CTAG_VIDHM 3410#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET 0 3411#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN 4 3412#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG HSL_RW 3413 3414 3415#define EHMAC_RUL_M4 9 3416#define EHMAC_RUL_M4_OFFSET 0x59010 3417#define EHMAC_RUL_M4_E_LENGTH 4 3418#define EHMAC_RUL_M4_E_OFFSET 0x20 3419#define EHMAC_RUL_M4_NR_E 96 3420 3421#define CTAGGEDM 3422#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET 5 3423#define EHMAC_RUL_M4_CTAGGEDM_BLEN 1 3424#define EHMAC_RUL_M4_CTAGGEDM_FLAG HSL_RW 3425 3426#define CTAGGEDV 3427#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET 4 3428#define EHMAC_RUL_M4_CTAGGEDV_BLEN 1 3429#define EHMAC_RUL_M4_CTAGGEDV_FLAG HSL_RW 3430 3431#define CVIDMSK 3432#define EHMAC_RUL_M4_CVIDMSK_BOFFSET 3 3433#define EHMAC_RUL_M4_CVIDMSK_BLEN 1 3434#define EHMAC_RUL_M4_CVIDMSK_FLAG HSL_RW 3435 3436 3437 3438 3439 /* PPPoE Session Table Define */ 3440#define PPPOE_SESSION 3441#define PPPOE_SESSION_OFFSET 0x5f000 3442#define PPPOE_SESSION_E_LENGTH 4 3443#define PPPOE_SESSION_E_OFFSET 0x4 3444#define PPPOE_SESSION_NR_E 16 3445 3446#define VRF_ID 3447#define PPPOE_SESSION_VRF_ID_BOFFSET 18 3448#define PPPOE_SESSION_VRF_ID_BLEN 3 3449#define PPPOE_SESSION_VRF_ID_FLAG HSL_RW 3450 3451#define ENTRY_VALID 3452#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 16 3453#define PPPOE_SESSION_ENTRY_VALID_BLEN 2 3454#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW 3455 3456#define SEESION_ID 3457#define PPPOE_SESSION_SEESION_ID_BOFFSET 0 3458#define PPPOE_SESSION_SEESION_ID_BLEN 16 3459#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW 3460 3461 3462 3463#define PPPOE_EDIT 3464#define PPPOE_EDIT_OFFSET 0x02200 3465#define PPPOE_EDIT_E_LENGTH 4 3466#define PPPOE_EDIT_E_OFFSET 0x10 3467#define PPPOE_EDIT_NR_E 16 3468 3469#define EDIT_ID 3470#define PPPOE_EDIT_EDIT_ID_BOFFSET 0 3471#define PPPOE_EDIT_EDIT_ID_BLEN 16 3472#define PPPOE_EDIT_EDIT_ID_FLAG HSL_RW 3473 3474 3475 3476 3477 /* L3 Host Entry Define */ 3478#define HOST_ENTRY0 3479#define HOST_ENTRY0_OFFSET 0x0e80 3480#define HOST_ENTRY0_E_LENGTH 4 3481#define HOST_ENTRY0_E_OFFSET 0x0 3482#define HOST_ENTRY0_NR_E 1 3483 3484#define IP_ADDR 3485#define HOST_ENTRY0_IP_ADDR_BOFFSET 0 3486#define HOST_ENTRY0_IP_ADDR_BLEN 32 3487#define HOST_ENTRY0_IP_ADDR_FLAG HSL_RW 3488 3489 3490#define HOST_ENTRY1 3491#define HOST_ENTRY1_OFFSET 0x0e84 3492#define HOST_ENTRY1_E_LENGTH 4 3493#define HOST_ENTRY1_E_OFFSET 0x0 3494#define HOST_ENTRY1_NR_E 1 3495 3496 3497#define HOST_ENTRY2 3498#define HOST_ENTRY2_OFFSET 0x0e88 3499#define HOST_ENTRY2_E_LENGTH 4 3500#define HOST_ENTRY2_E_OFFSET 0x0 3501#define HOST_ENTRY2_NR_E 1 3502 3503 3504#define HOST_ENTRY3 3505#define HOST_ENTRY3_OFFSET 0x0e8c 3506#define HOST_ENTRY3_E_LENGTH 4 3507#define HOST_ENTRY3_E_OFFSET 0x0 3508#define HOST_ENTRY3_NR_E 1 3509 3510 3511#define HOST_ENTRY4 3512#define HOST_ENTRY4_OFFSET 0x0e90 3513#define HOST_ENTRY4_E_LENGTH 4 3514#define HOST_ENTRY4_E_OFFSET 0x0 3515#define HOST_ENTRY4_NR_E 1 3516 3517#define MAC_ADDR2 3518#define HOST_ENTRY4_MAC_ADDR2_BOFFSET 24 3519#define HOST_ENTRY4_MAC_ADDR2_BLEN 8 3520#define HOST_ENTRY4_MAC_ADDR2_FLAG HSL_RW 3521 3522#define MAC_ADDR3 3523#define HOST_ENTRY4_MAC_ADDR3_BOFFSET 16 3524#define HOST_ENTRY4_MAC_ADDR3_BLEN 8 3525#define HOST_ENTRY4_MAC_ADDR3_FLAG HSL_RW 3526 3527#define MAC_ADDR4 3528#define HOST_ENTRY4_MAC_ADDR4_BOFFSET 8 3529#define HOST_ENTRY4_MAC_ADDR4_BLEN 8 3530#define HOST_ENTRY4_MAC_ADDR4_FLAG HSL_RW 3531 3532#define MAC_ADDR5 3533#define HOST_ENTRY4_MAC_ADDR5_BOFFSET 0 3534#define HOST_ENTRY4_MAC_ADDR5_BLEN 8 3535#define HOST_ENTRY4_MAC_ADDR5_FLAG HSL_RW 3536 3537#define HOST_ENTRY5 3538#define HOST_ENTRY5_OFFSET 0x0e94 3539#define HOST_ENTRY5_E_LENGTH 4 3540#define HOST_ENTRY5_E_OFFSET 0x0 3541#define HOST_ENTRY5_NR_E 1 3542 3543#define CPU_ADDR 3544#define HOST_ENTRY5_CPU_ADDR_BOFFSET 31 3545#define HOST_ENTRY5_CPU_ADDR_BLEN 1 3546#define HOST_ENTRY5_CPU_ADDR_FLAG HSL_RW 3547 3548#define SRC_PORT 3549#define HOST_ENTRY5_SRC_PORT_BOFFSET 28 3550#define HOST_ENTRY5_SRC_PORT_BLEN 3 3551#define HOST_ENTRY5_SRC_PORT_FLAG HSL_RW 3552 3553#define INTF_ID 3554#define HOST_ENTRY5_INTF_ID_BOFFSET 16 3555#define HOST_ENTRY5_INTF_ID_BLEN 12 3556#define HOST_ENTRY5_INTF_ID_FLAG HSL_RW 3557 3558#define MAC_ADDR0 3559#define HOST_ENTRY5_MAC_ADDR0_BOFFSET 8 3560#define HOST_ENTRY5_MAC_ADDR0_BLEN 8 3561#define HOST_ENTRY5_MAC_ADDR0_FLAG HSL_RW 3562 3563#define MAC_ADDR1 3564#define HOST_ENTRY5_MAC_ADDR1_BOFFSET 0 3565#define HOST_ENTRY5_MAC_ADDR1_BLEN 8 3566#define HOST_ENTRY5_MAC_ADDR1_FLAG HSL_RW 3567 3568 3569#define HOST_ENTRY6 3570#define HOST_ENTRY6_OFFSET 0x0e98 3571#define HOST_ENTRY6_E_LENGTH 4 3572#define HOST_ENTRY6_E_OFFSET 0x0 3573#define HOST_ENTRY6_NR_E 1 3574 3575#define LB_BIT 3576#define HOST_ENTRY6_LB_BIT_BOFFSET 19 3577#define HOST_ENTRY6_LB_BIT_BLEN 3 3578#define HOST_ENTRY6_LB_BIT_FLAG HSL_RW 3579 3580#define VRF_ID 3581#define HOST_ENTRY6_VRF_ID_BOFFSET 16 3582#define HOST_ENTRY6_VRF_ID_BLEN 3 3583#define HOST_ENTRY6_VRF_ID_FLAG HSL_RW 3584 3585#define IP_VER 3586#define HOST_ENTRY6_IP_VER_BOFFSET 15 3587#define HOST_ENTRY6_IP_VER_BLEN 1 3588#define HOST_ENTRY6_IP_VER_FLAG HSL_RW 3589 3590#define AGE_FLAG 3591#define HOST_ENTRY6_AGE_FLAG_BOFFSET 12 3592#define HOST_ENTRY6_AGE_FLAG_BLEN 3 3593#define HOST_ENTRY6_AGE_FLAG_FLAG HSL_RW 3594 3595#define PPPOE_EN 3596#define HOST_ENTRY6_PPPOE_EN_BOFFSET 11 3597#define HOST_ENTRY6_PPPOE_EN_BLEN 1 3598#define HOST_ENTRY6_PPPOE_EN_FLAG HSL_RW 3599 3600#define PPPOE_IDX 3601#define HOST_ENTRY6_PPPOE_IDX_BOFFSET 7 3602#define HOST_ENTRY6_PPPOE_IDX_BLEN 4 3603#define HOST_ENTRY6_PPPOE_IDX_FLAG HSL_RW 3604 3605#define CNT_EN 3606#define HOST_ENTRY6_CNT_EN_BOFFSET 6 3607#define HOST_ENTRY6_CNT_EN_BLEN 1 3608#define HOST_ENTRY6_CNT_EN_FLAG HSL_RW 3609 3610#define CNT_IDX 3611#define HOST_ENTRY6_CNT_IDX_BOFFSET 2 3612#define HOST_ENTRY6_CNT_IDX_BLEN 4 3613#define HOST_ENTRY6_CNT_IDX_FLAG HSL_RW 3614 3615#define ACTION 3616#define HOST_ENTRY6_ACTION_BOFFSET 0 3617#define HOST_ENTRY6_ACTION_BLEN 2 3618#define HOST_ENTRY6_ACTION_FLAG HSL_RW 3619 3620 3621#define HOST_ENTRY7 3622#define HOST_ENTRY7_OFFSET 0x0e58 3623#define HOST_ENTRY7_E_LENGTH 4 3624#define HOST_ENTRY7_E_OFFSET 0x0 3625#define HOST_ENTRY7_NR_E 1 3626 3627#define TBL_BUSY 3628#define HOST_ENTRY7_TBL_BUSY_BOFFSET 31 3629#define HOST_ENTRY7_TBL_BUSY_BLEN 1 3630#define HOST_ENTRY7_TBL_BUSY_FLAG HSL_RW 3631 3632#define SPEC_SYNC 3633#define HOST_ENTRY7_SPEC_SYNC_BOFFSET 23 3634#define HOST_ENTRY7_SPEC_SYNC_BLEN 1 3635#define HOST_ENTRY7_SPEC_SYNC_FLAG HSL_RW 3636 3637#define SPEC_SP 3638#define HOST_ENTRY7_SPEC_SP_BOFFSET 22 3639#define HOST_ENTRY7_SPEC_SP_BLEN 1 3640#define HOST_ENTRY7_SPEC_SP_FLAG HSL_RW 3641 3642#define SPEC_VID 3643#define HOST_ENTRY7_SPEC_VID_BOFFSET 21 3644#define HOST_ENTRY7_SPEC_VID_BLEN 1 3645#define HOST_ENTRY7_SPEC_VID_FLAG HSL_RW 3646 3647#define SPEC_PIP 3648#define HOST_ENTRY7_SPEC_PIP_BOFFSET 20 3649#define HOST_ENTRY7_SPEC_PIP_BLEN 1 3650#define HOST_ENTRY7_SPEC_PIP_FLAG HSL_RW 3651 3652#define SPEC_SIP 3653#define HOST_ENTRY7_SPEC_SIP_BOFFSET 19 3654#define HOST_ENTRY7_SPEC_SIP_BLEN 1 3655#define HOST_ENTRY7_SPEC_SIP_FLAG HSL_RW 3656 3657#define SPEC_STATUS 3658#define HOST_ENTRY7_SPEC_STATUS_BOFFSET 18 3659#define HOST_ENTRY7_SPEC_STATUS_BLEN 1 3660#define HOST_ENTRY7_SPEC_STATUS_FLAG HSL_RW 3661 3662#define TBL_IDX 3663#define HOST_ENTRY7_TBL_IDX_BOFFSET 8 3664#define HOST_ENTRY7_TBL_IDX_BLEN 10 3665#define HOST_ENTRY7_TBL_IDX_FLAG HSL_RW 3666 3667#define TBL_STAUS 3668#define HOST_ENTRY7_TBL_STAUS_BOFFSET 7 3669#define HOST_ENTRY7_TBL_STAUS_BLEN 1 3670#define HOST_ENTRY7_TBL_STAUS_FLAG HSL_RW 3671 3672#define TBL_SEL 3673#define HOST_ENTRY7_TBL_SEL_BOFFSET 4 3674#define HOST_ENTRY7_TBL_SEL_BLEN 2 3675#define HOST_ENTRY7_TBL_SEL_FLAG HSL_RW 3676 3677#define ENTRY_FUNC 3678#define HOST_ENTRY7_ENTRY_FUNC_BOFFSET 0 3679#define HOST_ENTRY7_ENTRY_FUNC_BLEN 3 3680#define HOST_ENTRY7_ENTRY_FUNC_FLAG HSL_RW 3681 3682 3683 3684 3685#define NAT_ENTRY0 3686#define NAT_ENTRY0_OFFSET 0x0e80 3687#define NAT_ENTRY0_E_LENGTH 4 3688#define NAT_ENTRY0_E_OFFSET 0x0 3689#define NAT_ENTRY0_NR_E 1 3690 3691#define IP_ADDR 3692#define NAT_ENTRY0_IP_ADDR_BOFFSET 0 3693#define NAT_ENTRY0_IP_ADDR_BLEN 32 3694#define NAT_ENTRY0_IP_ADDR_FLAG HSL_RW 3695 3696 3697#define NAT_ENTRY1 3698#define NAT_ENTRY1_OFFSET 0x0e84 3699#define NAT_ENTRY1_E_LENGTH 4 3700#define NAT_ENTRY1_E_OFFSET 0x0 3701#define NAT_ENTRY1_NR_E 1 3702 3703#define PRV_IPADDR0 3704#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET 24 3705#define NAT_ENTRY1_PRV_IPADDR0_BLEN 8 3706#define NAT_ENTRY1_PRV_IPADDR0_FLAG HSL_RW 3707 3708#define PORT_RANGE 3709#define NAT_ENTRY1_PORT_RANGE_BOFFSET 16 3710#define NAT_ENTRY1_PORT_RANGE_BLEN 8 3711#define NAT_ENTRY1_PORT_RANGE_FLAG HSL_RW 3712 3713#define PORT_NUM 3714#define NAT_ENTRY1_PORT_NUM_BOFFSET 0 3715#define NAT_ENTRY1_PORT_NUM_BLEN 16 3716#define NAT_ENTRY1_PORT_NUM_FLAG HSL_RW 3717 3718 3719#define NAT_ENTRY2 3720#define NAT_ENTRY2_OFFSET 0x0e88 3721#define NAT_ENTRY2_E_LENGTH 4 3722#define NAT_ENTRY2_E_OFFSET 0x0 3723#define NAT_ENTRY2_NR_E 1 3724 3725#define HASH_KEY 3726#define NAT_ENTRY2_HASH_KEY_BOFFSET 30 3727#define NAT_ENTRY2_HASH_KEY_BLEN 2 3728#define NAT_ENTRY2_HASH_KEY_FLAG HSL_RW 3729 3730#define ACTION 3731#define NAT_ENTRY2_ACTION_BOFFSET 28 3732#define NAT_ENTRY2_ACTION_BLEN 2 3733#define NAT_ENTRY2_ACTION_FLAG HSL_RW 3734 3735#define CNT_EN 3736#define NAT_ENTRY2_CNT_EN_BOFFSET 27 3737#define NAT_ENTRY2_CNT_EN_BLEN 1 3738#define NAT_ENTRY2_CNT_EN_FLAG HSL_RW 3739 3740#define CNT_IDX 3741#define NAT_ENTRY2_CNT_IDX_BOFFSET 24 3742#define NAT_ENTRY2_CNT_IDX_BLEN 3 3743#define NAT_ENTRY2_CNT_IDX_FLAG HSL_RW 3744 3745#define PRV_IPADDR1 3746#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET 0 3747#define NAT_ENTRY2_PRV_IPADDR1_BLEN 24 3748#define NAT_ENTRY2_PRV_IPADDR1_FLAG HSL_RW 3749 3750 3751#define NAT_ENTRY3 3752#define NAT_ENTRY3_OFFSET 0x0e8c 3753#define NAT_ENTRY3_E_LENGTH 4 3754#define NAT_ENTRY3_E_OFFSET 0x0 3755#define NAT_ENTRY3_NR_E 1 3756 3757#define VRF_ID 3758#define NAT_ENTRY3_VRF_ID_BOFFSET 4 3759#define NAT_ENTRY3_VRF_ID_BLEN 3 3760#define NAT_ENTRY3_VRF_ID_FLAG HSL_RW 3761 3762#define ENTRY_VALID 3763#define NAT_ENTRY3_ENTRY_VALID_BOFFSET 3 3764#define NAT_ENTRY3_ENTRY_VALID_BLEN 1 3765#define NAT_ENTRY3_ENTRY_VALID_FLAG HSL_RW 3766 3767#define PORT_EN 3768#define NAT_ENTRY3_PORT_EN_BOFFSET 2 3769#define NAT_ENTRY3_PORT_EN_BLEN 1 3770#define NAT_ENTRY3_PORT_EN_FLAG HSL_RW 3771 3772#define PRO_TYP 3773#define NAT_ENTRY3_PRO_TYP_BOFFSET 0 3774#define NAT_ENTRY3_PRO_TYP_BLEN 2 3775#define NAT_ENTRY3_PRO_TYP_FLAG HSL_RW 3776 3777 3778#define NAPT_ENTRY0 3779#define NAPT_ENTRY0_OFFSET 0x0e80 3780#define NAPT_ENTRY0_E_LENGTH 4 3781#define NAPT_ENTRY0_E_OFFSET 0x0 3782#define NAPT_ENTRY0_NR_E 1 3783 3784#define DST_IPADDR 3785#define NAPT_ENTRY0_DST_IPADDR_BOFFSET 0 3786#define NAPT_ENTRY0_DST_IPADDR_BLEN 32 3787#define NAPT_ENTRY0_DST_IPADDR_FLAG HSL_RW 3788 3789 3790#define NAPT_ENTRY1 3791#define NAPT_ENTRY1_OFFSET 0x0e84 3792#define NAPT_ENTRY1_E_LENGTH 4 3793#define NAPT_ENTRY1_E_OFFSET 0x0 3794#define NAPT_ENTRY1_NR_E 1 3795 3796#define SRC_PORT 3797#define NAPT_ENTRY1_SRC_PORT_BOFFSET 16 3798#define NAPT_ENTRY1_SRC_PORT_BLEN 16 3799#define NAPT_ENTRY1_SRC_PORT_FLAG HSL_RW 3800 3801#define DST_PORT 3802#define NAPT_ENTRY1_DST_PORT_BOFFSET 0 3803#define NAPT_ENTRY1_DST_PORT_BLEN 16 3804#define NAPT_ENTRY1_DST_PORT_FLAG HSL_RW 3805 3806 3807#define NAPT_ENTRY2 3808#define NAPT_ENTRY2_OFFSET 0x0e88 3809#define NAPT_ENTRY2_E_LENGTH 4 3810#define NAPT_ENTRY2_E_OFFSET 0x0 3811#define NAPT_ENTRY2_NR_E 1 3812 3813#define SRC_IPADDR0 3814#define NAPT_ENTRY2_SRC_IPADDR0_BOFFSET 20 3815#define NAPT_ENTRY2_SRC_IPADDR0_BLEN 12 3816#define NAPT_ENTRY2_SRC_IPADDR0_FLAG HSL_RW 3817 3818#define TRANS_IPADDR 3819#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET 16 3820#define NAPT_ENTRY2_TRANS_IPADDR_BLEN 4 3821#define NAPT_ENTRY2_TRANS_IPADDR_FLAG HSL_RW 3822 3823#define TRANS_PORT 3824#define NAPT_ENTRY2_TRANS_PORT_BOFFSET 0 3825#define NAPT_ENTRY2_TRANS_PORT_BLEN 16 3826#define NAPT_ENTRY2_TRANS_PORT_FLAG HSL_RW 3827 3828 3829#define NAPT_ENTRY3 3830#define NAPT_ENTRY3_OFFSET 0x0e8c 3831#define NAPT_ENTRY3_E_LENGTH 4 3832#define NAPT_ENTRY3_E_OFFSET 0x0 3833#define NAPT_ENTRY3_NR_E 1 3834 3835#define PRIORITY_EN 3836#define NAPT_ENTRY3_PRIORITY_EN_BOFFSET 31 3837#define NAPT_ENTRY3_PRIORITY_EN_BLEN 1 3838#define NAPT_ENTRY3_PRIORITY_EN_FLAG HSL_RW 3839 3840#define PRIORITY_VAL 3841#define NAPT_ENTRY3_PRIORITY_VAL_BOFFSET 28 3842#define NAPT_ENTRY3_PRIORITY_VAL_BLEN 3 3843#define NAPT_ENTRY3_PRIORITY_VAL_FLAG HSL_RW 3844 3845#define CNT_EN 3846#define NAPT_ENTRY3_CNT_EN_BOFFSET 27 3847#define NAPT_ENTRY3_CNT_EN_BLEN 1 3848#define NAPT_ENTRY3_CNT_EN_FLAG HSL_RW 3849 3850#define CNT_IDX 3851#define NAPT_ENTRY3_CNT_IDX_BOFFSET 24 3852#define NAPT_ENTRY3_CNT_IDX_BLEN 3 3853#define NAPT_ENTRY3_CNT_IDX_FLAG HSL_RW 3854 3855#define PROT_TYP 3856#define NAPT_ENTRY3_PROT_TYP_BOFFSET 22 3857#define NAPT_ENTRY3_PROT_TYP_BLEN 2 3858#define NAPT_ENTRY3_PROT_TYP_FLAG HSL_RW 3859 3860#define ACTION 3861#define NAPT_ENTRY3_ACTION_BOFFSET 20 3862#define NAPT_ENTRY3_ACTION_BLEN 2 3863#define NAPT_ENTRY3_ACTION_FLAG HSL_RW 3864 3865#define SRC_IPADDR1 3866#define NAPT_ENTRY3_SRC_IPADDR1_BOFFSET 0 3867#define NAPT_ENTRY3_SRC_IPADDR1_BLEN 20 3868#define NAPT_ENTRY3_SRC_IPADDR1_FLAG HSL_RW 3869 3870 3871#define NAPT_ENTRY4 3872#define NAPT_ENTRY4_OFFSET 0x0e90 3873#define NAPT_ENTRY4_E_LENGTH 4 3874#define NAPT_ENTRY4_E_OFFSET 0x0 3875#define NAPT_ENTRY4_NR_E 1 3876 3877#define LOAD_BALANCE 3878#define NAPT_ENTRY4_LOAD_BALANCE_BOFFSET 19 3879#define NAPT_ENTRY4_LOAD_BALANCE_BLEN 3 3880#define NAPT_ENTRY4_LOAD_BALANCE_FLAG HSL_RW 3881 3882#define FLOW_COOKIE 3883#define NAPT_ENTRY4_FLOW_COOKIE_BOFFSET 8 3884#define NAPT_ENTRY4_FLOW_COOKIE_BLEN 11 3885#define NAPT_ENTRY4_FLOW_COOKIE_FLAG HSL_RW 3886 3887#define VRF_ID 3888#define NAPT_ENTRY4_VRF_ID_BOFFSET 5 3889#define NAPT_ENTRY4_VRF_ID_BLEN 3 3890#define NAPT_ENTRY4_VRF_ID_FLAG HSL_RW 3891 3892#define AGE_SYNC 3893#define NAPT_ENTRY4_AGE_SYNC_BOFFSET 4 3894#define NAPT_ENTRY4_AGE_SYNC_BLEN 1 3895#define NAPT_ENTRY4_AGE_SYNC_FLAG HSL_RO 3896 3897#define AGE_FLAG 3898#define NAPT_ENTRY4_AGE_FLAG_BOFFSET 0 3899#define NAPT_ENTRY4_AGE_FLAG_BLEN 4 3900#define NAPT_ENTRY4_AGE_FLAG_FLAG HSL_RW 3901 3902 3903#define ROUTER_CTRL 3904#define ROUTER_CTRL_OFFSET 0x0e00 3905#define ROUTER_CTRL_E_LENGTH 4 3906#define ROUTER_CTRL_E_OFFSET 0x0 3907#define ROUTER_CTRL_NR_E 1 3908 3909#define ARP_LEARN_MODE 3910#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET 19 3911#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN 1 3912#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG HSL_RW 3913 3914#define GLB_LOCKTIME 3915#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET 16 3916#define ROUTER_CTRL_GLB_LOCKTIME_BLEN 2 3917#define ROUTER_CTRL_GLB_LOCKTIME_FLAG HSL_RW 3918 3919#define ARP_AGE_TIME 3920#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET 8 3921#define ROUTER_CTRL_ARP_AGE_TIME_BLEN 8 3922#define ROUTER_CTRL_ARP_AGE_TIME_FLAG HSL_RW 3923 3924#define WCMP_HAHS_DP 3925#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET 7 3926#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN 1 3927#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG HSL_RW 3928 3929#define WCMP_HAHS_DIP 3930#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET 6 3931#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN 1 3932#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG HSL_RW 3933 3934#define WCMP_HAHS_SP 3935#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET 5 3936#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN 1 3937#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG HSL_RW 3938 3939#define WCMP_HAHS_SIP 3940#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET 4 3941#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN 1 3942#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG HSL_RW 3943 3944#define ARP_AGE_MODE 3945#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET 1 3946#define ROUTER_CTRL_ARP_AGE_MODE_BLEN 1 3947#define ROUTER_CTRL_ARP_AGE_MODE_FLAG HSL_RW 3948 3949#define ROUTER_EN 3950#define ROUTER_CTRL_ROUTER_EN_BOFFSET 0 3951#define ROUTER_CTRL_ROUTER_EN_BLEN 1 3952#define ROUTER_CTRL_ROUTER_EN_FLAG HSL_RW 3953 3954 3955 3956 3957#define ROUTER_PTCTRL0 3958#define ROUTER_PTCTRL0_OFFSET 0x0e04 3959#define ROUTER_PTCTRL0_E_LENGTH 4 3960#define ROUTER_PTCTRL0_E_OFFSET 0x0 3961#define ROUTER_PTCTRL0_NR_E 1 3962 3963 3964 3965 3966#define ROUTER_PTCTRL1 3967#define ROUTER_PTCTRL1_OFFSET 0x0e08 3968#define ROUTER_PTCTRL1_E_LENGTH 4 3969#define ROUTER_PTCTRL1_E_OFFSET 0x0 3970#define ROUTER_PTCTRL1_NR_E 1 3971 3972 3973 3974#define ROUTER_PTCTRL2 3975#define ROUTER_PTCTRL2_OFFSET 0x0e0c 3976#define ROUTER_PTCTRL2_E_LENGTH 4 3977#define ROUTER_PTCTRL2_E_OFFSET 0x0 3978#define ROUTER_PTCTRL2_NR_E 1 3979 3980#define ARP_PT_UP 3981#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET 16 3982#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN 7 3983#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG HSL_RW 3984 3985#define ARP_LEARN_ACK 3986#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET 8 3987#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN 7 3988#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG HSL_RW 3989 3990#define ARP_LEARN_REQ 3991#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET 0 3992#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN 7 3993#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG HSL_RW 3994 3995 3996 3997 3998#define NAT_CTRL 3999#define NAT_CTRL_OFFSET 0x0e38 4000#define NAT_CTRL_E_LENGTH 4 4001#define NAT_CTRL_E_OFFSET 0x0 4002#define NAT_CTRL_NR_E 1 4003 4004#define NAT_HASH_MODE 4005#define NAT_CTRL_NAT_HASH_MODE_BOFFSET 5 4006#define NAT_CTRL_NAT_HASH_MODE_BLEN 2 4007#define NAT_CTRL_NAT_HASH_MODE_FLAG HSL_RW 4008 4009#define NAPT_OVERRIDE 4010#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET 4 4011#define NAT_CTRL_NAPT_OVERRIDE_BLEN 1 4012#define NAT_CTRL_NAPT_OVERRIDE_FLAG HSL_RW 4013 4014#define NAPT_MODE 4015#define NAT_CTRL_NAPT_MODE_BOFFSET 2 4016#define NAT_CTRL_NAPT_MODE_BLEN 2 4017#define NAT_CTRL_NAPT_MODE_FLAG HSL_RW 4018 4019#define NAT_EN 4020#define NAT_CTRL_NAT_EN_BOFFSET 1 4021#define NAT_CTRL_NAT_EN_BLEN 1 4022#define NAT_CTRL_NAT_EN_FLAG HSL_RW 4023 4024#define NAPT_EN 4025#define NAT_CTRL_NAPT_EN_BOFFSET 0 4026#define NAT_CTRL_NAPT_EN_BLEN 1 4027#define NAT_CTRL_NAPT_EN_FLAG HSL_RW 4028 4029 4030 4031#define FlOW_CMD_CTL 4032#define FlOW_CMD_CTL_OFFSET 0x0ea0 4033#define FlOW_CMD_CTL_E_LENGTH 4 4034#define FlOW_CMD_CTL_E_OFFSET 0x4 4035#define FlOW_CMD_CTL_NR_E 8 4036 4037#define LAN_2_LAN_DEFAULT 4038#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_BOFFSET 26 4039#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_BLEN 2 4040#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_FLAG HSL_RW 4041 4042#define WAN_2_LAN_DEFAULT 4043#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_BOFFSET 24 4044#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_BLEN 2 4045#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_FLAG HSL_RW 4046 4047#define LAN_2_WAN_DEFAULT 4048#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_BOFFSET 22 4049#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_BLEN 2 4050#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_FLAG HSL_RW 4051 4052#define WAN_2_WAN_DEFAULT 4053#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_BOFFSET 20 4054#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_BLEN 2 4055#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_FLAG HSL_RW 4056 4057 4058#define FlOW_RT_CMD_CTL 4059#define FlOW_RT_CMD_CTL_OFFSET 0x0ec0 4060#define FlOW_RT_CMD_CTL_E_LENGTH 4 4061#define FlOW_RT_CMD_CTL_E_OFFSET 0x4 4062#define FlOW_RT_CMD_CTL_NR_E 8 4063 4064#define LAN_2_LAN_DEFAULT 4065#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_BOFFSET 26 4066#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_BLEN 2 4067#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_FLAG HSL_RW 4068 4069#define WAN_2_LAN_DEFAULT 4070#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_BOFFSET 24 4071#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_BLEN 2 4072#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_FLAG HSL_RW 4073 4074#define LAN_2_WAN_DEFAULT 4075#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_BOFFSET 22 4076#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_BLEN 2 4077#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_FLAG HSL_RW 4078 4079#define WAN_2_WAN_DEFAULT 4080#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_BOFFSET 20 4081#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_BLEN 2 4082#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_FLAG HSL_RW 4083 4084 4085 4086#define PRV_BASEADDR 4087#define PRV_BASEADDR_OFFSET 0x0e5c 4088#define PRV_BASEADDR_E_LENGTH 4 4089#define PRV_BASEADDR_E_OFFSET 0x0 4090#define PRV_BASEADDR_NR_E 1 4091 4092#define IP4_ADDR 4093#define PRV_BASEADDR_IP4_ADDR_BOFFSET 0 4094#define PRV_BASEADDR_IP4_ADDR_BLEN 20 4095#define PRV_BASEADDR_IP4_ADDR_FLAG HSL_RW 4096 4097 4098 4099 4100#define PRVIP_ADDR 4101#define PRVIP_ADDR_OFFSET 0x0470 4102#define PRVIP_ADDR_E_LENGTH 4 4103#define PRVIP_ADDR_E_OFFSET 0x0 4104#define PRVIP_ADDR_NR_E 1 4105 4106#define IP4_BASEADDR 4107#define PRVIP_ADDR_IP4_BASEADDR_BOFFSET 0 4108#define PRVIP_ADDR_IP4_BASEADDR_BLEN 32 4109#define PRVIP_ADDR_IP4_BASEADDR_FLAG HSL_RW 4110 4111 4112#define PRVIP_MASK 4113#define PRVIP_MASK_OFFSET 0x0474 4114#define PRVIP_MASK_E_LENGTH 4 4115#define PRVIP_MASK_E_OFFSET 0x0 4116#define PRVIP_MASK_NR_E 1 4117 4118#define IP4_BASEMASK 4119#define PRVIP_MASK_IP4_BASEMASK_BOFFSET 0 4120#define PRVIP_MASK_IP4_BASEMASK_BLEN 32 4121#define PRVIP_MASK_IP4_BASEMASK_FLAG HSL_RW 4122 4123 4124 4125 4126#define PUB_ADDR0 4127#define PUB_ADDR0_OFFSET 0x5aa00 4128#define PUB_ADDR0_E_LENGTH 4 4129#define PUB_ADDR0_E_OFFSET 0x0 4130#define PUB_ADDR0_NR_E 1 4131 4132#define IP4_ADDR 4133#define PUB_ADDR0_IP4_ADDR_BOFFSET 0 4134#define PUB_ADDR0_IP4_ADDR_BLEN 32 4135#define PUB_ADDR0_IP4_ADDR_FLAG HSL_RW 4136 4137 4138#define PUB_ADDR1 4139#define PUB_ADDR1_OFFSET 0x5aa04 4140#define PUB_ADDR1_E_LENGTH 4 4141#define PUB_ADDR1_E_OFFSET 0x0 4142#define PUB_ADDR1_NR_E 1 4143 4144#define ADDR_VALID 4145#define PUB_ADDR1_ADDR_VALID_BOFFSET 0 4146#define PUB_ADDR1_ADDR_VALID_BLEN 1 4147#define PUB_ADDR1_ADDR_VALID_FLAG HSL_RW 4148 4149 4150 4151 4152#define INTF_ADDR_ENTRY0 4153#define INTF_ADDR_ENTRY0_OFFSET 0x5aa00 4154#define INTF_ADDR_ENTRY0_E_LENGTH 4 4155#define INTF_ADDR_ENTRY0_E_OFFSET 0x0 4156#define INTF_ADDR_ENTRY0_NR_E 8 4157 4158#define MAC_ADDR2 4159#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET 24 4160#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN 8 4161#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG HSL_RW 4162 4163#define MAC_ADDR3 4164#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET 16 4165#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN 8 4166#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG HSL_RW 4167 4168#define MAC_ADDR4 4169#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET 8 4170#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN 8 4171#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG HSL_RW 4172 4173#define MAC_ADDR5 4174#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET 0 4175#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN 8 4176#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG HSL_RW 4177 4178 4179#define INTF_ADDR_ENTRY1 4180#define INTF_ADDR_ENTRY1_OFFSET 0x5aa04 4181#define INTF_ADDR_ENTRY1_E_LENGTH 4 4182#define INTF_ADDR_ENTRY1_E_OFFSET 0x0 4183#define INTF_ADDR_ENTRY1_NR_E 8 4184 4185#define VID_HIGH0 4186#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET 28 4187#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN 4 4188#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG HSL_RW 4189 4190#define VID_LOW 4191#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET 16 4192#define INTF_ADDR_ENTRY1_VID_LOW_BLEN 12 4193#define INTF_ADDR_ENTRY1_VID_LOW_FLAG HSL_RW 4194 4195#define MAC_ADDR0 4196#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET 8 4197#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN 8 4198#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG HSL_RW 4199 4200#define MAC_ADDR1 4201#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET 0 4202#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN 8 4203#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG HSL_RW 4204 4205 4206#define INTF_ADDR_ENTRY2 4207#define INTF_ADDR_ENTRY2_OFFSET 0x5aa08 4208#define INTF_ADDR_ENTRY2_E_LENGTH 4 4209#define INTF_ADDR_ENTRY2_E_OFFSET 0x0 4210#define INTF_ADDR_ENTRY2_NR_E 8 4211 4212#define VRF_ID 4213#define INTF_ADDR_ENTRY2_VRF_ID_BOFFSET 10 4214#define INTF_ADDR_ENTRY2_VRF_ID_BLEN 3 4215#define INTF_ADDR_ENTRY2_VRF_ID_FLAG HSL_RW 4216 4217#define IP6_ROUTE 4218#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET 9 4219#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN 1 4220#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG HSL_RW 4221 4222#define IP4_ROUTE 4223#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET 8 4224#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN 1 4225#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG HSL_RW 4226 4227#define VID_HIGH1 4228#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET 0 4229#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN 8 4230#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG HSL_RW 4231 4232 4233#define IP4_DEFAULT_ROUTE_ENTRY 4234#define IP4_DEFAULT_ROUTE_ENTRY_OFFSET 0x004c4 4235#define IP4_DEFAULT_ROUTE_ENTRY_E_LENGTH 4 4236#define IP4_DEFAULT_ROUTE_ENTRY_E_OFFSET 0x0 4237#define IP4_DEFAULT_ROUTE_ENTRY_NR_E 8 4238 4239#define VALID 4240#define IP4_DEFAULT_ROUTE_ENTRY_VALID_BOFFSET 11 4241#define IP4_DEFAULT_ROUTE_ENTRY_VALID_BLEN 1 4242#define IP4_DEFAULT_ROUTE_ENTRY_VALID_FLAG HSL_RW 4243 4244#define VRF 4245#define IP4_DEFAULT_ROUTE_ENTRY_VRF_BOFFSET 8 4246#define IP4_DEFAULT_ROUTE_ENTRY_VRF_BLEN 3 4247#define IP4_DEFAULT_ROUTE_ENTRY_VRF_FLAG HSL_RW 4248 4249#define ARP_WCMP_TYPE 4250#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BOFFSET 7 4251#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BLEN 1 4252#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_FLAG HSL_RW 4253 4254#define ARP_WCMP_INDEX 4255#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BOFFSET 0 4256#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BLEN 7 4257#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_FLAG HSL_RW 4258 4259#define IP6_DEFAULT_ROUTE_ENTRY 4260#define IP6_DEFAULT_ROUTE_ENTRY_OFFSET 0x004c4 4261#define IP6_DEFAULT_ROUTE_ENTRY_E_LENGTH 4 4262#define IP6_DEFAULT_ROUTE_ENTRY_E_OFFSET 0x0 4263#define IP6_DEFAULT_ROUTE_ENTRY_NR_E 8 4264 4265#define VALID 4266#define IP6_DEFAULT_ROUTE_ENTRY_VALID_BOFFSET 11 4267#define IP6_DEFAULT_ROUTE_ENTRY_VALID_BLEN 1 4268#define IP6_DEFAULT_ROUTE_ENTRY_VALID_FLAG HSL_RW 4269 4270#define VRF 4271#define IP6_DEFAULT_ROUTE_ENTRY_VRF_BOFFSET 8 4272#define IP6_DEFAULT_ROUTE_ENTRY_VRF_BLEN 3 4273#define IP6_DEFAULT_ROUTE_ENTRY_VRF_FLAG HSL_RW 4274 4275#define ARP_WCMP_TYPE 4276#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BOFFSET 7 4277#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BLEN 1 4278#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_FLAG HSL_RW 4279 4280#define ARP_WCMP_INDEX 4281#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BOFFSET 0 4282#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BLEN 7 4283#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_FLAG HSL_RW 4284 4285#define IP4_HOST_ROUTE_ENTRY0 4286#define IP4_HOST_ROUTE_ENTRY0_OFFSET 0x5b000 4287#define IP4_HOST_ROUTE_ENTRY0_E_LENGTH 4 4288#define IP4_HOST_ROUTE_ENTRY0_E_OFFSET 0x0 4289#define IP4_HOST_ROUTE_ENTRY0_NR_E 16 4290 4291#define IP4_ADDRL 4292#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_BOFFSET 5 4293#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_BLEN 27 4294#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_FLAG HSL_RW 4295 4296#define PREFIX_LENGTH 4297#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BOFFSET 0 4298#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BLEN 5 4299#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_FLAG HSL_RW 4300 4301#define IP4_HOST_ROUTE_ENTRY1 4302#define IP4_HOST_ROUTE_ENTRY1_OFFSET 0x5b004 4303#define IP4_HOST_ROUTE_ENTRY1_E_LENGTH 4 4304#define IP4_HOST_ROUTE_ENTRY1_E_OFFSET 0x0 4305#define IP4_HOST_ROUTE_ENTRY1_NR_E 16 4306 4307#define VALID 4308#define IP4_HOST_ROUTE_ENTRY1_VALID_BOFFSET 8 4309#define IP4_HOST_ROUTE_ENTRY1_VALID_BLEN 1 4310#define IP4_HOST_ROUTE_ENTRY1_VALID_FLAG HSL_RW 4311 4312#define VRF 4313#define IP4_HOST_ROUTE_ENTRY1_VRF_BOFFSET 5 4314#define IP4_HOST_ROUTE_ENTRY1_VRF_BLEN 3 4315#define IP4_HOST_ROUTE_ENTRY1_VRF_FLAG HSL_RW 4316 4317#define IP4_ADDRH 4318#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_BOFFSET 0 4319#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_BLEN 5 4320#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_FLAG HSL_RW 4321 4322#define IP6_HOST_ROUTE_ENTRY0 4323#define IP6_HOST_ROUTE_ENTRY0_OFFSET 0x5b100 4324#define IP6_HOST_ROUTE_ENTRY0_E_LENGTH 4 4325#define IP6_HOST_ROUTE_ENTRY0_E_OFFSET 0x0 4326#define IP6_HOST_ROUTE_ENTRY0_NR_E 16 4327 4328#define PREFIX_LENGTH 4329#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BOFFSET 0 4330#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BLEN 7 4331#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_FLAG HSL_RW 4332 4333#define IP6_ADDR0L 4334#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_BOFFSET 7 4335#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_BLEN 25 4336#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_FLAG HSL_RW 4337 4338#define IP6_HOST_ROUTE_ENTRY1 4339#define IP6_HOST_ROUTE_ENTRY1_OFFSET 0x5b104 4340#define IP6_HOST_ROUTE_ENTRY1_E_LENGTH 4 4341#define IP6_HOST_ROUTE_ENTRY1_E_OFFSET 0x0 4342#define IP6_HOST_ROUTE_ENTRY1_NR_E 16 4343 4344#define IP6_ADDR0H 4345#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_BOFFSET 0 4346#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_BLEN 7 4347#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_FLAG HSL_RW 4348 4349#define IP6_ADDR1L 4350#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_BOFFSET 7 4351#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_BLEN 25 4352#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_FLAG HSL_RW 4353 4354#define IP6_HOST_ROUTE_ENTRY2 4355#define IP6_HOST_ROUTE_ENTRY2_OFFSET 0x5b108 4356#define IP6_HOST_ROUTE_ENTRY2_E_LENGTH 4 4357#define IP6_HOST_ROUTE_ENTRY2_E_OFFSET 0x0 4358#define IP6_HOST_ROUTE_ENTRY2_NR_E 16 4359 4360#define IP6_ADDR1H 4361#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_BOFFSET 0 4362#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_BLEN 7 4363#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_FLAG HSL_RW 4364 4365#define IP6_ADDR2L 4366#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_BOFFSET 7 4367#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_BLEN 25 4368#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_FLAG HSL_RW 4369 4370#define IP6_HOST_ROUTE_ENTRY3 4371#define IP6_HOST_ROUTE_ENTRY3_OFFSET 0x5b10c 4372#define IP6_HOST_ROUTE_ENTRY3_E_LENGTH 4 4373#define IP6_HOST_ROUTE_ENTRY3_E_OFFSET 0x0 4374#define IP6_HOST_ROUTE_ENTRY3_NR_E 16 4375 4376#define IP6_ADDR2H 4377#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_BOFFSET 0 4378#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_BLEN 7 4379#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_FLAG HSL_RW 4380 4381#define IP6_ADDR3L 4382#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_BOFFSET 7 4383#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_BLEN 25 4384#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_FLAG HSL_RW 4385 4386#define IP6_HOST_ROUTE_ENTRY4 4387#define IP6_HOST_ROUTE_ENTRY4_OFFSET 0x5b110 4388#define IP6_HOST_ROUTE_ENTRY4_E_LENGTH 4 4389#define IP6_HOST_ROUTE_ENTRY4_E_OFFSET 0x0 4390#define IP6_HOST_ROUTE_ENTRY4_NR_E 16 4391 4392#define IP6_ADDR3H 4393#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_BOFFSET 0 4394#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_BLEN 7 4395#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_FLAG HSL_RW 4396 4397#define VRF 4398#define IP6_HOST_ROUTE_ENTRY4_VRF_BOFFSET 7 4399#define IP6_HOST_ROUTE_ENTRY4_VRF_BLEN 3 4400#define IP6_HOST_ROUTE_ENTRY4_VRF_FLAG HSL_RW 4401 4402#define VALID 4403#define IP6_HOST_ROUTE_ENTRY4_VALID_BOFFSET 10 4404#define IP6_HOST_ROUTE_ENTRY4_VALID_BLEN 1 4405#define IP6_HOST_ROUTE_ENTRY4_VALID_FLAG HSL_RW 4406 4407 4408 /* Port Shaper Register0 */ 4409#define EG_SHAPER0 4410#define EG_SHAPER0_OFFSET 0x0890 4411#define EG_SHAPER0_E_LENGTH 4 4412#define EG_SHAPER0_E_OFFSET 0x0020 4413#define EG_SHAPER0_NR_E 7 4414 4415#define EG_Q1_CIR 4416#define EG_SHAPER0_EG_Q1_CIR_BOFFSET 16 4417#define EG_SHAPER0_EG_Q1_CIR_BLEN 15 4418#define EG_SHAPER0_EG_Q1_CIR_FLAG HSL_RW 4419 4420#define EG_Q0_CIR 4421#define EG_SHAPER0_EG_Q0_CIR_BOFFSET 0 4422#define EG_SHAPER0_EG_Q0_CIR_BLEN 15 4423#define EG_SHAPER0_EG_Q0_CIR_FLAG HSL_RW 4424 4425 4426 /* Port Shaper Register1 */ 4427#define EG_SHAPER1 4428#define EG_SHAPER1_OFFSET 0x0894 4429#define EG_SHAPER1_E_LENGTH 4 4430#define EG_SHAPER1_E_OFFSET 0x0020 4431#define EG_SHAPER1_NR_E 7 4432 4433#define EG_Q3_CIR 4434#define EG_SHAPER1_EG_Q3_CIR_BOFFSET 16 4435#define EG_SHAPER1_EG_Q3_CIR_BLEN 15 4436#define EG_SHAPER1_EG_Q3_CIR_FLAG HSL_RW 4437 4438#define EG_Q2_CIR 4439#define EG_SHAPER1_EG_Q2_CIR_BOFFSET 0 4440#define EG_SHAPER1_EG_Q2_CIR_BLEN 15 4441#define EG_SHAPER1_EG_Q2_CIR_FLAG HSL_RW 4442 4443 4444 /* Port Shaper Register2 */ 4445#define EG_SHAPER2 4446#define EG_SHAPER2_OFFSET 0x0898 4447#define EG_SHAPER2_E_LENGTH 4 4448#define EG_SHAPER2_E_OFFSET 0x0020 4449#define EG_SHAPER2_NR_E 7 4450 4451#define EG_Q5_CIR 4452#define EG_SHAPER2_EG_Q5_CIR_BOFFSET 16 4453#define EG_SHAPER2_EG_Q5_CIR_BLEN 15 4454#define EG_SHAPER2_EG_Q5_CIR_FLAG HSL_RW 4455 4456#define EG_Q4_CIR 4457#define EG_SHAPER2_EG_Q4_CIR_BOFFSET 0 4458#define EG_SHAPER2_EG_Q4_CIR_BLEN 15 4459#define EG_SHAPER2_EG_Q4_CIR_FLAG HSL_RW 4460 4461 4462 /* Port Shaper Register3 */ 4463#define EG_SHAPER3 4464#define EG_SHAPER3_OFFSET 0x089c 4465#define EG_SHAPER3_E_LENGTH 4 4466#define EG_SHAPER3_E_OFFSET 0x0020 4467#define EG_SHAPER3_NR_E 7 4468 4469#define EG_Q1_EIR 4470#define EG_SHAPER3_EG_Q1_EIR_BOFFSET 16 4471#define EG_SHAPER3_EG_Q1_EIR_BLEN 15 4472#define EG_SHAPER3_EG_Q1_EIR_FLAG HSL_RW 4473 4474#define EG_Q0_EIR 4475#define EG_SHAPER3_EG_Q0_EIR_BOFFSET 0 4476#define EG_SHAPER3_EG_Q0_EIR_BLEN 15 4477#define EG_SHAPER3_EG_Q0_EIR_FLAG HSL_RW 4478 4479 4480 /* Port Shaper Register4 */ 4481#define EG_SHAPER4 4482#define EG_SHAPER4_OFFSET 0x08a0 4483#define EG_SHAPER4_E_LENGTH 4 4484#define EG_SHAPER4_E_OFFSET 0x0020 4485#define EG_SHAPER4_NR_E 7 4486 4487#define EG_Q3_EIR 4488#define EG_SHAPER4_EG_Q3_EIR_BOFFSET 16 4489#define EG_SHAPER4_EG_Q3_EIR_BLEN 15 4490#define EG_SHAPER4_EG_Q3_EIR_FLAG HSL_RW 4491 4492#define EG_Q2_EIR 4493#define EG_SHAPER4_EG_Q2_EIR_BOFFSET 0 4494#define EG_SHAPER4_EG_Q2_EIR_BLEN 15 4495#define EG_SHAPER4_EG_Q2_EIR_FLAG HSL_RW 4496 4497 4498 /* Port Shaper Register5 */ 4499#define EG_SHAPER5 4500#define EG_SHAPER5_OFFSET 0x08a4 4501#define EG_SHAPER5_E_LENGTH 4 4502#define EG_SHAPER5_E_OFFSET 0x0020 4503#define EG_SHAPER5_NR_E 7 4504 4505#define EG_Q5_EIR 4506#define EG_SHAPER5_EG_Q5_EIR_BOFFSET 16 4507#define EG_SHAPER5_EG_Q5_EIR_BLEN 15 4508#define EG_SHAPER5_EG_Q5_EIR_FLAG HSL_RW 4509 4510#define EG_Q4_EIR 4511#define EG_SHAPER5_EG_Q4_EIR_BOFFSET 0 4512#define EG_SHAPER5_EG_Q4_EIR_BLEN 15 4513#define EG_SHAPER5_EG_Q4_EIR_FLAG HSL_RW 4514 4515 4516 /* Port Shaper Register6 */ 4517#define EG_SHAPER6 4518#define EG_SHAPER6_OFFSET 0x08a8 4519#define EG_SHAPER6_E_LENGTH 4 4520#define EG_SHAPER6_E_OFFSET 0x0020 4521#define EG_SHAPER6_NR_E 7 4522 4523#define EG_Q3_CBS 4524#define EG_SHAPER6_EG_Q3_CBS_BOFFSET 28 4525#define EG_SHAPER6_EG_Q3_CBS_BLEN 3 4526#define EG_SHAPER6_EG_Q3_CBS_FLAG HSL_RW 4527 4528#define EG_Q3_EBS 4529#define EG_SHAPER6_EG_Q3_EBS_BOFFSET 24 4530#define EG_SHAPER6_EG_Q3_EBS_BLEN 3 4531#define EG_SHAPER6_EG_Q3_EBS_FLAG HSL_RW 4532 4533#define EG_Q2_CBS 4534#define EG_SHAPER6_EG_Q2_CBS_BOFFSET 20 4535#define EG_SHAPER6_EG_Q2_CBS_BLEN 3 4536#define EG_SHAPER6_EG_Q2_CBS_FLAG HSL_RW 4537 4538#define EG_Q2_EBS 4539#define EG_SHAPER6_EG_Q2_EBS_BOFFSET 16 4540#define EG_SHAPER6_EG_Q2_EBS_BLEN 3 4541#define EG_SHAPER6_EG_Q2_EBS_FLAG HSL_RW 4542 4543#define EG_Q1_CBS 4544#define EG_SHAPER6_EG_Q1_CBS_BOFFSET 12 4545#define EG_SHAPER6_EG_Q1_CBS_BLEN 3 4546#define EG_SHAPER6_EG_Q1_CBS_FLAG HSL_RW 4547 4548#define EG_Q1_EBS 4549#define EG_SHAPER6_EG_Q1_EBS_BOFFSET 8 4550#define EG_SHAPER6_EG_Q1_EBS_BLEN 3 4551#define EG_SHAPER6_EG_Q1_EBS_FLAG HSL_RW 4552 4553#define EG_Q0_CBS 4554#define EG_SHAPER6_EG_Q0_CBS_BOFFSET 4 4555#define EG_SHAPER6_EG_Q0_CBS_BLEN 3 4556#define EG_SHAPER6_EG_Q0_CBS_FLAG HSL_RW 4557 4558#define EG_Q0_EBS 4559#define EG_SHAPER6_EG_Q0_EBS_BOFFSET 0 4560#define EG_SHAPER6_EG_Q0_EBS_BLEN 3 4561#define EG_SHAPER6_EG_Q0_EBS_FLAG HSL_RW 4562 4563 4564 /* Port Shaper Register7 */ 4565#define EG_SHAPER7 4566#define EG_SHAPER7_OFFSET 0x08ac 4567#define EG_SHAPER7_E_LENGTH 4 4568#define EG_SHAPER7_E_OFFSET 0x0020 4569#define EG_SHAPER7_NR_E 7 4570 4571#define EG_Q5_CBS 4572#define EG_SHAPER7_EG_Q5_CBS_BOFFSET 28 4573#define EG_SHAPER7_EG_Q5_CBS_BLEN 3 4574#define EG_SHAPER7_EG_Q5_CBS_FLAG HSL_RW 4575 4576#define EG_Q5_EBS 4577#define EG_SHAPER7_EG_Q5_EBS_BOFFSET 24 4578#define EG_SHAPER7_EG_Q5_EBS_BLEN 3 4579#define EG_SHAPER7_EG_Q5_EBS_FLAG HSL_RW 4580 4581#define EG_Q4_CBS 4582#define EG_SHAPER7_EG_Q4_CBS_BOFFSET 20 4583#define EG_SHAPER7_EG_Q4_CBS_BLEN 3 4584#define EG_SHAPER7_EG_Q4_CBS_FLAG HSL_RW 4585 4586#define EG_Q4_EBS 4587#define EG_SHAPER7_EG_Q4_EBS_BOFFSET 16 4588#define EG_SHAPER7_EG_Q4_EBS_BLEN 3 4589#define EG_SHAPER7_EG_Q4_EBS_FLAG HSL_RW 4590 4591#define EG_Q5_UNIT 4592#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET 13 4593#define EG_SHAPER7_EG_Q5_UNIT_BLEN 1 4594#define EG_SHAPER7_EG_Q5_UNIT_FLAG HSL_RW 4595 4596#define EG_Q4_UNIT 4597#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET 12 4598#define EG_SHAPER7_EG_Q4_UNIT_BLEN 1 4599#define EG_SHAPER7_EG_Q4_UNIT_FLAG HSL_RW 4600 4601#define EG_Q3_UNIT 4602#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET 11 4603#define EG_SHAPER7_EG_Q3_UNIT_BLEN 1 4604#define EG_SHAPER7_EG_Q3_UNIT_FLAG HSL_RW 4605 4606#define EG_Q2_UNIT 4607#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET 10 4608#define EG_SHAPER7_EG_Q2_UNIT_BLEN 1 4609#define EG_SHAPER7_EG_Q2_UNIT_FLAG HSL_RW 4610 4611#define EG_Q1_UNIT 4612#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET 9 4613#define EG_SHAPER7_EG_Q1_UNIT_BLEN 1 4614#define EG_SHAPER7_EG_Q1_UNIT_FLAG HSL_RW 4615 4616#define EG_Q0_UNIT 4617#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET 8 4618#define EG_SHAPER7_EG_Q0_UNIT_BLEN 1 4619#define EG_SHAPER7_EG_Q0_UNIT_FLAG HSL_RW 4620 4621#define EG_PT 4622#define EG_SHAPER7_EG_PT_BOFFSET 3 4623#define EG_SHAPER7_EG_PT_BLEN 1 4624#define EG_SHAPER7_EG_PT_FLAG HSL_RW 4625 4626#define EG_TS 4627#define EG_SHAPER7_EG_TS_BOFFSET 0 4628#define EG_SHAPER7_EG_TS_BLEN 3 4629#define EG_SHAPER7_EG_TS_FLAG HSL_RW 4630 4631 4632 4633 /* ACL Policer Register0 */ 4634#define ACL_POLICER0 4635#define ACL_POLICER0_OFFSET 0x0a00 4636#define ACL_POLICER0_E_LENGTH 4 4637#define ACL_POLICER0_E_OFFSET 0x0008 4638#define ACL_POLICER0_NR_E 32 4639 4640#define ACL_CBS 4641#define ACL_POLICER0_ACL_CBS_BOFFSET 15 4642#define ACL_POLICER0_ACL_CBS_BLEN 3 4643#define ACL_POLICER0_ACL_CBS_FLAG HSL_RW 4644 4645#define ACL_CIR 4646#define ACL_POLICER0_ACL_CIR_BOFFSET 0 4647#define ACL_POLICER0_ACL_CIR_BLEN 15 4648#define ACL_POLICER0_ACL_CIR_FLAG HSL_RW 4649 4650 4651 /* ACL Policer Register1 */ 4652#define ACL_POLICER1 4653#define ACL_POLICER1_OFFSET 0x0a04 4654#define ACL_POLICER1_E_LENGTH 4 4655#define ACL_POLICER1_E_OFFSET 0x0008 4656#define ACL_POLICER1_NR_E 32 4657 4658#define ACL_BORROW 4659#define ACL_POLICER1_ACL_BORROW_BOFFSET 23 4660#define ACL_POLICER1_ACL_BORROW_BLEN 1 4661#define ACL_POLICER1_ACL_BORROW_FLAG HSL_RW 4662 4663#define ACL_UNIT 4664#define ACL_POLICER1_ACL_UNIT_BOFFSET 22 4665#define ACL_POLICER1_ACL_UNIT_BLEN 1 4666#define ACL_POLICER1_ACL_UNIT_FLAG HSL_RW 4667 4668#define ACL_CF 4669#define ACL_POLICER1_ACL_CF_BOFFSET 21 4670#define ACL_POLICER1_ACL_CF_BLEN 1 4671#define ACL_POLICER1_ACL_CF_FLAG HSL_RW 4672 4673#define ACL_CM 4674#define ACL_POLICER1_ACL_CM_BOFFSET 20 4675#define ACL_POLICER1_ACL_CM_BLEN 1 4676#define ACL_POLICER1_ACL_CM_FLAG HSL_RW 4677 4678#define ACL_TS 4679#define ACL_POLICER1_ACL_TS_BOFFSET 18 4680#define ACL_POLICER1_ACL_TS_BLEN 2 4681#define ACL_POLICER1_ACL_TS_FLAG HSL_RW 4682 4683#define ACL_EBS 4684#define ACL_POLICER1_ACL_EBS_BOFFSET 15 4685#define ACL_POLICER1_ACL_EBS_BLEN 3 4686#define ACL_POLICER1_ACL_EBS_FLAG HSL_RW 4687 4688#define ACL_EIR 4689#define ACL_POLICER1_ACL_EIR_BOFFSET 0 4690#define ACL_POLICER1_ACL_EIR_BLEN 15 4691#define ACL_POLICER1_ACL_EIR_FLAG HSL_RW 4692 4693 4694 /* Flow Congestion Drop CTRL0 */ 4695#define FLOW_CONGE_DROP_CTRL0 4696#define FLOW_CONGE_DROP_CTRL0_OFFSET 0x0b74 4697#define FLOW_CONGE_DROP_CTRL0_E_LENGTH 4 4698#define FLOW_CONGE_DROP_CTRL0_E_OFFSET 4 4699#define FLOW_CONGE_DROP_CTRL0_NR_E 1 4700 4701#define EN5 4702#define FLOW_CONGE_DROP_CTRL0_EN5_BOFFSET 22 4703#define FLOW_CONGE_DROP_CTRL0_EN5_BLEN 6 4704#define FLOW_CONGE_DROP_CTRL0_EN5_FLAG HSL_RW 4705 4706#define EN4 4707#define FLOW_CONGE_DROP_CTRL0_EN4_BOFFSET 18 4708#define FLOW_CONGE_DROP_CTRL0_EN4_BLEN 4 4709#define FLOW_CONGE_DROP_CTRL0_EN4_FLAG HSL_RW 4710 4711#define EN3 4712#define FLOW_CONGE_DROP_CTRL0_EN3_BOFFSET 14 4713#define FLOW_CONGE_DROP_CTRL0_EN3_BLEN 4 4714#define FLOW_CONGE_DROP_CTRL0_EN3_FLAG HSL_RW 4715 4716#define EN2 4717#define FLOW_CONGE_DROP_CTRL0_EN2_BOFFSET 10 4718#define FLOW_CONGE_DROP_CTRL0_EN2_BLEN 4 4719#define FLOW_CONGE_DROP_CTRL0_EN2_FLAG HSL_RW 4720 4721#define EN1 4722#define FLOW_CONGE_DROP_CTRL0_EN1_BOFFSET 6 4723#define FLOW_CONGE_DROP_CTRL0_EN1_BLEN 4 4724#define FLOW_CONGE_DROP_CTRL0_EN1_FLAG HSL_RW 4725 4726#define EN0 4727#define FLOW_CONGE_DROP_CTRL0_EN0_BOFFSET 0 4728#define FLOW_CONGE_DROP_CTRL0_EN0_BLEN 6 4729#define FLOW_CONGE_DROP_CTRL0_EN0_FLAG HSL_RW 4730 4731 /* Ring Flow Control Threshold Register*/ 4732#define RING_FLOW_CTRL_THRES 4733#define RING_FLOW_CTRL_THRES_OFFSET 0x0b80 4734#define RING_FLOW_CTRL_THRES_E_LENGTH 4 4735#define RING_FLOW_CTRL_THRES_E_OFFSET 4 4736#define RING_FLOW_CTRL_THRES_NR_E 8 4737 4738#define XON 4739#define RING_FLOW_CTRL_THRES_XON_BOFFSET 16 4740#define RING_FLOW_CTRL_THRES_XON_BLEN 8 4741#define RING_FLOW_CTRL_THRES_XON_FLAG HSL_RW 4742 4743#define XOFF 4744#define RING_FLOW_CTRL_THRES_XOFF_BOFFSET 0 4745#define RING_FLOW_CTRL_THRES_XOFF_BLEN 8 4746#define RING_FLOW_CTRL_THRES_XOFF_FLAG HSL_RW 4747 4748 4749 4750 4751 /* ACL Counter Register0 */ 4752#define ACL_COUNTER0 4753#define ACL_COUNTER0_OFFSET 0x1c000 4754#define ACL_COUNTER0_E_LENGTH 4 4755#define ACL_COUNTER0_E_OFFSET 0x0008 4756#define ACL_COUNTER0_NR_E 32 4757 4758 /* ACL Counter Register1 */ 4759#define ACL_COUNTER1 4760#define ACL_COUNTER1_OFFSET 0x1c004 4761#define ACL_COUNTER1_E_LENGTH 4 4762#define ACL_COUNTER1_E_OFFSET 0x0008 4763#define ACL_COUNTER1_NR_E 32 4764 4765 4766 4767 4768 /* INGRESS Policer Register0 */ 4769#define INGRESS_POLICER0 4770#define INGRESS_POLICER0_OFFSET 0x0b00 4771#define INGRESS_POLICER0_E_LENGTH 4 4772#define INGRESS_POLICER0_E_OFFSET 0x0010 4773#define INGRESS_POLICER0_NR_E 7 4774 4775#define ADD_RATE_BYTE 4776#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24 4777#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8 4778#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW 4779 4780#define C_ING_TS 4781#define INGRESS_POLICER0_C_ING_TS_BOFFSET 22 4782#define INGRESS_POLICER0_C_ING_TS_BLEN 2 4783#define INGRESS_POLICER0_C_ING_TS_FLAG HSL_RW 4784 4785#define RATE_MODE 4786#define INGRESS_POLICER0_RATE_MODE_BOFFSET 20 4787#define INGRESS_POLICER0_RATE_MODE_BLEN 1 4788#define INGRESS_POLICER0_RATE_MODE_FLAG HSL_RW 4789 4790#define INGRESS_CBS 4791#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET 15 4792#define INGRESS_POLICER0_INGRESS_CBS_BLEN 3 4793#define INGRESS_POLICER0_INGRESS_CBS_FLAG HSL_RW 4794 4795#define INGRESS_CIR 4796#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET 0 4797#define INGRESS_POLICER0_INGRESS_CIR_BLEN 15 4798#define INGRESS_POLICER0_INGRESS_CIR_FLAG HSL_RW 4799 4800 4801 /* INGRESS Policer Register1 */ 4802#define INGRESS_POLICER1 4803#define INGRESS_POLICER1_OFFSET 0x0b04 4804#define INGRESS_POLICER1_E_LENGTH 4 4805#define INGRESS_POLICER1_E_OFFSET 0x0010 4806#define INGRESS_POLICER1_NR_E 7 4807 4808#define INGRESS_BORROW 4809#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET 23 4810#define INGRESS_POLICER1_INGRESS_BORROW_BLEN 1 4811#define INGRESS_POLICER1_INGRESS_BORROW_FLAG HSL_RW 4812 4813#define INGRESS_UNIT 4814#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET 22 4815#define INGRESS_POLICER1_INGRESS_UNIT_BLEN 1 4816#define INGRESS_POLICER1_INGRESS_UNIT_FLAG HSL_RW 4817 4818#define INGRESS_CF 4819#define INGRESS_POLICER1_INGRESS_CF_BOFFSET 21 4820#define INGRESS_POLICER1_INGRESS_CF_BLEN 1 4821#define INGRESS_POLICER1_INGRESS_CF_FLAG HSL_RW 4822 4823#define INGRESS_CM 4824#define INGRESS_POLICER1_INGRESS_CM_BOFFSET 20 4825#define INGRESS_POLICER1_INGRESS_CM_BLEN 1 4826#define INGRESS_POLICER1_INGRESS_CM_FLAG HSL_RW 4827 4828#define E_ING_TS 4829#define INGRESS_POLICER1_E_ING_TS_BOFFSET 18 4830#define INGRESS_POLICER1_E_ING_TS_BLEN 2 4831#define INGRESS_POLICER1_E_ING_TS_FLAG HSL_RW 4832 4833#define INGRESS_EBS 4834#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET 15 4835#define INGRESS_POLICER1_INGRESS_EBS_BLEN 3 4836#define INGRESS_POLICER1_INGRESS_EBS_FLAG HSL_RW 4837 4838#define INGRESS_EIR 4839#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET 0 4840#define INGRESS_POLICER1_INGRESS_EIR_BLEN 15 4841#define INGRESS_POLICER1_INGRESS_EIR_FLAG HSL_RW 4842 4843 4844 /* INGRESS Policer Register2 */ 4845#define INGRESS_POLICER2 4846#define INGRESS_POLICER2_OFFSET 0x0b08 4847#define INGRESS_POLICER2_E_LENGTH 4 4848#define INGRESS_POLICER2_E_OFFSET 0x0010 4849#define INGRESS_POLICER2_NR_E 7 4850 4851#define C_MUL 4852#define INGRESS_POLICER2_C_MUL_BOFFSET 15 4853#define INGRESS_POLICER2_C_MUL_BLEN 1 4854#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW 4855 4856#define C_UNI 4857#define INGRESS_POLICER2_C_UNI_BOFFSET 14 4858#define INGRESS_POLICER2_C_UNI_BLEN 1 4859#define INGRESS_POLICER2_C_UNI_FLAG HSL_RW 4860 4861#define C_UNK_MUL 4862#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET 13 4863#define INGRESS_POLICER2_C_UNK_MUL_BLEN 1 4864#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW 4865 4866#define C_UNK_UNI 4867#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET 12 4868#define INGRESS_POLICER2_C_UNK_UNI_BLEN 1 4869#define INGRESS_POLICER2_C_UNK_UNI_FLAG HSL_RW 4870 4871#define C_BROAD 4872#define INGRESS_POLICER2_C_BROAD_BOFFSET 11 4873#define INGRESS_POLICER2_C_BROAD_BLEN 1 4874#define INGRESS_POLICER2_C_BROAD_FLAG HSL_RW 4875 4876#define C_MANAGE 4877#define INGRESS_POLICER2_C_MANAGC_BOFFSET 10 4878#define INGRESS_POLICER2_C_MANAGC_BLEN 1 4879#define INGRESS_POLICER2_C_MANAGC_FLAG HSL_RW 4880 4881#define C_TCP 4882#define INGRESS_POLICER2_C_TCP_BOFFSET 9 4883#define INGRESS_POLICER2_C_TCP_BLEN 1 4884#define INGRESS_POLICER2_C_TCP_FLAG HSL_RW 4885 4886#define C_MIRR 4887#define INGRESS_POLICER2_C_MIRR_BOFFSET 8 4888#define INGRESS_POLICER2_C_MIRR_BLEN 1 4889#define INGRESS_POLICER2_C_MIRR_FLAG HSL_RW 4890 4891#define E_MUL 4892#define INGRESS_POLICER2_E_MUL_BOFFSET 7 4893#define INGRESS_POLICER2_E_MUL_BLEN 1 4894#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW 4895 4896#define E_UNI 4897#define INGRESS_POLICER2_E_UNI_BOFFSET 6 4898#define INGRESS_POLICER2_E_UNI_BLEN 1 4899#define INGRESS_POLICER2_E_UNI_FLAG HSL_RW 4900 4901#define E_UNK_MUL 4902#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET 5 4903#define INGRESS_POLICER2_E_UNK_MUL_BLEN 1 4904#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW 4905 4906#define E_UNK_UNI 4907#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET 4 4908#define INGRESS_POLICER2_E_UNK_UNI_BLEN 1 4909#define INGRESS_POLICER2_E_UNK_UNI_FLAG HSL_RW 4910 4911#define E_BROAD 4912#define INGRESS_POLICER2_E_BROAD_BOFFSET 3 4913#define INGRESS_POLICER2_E_BROAD_BLEN 1 4914#define INGRESS_POLICER2_E_BROAD_FLAG HSL_RW 4915 4916#define E_MANAGE 4917#define INGRESS_POLICER2_E_MANAGE_BOFFSET 2 4918#define INGRESS_POLICER2_E_MANAGE_BLEN 1 4919#define INGRESS_POLICER2_E_MANAGE_FLAG HSL_RW 4920 4921#define E_TCP 4922#define INGRESS_POLICER2_E_TCP_BOFFSET 1 4923#define INGRESS_POLICER2_E_TCP_BLEN 1 4924#define INGRESS_POLICER2_E_TCP_FLAG HSL_RW 4925 4926#define E_MIRR 4927#define INGRESS_POLICER2_E_MIRR_BOFFSET 0 4928#define INGRESS_POLICER2_E_MIRR_BLEN 1 4929#define INGRESS_POLICER2_E_MIRR_FLAG HSL_RW 4930 4931 4932 4933 4934 /* Port Rate Limit2 Register */ 4935#define WRR_CTRL 4936#define WRR_CTRL_OFFSET 0x0830 4937#define WRR_CTRL_E_LENGTH 4 4938#define WRR_CTRL_E_OFFSET 0x0004 4939#define WRR_CTRL_NR_E 7 4940 4941#define SCH_MODE 4942#define WRR_CTRL_SCH_MODE_BOFFSET 30 4943#define WRR_CTRL_SCH_MODE_BLEN 2 4944#define WRR_CTRL_SCH_MODE_FLAG HSL_RW 4945 4946#define Q5_W 4947#define WRR_CTRL_Q5_W_BOFFSET 25 4948#define WRR_CTRL_Q5_W_BLEN 5 4949#define WRR_CTRL_Q5_W_FLAG HSL_RW 4950 4951#define Q4_W 4952#define WRR_CTRL_Q4_W_BOFFSET 20 4953#define WRR_CTRL_Q4_W_BLEN 5 4954#define WRR_CTRL_Q4_W_FLAG HSL_RW 4955 4956#define Q3_W 4957#define WRR_CTRL_Q3_W_BOFFSET 15 4958#define WRR_CTRL_Q3_W_BLEN 5 4959#define WRR_CTRL_Q3_W_FLAG HSL_RW 4960 4961#define Q2_W 4962#define WRR_CTRL_Q2_W_BOFFSET 10 4963#define WRR_CTRL_Q2_W_BLEN 5 4964#define WRR_CTRL_Q2_W_FLAG HSL_RW 4965 4966#define Q1_W 4967#define WRR_CTRL_Q1_W_BOFFSET 5 4968#define WRR_CTRL_Q1_W_BLEN 5 4969#define WRR_CTRL_Q1_W_FLAG HSL_RW 4970 4971#define Q0_W 4972#define WRR_CTRL_Q0_W_BOFFSET 0 4973#define WRR_CTRL_Q0_W_BLEN 5 4974#define WRR_CTRL_Q0_W_FLAG HSL_RW 4975 4976/* Global Interrupt Register0 */ 4977#define GLOBAL_INT0 4978#define GLOBAL_INT0_OFFSET 0x0020 4979#define GLOBAL_INT0_E_LENGTH 4 4980#define GLOBAL_INT0_E_OFFSET 0 4981#define GLOBAL_INT0_NR_E 1 4982 4983/* Global Interrupt Register1 */ 4984#define GLOBAL_INT1 4985#define GLOBAL_INT1_OFFSET 0x0024 4986#define GLOBAL_INT1_E_LENGTH 4 4987#define GLOBAL_INT1_E_OFFSET 0 4988#define GLOBAL_INT1_NR_E 1 4989 4990/* Global Interrupt Mask Register0 */ 4991#define GLOBAL_INT0_MASK 4992#define GLOBAL_INT0_MASK_OFFSET 0x0028 4993#define GLOBAL_INT0_MASK_E_LENGTH 4 4994#define GLOBAL_INT0_MASK_E_OFFSET 0 4995#define GLOBAL_INT0_MASK_NR_E 1 4996 4997/* Global Interrupt Mask Register1 */ 4998#define GLOBAL_INT1_MASK 4999#define GLOBAL_INT1_MASK_OFFSET 0x002c 5000#define GLOBAL_INT1_MASK_E_LENGTH 4 5001#define GLOBAL_INT1_MASK_E_OFFSET 0 5002#define GLOBAL_INT1_MASK_NR_E 1 5003 5004 5005 5006 5007#ifdef __cplusplus 5008} 5009#endif /* __cplusplus */ 5010#endif /* _DESS_REG_H_ */ 5011 5012