1/*
2 **************************************************************************
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all copies.
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
13 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 **************************************************************************
15 */
16
17/**
18 * nss_hal_pvt.h
19 *	NSS HAL private declarations.for IPQ806x platform
20 */
21
22#ifndef __NSS_HAL_PVT_H
23#define __NSS_HAL_PVT_H
24
25#include "nss_regs.h"
26#include "nss_clocks.h"
27#include <linux/types.h>
28#include <linux/platform_device.h>
29
30#define NSS_HAL_SUPPORTED_INTERRUPTS (NSS_REGS_N2H_INTR_STATUS_EMPTY_BUFFER_QUEUE | \
31					NSS_REGS_N2H_INTR_STATUS_DATA_COMMAND_QUEUE | \
32					NSS_REGS_N2H_INTR_STATUS_DATA_QUEUE_1 | \
33					NSS_REGS_N2H_INTR_STATUS_EMPTY_BUFFERS_SOS | \
34					NSS_REGS_N2H_INTR_STATUS_TX_UNBLOCKED | \
35					NSS_REGS_N2H_INTR_STATUS_COREDUMP_COMPLETE_0 | \
36					NSS_REGS_N2H_INTR_STATUS_COREDUMP_COMPLETE_1)
37
38
39/*
40 * __nss_hal_read_interrupt_cause()
41 */
42static inline void __nss_hal_read_interrupt_cause(uint32_t map, uint32_t irq __attribute__ ((unused)), uint32_t shift_factor, uint32_t *cause)
43{
44	uint32_t value = nss_read_32(map, NSS_REGS_N2H_INTR_STATUS_OFFSET);
45	*cause = (((value)>> shift_factor) & 0x7FFF);
46}
47
48/*
49 * __nss_hal_clear_interrupt_cause()
50 */
51static inline void __nss_hal_clear_interrupt_cause(uint32_t map, uint32_t irq __attribute__ ((unused)), uint32_t shift_factor, uint32_t cause)
52{
53	nss_write_32(map, NSS_REGS_N2H_INTR_CLR_OFFSET, (cause << shift_factor));
54}
55
56/*
57 * __nss_hal_disable_interrupt()
58 */
59static inline void __nss_hal_disable_interrupt(uint32_t map, uint32_t irq __attribute__ ((unused)), uint32_t shift_factor, uint32_t cause)
60{
61	nss_write_32(map, NSS_REGS_N2H_INTR_MASK_CLR_OFFSET, (cause << shift_factor));
62}
63
64/*
65 * __nss_hal_enable_interrupt()
66 */
67static inline void __nss_hal_enable_interrupt(uint32_t map, uint32_t irq __attribute__ ((unused)), uint32_t shift_factor, uint32_t cause)
68{
69	nss_write_32(map, NSS_REGS_N2H_INTR_MASK_SET_OFFSET, (cause << shift_factor));
70}
71
72/*
73 * __nss_hal_send_interrupt()
74 */
75static inline void __nss_hal_send_interrupt(uint32_t map, uint32_t irq __attribute__ ((unused)), uint32_t cause)
76{
77	nss_write_32(map, NSS_REGS_C2C_INTR_SET_OFFSET, cause);
78}
79
80#if (NSS_DT_SUPPORT == 1)
81extern void __nss_hal_core_reset(uint32_t map, uint32_t reset);
82#else
83extern void __nss_hal_core_reset(uint32_t core_id, uint32_t map, uint32_t addr, uint32_t clk_src);
84extern void __nss_hal_common_reset(uint32_t *clk_src);
85extern uint32_t nss_hal_pvt_divide_pll18(uint32_t core_id, uint32_t divider);
86extern void nss_hal_pvt_pll_change(uint32_t pll);
87extern uint32_t nss_hal_pvt_enable_pll18(uint32_t speed);
88extern void nss_hal_pvt_register_dump(void);
89#endif
90extern void __nss_hal_debug_enable(void);
91#endif /* __NSS_HAL_PVT_H */
92