device_wake_opt devpath%d %d:%s devid wl0id host_wake_opt regwindowsz boardtype subvid boardvendor manfid prodid boardrev boardflags t xtalfreq muxenab swdenable
GCC: (Buildroot 2012.02) 4.5.3
.symtab .strtab .shstrtab .rel.text .data .bss .ARM.extab .rel.ARM.exidx .rel.rodata .rodata.str1.1 .comment .note.GNU-stack .ARM.attributes
siutils.c $a factor6 $d si_ispcie socram_banksize.clone.1 si_findcoreidx.clone.5 si_setcore.clone.6 si_slowclk_src si_slowclk_freq si_gci_gpio_chipcontrol si_gci_gpio_reg si_gci_gpio_wakemask _si_clkctl_cc si_devpathvar.clone.7 si_pcie_devpathvar.clone.4 si_doattach CSWTCH.185 rstr_device_wake_opt mux4335_uartopt mux4335_hostwakeopt mux4350_uartopt rstr_devpathD rstr_D_S rstr_devid rstr_wl0id rstr_host_wake_opt cis_sel.31004 cis_43236_sel.31005 rstr_regwindowsz rstr_boardtype rstr_subvid rstr_boardvendor rstr_manfid rstr_prodid rstr_boardrev rstr_boardflags C.180.39498 rstr_xtalfreq rstr_muxenab rstr_swdenab ksii wd_msticks si_gpioreservation ksii_attached.28951 __aeabi_unwind_cpp_pr0 pcicore_find_pci_capability __aeabi_unwind_cpp_pr1 osl_pcie_rreg outer_cache sb_setcoreidx ai_setcoreidx si_gci_gpioint_handler_unregister osl_mfree si_gci_gpioint_handler_register osl_malloc si_cc_get_reg16 si_cc_get_reg32 si_cc_set_reg32 si_gci_preinit_upd_indirect si_gci_uart_init si_detach __iounmap pcicore_deinit si_osh si_setosh si_register_intr_callback si_deregister_intr_callback si_intflag sb_intflag si_flag sb_flag ai_flag si_flag_alt ai_flag_alt si_setint sb_setint ai_setint si_coreid si_coreidx si_coreunit si_corevendor sb_corevendor ai_corevendor si_backplane64 si_corerev sb_corerev ai_corerev si_findcoreidx si_corelist memcpy si_wrapperregs si_coreregs si_setcore si_setcoreidx osl_pci_read_config __aeabi_uidiv si_switch_core si_restore_core si_numaddrspaces sb_numaddrspaces ai_numaddrspaces si_addrspace sb_addrspace ai_addrspace si_addrspacesize sb_addrspacesize ai_addrspacesize si_coreaddrspaceX ai_coreaddrspaceX si_core_cflags sb_core_cflags ai_core_cflags si_core_cflags_wo sb_core_cflags_wo ai_core_cflags_wo si_core_sflags sb_core_sflags ai_core_sflags si_iscoreup sb_iscoreup ai_iscoreup si_wrapperreg ai_wrap_reg si_corereg sb_corereg ai_corereg si_gci_chipstatus si_gci_get_functionsel si_gci_chipcontrol si_gci_set_functionsel si_gci_clear_functionsel si_gci_chipctrl_overrides snprintf getvar getintvar si_gci_gpio_status si_gci_handler_process si_gci_int_enable si_gci_output si_gci_input si_gci_indirect si_enable_device_wake si_pmu_chipcontrol printk si_gci_direct si_gci_reset si_muxenab si_swdenable si_pmu_corereg si_corereg_addr sb_corereg_addr ai_corereg_addr si_ldo_war osl_pci_write_config osl_delay si_core_disable sb_core_disable ai_core_disable si_core_reset sb_core_reset ai_core_reset si_corebist si_clock_rate si_chip_hostif si_read_pmu_autopll si_pmu_is_autoresetphyclk_disabled si_clock si_pmu_si_clock si_alp_clock si_pmu_alp_clock __arm_ioremap si_ilp_clock si_pmu_ilp_clock si_watchdog_msticks si_taclear si_clkctl_init si_clkctl_fast_pwrup_delay si_pmu_fast_pwrup_delay si_clkctl_xtal si_clkctl_cc si_watchdog si_watchdog_ms si_devpath osl_pci_bus osl_pci_slot strlen strncpy si_devpath_pcie osl_pcie_domain osl_pcie_bus si_coded_devpathvar memcmp si_getdevpathvar si_getdevpathintvar si_d11_devid si_corepciid si_getnvramflvar si_ccreg si_pciereg pcicore_pciereg si_pcieserdesreg pcicore_pcieserdesreg si_pci_pmeen pcicore_pmeen si_pci_pmestat pcicore_pmestat si_pci_pmeclr pcicore_pmeclr si_pci_pmestatclr pcicore_pmestatclr si_pcmcia_init osl_pcmcia_read_attr osl_pcmcia_write_attr si_pci_war16165 si_pcie_war_ovr_update pcie_war_ovr_aspm_update si_pcie_power_save_enable pcie_power_save_enable si_pcie_set_maxpayload_size pcie_set_maxpayload_size si_pcie_get_maxpayload_size pcie_get_maxpayload_size si_pcie_set_request_size pcie_set_request_size si_pcie_get_request_size pcie_get_request_size si_pcie_get_ssid pcie_get_ssid si_pcie_get_bar0 pcie_get_bar0 si_pcie_configspace_cache pcie_configspace_cache si_pcie_configspace_restore pcie_configspace_restore si_pcie_configspace_get pcie_configspace_get si_chippkg_set si_pcie_hw_L1SS_war pcie_hw_L1SS_war si_pci_up pcicore_up sb_set_initiator_to si_pci_sleep pcicore_sleep si_pci_down pcicore_down si_pci_setup si_pcieclkreq pcie_clkreq si_pcielcreg pcie_lcreg si_pcieltrenable pcie_ltrenable si_pcieobffenable pcie_obffenable si_pcieltr_reg pcie_ltr_reg si_pcieltrspacing_reg pcieltrspacing_reg si_pcieltrhysteresiscnt_reg pcieltrhysteresiscnt_reg si_pcie_set_error_injection pcie_set_error_injection si_pcie_set_L1substate pcie_set_L1substate si_pcie_get_L1substate pcie_get_L1substate si_pcie_readreg pcie_readreg si_pcie_writereg pcie_writereg si_pci_fixcfg pcicore_hwup si_dump_pcieinfo pcicore_dump_pcieinfo si_gpiosetcore si_gpiocontrol si_gpioouten si_gpioout si_gci_enable_gpio si_gci_host_wake_gpio_enable si_gci_host_wake_gpio_init si_gpioreserve si_gpiorelease si_gpioin si_gpiointpolarity si_gpiointmask si_gpioled si_gpiotimerval si_gpiopull si_gpioevent si_gpio_handler_register __memzero si_gpio_handler_unregister si_gpio_handler_process si_gpio_int_enable si_socdevram si_socdevram_remap_isenb si_socdevram_size si_socdevram_pkg si_socdevram_remap_size si_socram_size si_socram_srmem_size si_btcgpiowar si_chipcontrl_btshd0_4331 si_chipcontrl_restore si_chipcontrl_read si_chipcontrl_epa4331 si_chipcontrl_srom4360 si_chipcontrl_epa4331_wowl si_pll_reset si_pll_minresmask_reset si_epa_4313war si_clk_pmu_htavail_set si_pmu_minresmask_htavail_set si_pmu_synth_pwrsw_4313_war si_btcombo_p250_4313_war si_btc_enable_chipcontrol si_btcombo_43228_war si_deviceremoved si_is_sprom_available si_is_otp_disabled si_is_otp_powered si_pmu_is_otp_powered si_otp_power si_pmu_otp_power si_is_sprom_enabled si_pmu_is_sprom_enabled si_sprom_enable si_pmu_sprom_enable si_cis_source si_otp_fabid otp_read_word si_fabid si_get_sromctl si_set_sromctl si_core_wrapperreg si_update_masks si_pmu_res_minmax_update si_pmu_pllcontrol si_pmu_pllupd si_force_islanding si_pmu_res_req_timer_clr si_pmu_rfldo si_pmu_regcontrol si_pcie_set_ctrlreg pcie_set_ctrlreg si_survive_perst_war si_pcie_ltr_war pcie_ltr_war si_pcie_hw_LTR_war pcie_hw_LTR_war si_pciedev_reg_pm_clk_period pciedev_reg_pm_clk_period si_pciedev_crwlpciegen2 pciedev_crwlpciegen2 si_pcie_prep_D3 pciedev_prep_D3 si_corereg_ifup si_lowpwr_opt sb_scan ai_scan ai_enable_backplane_timeouts pcicore_init pcie_disable_TL_clk_gating pcie_set_L1_entry_time nvram_init srom_var_init si_pmu_init si_pmu_chip_init si_pmu_measure_alpclk si_pmu_pll_init si_pmu_res_init si_pmu_swreg_init pcicore_attach si_kattach si_attach si_clear_backplane_to ai_clear_backplane_to do_4360_pcie2_war