1/* 2 * Misc utility routines for accessing the SOC Interconnects 3 * of Broadcom HNBU chips. 4 * 5 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $Id: siutils.h 468310 2014-04-07 09:48:43Z $ 20 */ 21 22#ifndef _siutils_h_ 23#define _siutils_h_ 24 25#ifdef SR_DEBUG 26#include "wlioctl.h" 27#endif /* SR_DEBUG */ 28 29#if defined(WLC_HIGH) && !defined(WLC_LOW) 30#include "bcm_rpc.h" 31#endif 32 33/* 34 * Data structure to export all chip specific common variables 35 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach() 36 */ 37struct si_pub { 38 uint socitype; /* SOCI_SB, SOCI_AI */ 39 40 uint bustype; /* SI_BUS, PCI_BUS */ 41 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */ 42 uint buscorerev; /* buscore rev */ 43 uint buscoreidx; /* buscore index */ 44 int ccrev; /* chip common core rev */ 45 uint32 cccaps; /* chip common capabilities */ 46 uint32 cccaps_ext; /* chip common capabilities extension */ 47 int pmurev; /* pmu core rev */ 48 uint32 pmucaps; /* pmu capabilities */ 49 uint boardtype; /* board type */ 50 uint boardrev; /* board rev */ 51 uint boardvendor; /* board vendor */ 52 uint boardflags; /* board flags */ 53 uint boardflags2; /* board flags2 */ 54 uint chip; /* chip number */ 55 uint chiprev; /* chip revision */ 56 uint chippkg; /* chip package option */ 57 uint32 chipst; /* chip status */ 58 bool issim; /* chip is in simulation or emulation */ 59 uint socirev; /* SOC interconnect rev */ 60 bool pci_pr32414; 61 62#if defined(WLC_HIGH) && !defined(WLC_LOW) 63 rpc_info_t *rpc; 64#endif 65#ifdef SI_ENUM_BASE_VARIABLE 66 uint32 si_enum_base; 67#endif /* SI_ENUM_BASE_VARIABLE */ 68}; 69 70/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver 71 * for monolithic driver, it is readonly to prevent accident change 72 */ 73#if defined(WLC_HIGH) && !defined(WLC_LOW) 74typedef struct si_pub si_t; 75#else 76typedef const struct si_pub si_t; 77#endif 78 79/* 80 * Many of the routines below take an 'sih' handle as their first arg. 81 * Allocate this by calling si_attach(). Free it by calling si_detach(). 82 * At any one time, the sih is logically focused on one particular si core 83 * (the "current core"). 84 * Use si_setcore() or si_setcoreidx() to change the association to another core. 85 */ 86#define SI_OSH NULL /* Use for si_kattach when no osh is available */ 87 88#define BADIDX (SI_MAXCORES + 1) 89 90/* clkctl xtal what flags */ 91#define XTAL 0x1 /* primary crystal oscillator (2050) */ 92#define PLL 0x2 /* main chip pll */ 93 94/* clkctl clk mode */ 95#define CLK_FAST 0 /* force fast (pll) clock */ 96#define CLK_DYNAMIC 2 /* enable dynamic clock control */ 97 98/* GPIO usage priorities */ 99#define GPIO_DRV_PRIORITY 0 /* Driver */ 100#define GPIO_APP_PRIORITY 1 /* Application */ 101#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */ 102 103/* GPIO pull up/down */ 104#define GPIO_PULLUP 0 105#define GPIO_PULLDN 1 106 107/* GPIO event regtype */ 108#define GPIO_REGEVT 0 /* GPIO register event */ 109#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */ 110#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */ 111 112/* device path */ 113#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */ 114 115/* SI routine enumeration: to be used by update function with multiple hooks */ 116#define SI_DOATTACH 1 117#define SI_PCIDOWN 2 118#define SI_PCIUP 3 119 120#ifdef SR_DEBUG 121#define PMU_RES 31 122#endif /* SR_DEBUG */ 123 124#if defined(BCMQT) 125#define ISSIM_ENAB(sih) TRUE 126#else 127#define ISSIM_ENAB(sih) FALSE 128#endif 129 130/* PMU clock/power control */ 131#if defined(BCMPMUCTL) 132#define PMUCTL_ENAB(sih) (BCMPMUCTL) 133#else 134#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) 135#endif 136 137#define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \ 138 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0) 139 140/* chipcommon clock/power control (exclusive with PMU's) */ 141#if defined(BCMPMUCTL) && BCMPMUCTL 142#define CCCTL_ENAB(sih) (0) 143#define CCPLL_ENAB(sih) (0) 144#else 145#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) 146#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) 147#endif 148 149typedef void (*gpio_handler_t)(uint32 stat, void *arg); 150typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg); 151/* External BT Coex enable mask */ 152#define CC_BTCOEX_EN_MASK 0x01 153/* External PA enable mask */ 154#define GPIO_CTRL_EPA_EN_MASK 0x40 155/* WL/BT control enable mask */ 156#define GPIO_CTRL_5_6_EN_MASK 0x60 157#define GPIO_CTRL_7_6_EN_MASK 0xC0 158#define GPIO_OUT_7_EN_MASK 0x80 159 160 161#if defined(WLOFFLD) 162/* CR4 specific defines used by the host driver */ 163#define SI_CR4_CAP (0x04) 164#define SI_CR4_BANKIDX (0x40) 165#define SI_CR4_BANKINFO (0x44) 166#define SI_CR4_BANKPDA (0x4C) 167 168#define ARMCR4_TCBBNB_MASK 0xf0 169#define ARMCR4_TCBBNB_SHIFT 4 170#define ARMCR4_TCBANB_MASK 0xf 171#define ARMCR4_TCBANB_SHIFT 0 172 173#define SICF_CPUHALT (0x0020) 174#define ARMCR4_BSZ_MASK 0x3f 175#define ARMCR4_BSZ_MULT 8192 176#endif 177 178#include <osl_decl.h> 179/* === exported functions === */ 180extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 181 void *sdh, char **vars, uint *varsz); 182extern si_t *si_kattach(osl_t *osh); 183extern void si_detach(si_t *sih); 184extern bool si_pci_war16165(si_t *sih); 185 186extern uint si_corelist(si_t *sih, uint coreid[]); 187extern uint si_coreid(si_t *sih); 188extern uint si_flag(si_t *sih); 189extern uint si_flag_alt(si_t *sih); 190extern uint si_intflag(si_t *sih); 191extern uint si_coreidx(si_t *sih); 192extern uint si_coreunit(si_t *sih); 193extern uint si_corevendor(si_t *sih); 194extern uint si_corerev(si_t *sih); 195extern void *si_osh(si_t *sih); 196extern void si_setosh(si_t *sih, osl_t *osh); 197extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 198extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val); 199extern uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff); 200extern void *si_coreregs(si_t *sih); 201extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 202extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val); 203extern void *si_wrapperregs(si_t *sih); 204extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); 205extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 206extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); 207#ifdef WLC_HIGH_ONLY 208extern bool wlc_bmac_iscoreup(si_t *sih); 209#define si_iscoreup(sih) wlc_bmac_iscoreup(sih) 210#else 211extern bool si_iscoreup(si_t *sih); 212#endif /* __CONFIG_USBAP__ */ 213extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit); 214extern void *si_setcoreidx(si_t *sih, uint coreidx); 215extern void *si_setcore(si_t *sih, uint coreid, uint coreunit); 216#ifdef WLC_LOW 217extern uint si_corereg_ifup(si_t *sih, uint core_id, uint regoff, uint mask, uint val); 218extern void si_lowpwr_opt(si_t *sih); 219#endif /* WLC_LOW */ 220extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val); 221extern void si_restore_core(si_t *sih, uint coreid, uint intr_val); 222extern int si_numaddrspaces(si_t *sih); 223extern uint32 si_addrspace(si_t *sih, uint asidx); 224extern uint32 si_addrspacesize(si_t *sih, uint asidx); 225extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 226extern int si_corebist(si_t *sih); 227extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 228extern void si_core_disable(si_t *sih, uint32 bits); 229extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m); 230extern uint si_chip_hostif(si_t *sih); 231extern bool si_read_pmu_autopll(si_t *sih); 232extern uint32 si_clock(si_t *sih); 233extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */ 234extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */ 235extern void si_pci_setup(si_t *sih, uint coremask); 236extern void si_pcmcia_init(si_t *sih); 237extern void si_setint(si_t *sih, int siflag); 238extern bool si_backplane64(si_t *sih); 239extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, 240 void *intrsenabled_fn, void *intr_arg); 241extern void si_deregister_intr_callback(si_t *sih); 242extern void si_clkctl_init(si_t *sih); 243extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih); 244extern bool si_clkctl_cc(si_t *sih, uint mode); 245extern int si_clkctl_xtal(si_t *sih, uint what, bool on); 246extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val); 247extern void si_btcgpiowar(si_t *sih); 248extern bool si_deviceremoved(si_t *sih); 249extern uint32 si_socram_size(si_t *sih); 250extern uint32 si_socdevram_size(si_t *sih); 251extern uint32 si_socram_srmem_size(si_t *sih); 252extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap); 253extern bool si_socdevram_pkg(si_t *sih); 254extern bool si_socdevram_remap_isenb(si_t *sih); 255extern uint32 si_socdevram_remap_size(si_t *sih); 256 257extern void si_watchdog(si_t *sih, uint ticks); 258extern void si_watchdog_ms(si_t *sih, uint32 ms); 259extern uint32 si_watchdog_msticks(void); 260extern void *si_gpiosetcore(si_t *sih); 261extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority); 262extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority); 263extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority); 264extern uint32 si_gpioin(si_t *sih); 265extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority); 266extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority); 267extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val); 268extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority); 269extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority); 270extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val); 271extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val); 272extern uint32 si_gpio_int_enable(si_t *sih, bool enable); 273extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode); 274extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value); 275extern uint8 si_gci_host_wake_gpio_init(si_t *sih); 276extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state); 277 278/* GPIO event handlers */ 279extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg); 280extern void si_gpio_handler_unregister(si_t *sih, void* gpioh); 281extern void si_gpio_handler_process(si_t *sih); 282 283/* GCI interrupt handlers */ 284extern void si_gci_handler_process(si_t *sih); 285 286/* GCI GPIO event handlers */ 287extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts, 288 gci_gpio_handler_t cb, void *arg); 289extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i); 290extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value); 291 292/* Wake-on-wireless-LAN (WOWL) */ 293extern bool si_pci_pmecap(si_t *sih); 294extern bool si_pci_fastpmecap(osl_t *osh); 295extern bool si_pci_pmestat(si_t *sih); 296extern void si_pci_pmeclr(si_t *sih); 297extern void si_pci_pmeen(si_t *sih); 298extern void si_pci_pmestatclr(si_t *sih); 299extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset); 300extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val); 301 302 303 304extern uint16 si_d11_devid(si_t *sih); 305extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice, 306 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader); 307 308#if defined(BCMECICOEX) 309extern bool si_eci(si_t *sih); 310extern int si_eci_init(si_t *sih); 311extern void si_eci_notify_bt(si_t *sih, uint32 mask, uint32 val, bool interrupt); 312extern bool si_seci(si_t *sih); 313extern void* si_seci_init(si_t *sih, uint8 seci_mode); 314extern void* si_gci_init(si_t *sih); 315extern void si_seci_down(si_t *sih); 316extern void si_seci_upd(si_t *sih, bool enable); 317extern bool si_gci(si_t *sih); 318#else 319#define si_eci(sih) 0 320static INLINE void * si_eci_init(si_t *sih) {return NULL;} 321#define si_eci_notify_bt(sih, type, val) (0) 322#define si_seci(sih) 0 323#define si_seci_upd(sih, a) do {} while (0) 324static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;} 325static INLINE void * si_gci_init(si_t *sih) {return NULL;} 326#define si_seci_down(sih) do {} while (0) 327#define si_gci(sih) 0 328#endif /* BCMECICOEX */ 329 330/* OTP status */ 331extern bool si_is_otp_disabled(si_t *sih); 332extern bool si_is_otp_powered(si_t *sih); 333extern void si_otp_power(si_t *sih, bool on, uint32* min_res_mask); 334 335/* SPROM availability */ 336extern bool si_is_sprom_available(si_t *sih); 337extern bool si_is_sprom_enabled(si_t *sih); 338extern void si_sprom_enable(si_t *sih, bool enable); 339#ifdef SI_SPROM_PROBE 340extern void si_sprom_init(si_t *sih); 341#endif /* SI_SPROM_PROBE */ 342 343/* OTP/SROM CIS stuff */ 344extern int si_cis_source(si_t *sih); 345#define CIS_DEFAULT 0 346#define CIS_SROM 1 347#define CIS_OTP 2 348 349/* Fab-id information */ 350#define DEFAULT_FAB 0x0 /* Original/first fab used for this chip */ 351#define CSM_FAB7 0x1 /* CSM Fab7 chip */ 352#define TSMC_FAB12 0x2 /* TSMC Fab12/Fab14 chip */ 353#define SMIC_FAB4 0x3 /* SMIC Fab4 chip */ 354 355extern int BCMINITFN(si_otp_fabid)(si_t *sih, uint16 *fabid, bool rw); 356extern uint16 BCMATTACHFN(si_fabid)(si_t *sih); 357 358/* 359 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ. 360 * The returned path is NULL terminated and has trailing '/'. 361 * Return 0 on success, nonzero otherwise. 362 */ 363extern int si_devpath(si_t *sih, char *path, int size); 364extern int si_devpath_pcie(si_t *sih, char *path, int size); 365/* Read variable with prepending the devpath to the name */ 366extern char *si_getdevpathvar(si_t *sih, const char *name); 367extern int si_getdevpathintvar(si_t *sih, const char *name); 368extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name); 369 370 371extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val); 372extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val); 373extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val); 374extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val); 375extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val); 376extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val); 377extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val); 378extern void si_pcie_set_error_injection(si_t *sih, uint32 mode); 379extern void si_pcie_set_L1substate(si_t *sih, uint32 substate); 380#ifndef BCM_BOOTLOADER 381extern uint32 si_pcie_get_L1substate(si_t *sih); 382#endif /* BCM_BOOTLOADER */ 383extern void si_war42780_clkreq(si_t *sih, bool clkreq); 384extern void si_pci_down(si_t *sih); 385extern void si_pci_up(si_t *sih); 386#ifdef WLC_HIGH_ONLY 387#define si_pci_sleep(sih) do { ASSERT(0); } while (0) 388#define si_pcie_war_ovr_update(sih, aspm) do { ASSERT(0); } while (0) 389#define si_pcie_power_save_enable(sih, up) do { ASSERT(0); } while (0) 390#else 391extern void si_pci_sleep(si_t *sih); 392extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm); 393extern void si_pcie_power_save_enable(si_t *sih, bool enable); 394#endif /* __CONFIG_USBAP__ */ 395extern void si_pcie_extendL1timer(si_t *sih, bool extend); 396extern int si_pci_fixcfg(si_t *sih); 397extern bool si_ldo_war(si_t *sih, uint devid); 398extern void si_chippkg_set(si_t *sih, uint); 399 400extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on); 401extern void si_chipcontrl_restore(si_t *sih, uint32 val); 402extern uint32 si_chipcontrl_read(si_t *sih); 403extern void si_chipcontrl_epa4331(si_t *sih, bool on); 404extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl); 405extern void si_chipcontrl_srom4360(si_t *sih, bool on); 406/* Enable BT-COEX & Ex-PA for 4313 */ 407extern void si_epa_4313war(si_t *sih); 408extern void si_btc_enable_chipcontrol(si_t *sih); 409/* BT/WL selection for 4313 bt combo >= P250 boards */ 410extern void si_btcombo_p250_4313_war(si_t *sih); 411extern void si_btcombo_43228_war(si_t *sih); 412extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear); 413extern void si_pmu_synth_pwrsw_4313_war(si_t *sih); 414extern uint si_pll_reset(si_t *sih); 415/* === debug routines === */ 416 417extern bool si_taclear(si_t *sih, bool details); 418 419#if defined(BCMDBG_DUMP) || defined(WLTEST) 420struct bcmstrbuf; 421extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b); 422#endif 423 424#if defined(BCMDBG_DUMP) 425extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b); 426#endif 427 428extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 429extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type); 430#ifdef SR_DEBUG 431extern void si_dump_pmu(si_t *sih, void *pmu_var); 432extern void si_pmu_keep_on(si_t *sih, int32 int_val); 433extern uint32 si_pmu_keep_on_get(si_t *sih); 434extern uint32 si_power_island_set(si_t *sih, uint32 int_val); 435extern uint32 si_power_island_get(si_t *sih); 436#endif /* SR_DEBUG */ 437extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val); 438extern void si_pcie_set_request_size(si_t *sih, uint16 size); 439extern uint16 si_pcie_get_request_size(si_t *sih); 440extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size); 441extern uint16 si_pcie_get_maxpayload_size(si_t *sih); 442extern uint16 si_pcie_get_ssid(si_t *sih); 443extern uint32 si_pcie_get_bar0(si_t *sih); 444extern int si_pcie_configspace_cache(si_t *sih); 445extern int si_pcie_configspace_restore(si_t *sih); 446extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size); 447 448#ifndef DONGLEBUILD 449char *si_getnvramflvar(si_t *sih, const char *name); 450#endif /* DONGLEBUILD */ 451 452extern void si_muxenab(si_t *sih, uint32 w); 453extern void si_clear_backplane_to(si_t *sih); 454 455#if defined(WLOFFLD) 456extern uint32 si_tcm_size(si_t *sih); 457extern bool si_has_flops(si_t *sih); 458#endif 459 460extern int si_set_sromctl(si_t *sih, uint32 value); 461extern uint32 si_get_sromctl(si_t *sih); 462 463extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val); 464extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val); 465extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val); 466extern uint32 si_gci_input(si_t *sih, uint reg); 467extern uint32 si_gci_int_enable(si_t *sih, bool enable); 468extern void si_gci_reset(si_t *sih); 469#ifdef BCMLTECOEX 470extern void si_ercx_init(si_t *sih, uint32 ltecx_mux); 471extern void si_wci2_init(si_t *sih, uint baudrate, uint32 ltecx_mux); 472extern void si_gci_seci_init(si_t *sih); 473#endif /* BCMLTECOEX */ 474extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel); 475extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin); 476extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel); 477extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos); 478extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); 479extern uint32 si_gci_chipstatus(si_t *sih, uint reg); 480#ifndef SI_ENUM_BASE_VARIABLE /* don't bother supporting variable enum base */ 481extern uint16 si_cc_get_reg16(uint32 reg_offs); 482extern uint32 si_cc_get_reg32(uint32 reg_offs); 483extern uint32 si_cc_set_reg32(uint32 reg_offs, uint32 val); 484extern uint32 si_gci_preinit_upd_indirect(uint32 regidx, uint32 setval, uint32 mask); 485#endif /* SI_ENUM_BASE_VARIABLE */ 486extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status); 487extern void si_swdenable(si_t *sih, uint32 swdflag); 488 489#define CHIPCTRLREG1 0x1 490#define CHIPCTRLREG2 0x2 491#define CHIPCTRLREG3 0x3 492#define CHIPCTRLREG4 0x4 493#define CHIPCTRLREG5 0x5 494#define MINRESMASKREG 0x618 495#define MAXRESMASKREG 0x61c 496#define CHIPCTRLADDR 0x650 497#define CHIPCTRLDATA 0x654 498#define RSRCTABLEADDR 0x620 499#define RSRCUPDWNTIME 0x628 500#define PMUREG_RESREQ_MASK 0x68c 501 502void si_update_masks(si_t *sih); 503void si_force_islanding(si_t *sih, bool enable); 504extern uint32 si_pmu_res_req_timer_clr(si_t *sih); 505extern void si_pmu_rfldo(si_t *sih, bool on); 506extern void si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 spert_val); 507extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask, uint32 spert_val); 508extern void si_pcie_ltr_war(si_t *sih); 509extern void si_pcie_hw_LTR_war(si_t *sih); 510extern void si_pcie_hw_L1SS_war(si_t *sih); 511extern void si_pciedev_crwlpciegen2(si_t *sih); 512extern void si_pcie_prep_D3(si_t *sih, bool enter_D3); 513extern void si_pciedev_reg_pm_clk_period(si_t *sih); 514 515 516/* Macro to enable clock gating changes in different cores */ 517#define MEM_CLK_GATE_BIT 5 518#define GCI_CLK_GATE_BIT 18 519 520#define USBAPP_CLK_BIT 0 521#define PCIE_CLK_BIT 3 522#define ARMCR4_DBG_CLK_BIT 4 523#define SAMPLE_SYNC_CLK_BIT 17 524#define PCIE_TL_CLK_BIT 18 525#define HQ_REQ_BIT 24 526#define PLL_DIV2_BIT_START 9 527#define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START) 528#define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START) 529 530#if defined(WLTEST) && defined(DONGLEBUILD) 531#define UART_BAUDBASE_DIVIDER 16 532#define UART_REG_BIT_MASK 0xFF 533#define UART_INTERFACE_OFFSET 0x100 534#define UART_REG_ADD_GET(cc, intf, reg) ((uint8 *)(&cc->uart0data + reg + \ 535 intf * UART_INTERFACE_OFFSET)) 536 537extern int32 si_serial_baudrate_get(si_t *sih, void* param, void* arg); 538extern int32 si_serial_baudrate_set(si_t *sih, void* serialParam); 539#endif /* WLTEST && DONGLEBUILD */ 540 541#define PMUREG(si, member) \ 542 (AOB_ENAB(si) ? \ 543 si_corereg_addr(si, si_findcoreidx(si, PMU_CORE_ID, 0), \ 544 OFFSETOF(pmuregs_t, member)): \ 545 si_corereg_addr(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member))) 546 547#define pmu_corereg(si, cc_idx, member, mask, val) \ 548 (AOB_ENAB(si) ? \ 549 si_pmu_corereg(si, si_findcoreidx(sih, PMU_CORE_ID, 0), \ 550 OFFSETOF(pmuregs_t, member), mask, val): \ 551 si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), mask, val)) 552 553/* GCI Constants */ 554#define ALLONES_32 0xFFFFFFFF 555#define GCI_CORECTRL_SECI_RST 0x1 556#define GCI_CORECTRL_SECI_EN 0x4 557#define GCI_CORECTRL_MODE_OFFSET 4 558#define GCI_CORECTRL_MODE_UART (0x0 << GCI_CORECTRL_MODE_OFFSET) 559#define GCI_CORECTRL_MODE_SECI (0x1 << GCI_CORECTRL_MODE_OFFSET) 560#define GCI_CORECTRL_MODE_BTSIG (0x2 << GCI_CORECTRL_MODE_OFFSET) 561#define GCI_CORECTRL_MODE_GPIO (0x3 << GCI_CORECTRL_MODE_OFFSET) 562#define GCI_CORECTRL_SCS_OFFSET 24 /* SECI Clk Stretch */ 563#define GCI_CORECTRL_SCS_DEF (0x19 << GCI_CORECTRL_SCS_OFFSET) 564 565/* GCI bit definitions - From LTE */ 566#define GCI_FROMLTE_FRAMESYNC 0x1 567/* End - GCI Constants */ 568 569#endif /* _siutils_h_ */ 570