1/* 2 * Table that encodes the srom formats for PCI/PCIe NICs. 3 * 4 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: bcmsrom_tbl.h 502763 2014-09-16 02:48:59Z $ 19 */ 20 21#ifndef _bcmsrom_tbl_h_ 22#define _bcmsrom_tbl_h_ 23 24#include "sbpcmcia.h" 25#include "wlioctl.h" 26 27typedef struct { 28 const char *name; 29 uint32 revmask; 30 uint32 flags; 31 uint16 off; 32 uint16 mask; 33} sromvar_t; 34 35#define SRFL_MORE 1 /* value continues as described by the next entry */ 36#define SRFL_NOFFS 2 /* value bits can't be all one's */ 37#define SRFL_PRHEX 4 /* value is in hexdecimal format */ 38#define SRFL_PRSIGN 8 /* value is in signed decimal format */ 39#define SRFL_CCODE 0x10 /* value is in country code format */ 40#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */ 41#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */ 42#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */ 43#define SRFL_ARRAY 0x100 /* value is in an array. All elements EXCEPT FOR THE LAST 44 * ONE in the array should have this flag set. 45 */ 46 47 48#define SROM_DEVID_PCIE 48 49 50/* Assumptions: 51 * - Ethernet address spans across 3 consective words 52 * 53 * Table rules: 54 * - Add multiple entries next to each other if a value spans across multiple words 55 * (even multiple fields in the same word) with each entry except the last having 56 * it's SRFL_MORE bit set. 57 * - Ethernet address entry does not follow above rule and must not have SRFL_MORE 58 * bit set. Its SRFL_ETHADDR bit implies it takes multiple words. 59 * - The last entry's name field must be NULL to indicate the end of the table. Other 60 * entries must have non-NULL name. 61 */ 62 63static const sromvar_t BCMATTACHDATA(pci_sromvars)[] = { 64#if defined(CABLECPE) 65 {"devid", 0xffffff00, SRFL_PRHEX, PCI_F0DEVID, 0xffff}, 66#elif defined(BCMPCIEDEV) && defined(BCMPCIEDEV_ENABLED) 67 {"devid", 0xffffff00, SRFL_PRHEX, SROM_DEVID_PCIE, 0xffff}, 68#else 69 {"devid", 0xffffff00, SRFL_PRHEX|SRFL_NOVAR, PCI_F0DEVID, 0xffff}, 70#endif 71 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, 72 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, 73 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, 74 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff}, 75 {"boardflags", 0x00000004, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff}, 76 {"", 0, 0, SROM_BFL2, 0xffff}, 77 {"boardflags", 0x00000008, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff}, 78 {"", 0, 0, SROM3_BFL2, 0xffff}, 79 {"boardflags", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL0, 0xffff}, 80 {"", 0, 0, SROM4_BFL1, 0xffff}, 81 {"boardflags", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL0, 0xffff}, 82 {"", 0, 0, SROM5_BFL1, 0xffff}, 83 {"boardflags", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL0, 0xffff}, 84 {"", 0, 0, SROM8_BFL1, 0xffff}, 85 {"boardflags2", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL2, 0xffff}, 86 {"", 0, 0, SROM4_BFL3, 0xffff}, 87 {"boardflags2", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL2, 0xffff}, 88 {"", 0, 0, SROM5_BFL3, 0xffff}, 89 {"boardflags2", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL2, 0xffff}, 90 {"", 0, 0, SROM8_BFL3, 0xffff}, 91 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, 92 {"subvid", 0xfffffffc, SRFL_PRHEX, SROM_SVID, 0xffff}, 93 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, 94 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, 95 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, 96 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff}, 97 {"boardnum", 0x00000700, 0, SROM8_MACLO, 0xffff}, 98 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK}, 99 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00}, 100 {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff}, 101 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff}, 102 {"regrev", 0x00000700, 0, SROM8_REGREV, 0x00ff}, 103 {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff}, 104 {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00}, 105 {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff}, 106 {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00}, 107 {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff}, 108 {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00}, 109 {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff}, 110 {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00}, 111 {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff}, 112 {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00}, 113 {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff}, 114 {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00}, 115 {"ledbh0", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, 116 {"ledbh1", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, 117 {"ledbh2", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, 118 {"ledbh3", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, 119 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff}, 120 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff}, 121 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff}, 122 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff}, 123 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff}, 124 {"pa0b0", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, 125 {"pa0b1", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, 126 {"pa0b2", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, 127 {"pa0itssit", 0x00000700, 0, SROM8_W0_ITTMAXP, 0xff00}, 128 {"pa0maxpwr", 0x00000700, 0, SROM8_W0_ITTMAXP, 0x00ff}, 129 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff}, 130 {"opo", 0x00000700, 0, SROM8_2G_OFDMPO, 0x00ff}, 131 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK}, 132 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff}, 133 {"aa2g", 0x00000700, 0, SROM8_AA, 0x00ff}, 134 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK}, 135 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00}, 136 {"aa5g", 0x00000700, 0, SROM8_AA, 0xff00}, 137 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff}, 138 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00}, 139 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff}, 140 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00}, 141 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff}, 142 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00}, 143 {"ag0", 0x00000700, 0, SROM8_AG10, 0x00ff}, 144 {"ag1", 0x00000700, 0, SROM8_AG10, 0xff00}, 145 {"ag2", 0x00000700, 0, SROM8_AG32, 0x00ff}, 146 {"ag3", 0x00000700, 0, SROM8_AG32, 0xff00}, 147 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff}, 148 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff}, 149 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff}, 150 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff}, 151 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff}, 152 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff}, 153 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff}, 154 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff}, 155 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff}, 156 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00}, 157 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00}, 158 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00}, 159 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff}, 160 {"pa1b0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, 161 {"pa1b1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, 162 {"pa1b2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, 163 {"pa1lob0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff}, 164 {"pa1lob1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff}, 165 {"pa1lob2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff}, 166 {"pa1hib0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff}, 167 {"pa1hib1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff}, 168 {"pa1hib2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff}, 169 {"pa1itssit", 0x00000700, 0, SROM8_W1_ITTMAXP, 0xff00}, 170 {"pa1maxpwr", 0x00000700, 0, SROM8_W1_ITTMAXP, 0x00ff}, 171 {"pa1lomaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0xff00}, 172 {"pa1himaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, 173 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800}, 174 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700}, 175 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0}, 176 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f}, 177 {"bxa2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x1800}, 178 {"rssisav2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x0700}, 179 {"rssismc2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x00f0}, 180 {"rssismf2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x000f}, 181 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800}, 182 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700}, 183 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0}, 184 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f}, 185 {"bxa5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x1800}, 186 {"rssisav5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x0700}, 187 {"rssismc5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x00f0}, 188 {"rssismf5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x000f}, 189 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff}, 190 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00}, 191 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff}, 192 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00}, 193 {"tri2g", 0x00000700, 0, SROM8_TRI52G, 0x00ff}, 194 {"tri5g", 0x00000700, 0, SROM8_TRI52G, 0xff00}, 195 {"tri5gl", 0x00000700, 0, SROM8_TRI5GHL, 0x00ff}, 196 {"tri5gh", 0x00000700, 0, SROM8_TRI5GHL, 0xff00}, 197 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff}, 198 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00}, 199 {"rxpo2g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, 200 {"rxpo5g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, 201 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK}, 202 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK}, 203 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK}, 204 {"txchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK}, 205 {"rxchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK}, 206 {"antswitch", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK}, 207 {"tssipos2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK}, 208 {"extpagain2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK}, 209 {"pdetrange2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK}, 210 {"triso2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK}, 211 {"antswctl2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK}, 212 {"tssipos5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK}, 213 {"extpagain5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK}, 214 {"pdetrange5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK}, 215 {"triso5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK}, 216 {"antswctl5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK}, 217 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, 218 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00}, 219 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff}, 220 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00}, 221 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff}, 222 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00}, 223 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff}, 224 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00}, 225 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff}, 226 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00}, 227 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff}, 228 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00}, 229 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff}, 230 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00}, 231 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff}, 232 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00}, 233 234 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff}, 235 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff}, 236 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff}, 237 {"ccode", 0x00000700, SRFL_CCODE, SROM8_CCODE, 0xffff}, 238 {"macaddr", 0x00000700, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, 239 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff}, 240 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff}, 241 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff}, 242 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff}, 243 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff}, 244 {"leddc", 0x00000700, SRFL_NOFFS|SRFL_LEDDC, SROM8_LEDDC, 0xffff}, 245 {"leddc", 0x000000e0, SRFL_NOFFS|SRFL_LEDDC, SROM5_LEDDC, 0xffff}, 246 {"leddc", 0x00000010, SRFL_NOFFS|SRFL_LEDDC, SROM4_LEDDC, 0xffff}, 247 {"leddc", 0x00000008, SRFL_NOFFS|SRFL_LEDDC, SROM3_LEDDC, 0xffff}, 248 249 {"tempthresh", 0x00000700, 0, SROM8_THERMAL, 0xff00}, 250 {"tempoffset", 0x00000700, 0, SROM8_THERMAL, 0x00ff}, 251 {"rawtempsense", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff}, 252 {"measpower", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00}, 253 {"tempsense_slope", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x00ff}, 254 {"tempcorrx", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00}, 255 {"tempsense_option", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x0300}, 256 {"freqoffset_corr", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x000f}, 257 {"iqcal_swp_dis", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010}, 258 {"hw_iqcal_en", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020}, 259 {"elna2g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0x00ff}, 260 {"elna5g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0xff00}, 261 {"phycal_tempdelta", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff}, 262 {"temps_period", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x0f00}, 263 {"temps_hysteresis", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0xf000}, 264 {"measpower1", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x007f}, 265 {"measpower2", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x3f80}, 266 267 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff}, 268 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, 269 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff}, 270 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff}, 271 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff}, 272 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff}, 273 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff}, 274 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff}, 275 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff}, 276 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff}, 277 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, 278 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, 279 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, 280 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff}, 281 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff}, 282 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, 283 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, 284 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, 285 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff}, 286 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff}, 287 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff}, 288 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff}, 289 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff}, 290 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff}, 291 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff}, 292 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff}, 293 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff}, 294 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff}, 295 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff}, 296 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff}, 297 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff}, 298 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff}, 299 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff}, 300 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff}, 301 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff}, 302 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff}, 303 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff}, 304 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff}, 305 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff}, 306 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff}, 307 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff}, 308 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff}, 309 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff}, 310 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff}, 311 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff}, 312 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff}, 313 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff}, 314 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff}, 315 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff}, 316 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff}, 317 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, 318 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, 319 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, 320 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff}, 321 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff}, 322 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff}, 323 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff}, 324 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff}, 325 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff}, 326 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff}, 327 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff}, 328 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff}, 329 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff}, 330 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff}, 331 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff}, 332 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff}, 333 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff}, 334 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff}, 335 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff}, 336 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff}, 337 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff}, 338 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff}, 339 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff}, 340 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff}, 341 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff}, 342 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff}, 343 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff}, 344 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff}, 345 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff}, 346 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, 347 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, 348 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, 349 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff}, 350 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff}, 351 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff}, 352 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff}, 353 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff}, 354 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff}, 355 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff}, 356 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff}, 357 358 /* power per rate from sromrev 9 */ 359 {"cckbw202gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20, 0xffff}, 360 {"cckbw20ul2gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20UL, 0xffff}, 361 {"legofdmbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20, 0xffff}, 362 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff}, 363 {"legofdmbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, 0xffff}, 364 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff}, 365 {"legofdmbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, 0xffff}, 366 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff}, 367 {"legofdmbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, 0xffff}, 368 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff}, 369 {"legofdmbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, 0xffff}, 370 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff}, 371 {"legofdmbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, 0xffff}, 372 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff}, 373 {"legofdmbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, 0xffff}, 374 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff}, 375 {"legofdmbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, 0xffff}, 376 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff}, 377 {"mcsbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff}, 378 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff}, 379 {"mcsbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff}, 380 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff}, 381 {"mcsbw402gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff}, 382 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff}, 383 {"mcsbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff}, 384 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff}, 385 {"mcsbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, 0xffff}, 386 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff}, 387 {"mcsbw405glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff}, 388 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff}, 389 {"mcsbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff}, 390 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff}, 391 {"mcsbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, 0xffff}, 392 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff}, 393 {"mcsbw405gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff}, 394 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff}, 395 {"mcsbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff}, 396 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff}, 397 {"mcsbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, 0xffff}, 398 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff}, 399 {"mcsbw405ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff}, 400 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff}, 401 {"mcs32po", 0x00000600, 0, SROM9_PO_MCS32, 0xffff}, 402 {"legofdm40duppo", 0x00000600, 0, SROM9_PO_LOFDM40DUP, 0xffff}, 403 {"pcieingress_war", 0x00000700, 0, SROM8_PCIEINGRESS_WAR, 0xf}, 404 {"eu_edthresh2g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0x00ff}, 405 {"eu_edthresh5g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0xff00}, 406 {"eu_edthresh2g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0x00ff}, 407 {"eu_edthresh5g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0xff00}, 408 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f}, 409 {"rxgainerr2ga1", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x07c0}, 410 {"rxgainerr2ga2", 0x00000700, 0, SROM8_RXGAINERR_2G, 0xf800}, 411 {"rxgainerr5gla0", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x003f}, 412 {"rxgainerr5gla1", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x07c0}, 413 {"rxgainerr5gla2", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0xf800}, 414 {"rxgainerr5gma0", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x003f}, 415 {"rxgainerr5gma1", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x07c0}, 416 {"rxgainerr5gma2", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0xf800}, 417 {"rxgainerr5gha0", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x003f}, 418 {"rxgainerr5gha1", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x07c0}, 419 {"rxgainerr5gha2", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0xf800}, 420 {"rxgainerr5gua0", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x003f}, 421 {"rxgainerr5gua1", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x07c0}, 422 {"rxgainerr5gua2", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0xf800}, 423 {"sar2g", 0x00000600, 0, SROM9_SAR, 0x00ff}, 424 {"sar5g", 0x00000600, 0, SROM9_SAR, 0xff00}, 425 {"noiselvl2ga0", 0x00000700, 0, SROM8_NOISELVL_2G, 0x001f}, 426 {"noiselvl2ga1", 0x00000700, 0, SROM8_NOISELVL_2G, 0x03e0}, 427 {"noiselvl2ga2", 0x00000700, 0, SROM8_NOISELVL_2G, 0x7c00}, 428 {"noiselvl5gla0", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x001f}, 429 {"noiselvl5gla1", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x03e0}, 430 {"noiselvl5gla2", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x7c00}, 431 {"noiselvl5gma0", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x001f}, 432 {"noiselvl5gma1", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x03e0}, 433 {"noiselvl5gma2", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x7c00}, 434 {"noiselvl5gha0", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x001f}, 435 {"noiselvl5gha1", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x03e0}, 436 {"noiselvl5gha2", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x7c00}, 437 {"noiselvl5gua0", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x001f}, 438 {"noiselvl5gua1", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x03e0}, 439 {"noiselvl5gua2", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x7c00}, 440 {"noisecaloffset", 0x00000300, 0, SROM8_NOISECALOFFSET, 0x00ff}, 441 {"noisecaloffset5g", 0x00000300, 0, SROM8_NOISECALOFFSET, 0xff00}, 442 {"subband5gver", 0x00000700, 0, SROM8_SUBBAND_PPR, 0x7}, 443 444 {"cckPwrOffset", 0x00000400, 0, SROM10_CCKPWROFFSET, 0xffff}, 445 {"eu_edthresh2g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0x00ff}, 446 {"eu_edthresh5g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0xff00}, 447 /* swctrlmap_2g array, note that the last element doesn't have SRFL_ARRAY flag set */ 448 {"swctrlmap_2g", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G, 0xffff}, 449 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 1, 0xffff}, 450 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 2, 0xffff}, 451 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 3, 0xffff}, 452 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 4, 0xffff}, 453 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 5, 0xffff}, 454 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 6, 0xffff}, 455 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 7, 0xffff}, 456 {"", 0x00000400, SRFL_PRHEX, SROM10_SWCTRLMAP_2G + 8, 0xffff}, 457 458 /* sromrev 11 */ 459 {"boardflags3", 0xfffff800, SRFL_PRHEX|SRFL_MORE, SROM11_BFL4, 0xffff}, 460 {"", 0, 0, SROM11_BFL5, 0xffff}, 461 {"boardnum", 0xfffff800, 0, SROM11_MACLO, 0xffff}, 462 {"macaddr", 0xfffff800, SRFL_ETHADDR, SROM11_MACHI, 0xffff}, 463 {"ccode", 0xfffff800, SRFL_CCODE, SROM11_CCODE, 0xffff}, 464 {"regrev", 0xfffff800, 0, SROM11_REGREV, 0x00ff}, 465 {"ledbh0", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0x00ff}, 466 {"ledbh1", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0xff00}, 467 {"ledbh2", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0x00ff}, 468 {"ledbh3", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0xff00}, 469 {"leddc", 0xfffff800, SRFL_NOFFS|SRFL_LEDDC, SROM11_LEDDC, 0xffff}, 470 {"aa2g", 0xfffff800, 0, SROM11_AA, 0x00ff}, 471 {"aa5g", 0xfffff800, 0, SROM11_AA, 0xff00}, 472 {"agbg0", 0xfffff800, 0, SROM11_AGBG10, 0xff00}, 473 {"agbg1", 0xfffff800, 0, SROM11_AGBG10, 0x00ff}, 474 {"agbg2", 0xfffff800, 0, SROM11_AGBG2A0, 0xff00}, 475 {"aga0", 0xfffff800, 0, SROM11_AGBG2A0, 0x00ff}, 476 {"aga1", 0xfffff800, 0, SROM11_AGA21, 0xff00}, 477 {"aga2", 0xfffff800, 0, SROM11_AGA21, 0x00ff}, 478 {"txchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_TXCHAIN_MASK}, 479 {"rxchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_RXCHAIN_MASK}, 480 {"antswitch", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_SWITCH_MASK}, 481 482 {"tssiposslope2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0001}, 483 {"epagain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x000e}, 484 {"pdgain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x01f0}, 485 {"tworangetssi2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0200}, 486 {"papdcap2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0400}, 487 {"femctrl", 0xfffff800, 0, SROM11_FEM_CFG1, 0xf800}, 488 489 {"tssiposslope5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0001}, 490 {"epagain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x000e}, 491 {"pdgain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x01f0}, 492 {"tworangetssi5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0200}, 493 {"papdcap5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0400}, 494 {"gainctrlsph", 0xfffff800, 0, SROM11_FEM_CFG2, 0xf800}, 495 496 {"tempthresh", 0xfffff800, 0, SROM11_THERMAL, 0xff00}, 497 {"tempoffset", 0xfffff800, 0, SROM11_THERMAL, 0x00ff}, 498 {"rawtempsense", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0x01ff}, 499 {"measpower", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0xfe00}, 500 {"tempsense_slope", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x00ff}, 501 {"tempcorrx", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0xfc00}, 502 {"tempsense_option", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x0300}, 503 {"xtalfreq", 0xfffff800, 0, SROM11_XTAL_FREQ, 0xffff}, 504 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #1 */ 505 {"pa5gbw4080a1", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W0_A1, 0xffff}, 506 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W1_A1, 0xffff}, 507 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W2_A1, 0xffff}, 508 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_4080_W0_A1, 0xffff}, 509 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA, 0xffff}, 510 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA + 1, 0xffff}, 511 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA, 0xffff}, 512 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 1, 0xffff}, 513 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 2, 0xffff}, 514 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA, 0xffff}, 515 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA + 1, 0xffff}, 516 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_4080_PA + 2, 0xffff}, 517 {"phycal_tempdelta", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x00ff}, 518 {"temps_period", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x0f00}, 519 {"temps_hysteresis", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0xf000}, 520 {"measpower1", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x007f}, 521 {"measpower2", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x3f80}, 522 {"tssifloor2g", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_2G, 0x03ff}, 523 {"tssifloor5g", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GL, 0x03ff}, 524 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GM, 0x03ff}, 525 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GH, 0x03ff}, 526 {"", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_5GU, 0x03ff}, 527 {"pdoffset2g40ma0", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x000f}, 528 {"pdoffset2g40ma1", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x00f0}, 529 {"pdoffset2g40ma2", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x0f00}, 530 {"pdoffset2g40mvalid", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x8000}, 531 {"pdoffset40ma0", 0xfffff800, 0, SROM11_PDOFF_40M_A0, 0xffff}, 532 {"pdoffset40ma1", 0xfffff800, 0, SROM11_PDOFF_40M_A1, 0xffff}, 533 {"pdoffset40ma2", 0xfffff800, 0, SROM11_PDOFF_40M_A2, 0xffff}, 534 {"pdoffset80ma0", 0xfffff800, 0, SROM11_PDOFF_80M_A0, 0xffff}, 535 {"pdoffset80ma1", 0xfffff800, 0, SROM11_PDOFF_80M_A1, 0xffff}, 536 {"pdoffset80ma2", 0xfffff800, 0, SROM11_PDOFF_80M_A2, 0xffff}, 537 538 {"subband5gver", 0xfffff800, SRFL_PRHEX, SROM11_SUBBAND5GVER, 0xffff}, 539 {"paparambwver", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0xf000}, 540 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #0 */ 541 {"pa5gbw4080a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 +SROM11_5GB0_PA, 0xffff}, 542 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff}, 543 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff}, 544 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 0xffff}, 545 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff}, 546 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff}, 547 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 0xffff}, 548 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff}, 549 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff}, 550 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 0xffff}, 551 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff}, 552 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 553 /* Special PA Params for 4335 5G Band, 40 MHz BW */ 554 {"pa5gbw40a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA, 0xffff}, 555 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 1, 0xffff}, 556 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 2, 0xffff}, 557 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA, 0xffff}, 558 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 1, 0xffff}, 559 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 2, 0xffff}, 560 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA, 0xffff}, 561 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 1, 0xffff}, 562 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 2, 0xffff}, 563 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA, 0xffff}, 564 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA + 1, 0xffff}, 565 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_5GB3_PA + 2, 0xffff}, 566 /* Special PA Params for 4335 5G Band, 80 MHz BW */ 567 {"pa5gbw80a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA, 0xffff}, 568 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff}, 569 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff}, 570 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 0xffff}, 571 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff}, 572 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff}, 573 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 0xffff}, 574 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff}, 575 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff}, 576 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 0xffff}, 577 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff}, 578 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 579 /* Special PA Params for 4335 2G Band, CCK */ 580 {"pa2gccka0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA, 0xffff}, 581 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA + 1, 0xffff}, 582 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_2G_PA + 2, 0xffff}, 583 584 /* power per rate */ 585 {"cckbw202gpo", 0xfffff800, 0, SROM11_CCKBW202GPO, 0xffff}, 586 {"cckbw20ul2gpo", 0xfffff800, 0, SROM11_CCKBW20UL2GPO, 0xffff}, 587 {"mcsbw202gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW202GPO, 0xffff}, 588 {"", 0xfffff800, 0, SROM11_MCSBW202GPO_1, 0xffff}, 589 {"mcsbw402gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW402GPO, 0xffff}, 590 {"", 0xfffff800, 0, SROM11_MCSBW402GPO_1, 0xffff}, 591 {"dot11agofdmhrbw202gpo", 0xfffff800, 0, SROM11_DOT11AGOFDMHRBW202GPO, 0xffff}, 592 {"ofdmlrbw202gpo", 0xfffff800, 0, SROM11_OFDMLRBW202GPO, 0xffff}, 593 {"mcsbw205glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GLPO, 0xffff}, 594 {"", 0xfffff800, 0, SROM11_MCSBW205GLPO_1, 0xffff}, 595 {"mcsbw405glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GLPO, 0xffff}, 596 {"", 0xfffff800, 0, SROM11_MCSBW405GLPO_1, 0xffff}, 597 {"mcsbw805glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GLPO, 0xffff}, 598 {"", 0xfffff800, 0, SROM11_MCSBW805GLPO_1, 0xffff}, 599 {"mcsbw205gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GMPO, 0xffff}, 600 {"", 0xfffff800, 0, SROM11_MCSBW205GMPO_1, 0xffff}, 601 {"mcsbw405gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GMPO, 0xffff}, 602 {"", 0xfffff800, 0, SROM11_MCSBW405GMPO_1, 0xffff}, 603 {"mcsbw805gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GMPO, 0xffff}, 604 {"", 0xfffff800, 0, SROM11_MCSBW805GMPO_1, 0xffff}, 605 {"mcsbw205ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GHPO, 0xffff}, 606 {"", 0xfffff800, 0, SROM11_MCSBW205GHPO_1, 0xffff}, 607 {"mcsbw405ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GHPO, 0xffff}, 608 {"", 0xfffff800, 0, SROM11_MCSBW405GHPO_1, 0xffff}, 609 {"mcsbw805ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GHPO, 0xffff}, 610 {"", 0xfffff800, 0, SROM11_MCSBW805GHPO_1, 0xffff}, 611 {"mcslr5glpo", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0x0fff}, 612 {"mcslr5gmpo", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0xffff}, 613 {"mcslr5ghpo", 0xfffff800, 0, SROM11_MCSLR5GHPO, 0xffff}, 614 {"sb20in40hrpo", 0xfffff800, 0, SROM11_SB20IN40HRPO, 0xffff}, 615 {"sb20in80and160hr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GLPO, 0xffff}, 616 {"sb40and80hr5glpo", 0xfffff800, 0, SROM11_SB40AND80HR5GLPO, 0xffff}, 617 {"sb20in80and160hr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GMPO, 0xffff}, 618 {"sb40and80hr5gmpo", 0xfffff800, 0, SROM11_SB40AND80HR5GMPO, 0xffff}, 619 {"sb20in80and160hr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GHPO, 0xffff}, 620 {"sb40and80hr5ghpo", 0xfffff800, 0, SROM11_SB40AND80HR5GHPO, 0xffff}, 621 {"sb20in40lrpo", 0xfffff800, 0, SROM11_SB20IN40LRPO, 0xffff}, 622 {"sb20in80and160lr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GLPO, 0xffff}, 623 {"sb40and80lr5glpo", 0xfffff800, 0, SROM11_SB40AND80LR5GLPO, 0xffff}, 624 {"sb20in80and160lr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GMPO, 0xffff}, 625 {"sb40and80lr5gmpo", 0xfffff800, 0, SROM11_SB40AND80LR5GMPO, 0xffff}, 626 {"sb20in80and160lr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GHPO, 0xffff}, 627 {"sb40and80lr5ghpo", 0xfffff800, 0, SROM11_SB40AND80LR5GHPO, 0xffff}, 628 {"dot11agduphrpo", 0xfffff800, 0, SROM11_DOT11AGDUPHRPO, 0xffff}, 629 {"dot11agduplrpo", 0xfffff800, 0, SROM11_DOT11AGDUPLRPO, 0xffff}, 630 631 /* Misc */ 632 {"sar2g", 0xfffff800, 0, SROM11_SAR, 0x00ff}, 633 {"sar5g", 0xfffff800, 0, SROM11_SAR, 0xff00}, 634 635 {"noiselvl2ga0", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x001f}, 636 {"noiselvl2ga1", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x03e0}, 637 {"noiselvl2ga2", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x7c00}, 638 {"noiselvl5ga0", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x001f}, 639 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x001f}, 640 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x001f}, 641 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x001f}, 642 {"noiselvl5ga1", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x03e0}, 643 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x03e0}, 644 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x03e0}, 645 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x03e0}, 646 {"noiselvl5ga2", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x7c00}, 647 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x7c00}, 648 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x7c00}, 649 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x7c00}, 650 651 {"eu_edthresh2g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0x00ff}, 652 {"eu_edthresh5g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0xff00}, 653 654 {"rxgainerr2ga0", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x003f}, 655 {"rxgainerr2ga1", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x07c0}, 656 {"rxgainerr2ga2", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0xf800}, 657 {"rxgainerr5ga0", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x003f}, 658 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x003f}, 659 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x003f}, 660 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x003f}, 661 {"rxgainerr5ga1", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x07c0}, 662 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x07c0}, 663 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x07c0}, 664 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x07c0}, 665 {"rxgainerr5ga2", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0xf800}, 666 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0xf800}, 667 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0xf800}, 668 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0xf800}, 669 {"rpcal2g", 0xfffff800, 0, SROM11_RPCAL_2G, 0xffff}, 670 {"rpcal5gb0", 0xfffff800, 0, SROM11_RPCAL_5GL, 0xffff}, 671 {"rpcal5gb1", 0xfffff800, 0, SROM11_RPCAL_5GM, 0xffff}, 672 {"rpcal5gb2", 0xfffff800, 0, SROM11_RPCAL_5GH, 0xffff}, 673 {"rpcal5gb3", 0xfffff800, 0, SROM11_RPCAL_5GU, 0xffff}, 674 {"txidxcap2g", 0xfffff800, 0, SROM11_TXIDXCAP2G, 0x0ff0}, 675 {"txidxcap5g", 0xfffff800, 0, SROM11_TXIDXCAP5G, 0x0ff0}, 676 {"pdoffsetcckma0", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x000f}, 677 {"pdoffsetcckma1", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x00f0}, 678 {"pdoffsetcckma2", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x0f00}, 679 {NULL, 0, 0, 0, 0} 680}; 681 682static const sromvar_t perpath_pci_sromvars[] = { 683 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff}, 684 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00}, 685 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00}, 686 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff}, 687 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff}, 688 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff}, 689 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff}, 690 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff}, 691 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff}, 692 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00}, 693 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff}, 694 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff}, 695 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff}, 696 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff}, 697 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff}, 698 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff}, 699 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff}, 700 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff}, 701 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff}, 702 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff}, 703 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff}, 704 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff}, 705 {"maxp2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0x00ff}, 706 {"itt2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0xff00}, 707 {"itt5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0xff00}, 708 {"pa2gw0a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA, 0xffff}, 709 {"pa2gw1a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff}, 710 {"pa2gw2a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff}, 711 {"maxp5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0x00ff}, 712 {"maxp5gha", 0x00000700, 0, SROM8_5GLH_MAXP, 0x00ff}, 713 {"maxp5gla", 0x00000700, 0, SROM8_5GLH_MAXP, 0xff00}, 714 {"pa5gw0a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA, 0xffff}, 715 {"pa5gw1a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff}, 716 {"pa5gw2a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff}, 717 {"pa5glw0a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA, 0xffff}, 718 {"pa5glw1a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff}, 719 {"pa5glw2a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff}, 720 {"pa5ghw0a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA, 0xffff}, 721 {"pa5ghw1a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff}, 722 {"pa5ghw2a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff}, 723 724 /* sromrev 11 */ 725 {"maxp2ga", 0xfffff800, 0, SROM11_2G_MAXP, 0x00ff}, 726 {"pa2ga", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA, 0xffff}, 727 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA + 1, 0xffff}, 728 {"", 0xfffff800, SRFL_PRHEX, SROM11_2G_PA + 2, 0xffff}, 729 {"rxgains5gmelnagaina", 0xfffff800, 0, SROM11_RXGAINS1, 0x0007}, 730 {"rxgains5gmtrisoa", 0xfffff800, 0, SROM11_RXGAINS1, 0x0078}, 731 {"rxgains5gmtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS1, 0x0080}, 732 {"rxgains5ghelnagaina", 0xfffff800, 0, SROM11_RXGAINS1, 0x0700}, 733 {"rxgains5ghtrisoa", 0xfffff800, 0, SROM11_RXGAINS1, 0x7800}, 734 {"rxgains5ghtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS1, 0x8000}, 735 {"rxgains2gelnagaina", 0xfffff800, 0, SROM11_RXGAINS, 0x0007}, 736 {"rxgains2gtrisoa", 0xfffff800, 0, SROM11_RXGAINS, 0x0078}, 737 {"rxgains2gtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS, 0x0080}, 738 {"rxgains5gelnagaina", 0xfffff800, 0, SROM11_RXGAINS, 0x0700}, 739 {"rxgains5gtrisoa", 0xfffff800, 0, SROM11_RXGAINS, 0x7800}, 740 {"rxgains5gtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS, 0x8000}, 741 {"maxp5ga", 0xfffff800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0x00ff}, 742 {"", 0xfffff800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0xff00}, 743 {"", 0xfffff800, SRFL_ARRAY, SROM11_5GB3B2_MAXP, 0x00ff}, 744 {"", 0xfffff800, 0, SROM11_5GB3B2_MAXP, 0xff00}, 745 {"pa5ga", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA, 0xffff}, 746 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 1, 0xffff}, 747 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 2, 0xffff}, 748 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA, 0xffff}, 749 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 1, 0xffff}, 750 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 2, 0xffff}, 751 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA, 0xffff}, 752 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 1, 0xffff}, 753 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 2, 0xffff}, 754 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA, 0xffff}, 755 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA + 1, 0xffff}, 756 {"", 0xfffff800, SRFL_PRHEX, SROM11_5GB3_PA + 2, 0xffff}, 757 758 {NULL, 0, 0, 0, 0} 759}; 760 761#if !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) 762#define PHY_TYPE_HT 7 /* HT-Phy value */ 763#define PHY_TYPE_N 4 /* N-Phy value */ 764#define PHY_TYPE_LP 5 /* LP-Phy value */ 765#endif /* !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */ 766#if !defined(PHY_TYPE_AC) 767#define PHY_TYPE_AC 11 /* AC-Phy value */ 768#endif /* !defined(PHY_TYPE_AC) */ 769#if !defined(PHY_TYPE_NULL) 770#define PHY_TYPE_NULL 0xf /* Invalid Phy value */ 771#endif /* !defined(PHY_TYPE_NULL) */ 772 773typedef struct { 774 uint16 phy_type; 775 uint16 bandrange; 776 uint16 chain; 777 const char *vars; 778} pavars_t; 779 780static const pavars_t pavars[] = { 781 /* HTPHY */ 782 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"}, 783 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"}, 784 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 2, "pa2gw0a2 pa2gw1a2 pa2gw2a2"}, 785 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"}, 786 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"}, 787 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 2, "pa5glw0a2 pa5glw1a2 pa5glw2a2"}, 788 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"}, 789 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"}, 790 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 2, "pa5gw0a2 pa5gw1a2 pa5gw2a2"}, 791 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"}, 792 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"}, 793 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 2, "pa5ghw0a2 pa5ghw1a2 pa5ghw2a2"}, 794 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 0, "pa5gw0a3 pa5gw1a3 pa5gw2a3"}, 795 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 1, "pa5glw0a3 pa5glw1a3 pa5glw2a3"}, 796 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 2, "pa5ghw0a3 pa5ghw1a3 pa5ghw2a3"}, 797 /* NPHY */ 798 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"}, 799 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"}, 800 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"}, 801 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"}, 802 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"}, 803 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"}, 804 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"}, 805 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"}, 806 /* LPPHY */ 807 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"}, 808 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"}, 809 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"}, 810 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"}, 811 /* ACPHY */ 812 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 813 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 814 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"}, 815 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 816 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 817 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5ga2"}, 818 {PHY_TYPE_NULL, 0, 0, ""} 819}; 820 821/* pavars table when paparambwver is 1 */ 822static const pavars_t pavars_bwver_1[] = { 823 /* ACPHY */ 824 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 825 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gccka0"}, 826 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga2"}, 827 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 828 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5gbw40a0"}, 829 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw80a0"}, 830 {PHY_TYPE_NULL, 0, 0, ""} 831}; 832 833/* pavars table when paparambwver is 2 */ 834static const pavars_t pavars_bwver_2[] = { 835 /* ACPHY */ 836 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 837 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 838 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 839 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 840 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw4080a0"}, 841 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 3, "pa5gbw4080a1"}, 842 {PHY_TYPE_NULL, 0, 0, ""} 843}; 844 845typedef struct { 846 uint16 phy_type; 847 uint16 bandrange; 848 const char *vars; 849} povars_t; 850 851static const povars_t povars[] = { 852 /* NPHY */ 853 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 " 854 "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"}, 855 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 " 856 "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"}, 857 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 " 858 "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"}, 859 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 " 860 "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"}, 861 {PHY_TYPE_NULL, 0, ""} 862}; 863 864typedef struct { 865 uint8 tag; /* Broadcom subtag name */ 866 uint32 revmask; /* Supported cis_sromrev */ 867 uint8 len; /* Length field of the tuple, note that it includes the 868 * subtag name (1 byte): 1 + tuple content length 869 */ 870 const char *params; 871} cis_tuple_t; 872 873#define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */ 874#define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */ 875#define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */ 876#define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */ 877 878static const cis_tuple_t cis_hnbuvars[] = { 879 {OTP_RAW1, 0xffffffff, 0, ""}, /* special case */ 880 {OTP_VERS_1, 0xffffffff, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */ 881 {OTP_MANFID, 0xffffffff, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */ 882 /* Unified OTP: tupple to embed USB manfid inside SDIO CIS */ 883 {HNBU_UMANFID, 0xffffffff, 8, "8usbmanfid"}, 884 {HNBU_SROMREV, 0xffffffff, 2, "1sromrev"}, 885 /* NOTE: subdevid is also written to boardtype. 886 * Need to write HNBU_BOARDTYPE to change it if it is different. 887 */ 888 {HNBU_CHIPID, 0xffffffff, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"}, 889 {HNBU_BOARDREV, 0xffffffff, 3, "2boardrev"}, 890 {HNBU_PAPARMS, 0xffffffff, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"}, 891 {HNBU_AA, 0xffffffff, 3, "1aa2g 1aa5g"}, 892 {HNBU_AA, 0xffffffff, 3, "1aa0 1aa1"}, /* backward compatibility */ 893 {HNBU_AG, 0xffffffff, 5, "1ag0 1ag1 1ag2 1ag3"}, 894 {HNBU_BOARDFLAGS, 0xffffffff, 13, "4boardflags 4boardflags2 4boardflags3"}, 895 {HNBU_LEDS, 0xffffffff, 17, "1ledbh0 1ledbh1 1ledbh2 1ledbh3 1ledbh4 1ledbh5 " 896 "1ledbh6 1ledbh7 1ledbh8 1ledbh9 1ledbh10 1ledbh11 1ledbh12 1ledbh13 1ledbh14 1ledbh15"}, 897 {HNBU_CCODE, 0xffffffff, 4, "2ccode 1cctl"}, 898 {HNBU_CCKPO, 0xffffffff, 3, "2cckpo"}, 899 {HNBU_OFDMPO, 0xffffffff, 5, "4ofdmpo"}, 900 {HNBU_PAPARMS5G, 0xffffffff, 23, "2pa1b0 2pa1b1 2pa1b2 2pa1lob0 2pa1lob1 2pa1lob2 " 901 "2pa1hib0 2pa1hib1 2pa1hib2 1pa1itssit " 902 "1pa1maxpwr 1pa1lomaxpwr 1pa1himaxpwr"}, 903 {HNBU_RDLID, 0xffffffff, 3, "2rdlid"}, 904 {HNBU_RSSISMBXA2G, 0xffffffff, 3, "0rssismf2g 0rssismc2g " 905 "0rssisav2g 0bxa2g"}, /* special case */ 906 {HNBU_RSSISMBXA5G, 0xffffffff, 3, "0rssismf5g 0rssismc5g " 907 "0rssisav5g 0bxa5g"}, /* special case */ 908 {HNBU_XTALFREQ, 0xffffffff, 5, "4xtalfreq"}, 909 {HNBU_TRI2G, 0xffffffff, 2, "1tri2g"}, 910 {HNBU_TRI5G, 0xffffffff, 4, "1tri5gl 1tri5g 1tri5gh"}, 911 {HNBU_RXPO2G, 0xffffffff, 2, "1rxpo2g"}, 912 {HNBU_RXPO5G, 0xffffffff, 2, "1rxpo5g"}, 913 {HNBU_BOARDNUM, 0xffffffff, 3, "2boardnum"}, 914 {HNBU_MACADDR, 0xffffffff, 7, "6macaddr"}, /* special case */ 915 {HNBU_RDLSN, 0xffffffff, 3, "2rdlsn"}, 916 {HNBU_BOARDTYPE, 0xffffffff, 3, "2boardtype"}, 917 {HNBU_LEDDC, 0xffffffff, 3, "2leddc"}, 918 {HNBU_RDLRNDIS, 0xffffffff, 2, "1rdlndis"}, 919 {HNBU_CHAINSWITCH, 0xffffffff, 5, "1txchain 1rxchain 2antswitch"}, 920 {HNBU_REGREV, 0xffffffff, 2, "1regrev"}, 921 {HNBU_FEM, 0x000007fe, 5, "0antswctl2g 0triso2g 0pdetrange2g 0extpagain2g " 922 "0tssipos2g 0antswctl5g 0triso5g 0pdetrange5g 0extpagain5g 0tssipos5g"}, /* special case */ 923 {HNBU_PAPARMS_C0, 0x000007fe, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 " 924 "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 2pa5gw1a0 2pa5gw2a0 " 925 "2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 2pa5ghw1a0 2pa5ghw2a0"}, 926 {HNBU_PAPARMS_C1, 0x000007fe, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 " 927 "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 2pa5gw1a1 2pa5gw2a1 " 928 "2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 2pa5ghw1a1 2pa5ghw2a1"}, 929 {HNBU_PO_CCKOFDM, 0xffffffff, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo " 930 "4ofdm5ghpo"}, 931 {HNBU_PO_MCS2G, 0xffffffff, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 " 932 "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"}, 933 {HNBU_PO_MCS5GM, 0xffffffff, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 " 934 "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"}, 935 {HNBU_PO_MCS5GLH, 0xffffffff, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 " 936 "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 " 937 "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 " 938 "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"}, 939 {HNBU_CCKFILTTYPE, 0xffffffff, 2, "1cckdigfilttype"}, 940 {HNBU_PO_CDD, 0xffffffff, 3, "2cddpo"}, 941 {HNBU_PO_STBC, 0xffffffff, 3, "2stbcpo"}, 942 {HNBU_PO_40M, 0xffffffff, 3, "2bw40po"}, 943 {HNBU_PO_40MDUP, 0xffffffff, 3, "2bwduppo"}, 944 {HNBU_RDLRWU, 0xffffffff, 2, "1rdlrwu"}, 945 {HNBU_WPS, 0xffffffff, 3, "1wpsgpio 1wpsled"}, 946 {HNBU_USBFS, 0xffffffff, 2, "1usbfs"}, 947 {HNBU_ELNA2G, 0xffffffff, 2, "1elna2g"}, 948 {HNBU_ELNA5G, 0xffffffff, 2, "1elna5g"}, 949 {HNBU_CUSTOM1, 0xffffffff, 5, "4customvar1"}, 950 {OTP_RAW, 0xffffffff, 0, ""}, /* special case */ 951 {HNBU_OFDMPO5G, 0xffffffff, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"}, 952 {HNBU_USBEPNUM, 0xffffffff, 3, "2usbepnum"}, 953 {HNBU_CCKBW202GPO, 0xffffffff, 5, "2cckbw202gpo 2cckbw20ul2gpo"}, 954 {HNBU_LEGOFDMBW202GPO, 0xffffffff, 9, "4legofdmbw202gpo 4legofdmbw20ul2gpo"}, 955 {HNBU_LEGOFDMBW205GPO, 0xffffffff, 25, "4legofdmbw205glpo 4legofdmbw20ul5glpo " 956 "4legofdmbw205gmpo 4legofdmbw20ul5gmpo 4legofdmbw205ghpo 4legofdmbw20ul5ghpo"}, 957 {HNBU_MCS2GPO, 0xffffffff, 13, "4mcsbw202gpo 4mcsbw20ul2gpo 4mcsbw402gpo"}, 958 {HNBU_MCS5GLPO, 0xffffffff, 13, "4mcsbw205glpo 4mcsbw20ul5glpo 4mcsbw405glpo"}, 959 {HNBU_MCS5GMPO, 0xffffffff, 13, "4mcsbw205gmpo 4mcsbw20ul5gmpo 4mcsbw405gmpo"}, 960 {HNBU_MCS5GHPO, 0xffffffff, 13, "4mcsbw205ghpo 4mcsbw20ul5ghpo 4mcsbw405ghpo"}, 961 {HNBU_MCS32PO, 0xffffffff, 3, "2mcs32po"}, 962 {HNBU_LEG40DUPPO, 0xffffffff, 3, "2legofdm40duppo"}, 963 {HNBU_TEMPTHRESH, 0xffffffff, 7, "1tempthresh 0temps_period 0temps_hysteresis " 964 "1tempoffset 1tempsense_slope 0tempcorrx 0tempsense_option " 965 "1phycal_tempdelta"}, /* special case */ 966 {HNBU_MUXENAB, 0xffffffff, 2, "1muxenab"}, 967 {HNBU_FEM_CFG, 0xfffff800, 5, "0femctrl 0papdcap2g 0tworangetssi2g 0pdgain2g " 968 "0epagain2g 0tssiposslope2g 0gainctrlsph 0papdcap5g 0tworangetssi5g 0pdgain5g 0epagain5g " 969 "0tssiposslope5g"}, /* special case */ 970 {HNBU_ACPA_C0, 0xfffff800, 39, "2subband5gver 2maxp2ga0 2*3pa2ga0 " 971 "1*4maxp5ga0 2*12pa5ga0"}, 972 {HNBU_ACPA_C1, 0xfffff800, 37, "2maxp2ga1 2*3pa2ga1 1*4maxp5ga1 2*12pa5ga1"}, 973 {HNBU_ACPA_C2, 0xfffff800, 37, "2maxp2ga2 2*3pa2ga2 1*4maxp5ga2 2*12pa5ga2"}, 974 {HNBU_MEAS_PWR, 0xfffff800, 5, "1measpower 1measpower1 1measpower2 2rawtempsense"}, 975 {HNBU_PDOFF, 0xfffff800, 13, "2pdoffset40ma0 2pdoffset40ma1 2pdoffset40ma2 " 976 "2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"}, 977 {HNBU_ACPPR_2GPO, 0xfffff800, 5, "2dot11agofdmhrbw202gpo 2ofdmlrbw202gpo"}, 978 {HNBU_ACPPR_5GPO, 0xfffff800, 31, "4mcsbw805glpo 4mcsbw1605glpo 4mcsbw805gmpo " 979 "4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5glpo 2mcslr5gmpo 2mcslr5ghpo"}, 980 {HNBU_ACPPR_SBPO, 0xfffff800, 33, "2sb20in40hrpo 2sb20in80and160hr5glpo " 981 "2sb40and80hr5glpo 2sb20in80and160hr5gmpo 2sb40and80hr5gmpo 2sb20in80and160hr5ghpo " 982 "2sb40and80hr5ghpo 2sb20in40lrpo 2sb20in80and160lr5glpo 2sb40and80lr5glpo " 983 "2sb20in80and160lr5gmpo 2sb40and80lr5gmpo 2sb20in80and160lr5ghpo 2sb40and80lr5ghpo " 984 "2dot11agduphrpo 2dot11agduplrpo"}, 985 {HNBU_NOISELVL, 0xfffff800, 16, "1noiselvl2ga0 1noiselvl2ga1 1noiselvl2ga2 " 986 "1*4noiselvl5ga0 1*4noiselvl5ga1 1*4noiselvl5ga2"}, 987 {HNBU_RXGAIN_ERR, 0xfffff800, 16, "1rxgainerr2ga0 1rxgainerr2ga1 1rxgainerr2ga2 " 988 "1*4rxgainerr5ga0 1*4rxgainerr5ga1 1*4rxgainerr5ga2"}, 989 {HNBU_AGBGA, 0xfffff800, 7, "1agbg0 1agbg1 1agbg2 1aga0 1aga1 1aga2"}, 990 {HNBU_USBDESC_COMPOSITE, 0xffffffff, 3, "2usbdesc_composite"}, 991 {HNBU_UUID, 0xffffffff, 17, "16uuid"}, 992 {HNBU_WOWLGPIO, 0xffffffff, 2, "1wowl_gpio"}, 993 {HNBU_ACRXGAINS_C0, 0xfffff800, 5, "0rxgains5gtrelnabypa0 0rxgains5gtrisoa0 " 994 "0rxgains5gelnagaina0 0rxgains2gtrelnabypa0 0rxgains2gtrisoa0 0rxgains2gelnagaina0 " 995 "0rxgains5ghtrelnabypa0 0rxgains5ghtrisoa0 0rxgains5ghelnagaina0 0rxgains5gmtrelnabypa0 " 996 "0rxgains5gmtrisoa0 0rxgains5gmelnagaina0"}, /* special case */ 997 {HNBU_ACRXGAINS_C1, 0xfffff800, 5, "0rxgains5gtrelnabypa1 0rxgains5gtrisoa1 " 998 "0rxgains5gelnagaina1 0rxgains2gtrelnabypa1 0rxgains2gtrisoa1 0rxgains2gelnagaina1 " 999 "0rxgains5ghtrelnabypa1 0rxgains5ghtrisoa1 0rxgains5ghelnagaina1 0rxgains5gmtrelnabypa1 " 1000 "0rxgains5gmtrisoa1 0rxgains5gmelnagaina1"}, /* special case */ 1001 {HNBU_ACRXGAINS_C2, 0xfffff800, 5, "0rxgains5gtrelnabypa2 0rxgains5gtrisoa2 " 1002 "0rxgains5gelnagaina2 0rxgains2gtrelnabypa2 0rxgains2gtrisoa2 0rxgains2gelnagaina2 " 1003 "0rxgains5ghtrelnabypa2 0rxgains5ghtrisoa2 0rxgains5ghelnagaina2 0rxgains5gmtrelnabypa2 " 1004 "0rxgains5gmtrisoa2 0rxgains5gmelnagaina2"}, /* special case */ 1005 {HNBU_TXDUTY, 0xfffff800, 9, "2tx_duty_cycle_ofdm_40_5g " 1006 "2tx_duty_cycle_thresh_40_5g 2tx_duty_cycle_ofdm_80_5g 2tx_duty_cycle_thresh_80_5g"}, 1007 {HNBU_PDOFF_2G, 0xfffff800, 3, "0pdoffset2g40ma0 0pdoffset2g40ma1 " 1008 "0pdoffset2g40ma2 0pdoffset2g40mvalid"}, 1009 {HNBU_ACPA_CCK, 0xfffff800, 7, "2*3pa2gccka0"}, 1010 {HNBU_ACPA_40, 0xfffff800, 25, "2*12pa5gbw40a0"}, 1011 {HNBU_ACPA_80, 0xfffff800, 25, "2*12pa5gbw80a0"}, 1012 {HNBU_ACPA_4080, 0xfffff800, 49, "2*12pa5gbw4080a0 2*12pa5gbw4080a1"}, 1013 {HNBU_SUBBAND5GVER, 0xfffff800, 3, "2subband5gver"}, 1014 {HNBU_PAPARAMBWVER, 0xfffff800, 2, "1paparambwver"}, 1015 {HNBU_USB30U1U2, 0xfffff800, 3, "2usb30u1u2"}, 1016 {HNBU_USB30REGS0, 0xfffff800, 41, "4*10usb30regs0"}, 1017 {HNBU_USB30REGS1, 0xfffff800, 41, "4*10usb30regs1"}, 1018 {HNBU_TXBFRPCALS, 0xfffff800, 11, 1019 "2rpcal2g 2rpcal5gb0 2rpcal5gb1 2rpcal5gb2 2rpcal5gb3"}, /* txbf rpcalvars */ 1020 {0xFF, 0xffffffff, 0, ""} 1021}; 1022 1023#endif /* _bcmsrom_tbl_h_ */ 1024