1/* 2 * SROM format definition. 3 * 4 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: bcmsrom_fmt.h 502763 2014-09-16 02:48:59Z $ 19 */ 20 21#ifndef _bcmsrom_fmt_h_ 22#define _bcmsrom_fmt_h_ 23 24#define SROM_MAXREV 11 /* max revisiton supported by driver */ 25 26/* Maximum srom: 6 Kilobits == 768 bytes */ 27#define SROM_MAX 768 28#define SROM_MAXW 384 29#define VARS_MAX 4096 30 31/* PCI fields */ 32#define PCI_F0DEVID 48 33 34 35#define SROM_WORDS 64 36 37#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ 38 39#define SROM_SSID 2 40#define SROM_SVID 3 41 42#define SROM_WL1LHMAXP 29 43 44#define SROM_WL1LPAB0 30 45#define SROM_WL1LPAB1 31 46#define SROM_WL1LPAB2 32 47 48#define SROM_WL1HPAB0 33 49#define SROM_WL1HPAB1 34 50#define SROM_WL1HPAB2 35 51 52#define SROM_MACHI_IL0 36 53#define SROM_MACMID_IL0 37 54#define SROM_MACLO_IL0 38 55#define SROM_MACHI_ET0 39 56#define SROM_MACMID_ET0 40 57#define SROM_MACLO_ET0 41 58#define SROM_MACHI_ET1 42 59#define SROM_MACMID_ET1 43 60#define SROM_MACLO_ET1 44 61#define SROM3_MACHI 37 62#define SROM3_MACMID 38 63#define SROM3_MACLO 39 64 65#define SROM_BXARSSI2G 40 66#define SROM_BXARSSI5G 41 67 68#define SROM_TRI52G 42 69#define SROM_TRI5GHL 43 70 71#define SROM_RXPO52G 45 72 73#define SROM2_ENETPHY 45 74 75#define SROM_AABREV 46 76/* Fields in AABREV */ 77#define SROM_BR_MASK 0x00ff 78#define SROM_CC_MASK 0x0f00 79#define SROM_CC_SHIFT 8 80#define SROM_AA0_MASK 0x3000 81#define SROM_AA0_SHIFT 12 82#define SROM_AA1_MASK 0xc000 83#define SROM_AA1_SHIFT 14 84 85#define SROM_WL0PAB0 47 86#define SROM_WL0PAB1 48 87#define SROM_WL0PAB2 49 88 89#define SROM_LEDBH10 50 90#define SROM_LEDBH32 51 91 92#define SROM_WL10MAXP 52 93 94#define SROM_WL1PAB0 53 95#define SROM_WL1PAB1 54 96#define SROM_WL1PAB2 55 97 98#define SROM_ITT 56 99 100#define SROM_BFL 57 101#define SROM_BFL2 28 102#define SROM3_BFL2 61 103 104#define SROM_AG10 58 105 106#define SROM_CCODE 59 107 108#define SROM_OPO 60 109 110#define SROM3_LEDDC 62 111 112#define SROM_CRCREV 63 113 114/* SROM Rev 4: Reallocate the software part of the srom to accomodate 115 * MIMO features. It assumes up to two PCIE functions and 440 bytes 116 * of useable srom i.e. the useable storage in chips with OTP that 117 * implements hardware redundancy. 118 */ 119 120#define SROM4_WORDS 220 121 122#define SROM4_SIGN 32 123#define SROM4_SIGNATURE 0x5372 124 125#define SROM4_BREV 33 126 127#define SROM4_BFL0 34 128#define SROM4_BFL1 35 129#define SROM4_BFL2 36 130#define SROM4_BFL3 37 131#define SROM5_BFL0 37 132#define SROM5_BFL1 38 133#define SROM5_BFL2 39 134#define SROM5_BFL3 40 135 136#define SROM4_MACHI 38 137#define SROM4_MACMID 39 138#define SROM4_MACLO 40 139#define SROM5_MACHI 41 140#define SROM5_MACMID 42 141#define SROM5_MACLO 43 142 143#define SROM4_CCODE 41 144#define SROM4_REGREV 42 145#define SROM5_CCODE 34 146#define SROM5_REGREV 35 147 148#define SROM4_LEDBH10 43 149#define SROM4_LEDBH32 44 150#define SROM5_LEDBH10 59 151#define SROM5_LEDBH32 60 152 153#define SROM4_LEDDC 45 154#define SROM5_LEDDC 45 155 156#define SROM4_AA 46 157#define SROM4_AA2G_MASK 0x00ff 158#define SROM4_AA2G_SHIFT 0 159#define SROM4_AA5G_MASK 0xff00 160#define SROM4_AA5G_SHIFT 8 161 162#define SROM4_AG10 47 163#define SROM4_AG32 48 164 165#define SROM4_TXPID2G 49 166#define SROM4_TXPID5G 51 167#define SROM4_TXPID5GL 53 168#define SROM4_TXPID5GH 55 169 170#define SROM4_TXRXC 61 171#define SROM4_TXCHAIN_MASK 0x000f 172#define SROM4_TXCHAIN_SHIFT 0 173#define SROM4_RXCHAIN_MASK 0x00f0 174#define SROM4_RXCHAIN_SHIFT 4 175#define SROM4_SWITCH_MASK 0xff00 176#define SROM4_SWITCH_SHIFT 8 177 178 179/* Per-path fields */ 180#define MAX_PATH_SROM 4 181#define SROM4_PATH0 64 182#define SROM4_PATH1 87 183#define SROM4_PATH2 110 184#define SROM4_PATH3 133 185 186#define SROM4_2G_ITT_MAXP 0 187#define SROM4_2G_PA 1 188#define SROM4_5G_ITT_MAXP 5 189#define SROM4_5GLH_MAXP 6 190#define SROM4_5G_PA 7 191#define SROM4_5GL_PA 11 192#define SROM4_5GH_PA 15 193 194/* Fields in the ITT_MAXP and 5GLH_MAXP words */ 195#define B2G_MAXP_MASK 0xff 196#define B2G_ITT_SHIFT 8 197#define B5G_MAXP_MASK 0xff 198#define B5G_ITT_SHIFT 8 199#define B5GH_MAXP_MASK 0xff 200#define B5GL_MAXP_SHIFT 8 201 202/* All the miriad power offsets */ 203#define SROM4_2G_CCKPO 156 204#define SROM4_2G_OFDMPO 157 205#define SROM4_5G_OFDMPO 159 206#define SROM4_5GL_OFDMPO 161 207#define SROM4_5GH_OFDMPO 163 208#define SROM4_2G_MCSPO 165 209#define SROM4_5G_MCSPO 173 210#define SROM4_5GL_MCSPO 181 211#define SROM4_5GH_MCSPO 189 212#define SROM4_CDDPO 197 213#define SROM4_STBCPO 198 214#define SROM4_BW40PO 199 215#define SROM4_BWDUPPO 200 216 217#define SROM4_CRCREV 219 218 219 220/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. 221 * This is acombined srom for both MIMO and SISO boards, usable in 222 * the .130 4Kilobit OTP with hardware redundancy. 223 */ 224 225#define SROM8_SIGN 64 226 227#define SROM8_BREV 65 228 229#define SROM8_BFL0 66 230#define SROM8_BFL1 67 231#define SROM8_BFL2 68 232#define SROM8_BFL3 69 233 234#define SROM8_MACHI 70 235#define SROM8_MACMID 71 236#define SROM8_MACLO 72 237 238#define SROM8_CCODE 73 239#define SROM8_REGREV 74 240 241#define SROM8_LEDBH10 75 242#define SROM8_LEDBH32 76 243 244#define SROM8_LEDDC 77 245 246#define SROM8_AA 78 247 248#define SROM8_AG10 79 249#define SROM8_AG32 80 250 251#define SROM8_TXRXC 81 252 253#define SROM8_BXARSSI2G 82 254#define SROM8_BXARSSI5G 83 255#define SROM8_TRI52G 84 256#define SROM8_TRI5GHL 85 257#define SROM8_RXPO52G 86 258 259#define SROM8_FEM2G 87 260#define SROM8_FEM5G 88 261#define SROM8_FEM_ANTSWLUT_MASK 0xf800 262#define SROM8_FEM_ANTSWLUT_SHIFT 11 263#define SROM8_FEM_TR_ISO_MASK 0x0700 264#define SROM8_FEM_TR_ISO_SHIFT 8 265#define SROM8_FEM_PDET_RANGE_MASK 0x00f8 266#define SROM8_FEM_PDET_RANGE_SHIFT 3 267#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006 268#define SROM8_FEM_EXTPA_GAIN_SHIFT 1 269#define SROM8_FEM_TSSIPOS_MASK 0x0001 270#define SROM8_FEM_TSSIPOS_SHIFT 0 271 272#define SROM8_THERMAL 89 273 274/* Temp sense related entries */ 275#define SROM8_MPWR_RAWTS 90 276#define SROM8_TS_SLP_OPT_CORRX 91 277/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */ 278#define SROM8_FOC_HWIQ_IQSWP 92 279 280#define SROM8_EXTLNAGAIN 93 281 282/* Temperature delta for PHY calibration */ 283#define SROM8_PHYCAL_TEMPDELTA 94 284 285/* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */ 286#define SROM8_MPWR_1_AND_2 95 287 288 289/* Per-path offsets & fields */ 290#define SROM8_PATH0 96 291#define SROM8_PATH1 112 292#define SROM8_PATH2 128 293#define SROM8_PATH3 144 294 295#define SROM8_2G_ITT_MAXP 0 296#define SROM8_2G_PA 1 297#define SROM8_5G_ITT_MAXP 4 298#define SROM8_5GLH_MAXP 5 299#define SROM8_5G_PA 6 300#define SROM8_5GL_PA 9 301#define SROM8_5GH_PA 12 302 303/* All the miriad power offsets */ 304#define SROM8_2G_CCKPO 160 305 306#define SROM8_2G_OFDMPO 161 307#define SROM8_5G_OFDMPO 163 308#define SROM8_5GL_OFDMPO 165 309#define SROM8_5GH_OFDMPO 167 310 311#define SROM8_2G_MCSPO 169 312#define SROM8_5G_MCSPO 177 313#define SROM8_5GL_MCSPO 185 314#define SROM8_5GH_MCSPO 193 315 316#define SROM8_CDDPO 201 317#define SROM8_STBCPO 202 318#define SROM8_BW40PO 203 319#define SROM8_BWDUPPO 204 320 321/* SISO PA parameters are in the path0 spaces */ 322#define SROM8_SISO 96 323 324/* Legacy names for SISO PA paramters */ 325#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) 326#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) 327#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) 328#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) 329#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) 330#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) 331#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) 332#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) 333#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) 334#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) 335#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) 336#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) 337#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) 338#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) 339#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) 340 341#define SROM8_CRCREV 219 342 343/* SROM REV 9 */ 344#define SROM9_2GPO_CCKBW20 160 345#define SROM9_2GPO_CCKBW20UL 161 346#define SROM9_2GPO_LOFDMBW20 162 347#define SROM9_2GPO_LOFDMBW20UL 164 348 349#define SROM9_5GLPO_LOFDMBW20 166 350#define SROM9_5GLPO_LOFDMBW20UL 168 351#define SROM9_5GMPO_LOFDMBW20 170 352#define SROM9_5GMPO_LOFDMBW20UL 172 353#define SROM9_5GHPO_LOFDMBW20 174 354#define SROM9_5GHPO_LOFDMBW20UL 176 355 356#define SROM9_2GPO_MCSBW20 178 357#define SROM9_2GPO_MCSBW20UL 180 358#define SROM9_2GPO_MCSBW40 182 359 360#define SROM9_5GLPO_MCSBW20 184 361#define SROM9_5GLPO_MCSBW20UL 186 362#define SROM9_5GLPO_MCSBW40 188 363#define SROM9_5GMPO_MCSBW20 190 364#define SROM9_5GMPO_MCSBW20UL 192 365#define SROM9_5GMPO_MCSBW40 194 366#define SROM9_5GHPO_MCSBW20 196 367#define SROM9_5GHPO_MCSBW20UL 198 368#define SROM9_5GHPO_MCSBW40 200 369 370#define SROM9_PO_MCS32 202 371#define SROM9_PO_LOFDM40DUP 203 372#define SROM9_EU_EDCRSTH 204 373#define SROM10_EU_EDCRSTH 204 374#define SROM8_RXGAINERR_2G 205 375#define SROM8_RXGAINERR_5GL 206 376#define SROM8_RXGAINERR_5GM 207 377#define SROM8_RXGAINERR_5GH 208 378#define SROM8_RXGAINERR_5GU 209 379#define SROM8_SUBBAND_PPR 210 380#define SROM8_PCIEINGRESS_WAR 211 381#define SROM8_EU_EDCRSTH 212 382#define SROM9_SAR 212 383 384#define SROM8_NOISELVL_2G 213 385#define SROM8_NOISELVL_5GL 214 386#define SROM8_NOISELVL_5GM 215 387#define SROM8_NOISELVL_5GH 216 388#define SROM8_NOISELVL_5GU 217 389#define SROM8_NOISECALOFFSET 218 390 391#define SROM9_REV_CRC 219 392 393#define SROM10_CCKPWROFFSET 218 394#define SROM10_SIGN 219 395#define SROM10_SWCTRLMAP_2G 220 396#define SROM10_CRCREV 229 397 398#define SROM10_WORDS 230 399#define SROM10_SIGNATURE SROM4_SIGNATURE 400 401 402/* SROM REV 11 */ 403#define SROM11_BREV 65 404 405#define SROM11_BFL0 66 406#define SROM11_BFL1 67 407#define SROM11_BFL2 68 408#define SROM11_BFL3 69 409#define SROM11_BFL4 70 410#define SROM11_BFL5 71 411 412#define SROM11_MACHI 72 413#define SROM11_MACMID 73 414#define SROM11_MACLO 74 415 416#define SROM11_CCODE 75 417#define SROM11_REGREV 76 418 419#define SROM11_LEDBH10 77 420#define SROM11_LEDBH32 78 421 422#define SROM11_LEDDC 79 423 424#define SROM11_AA 80 425 426#define SROM11_AGBG10 81 427#define SROM11_AGBG2A0 82 428#define SROM11_AGA21 83 429 430#define SROM11_TXRXC 84 431 432#define SROM11_FEM_CFG1 85 433#define SROM11_FEM_CFG2 86 434 435/* Masks and offsets for FEM_CFG */ 436#define SROM11_FEMCTRL_MASK 0xf800 437#define SROM11_FEMCTRL_SHIFT 11 438#define SROM11_PAPDCAP_MASK 0x0400 439#define SROM11_PAPDCAP_SHIFT 10 440#define SROM11_TWORANGETSSI_MASK 0x0200 441#define SROM11_TWORANGETSSI_SHIFT 9 442#define SROM11_PDGAIN_MASK 0x01f0 443#define SROM11_PDGAIN_SHIFT 4 444#define SROM11_EPAGAIN_MASK 0x000e 445#define SROM11_EPAGAIN_SHIFT 1 446#define SROM11_TSSIPOSSLOPE_MASK 0x0001 447#define SROM11_TSSIPOSSLOPE_SHIFT 0 448#define SROM11_GAINCTRLSPH_MASK 0xf800 449#define SROM11_GAINCTRLSPH_SHIFT 11 450 451#define SROM11_THERMAL 87 452#define SROM11_MPWR_RAWTS 88 453#define SROM11_TS_SLP_OPT_CORRX 89 454#define SROM11_XTAL_FREQ 90 455#define SROM11_5GB0_4080_W0_A1 91 456#define SROM11_PHYCAL_TEMPDELTA 92 457#define SROM11_MPWR_1_AND_2 93 458#define SROM11_5GB0_4080_W1_A1 94 459#define SROM11_TSSIFLOOR_2G 95 460#define SROM11_TSSIFLOOR_5GL 96 461#define SROM11_TSSIFLOOR_5GM 97 462#define SROM11_TSSIFLOOR_5GH 98 463#define SROM11_TSSIFLOOR_5GU 99 464 465/* Masks and offsets for Terrmal parameters */ 466#define SROM11_TEMPS_PERIOD_MASK 0xf0 467#define SROM11_TEMPS_PERIOD_SHIFT 4 468#define SROM11_TEMPS_HYSTERESIS_MASK 0x0f 469#define SROM11_TEMPS_HYSTERESIS_SHIFT 0 470#define SROM11_TEMPCORRX_MASK 0xfc 471#define SROM11_TEMPCORRX_SHIFT 2 472#define SROM11_TEMPSENSE_OPTION_MASK 0x3 473#define SROM11_TEMPSENSE_OPTION_SHIFT 0 474 475#define SROM11_PDOFF_2G_40M_A0_MASK 0x000f 476#define SROM11_PDOFF_2G_40M_A0_SHIFT 0 477#define SROM11_PDOFF_2G_40M_A1_MASK 0x00f0 478#define SROM11_PDOFF_2G_40M_A1_SHIFT 4 479#define SROM11_PDOFF_2G_40M_A2_MASK 0x0f00 480#define SROM11_PDOFF_2G_40M_A2_SHIFT 8 481#define SROM11_PDOFF_2G_40M_VALID_MASK 0x8000 482#define SROM11_PDOFF_2G_40M_VALID_SHIFT 15 483 484#define SROM11_PDOFF_2G_40M 100 485#define SROM11_PDOFF_40M_A0 101 486#define SROM11_PDOFF_40M_A1 102 487#define SROM11_PDOFF_40M_A2 103 488#define SROM11_5GB0_4080_W2_A1 103 489#define SROM11_PDOFF_80M_A0 104 490#define SROM11_PDOFF_80M_A1 105 491#define SROM11_PDOFF_80M_A2 106 492#define SROM11_5GB1_4080_W0_A1 106 493 494#define SROM11_SUBBAND5GVER 107 495 496/* Per-path fields and offset */ 497#define MAX_PATH_SROM_11 3 498#define SROM11_PATH0 108 499#define SROM11_PATH1 128 500#define SROM11_PATH2 148 501 502#define SROM11_2G_MAXP 0 503#define SROM11_5GB1_4080_PA 0 504#define SROM11_2G_PA 1 505#define SROM11_5GB2_4080_PA 2 506#define SROM11_RXGAINS1 4 507#define SROM11_RXGAINS 5 508#define SROM11_5GB3_4080_PA 5 509#define SROM11_5GB1B0_MAXP 6 510#define SROM11_5GB3B2_MAXP 7 511#define SROM11_5GB0_PA 8 512#define SROM11_5GB1_PA 11 513#define SROM11_5GB2_PA 14 514#define SROM11_5GB3_PA 17 515 516/* Masks and offsets for rxgains */ 517#define SROM11_RXGAINS5GTRELNABYPA_MASK 0x8000 518#define SROM11_RXGAINS5GTRELNABYPA_SHIFT 15 519#define SROM11_RXGAINS5GTRISOA_MASK 0x7800 520#define SROM11_RXGAINS5GTRISOA_SHIFT 11 521#define SROM11_RXGAINS5GELNAGAINA_MASK 0x0700 522#define SROM11_RXGAINS5GELNAGAINA_SHIFT 8 523#define SROM11_RXGAINS2GTRELNABYPA_MASK 0x0080 524#define SROM11_RXGAINS2GTRELNABYPA_SHIFT 7 525#define SROM11_RXGAINS2GTRISOA_MASK 0x0078 526#define SROM11_RXGAINS2GTRISOA_SHIFT 3 527#define SROM11_RXGAINS2GELNAGAINA_MASK 0x0007 528#define SROM11_RXGAINS2GELNAGAINA_SHIFT 0 529#define SROM11_RXGAINS5GHTRELNABYPA_MASK 0x8000 530#define SROM11_RXGAINS5GHTRELNABYPA_SHIFT 15 531#define SROM11_RXGAINS5GHTRISOA_MASK 0x7800 532#define SROM11_RXGAINS5GHTRISOA_SHIFT 11 533#define SROM11_RXGAINS5GHELNAGAINA_MASK 0x0700 534#define SROM11_RXGAINS5GHELNAGAINA_SHIFT 8 535#define SROM11_RXGAINS5GMTRELNABYPA_MASK 0x0080 536#define SROM11_RXGAINS5GMTRELNABYPA_SHIFT 7 537#define SROM11_RXGAINS5GMTRISOA_MASK 0x0078 538#define SROM11_RXGAINS5GMTRISOA_SHIFT 3 539#define SROM11_RXGAINS5GMELNAGAINA_MASK 0x0007 540#define SROM11_RXGAINS5GMELNAGAINA_SHIFT 0 541 542/* Power per rate */ 543#define SROM11_CCKBW202GPO 168 544#define SROM11_CCKBW20UL2GPO 169 545#define SROM11_MCSBW202GPO 170 546#define SROM11_MCSBW202GPO_1 171 547#define SROM11_MCSBW402GPO 172 548#define SROM11_MCSBW402GPO_1 173 549#define SROM11_DOT11AGOFDMHRBW202GPO 174 550#define SROM11_OFDMLRBW202GPO 175 551 552#define SROM11_MCSBW205GLPO 176 553#define SROM11_MCSBW205GLPO_1 177 554#define SROM11_MCSBW405GLPO 178 555#define SROM11_MCSBW405GLPO_1 179 556#define SROM11_MCSBW805GLPO 180 557#define SROM11_MCSBW805GLPO_1 181 558#define SROM11_RPCAL_2G 182 559#define SROM11_RPCAL_5GL 183 560#define SROM11_MCSBW205GMPO 184 561#define SROM11_MCSBW205GMPO_1 185 562#define SROM11_MCSBW405GMPO 186 563#define SROM11_MCSBW405GMPO_1 187 564#define SROM11_MCSBW805GMPO 188 565#define SROM11_MCSBW805GMPO_1 189 566#define SROM11_RPCAL_5GM 190 567#define SROM11_RPCAL_5GH 191 568#define SROM11_MCSBW205GHPO 192 569#define SROM11_MCSBW205GHPO_1 193 570#define SROM11_MCSBW405GHPO 194 571#define SROM11_MCSBW405GHPO_1 195 572#define SROM11_MCSBW805GHPO 196 573#define SROM11_MCSBW805GHPO_1 197 574#define SROM11_RPCAL_5GU 198 575#define SROM11_PDOFF_2G_CCK 199 576#define SROM11_MCSLR5GLPO 200 577#define SROM11_MCSLR5GMPO 201 578#define SROM11_MCSLR5GHPO 202 579 580#define SROM11_SB20IN40HRPO 203 581#define SROM11_SB20IN80AND160HR5GLPO 204 582#define SROM11_SB40AND80HR5GLPO 205 583#define SROM11_SB20IN80AND160HR5GMPO 206 584#define SROM11_SB40AND80HR5GMPO 207 585#define SROM11_SB20IN80AND160HR5GHPO 208 586#define SROM11_SB40AND80HR5GHPO 209 587#define SROM11_SB20IN40LRPO 210 588#define SROM11_SB20IN80AND160LR5GLPO 211 589#define SROM11_SB40AND80LR5GLPO 212 590#define SROM11_TXIDXCAP2G 212 591#define SROM11_SB20IN80AND160LR5GMPO 213 592#define SROM11_SB40AND80LR5GMPO 214 593#define SROM11_TXIDXCAP5G 214 594#define SROM11_SB20IN80AND160LR5GHPO 215 595#define SROM11_SB40AND80LR5GHPO 216 596 597#define SROM11_DOT11AGDUPHRPO 217 598#define SROM11_DOT11AGDUPLRPO 218 599 600/* MISC */ 601#define SROM11_PCIEINGRESS_WAR 220 602#define SROM11_SAR 221 603 604#define SROM11_NOISELVL_2G 222 605#define SROM11_NOISELVL_5GL 223 606#define SROM11_NOISELVL_5GM 224 607#define SROM11_NOISELVL_5GH 225 608#define SROM11_NOISELVL_5GU 226 609 610#define SROM11_RXGAINERR_2G 227 611#define SROM11_RXGAINERR_5GL 228 612#define SROM11_RXGAINERR_5GM 229 613#define SROM11_RXGAINERR_5GH 230 614#define SROM11_RXGAINERR_5GU 231 615 616#define SROM11_EU_EDCRSTH 232 617 618#define SROM11_SIGN 64 619#define SROM11_CRCREV 233 620 621#define SROM11_WORDS 234 622#define SROM11_SIGNATURE 0x0634 623 624typedef struct { 625 uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */ 626 uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 627 uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */ 628 uint8 triso; /* TR switch isolation */ 629 uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */ 630} srom_fem_t; 631 632#endif /* _bcmsrom_fmt_h_ */ 633