1/* 2 * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 SoC 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 */ 11 12#ifndef _MPC8610_I2S_H 13#define _MPC8610_I2S_H 14 15/* SSI Register Map */ 16struct ccsr_ssi { 17 __be32 stx0; /* 0x.0000 - SSI Transmit Data Register 0 */ 18 __be32 stx1; /* 0x.0004 - SSI Transmit Data Register 1 */ 19 __be32 srx0; /* 0x.0008 - SSI Receive Data Register 0 */ 20 __be32 srx1; /* 0x.000C - SSI Receive Data Register 1 */ 21 __be32 scr; /* 0x.0010 - SSI Control Register */ 22 __be32 sisr; /* 0x.0014 - SSI Interrupt Status Register Mixed */ 23 __be32 sier; /* 0x.0018 - SSI Interrupt Enable Register */ 24 __be32 stcr; /* 0x.001C - SSI Transmit Configuration Register */ 25 __be32 srcr; /* 0x.0020 - SSI Receive Configuration Register */ 26 __be32 stccr; /* 0x.0024 - SSI Transmit Clock Control Register */ 27 __be32 srccr; /* 0x.0028 - SSI Receive Clock Control Register */ 28 __be32 sfcsr; /* 0x.002C - SSI FIFO Control/Status Register */ 29 __be32 str; /* 0x.0030 - SSI Test Register */ 30 __be32 sor; /* 0x.0034 - SSI Option Register */ 31 __be32 sacnt; /* 0x.0038 - SSI AC97 Control Register */ 32 __be32 sacadd; /* 0x.003C - SSI AC97 Command Address Register */ 33 __be32 sacdat; /* 0x.0040 - SSI AC97 Command Data Register */ 34 __be32 satag; /* 0x.0044 - SSI AC97 Tag Register */ 35 __be32 stmsk; /* 0x.0048 - SSI Transmit Time Slot Mask Register */ 36 __be32 srmsk; /* 0x.004C - SSI Receive Time Slot Mask Register */ 37 __be32 saccst; /* 0x.0050 - SSI AC97 Channel Status Register */ 38 __be32 saccen; /* 0x.0054 - SSI AC97 Channel Enable Register */ 39 __be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */ 40}; 41 42#define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800 43#define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400 44#define CCSR_SSI_SCR_TCH_EN 0x00000100 45#define CCSR_SSI_SCR_SYS_CLK_EN 0x00000080 46#define CCSR_SSI_SCR_I2S_MODE_MASK 0x00000060 47#define CCSR_SSI_SCR_I2S_MODE_NORMAL 0x00000000 48#define CCSR_SSI_SCR_I2S_MODE_MASTER 0x00000020 49#define CCSR_SSI_SCR_I2S_MODE_SLAVE 0x00000040 50#define CCSR_SSI_SCR_SYN 0x00000010 51#define CCSR_SSI_SCR_NET 0x00000008 52#define CCSR_SSI_SCR_RE 0x00000004 53#define CCSR_SSI_SCR_TE 0x00000002 54#define CCSR_SSI_SCR_SSIEN 0x00000001 55 56#define CCSR_SSI_SISR_RFRC 0x01000000 57#define CCSR_SSI_SISR_TFRC 0x00800000 58#define CCSR_SSI_SISR_CMDAU 0x00040000 59#define CCSR_SSI_SISR_CMDDU 0x00020000 60#define CCSR_SSI_SISR_RXT 0x00010000 61#define CCSR_SSI_SISR_RDR1 0x00008000 62#define CCSR_SSI_SISR_RDR0 0x00004000 63#define CCSR_SSI_SISR_TDE1 0x00002000 64#define CCSR_SSI_SISR_TDE0 0x00001000 65#define CCSR_SSI_SISR_ROE1 0x00000800 66#define CCSR_SSI_SISR_ROE0 0x00000400 67#define CCSR_SSI_SISR_TUE1 0x00000200 68#define CCSR_SSI_SISR_TUE0 0x00000100 69#define CCSR_SSI_SISR_TFS 0x00000080 70#define CCSR_SSI_SISR_RFS 0x00000040 71#define CCSR_SSI_SISR_TLS 0x00000020 72#define CCSR_SSI_SISR_RLS 0x00000010 73#define CCSR_SSI_SISR_RFF1 0x00000008 74#define CCSR_SSI_SISR_RFF0 0x00000004 75#define CCSR_SSI_SISR_TFE1 0x00000002 76#define CCSR_SSI_SISR_TFE0 0x00000001 77 78#define CCSR_SSI_SIER_RFRC_EN 0x01000000 79#define CCSR_SSI_SIER_TFRC_EN 0x00800000 80#define CCSR_SSI_SIER_RDMAE 0x00400000 81#define CCSR_SSI_SIER_RIE 0x00200000 82#define CCSR_SSI_SIER_TDMAE 0x00100000 83#define CCSR_SSI_SIER_TIE 0x00080000 84#define CCSR_SSI_SIER_CMDAU_EN 0x00040000 85#define CCSR_SSI_SIER_CMDDU_EN 0x00020000 86#define CCSR_SSI_SIER_RXT_EN 0x00010000 87#define CCSR_SSI_SIER_RDR1_EN 0x00008000 88#define CCSR_SSI_SIER_RDR0_EN 0x00004000 89#define CCSR_SSI_SIER_TDE1_EN 0x00002000 90#define CCSR_SSI_SIER_TDE0_EN 0x00001000 91#define CCSR_SSI_SIER_ROE1_EN 0x00000800 92#define CCSR_SSI_SIER_ROE0_EN 0x00000400 93#define CCSR_SSI_SIER_TUE1_EN 0x00000200 94#define CCSR_SSI_SIER_TUE0_EN 0x00000100 95#define CCSR_SSI_SIER_TFS_EN 0x00000080 96#define CCSR_SSI_SIER_RFS_EN 0x00000040 97#define CCSR_SSI_SIER_TLS_EN 0x00000020 98#define CCSR_SSI_SIER_RLS_EN 0x00000010 99#define CCSR_SSI_SIER_RFF1_EN 0x00000008 100#define CCSR_SSI_SIER_RFF0_EN 0x00000004 101#define CCSR_SSI_SIER_TFE1_EN 0x00000002 102#define CCSR_SSI_SIER_TFE0_EN 0x00000001 103 104#define CCSR_SSI_STCR_TXBIT0 0x00000200 105#define CCSR_SSI_STCR_TFEN1 0x00000100 106#define CCSR_SSI_STCR_TFEN0 0x00000080 107#define CCSR_SSI_STCR_TFDIR 0x00000040 108#define CCSR_SSI_STCR_TXDIR 0x00000020 109#define CCSR_SSI_STCR_TSHFD 0x00000010 110#define CCSR_SSI_STCR_TSCKP 0x00000008 111#define CCSR_SSI_STCR_TFSI 0x00000004 112#define CCSR_SSI_STCR_TFSL 0x00000002 113#define CCSR_SSI_STCR_TEFS 0x00000001 114 115#define CCSR_SSI_SRCR_RXEXT 0x00000400 116#define CCSR_SSI_SRCR_RXBIT0 0x00000200 117#define CCSR_SSI_SRCR_RFEN1 0x00000100 118#define CCSR_SSI_SRCR_RFEN0 0x00000080 119#define CCSR_SSI_SRCR_RFDIR 0x00000040 120#define CCSR_SSI_SRCR_RXDIR 0x00000020 121#define CCSR_SSI_SRCR_RSHFD 0x00000010 122#define CCSR_SSI_SRCR_RSCKP 0x00000008 123#define CCSR_SSI_SRCR_RFSI 0x00000004 124#define CCSR_SSI_SRCR_RFSL 0x00000002 125#define CCSR_SSI_SRCR_REFS 0x00000001 126 127/* STCCR and SRCCR */ 128#define CCSR_SSI_SxCCR_DIV2 0x00040000 129#define CCSR_SSI_SxCCR_PSR 0x00020000 130#define CCSR_SSI_SxCCR_WL_SHIFT 13 131#define CCSR_SSI_SxCCR_WL_MASK 0x0001E000 132#define CCSR_SSI_SxCCR_WL(x) \ 133 (((((x) / 2) - 1) << CCSR_SSI_SxCCR_WL_SHIFT) & CCSR_SSI_SxCCR_WL_MASK) 134#define CCSR_SSI_SxCCR_DC_SHIFT 8 135#define CCSR_SSI_SxCCR_DC_MASK 0x00001F00 136#define CCSR_SSI_SxCCR_DC(x) \ 137 ((((x) - 1) << CCSR_SSI_SxCCR_DC_SHIFT) & CCSR_SSI_SxCCR_DC_MASK) 138#define CCSR_SSI_SxCCR_PM_SHIFT 0 139#define CCSR_SSI_SxCCR_PM_MASK 0x000000FF 140#define CCSR_SSI_SxCCR_PM(x) \ 141 ((((x) - 1) << CCSR_SSI_SxCCR_PM_SHIFT) & CCSR_SSI_SxCCR_PM_MASK) 142 143/* 144 * The xFCNT bits are read-only, and the xFWM bits are read/write. Use the 145 * CCSR_SSI_SFCSR_xFCNTy() macros to read the FIFO counters, and use the 146 * CCSR_SSI_SFCSR_xFWMy() macros to set the watermarks. 147 */ 148#define CCSR_SSI_SFCSR_RFCNT1_SHIFT 28 149#define CCSR_SSI_SFCSR_RFCNT1_MASK 0xF0000000 150#define CCSR_SSI_SFCSR_RFCNT1(x) \ 151 (((x) & CCSR_SSI_SFCSR_RFCNT1_MASK) >> CCSR_SSI_SFCSR_RFCNT1_SHIFT) 152#define CCSR_SSI_SFCSR_TFCNT1_SHIFT 24 153#define CCSR_SSI_SFCSR_TFCNT1_MASK 0x0F000000 154#define CCSR_SSI_SFCSR_TFCNT1(x) \ 155 (((x) & CCSR_SSI_SFCSR_TFCNT1_MASK) >> CCSR_SSI_SFCSR_TFCNT1_SHIFT) 156#define CCSR_SSI_SFCSR_RFWM1_SHIFT 20 157#define CCSR_SSI_SFCSR_RFWM1_MASK 0x00F00000 158#define CCSR_SSI_SFCSR_RFWM1(x) \ 159 (((x) << CCSR_SSI_SFCSR_RFWM1_SHIFT) & CCSR_SSI_SFCSR_RFWM1_MASK) 160#define CCSR_SSI_SFCSR_TFWM1_SHIFT 16 161#define CCSR_SSI_SFCSR_TFWM1_MASK 0x000F0000 162#define CCSR_SSI_SFCSR_TFWM1(x) \ 163 (((x) << CCSR_SSI_SFCSR_TFWM1_SHIFT) & CCSR_SSI_SFCSR_TFWM1_MASK) 164#define CCSR_SSI_SFCSR_RFCNT0_SHIFT 12 165#define CCSR_SSI_SFCSR_RFCNT0_MASK 0x0000F000 166#define CCSR_SSI_SFCSR_RFCNT0(x) \ 167 (((x) & CCSR_SSI_SFCSR_RFCNT0_MASK) >> CCSR_SSI_SFCSR_RFCNT0_SHIFT) 168#define CCSR_SSI_SFCSR_TFCNT0_SHIFT 8 169#define CCSR_SSI_SFCSR_TFCNT0_MASK 0x00000F00 170#define CCSR_SSI_SFCSR_TFCNT0(x) \ 171 (((x) & CCSR_SSI_SFCSR_TFCNT0_MASK) >> CCSR_SSI_SFCSR_TFCNT0_SHIFT) 172#define CCSR_SSI_SFCSR_RFWM0_SHIFT 4 173#define CCSR_SSI_SFCSR_RFWM0_MASK 0x000000F0 174#define CCSR_SSI_SFCSR_RFWM0(x) \ 175 (((x) << CCSR_SSI_SFCSR_RFWM0_SHIFT) & CCSR_SSI_SFCSR_RFWM0_MASK) 176#define CCSR_SSI_SFCSR_TFWM0_SHIFT 0 177#define CCSR_SSI_SFCSR_TFWM0_MASK 0x0000000F 178#define CCSR_SSI_SFCSR_TFWM0(x) \ 179 (((x) << CCSR_SSI_SFCSR_TFWM0_SHIFT) & CCSR_SSI_SFCSR_TFWM0_MASK) 180 181#define CCSR_SSI_STR_TEST 0x00008000 182#define CCSR_SSI_STR_RCK2TCK 0x00004000 183#define CCSR_SSI_STR_RFS2TFS 0x00002000 184#define CCSR_SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F) 185#define CCSR_SSI_STR_TXD2RXD 0x00000080 186#define CCSR_SSI_STR_TCK2RCK 0x00000040 187#define CCSR_SSI_STR_TFS2RFS 0x00000020 188#define CCSR_SSI_STR_TXSTATE(x) ((x) & 0x1F) 189 190#define CCSR_SSI_SOR_CLKOFF 0x00000040 191#define CCSR_SSI_SOR_RX_CLR 0x00000020 192#define CCSR_SSI_SOR_TX_CLR 0x00000010 193#define CCSR_SSI_SOR_INIT 0x00000008 194#define CCSR_SSI_SOR_WAIT_SHIFT 1 195#define CCSR_SSI_SOR_WAIT_MASK 0x00000006 196#define CCSR_SSI_SOR_WAIT(x) (((x) & 3) << CCSR_SSI_SOR_WAIT_SHIFT) 197#define CCSR_SSI_SOR_SYNRST 0x00000001 198 199/* Instantiation data for an SSI interface 200 * 201 * This structure contains all the information that the the SSI driver needs 202 * to instantiate an SSI interface with ALSA. The machine driver should 203 * create this structure, fill it in, call fsl_ssi_create_dai(), and then 204 * delete the structure. 205 * 206 * id: which SSI this is (0, 1, etc. ) 207 * ssi: pointer to the SSI's registers 208 * ssi_phys: physical address of the SSI registers 209 * irq: IRQ of this SSI 210 * dev: struct device, used to create the sysfs statistics file 211 * asynchronous: 0=synchronous mode, 1=asynchronous mode 212*/ 213struct fsl_ssi_info { 214 unsigned int id; 215 struct ccsr_ssi __iomem *ssi; 216 dma_addr_t ssi_phys; 217 unsigned int irq; 218 struct device *dev; 219 int asynchronous; 220}; 221 222struct snd_soc_dai *fsl_ssi_create_dai(struct fsl_ssi_info *ssi_info); 223void fsl_ssi_destroy_dai(struct snd_soc_dai *fsl_ssi_dai); 224 225#endif 226