1/* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 * 11 * This driver implements ASoC support for the Elo DMA controller, which is 12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 13 * the PCM driver is what handles the DMA buffer. 14 */ 15 16#include <linux/module.h> 17#include <linux/init.h> 18#include <linux/platform_device.h> 19#include <linux/dma-mapping.h> 20#include <linux/interrupt.h> 21#include <linux/delay.h> 22#include <linux/gfp.h> 23 24#include <sound/core.h> 25#include <sound/pcm.h> 26#include <sound/pcm_params.h> 27#include <sound/soc.h> 28 29#include <asm/io.h> 30 31#include "fsl_dma.h" 32 33/* 34 * The formats that the DMA controller supports, which is anything 35 * that is 8, 16, or 32 bits. 36 */ 37#define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 38 SNDRV_PCM_FMTBIT_U8 | \ 39 SNDRV_PCM_FMTBIT_S16_LE | \ 40 SNDRV_PCM_FMTBIT_S16_BE | \ 41 SNDRV_PCM_FMTBIT_U16_LE | \ 42 SNDRV_PCM_FMTBIT_U16_BE | \ 43 SNDRV_PCM_FMTBIT_S24_LE | \ 44 SNDRV_PCM_FMTBIT_S24_BE | \ 45 SNDRV_PCM_FMTBIT_U24_LE | \ 46 SNDRV_PCM_FMTBIT_U24_BE | \ 47 SNDRV_PCM_FMTBIT_S32_LE | \ 48 SNDRV_PCM_FMTBIT_S32_BE | \ 49 SNDRV_PCM_FMTBIT_U32_LE | \ 50 SNDRV_PCM_FMTBIT_U32_BE) 51 52#define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 53 SNDRV_PCM_RATE_CONTINUOUS) 54 55/* DMA global data. This structure is used by fsl_dma_open() to determine 56 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does 57 * not allow the machine driver to provide this information to the PCM 58 * driver in advance, and there's no way to differentiate between the two 59 * DMA controllers. So for now, this driver only supports one SSI device 60 * using two DMA channels. We cannot support multiple DMA devices. 61 * 62 * ssi_stx_phys: bus address of SSI STX register 63 * ssi_srx_phys: bus address of SSI SRX register 64 * dma_channel: pointer to the DMA channel's registers 65 * irq: IRQ for this DMA channel 66 * assigned: set to 1 if that DMA channel is assigned to a substream 67 */ 68static struct { 69 dma_addr_t ssi_stx_phys; 70 dma_addr_t ssi_srx_phys; 71 struct ccsr_dma_channel __iomem *dma_channel[2]; 72 unsigned int irq[2]; 73 unsigned int assigned[2]; 74} dma_global_data; 75 76/* 77 * The number of DMA links to use. Two is the bare minimum, but if you 78 * have really small links you might need more. 79 */ 80#define NUM_DMA_LINKS 2 81 82/** fsl_dma_private: p-substream DMA data 83 * 84 * Each substream has a 1-to-1 association with a DMA channel. 85 * 86 * The link[] array is first because it needs to be aligned on a 32-byte 87 * boundary, so putting it first will ensure alignment without padding the 88 * structure. 89 * 90 * @link[]: array of link descriptors 91 * @controller_id: which DMA controller (0, 1, ...) 92 * @channel_id: which DMA channel on the controller (0, 1, 2, ...) 93 * @dma_channel: pointer to the DMA channel's registers 94 * @irq: IRQ for this DMA channel 95 * @substream: pointer to the substream object, needed by the ISR 96 * @ssi_sxx_phys: bus address of the STX or SRX register to use 97 * @ld_buf_phys: physical address of the LD buffer 98 * @current_link: index into link[] of the link currently being processed 99 * @dma_buf_phys: physical address of the DMA buffer 100 * @dma_buf_next: physical address of the next period to process 101 * @dma_buf_end: physical address of the byte after the end of the DMA 102 * @buffer period_size: the size of a single period 103 * @num_periods: the number of periods in the DMA buffer 104 */ 105struct fsl_dma_private { 106 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 107 unsigned int controller_id; 108 unsigned int channel_id; 109 struct ccsr_dma_channel __iomem *dma_channel; 110 unsigned int irq; 111 struct snd_pcm_substream *substream; 112 dma_addr_t ssi_sxx_phys; 113 dma_addr_t ld_buf_phys; 114 unsigned int current_link; 115 dma_addr_t dma_buf_phys; 116 dma_addr_t dma_buf_next; 117 dma_addr_t dma_buf_end; 118 size_t period_size; 119 unsigned int num_periods; 120}; 121 122/** 123 * fsl_dma_hardare: define characteristics of the PCM hardware. 124 * 125 * The PCM hardware is the Freescale DMA controller. This structure defines 126 * the capabilities of that hardware. 127 * 128 * Since the sampling rate and data format are not controlled by the DMA 129 * controller, we specify no limits for those values. The only exception is 130 * period_bytes_min, which is set to a reasonably low value to prevent the 131 * DMA controller from generating too many interrupts per second. 132 * 133 * Since each link descriptor has a 32-bit byte count field, we set 134 * period_bytes_max to the largest 32-bit number. We also have no maximum 135 * number of periods. 136 * 137 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 138 * limitation in the SSI driver requires the sample rates for playback and 139 * capture to be the same. 140 */ 141static const struct snd_pcm_hardware fsl_dma_hardware = { 142 143 .info = SNDRV_PCM_INFO_INTERLEAVED | 144 SNDRV_PCM_INFO_MMAP | 145 SNDRV_PCM_INFO_MMAP_VALID | 146 SNDRV_PCM_INFO_JOINT_DUPLEX | 147 SNDRV_PCM_INFO_PAUSE, 148 .formats = FSLDMA_PCM_FORMATS, 149 .rates = FSLDMA_PCM_RATES, 150 .rate_min = 5512, 151 .rate_max = 192000, 152 .period_bytes_min = 512, /* A reasonable limit */ 153 .period_bytes_max = (u32) -1, 154 .periods_min = NUM_DMA_LINKS, 155 .periods_max = (unsigned int) -1, 156 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 157}; 158 159/** 160 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 161 * 162 * This function should be called by the ISR whenever the DMA controller 163 * halts data transfer. 164 */ 165static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 166{ 167 unsigned long flags; 168 169 snd_pcm_stream_lock_irqsave(substream, flags); 170 171 if (snd_pcm_running(substream)) 172 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 173 174 snd_pcm_stream_unlock_irqrestore(substream, flags); 175} 176 177/** 178 * fsl_dma_update_pointers - update LD pointers to point to the next period 179 * 180 * As each period is completed, this function changes the the link 181 * descriptor pointers for that period to point to the next period. 182 */ 183static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 184{ 185 struct fsl_dma_link_descriptor *link = 186 &dma_private->link[dma_private->current_link]; 187 188 /* Update our link descriptors to point to the next period */ 189 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 190 link->source_addr = 191 cpu_to_be32(dma_private->dma_buf_next); 192 else 193 link->dest_addr = 194 cpu_to_be32(dma_private->dma_buf_next); 195 196 /* Update our variables for next time */ 197 dma_private->dma_buf_next += dma_private->period_size; 198 199 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 200 dma_private->dma_buf_next = dma_private->dma_buf_phys; 201 202 if (++dma_private->current_link >= NUM_DMA_LINKS) 203 dma_private->current_link = 0; 204} 205 206/** 207 * fsl_dma_isr: interrupt handler for the DMA controller 208 * 209 * @irq: IRQ of the DMA channel 210 * @dev_id: pointer to the dma_private structure for this DMA channel 211 */ 212static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 213{ 214 struct fsl_dma_private *dma_private = dev_id; 215 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 216 irqreturn_t ret = IRQ_NONE; 217 u32 sr, sr2 = 0; 218 219 /* We got an interrupt, so read the status register to see what we 220 were interrupted for. 221 */ 222 sr = in_be32(&dma_channel->sr); 223 224 if (sr & CCSR_DMA_SR_TE) { 225 dev_err(dma_private->substream->pcm->card->dev, 226 "DMA transmit error (controller=%u channel=%u irq=%u\n", 227 dma_private->controller_id, 228 dma_private->channel_id, irq); 229 fsl_dma_abort_stream(dma_private->substream); 230 sr2 |= CCSR_DMA_SR_TE; 231 ret = IRQ_HANDLED; 232 } 233 234 if (sr & CCSR_DMA_SR_CH) 235 ret = IRQ_HANDLED; 236 237 if (sr & CCSR_DMA_SR_PE) { 238 dev_err(dma_private->substream->pcm->card->dev, 239 "DMA%u programming error (channel=%u irq=%u)\n", 240 dma_private->controller_id, 241 dma_private->channel_id, irq); 242 fsl_dma_abort_stream(dma_private->substream); 243 sr2 |= CCSR_DMA_SR_PE; 244 ret = IRQ_HANDLED; 245 } 246 247 if (sr & CCSR_DMA_SR_EOLNI) { 248 sr2 |= CCSR_DMA_SR_EOLNI; 249 ret = IRQ_HANDLED; 250 } 251 252 if (sr & CCSR_DMA_SR_CB) 253 ret = IRQ_HANDLED; 254 255 if (sr & CCSR_DMA_SR_EOSI) { 256 struct snd_pcm_substream *substream = dma_private->substream; 257 258 /* Tell ALSA we completed a period. */ 259 snd_pcm_period_elapsed(substream); 260 261 /* 262 * Update our link descriptors to point to the next period. We 263 * only need to do this if the number of periods is not equal to 264 * the number of links. 265 */ 266 if (dma_private->num_periods != NUM_DMA_LINKS) 267 fsl_dma_update_pointers(dma_private); 268 269 sr2 |= CCSR_DMA_SR_EOSI; 270 ret = IRQ_HANDLED; 271 } 272 273 if (sr & CCSR_DMA_SR_EOLSI) { 274 sr2 |= CCSR_DMA_SR_EOLSI; 275 ret = IRQ_HANDLED; 276 } 277 278 /* Clear the bits that we set */ 279 if (sr2) 280 out_be32(&dma_channel->sr, sr2); 281 282 return ret; 283} 284 285/** 286 * fsl_dma_new: initialize this PCM driver. 287 * 288 * This function is called when the codec driver calls snd_soc_new_pcms(), 289 * once for each .dai_link in the machine driver's snd_soc_card 290 * structure. 291 */ 292static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, 293 struct snd_pcm *pcm) 294{ 295 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32); 296 int ret; 297 298 if (!card->dev->dma_mask) 299 card->dev->dma_mask = &fsl_dma_dmamask; 300 301 if (!card->dev->coherent_dma_mask) 302 card->dev->coherent_dma_mask = fsl_dma_dmamask; 303 304 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 305 fsl_dma_hardware.buffer_bytes_max, 306 &pcm->streams[0].substream->dma_buffer); 307 if (ret) { 308 dev_err(card->dev, 309 "Can't allocate playback DMA buffer (size=%u)\n", 310 fsl_dma_hardware.buffer_bytes_max); 311 return -ENOMEM; 312 } 313 314 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 315 fsl_dma_hardware.buffer_bytes_max, 316 &pcm->streams[1].substream->dma_buffer); 317 if (ret) { 318 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 319 dev_err(card->dev, 320 "Can't allocate capture DMA buffer (size=%u)\n", 321 fsl_dma_hardware.buffer_bytes_max); 322 return -ENOMEM; 323 } 324 325 return 0; 326} 327 328/** 329 * fsl_dma_open: open a new substream. 330 * 331 * Each substream has its own DMA buffer. 332 * 333 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 334 * descriptors that ping-pong from one period to the next. For example, if 335 * there are six periods and two link descriptors, this is how they look 336 * before playback starts: 337 * 338 * The last link descriptor 339 * ____________ points back to the first 340 * | | 341 * V | 342 * ___ ___ | 343 * | |->| |->| 344 * |___| |___| 345 * | | 346 * | | 347 * V V 348 * _________________________________________ 349 * | | | | | | | The DMA buffer is 350 * | | | | | | | divided into 6 parts 351 * |______|______|______|______|______|______| 352 * 353 * and here's how they look after the first period is finished playing: 354 * 355 * ____________ 356 * | | 357 * V | 358 * ___ ___ | 359 * | |->| |->| 360 * |___| |___| 361 * | | 362 * |______________ 363 * | | 364 * V V 365 * _________________________________________ 366 * | | | | | | | 367 * | | | | | | | 368 * |______|______|______|______|______|______| 369 * 370 * The first link descriptor now points to the third period. The DMA 371 * controller is currently playing the second period. When it finishes, it 372 * will jump back to the first descriptor and play the third period. 373 * 374 * There are four reasons we do this: 375 * 376 * 1. The only way to get the DMA controller to automatically restart the 377 * transfer when it gets to the end of the buffer is to use chaining 378 * mode. Basic direct mode doesn't offer that feature. 379 * 2. We need to receive an interrupt at the end of every period. The DMA 380 * controller can generate an interrupt at the end of every link transfer 381 * (aka segment). Making each period into a DMA segment will give us the 382 * interrupts we need. 383 * 3. By creating only two link descriptors, regardless of the number of 384 * periods, we do not need to reallocate the link descriptors if the 385 * number of periods changes. 386 * 4. All of the audio data is still stored in a single, contiguous DMA 387 * buffer, which is what ALSA expects. We're just dividing it into 388 * contiguous parts, and creating a link descriptor for each one. 389 */ 390static int fsl_dma_open(struct snd_pcm_substream *substream) 391{ 392 struct snd_pcm_runtime *runtime = substream->runtime; 393 struct fsl_dma_private *dma_private; 394 struct ccsr_dma_channel __iomem *dma_channel; 395 dma_addr_t ld_buf_phys; 396 u64 temp_link; /* Pointer to next link descriptor */ 397 u32 mr; 398 unsigned int channel; 399 int ret = 0; 400 unsigned int i; 401 402 /* 403 * Reject any DMA buffer whose size is not a multiple of the period 404 * size. We need to make sure that the DMA buffer can be evenly divided 405 * into periods. 406 */ 407 ret = snd_pcm_hw_constraint_integer(runtime, 408 SNDRV_PCM_HW_PARAM_PERIODS); 409 if (ret < 0) { 410 dev_err(substream->pcm->card->dev, "invalid buffer size\n"); 411 return ret; 412 } 413 414 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 415 416 if (dma_global_data.assigned[channel]) { 417 dev_err(substream->pcm->card->dev, 418 "DMA channel already assigned\n"); 419 return -EBUSY; 420 } 421 422 dma_private = dma_alloc_coherent(substream->pcm->card->dev, 423 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL); 424 if (!dma_private) { 425 dev_err(substream->pcm->card->dev, 426 "can't allocate DMA private data\n"); 427 return -ENOMEM; 428 } 429 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 430 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys; 431 else 432 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys; 433 434 dma_private->dma_channel = dma_global_data.dma_channel[channel]; 435 dma_private->irq = dma_global_data.irq[channel]; 436 dma_private->substream = substream; 437 dma_private->ld_buf_phys = ld_buf_phys; 438 dma_private->dma_buf_phys = substream->dma_buffer.addr; 439 440 /* We only support one DMA controller for now */ 441 dma_private->controller_id = 0; 442 dma_private->channel_id = channel; 443 444 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 445 if (ret) { 446 dev_err(substream->pcm->card->dev, 447 "can't register ISR for IRQ %u (ret=%i)\n", 448 dma_private->irq, ret); 449 dma_free_coherent(substream->pcm->card->dev, 450 sizeof(struct fsl_dma_private), 451 dma_private, dma_private->ld_buf_phys); 452 return ret; 453 } 454 455 dma_global_data.assigned[channel] = 1; 456 457 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 458 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 459 runtime->private_data = dma_private; 460 461 /* Program the fixed DMA controller parameters */ 462 463 dma_channel = dma_private->dma_channel; 464 465 temp_link = dma_private->ld_buf_phys + 466 sizeof(struct fsl_dma_link_descriptor); 467 468 for (i = 0; i < NUM_DMA_LINKS; i++) { 469 dma_private->link[i].next = cpu_to_be64(temp_link); 470 471 temp_link += sizeof(struct fsl_dma_link_descriptor); 472 } 473 /* The last link descriptor points to the first */ 474 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 475 476 /* Tell the DMA controller where the first link descriptor is */ 477 out_be32(&dma_channel->clndar, 478 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 479 out_be32(&dma_channel->eclndar, 480 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 481 482 /* The manual says the BCR must be clear before enabling EMP */ 483 out_be32(&dma_channel->bcr, 0); 484 485 /* 486 * Program the mode register for interrupts, external master control, 487 * and source/destination hold. Also clear the Channel Abort bit. 488 */ 489 mr = in_be32(&dma_channel->mr) & 490 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 491 492 /* 493 * We want External Master Start and External Master Pause enabled, 494 * because the SSI is controlling the DMA controller. We want the DMA 495 * controller to be set up in advance, and then we signal only the SSI 496 * to start transferring. 497 * 498 * We want End-Of-Segment Interrupts enabled, because this will generate 499 * an interrupt at the end of each segment (each link descriptor 500 * represents one segment). Each DMA segment is the same thing as an 501 * ALSA period, so this is how we get an interrupt at the end of every 502 * period. 503 * 504 * We want Error Interrupt enabled, so that we can get an error if 505 * the DMA controller is mis-programmed somehow. 506 */ 507 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 508 CCSR_DMA_MR_EMS_EN; 509 510 /* For playback, we want the destination address to be held. For 511 capture, set the source address to be held. */ 512 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 513 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 514 515 out_be32(&dma_channel->mr, mr); 516 517 return 0; 518} 519 520/** 521 * fsl_dma_hw_params: continue initializing the DMA links 522 * 523 * This function obtains hardware parameters about the opened stream and 524 * programs the DMA controller accordingly. 525 * 526 * One drawback of big-endian is that when copying integers of different 527 * sizes to a fixed-sized register, the address to which the integer must be 528 * copied is dependent on the size of the integer. 529 * 530 * For example, if P is the address of a 32-bit register, and X is a 32-bit 531 * integer, then X should be copied to address P. However, if X is a 16-bit 532 * integer, then it should be copied to P+2. If X is an 8-bit register, 533 * then it should be copied to P+3. 534 * 535 * So for playback of 8-bit samples, the DMA controller must transfer single 536 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 537 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 538 * 539 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 540 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 541 * and 8 bytes at a time). So we do not support packed 24-bit samples. 542 * 24-bit data must be padded to 32 bits. 543 */ 544static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 545 struct snd_pcm_hw_params *hw_params) 546{ 547 struct snd_pcm_runtime *runtime = substream->runtime; 548 struct fsl_dma_private *dma_private = runtime->private_data; 549 550 /* Number of bits per sample */ 551 unsigned int sample_size = 552 snd_pcm_format_physical_width(params_format(hw_params)); 553 554 /* Number of bytes per frame */ 555 unsigned int frame_size = 2 * (sample_size / 8); 556 557 /* Bus address of SSI STX register */ 558 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 559 560 /* Size of the DMA buffer, in bytes */ 561 size_t buffer_size = params_buffer_bytes(hw_params); 562 563 /* Number of bytes per period */ 564 size_t period_size = params_period_bytes(hw_params); 565 566 /* Pointer to next period */ 567 dma_addr_t temp_addr = substream->dma_buffer.addr; 568 569 /* Pointer to DMA controller */ 570 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 571 572 u32 mr; /* DMA Mode Register */ 573 574 unsigned int i; 575 576 /* Initialize our DMA tracking variables */ 577 dma_private->period_size = period_size; 578 dma_private->num_periods = params_periods(hw_params); 579 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 580 dma_private->dma_buf_next = dma_private->dma_buf_phys + 581 (NUM_DMA_LINKS * period_size); 582 583 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 584 /* This happens if the number of periods == NUM_DMA_LINKS */ 585 dma_private->dma_buf_next = dma_private->dma_buf_phys; 586 587 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 588 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 589 590 /* Due to a quirk of the SSI's STX register, the target address 591 * for the DMA operations depends on the sample size. So we calculate 592 * that offset here. While we're at it, also tell the DMA controller 593 * how much data to transfer per sample. 594 */ 595 switch (sample_size) { 596 case 8: 597 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 598 ssi_sxx_phys += 3; 599 break; 600 case 16: 601 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 602 ssi_sxx_phys += 2; 603 break; 604 case 32: 605 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 606 break; 607 default: 608 /* We should never get here */ 609 dev_err(substream->pcm->card->dev, 610 "unsupported sample size %u\n", sample_size); 611 return -EINVAL; 612 } 613 614 /* 615 * BWC should always be a multiple of the frame size. BWC determines 616 * how many bytes are sent/received before the DMA controller checks the 617 * SSI to see if it needs to stop. For playback, the transmit FIFO can 618 * hold three frames, so we want to send two frames at a time. For 619 * capture, the receive FIFO is triggered when it contains one frame, so 620 * we want to receive one frame at a time. 621 */ 622 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 623 mr |= CCSR_DMA_MR_BWC(2 * frame_size); 624 else 625 mr |= CCSR_DMA_MR_BWC(frame_size); 626 627 out_be32(&dma_channel->mr, mr); 628 629 for (i = 0; i < NUM_DMA_LINKS; i++) { 630 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 631 632 link->count = cpu_to_be32(period_size); 633 634 /* Even though the DMA controller supports 36-bit addressing, 635 * for simplicity we allow only 32-bit addresses for the audio 636 * buffer itself. This was enforced in fsl_dma_new() with the 637 * DMA mask. 638 * 639 * The snoop bit tells the DMA controller whether it should tell 640 * the ECM to snoop during a read or write to an address. For 641 * audio, we use DMA to transfer data between memory and an I/O 642 * device (the SSI's STX0 or SRX0 register). Snooping is only 643 * needed if there is a cache, so we need to snoop memory 644 * addresses only. For playback, that means we snoop the source 645 * but not the destination. For capture, we snoop the 646 * destination but not the source. 647 * 648 * Note that failing to snoop properly is unlikely to cause 649 * cache incoherency if the period size is larger than the 650 * size of L1 cache. This is because filling in one period will 651 * flush out the data for the previous period. So if you 652 * increased period_bytes_min to a large enough size, you might 653 * get more performance by not snooping, and you'll still be 654 * okay. 655 */ 656 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 657 link->source_addr = cpu_to_be32(temp_addr); 658 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 659 660 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 661 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); 662 } else { 663 link->source_addr = cpu_to_be32(ssi_sxx_phys); 664 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); 665 666 link->dest_addr = cpu_to_be32(temp_addr); 667 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 668 } 669 670 temp_addr += period_size; 671 } 672 673 return 0; 674} 675 676/** 677 * fsl_dma_pointer: determine the current position of the DMA transfer 678 * 679 * This function is called by ALSA when ALSA wants to know where in the 680 * stream buffer the hardware currently is. 681 * 682 * For playback, the SAR register contains the physical address of the most 683 * recent DMA transfer. For capture, the value is in the DAR register. 684 * 685 * The base address of the buffer is stored in the source_addr field of the 686 * first link descriptor. 687 */ 688static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 689{ 690 struct snd_pcm_runtime *runtime = substream->runtime; 691 struct fsl_dma_private *dma_private = runtime->private_data; 692 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 693 dma_addr_t position; 694 snd_pcm_uframes_t frames; 695 696 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 697 position = in_be32(&dma_channel->sar); 698 else 699 position = in_be32(&dma_channel->dar); 700 701 /* 702 * When capture is started, the SSI immediately starts to fill its FIFO. 703 * This means that the DMA controller is not started until the FIFO is 704 * full. However, ALSA calls this function before that happens, when 705 * MR.DAR is still zero. In this case, just return zero to indicate 706 * that nothing has been received yet. 707 */ 708 if (!position) 709 return 0; 710 711 if ((position < dma_private->dma_buf_phys) || 712 (position > dma_private->dma_buf_end)) { 713 dev_err(substream->pcm->card->dev, 714 "dma pointer is out of range, halting stream\n"); 715 return SNDRV_PCM_POS_XRUN; 716 } 717 718 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 719 720 /* 721 * If the current address is just past the end of the buffer, wrap it 722 * around. 723 */ 724 if (frames == runtime->buffer_size) 725 frames = 0; 726 727 return frames; 728} 729 730/** 731 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 732 * 733 * Release the resources allocated in fsl_dma_hw_params() and de-program the 734 * registers. 735 * 736 * This function can be called multiple times. 737 */ 738static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 739{ 740 struct snd_pcm_runtime *runtime = substream->runtime; 741 struct fsl_dma_private *dma_private = runtime->private_data; 742 743 if (dma_private) { 744 struct ccsr_dma_channel __iomem *dma_channel; 745 746 dma_channel = dma_private->dma_channel; 747 748 /* Stop the DMA */ 749 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 750 out_be32(&dma_channel->mr, 0); 751 752 /* Reset all the other registers */ 753 out_be32(&dma_channel->sr, -1); 754 out_be32(&dma_channel->clndar, 0); 755 out_be32(&dma_channel->eclndar, 0); 756 out_be32(&dma_channel->satr, 0); 757 out_be32(&dma_channel->sar, 0); 758 out_be32(&dma_channel->datr, 0); 759 out_be32(&dma_channel->dar, 0); 760 out_be32(&dma_channel->bcr, 0); 761 out_be32(&dma_channel->nlndar, 0); 762 out_be32(&dma_channel->enlndar, 0); 763 } 764 765 return 0; 766} 767 768/** 769 * fsl_dma_close: close the stream. 770 */ 771static int fsl_dma_close(struct snd_pcm_substream *substream) 772{ 773 struct snd_pcm_runtime *runtime = substream->runtime; 774 struct fsl_dma_private *dma_private = runtime->private_data; 775 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 776 777 if (dma_private) { 778 if (dma_private->irq) 779 free_irq(dma_private->irq, dma_private); 780 781 if (dma_private->ld_buf_phys) { 782 dma_unmap_single(substream->pcm->card->dev, 783 dma_private->ld_buf_phys, 784 sizeof(dma_private->link), DMA_TO_DEVICE); 785 } 786 787 /* Deallocate the fsl_dma_private structure */ 788 dma_free_coherent(substream->pcm->card->dev, 789 sizeof(struct fsl_dma_private), 790 dma_private, dma_private->ld_buf_phys); 791 substream->runtime->private_data = NULL; 792 } 793 794 dma_global_data.assigned[dir] = 0; 795 796 return 0; 797} 798 799/* 800 * Remove this PCM driver. 801 */ 802static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 803{ 804 struct snd_pcm_substream *substream; 805 unsigned int i; 806 807 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 808 substream = pcm->streams[i].substream; 809 if (substream) { 810 snd_dma_free_pages(&substream->dma_buffer); 811 substream->dma_buffer.area = NULL; 812 substream->dma_buffer.addr = 0; 813 } 814 } 815} 816 817static struct snd_pcm_ops fsl_dma_ops = { 818 .open = fsl_dma_open, 819 .close = fsl_dma_close, 820 .ioctl = snd_pcm_lib_ioctl, 821 .hw_params = fsl_dma_hw_params, 822 .hw_free = fsl_dma_hw_free, 823 .pointer = fsl_dma_pointer, 824}; 825 826struct snd_soc_platform fsl_soc_platform = { 827 .name = "fsl-dma", 828 .pcm_ops = &fsl_dma_ops, 829 .pcm_new = fsl_dma_new, 830 .pcm_free = fsl_dma_free_dma_buffers, 831}; 832EXPORT_SYMBOL_GPL(fsl_soc_platform); 833 834/** 835 * fsl_dma_configure: store the DMA parameters from the fabric driver. 836 * 837 * This function is called by the ASoC fabric driver to give us the DMA and 838 * SSI channel information. 839 * 840 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI 841 * data when a substream is created, so for now we need to store this data 842 * into a global variable. This means that we can only support one DMA 843 * controller, and hence only one SSI. 844 */ 845int fsl_dma_configure(struct fsl_dma_info *dma_info) 846{ 847 static int initialized; 848 849 /* We only support one DMA controller for now */ 850 if (initialized) 851 return 0; 852 853 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys; 854 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys; 855 dma_global_data.dma_channel[0] = dma_info->dma_channel[0]; 856 dma_global_data.dma_channel[1] = dma_info->dma_channel[1]; 857 dma_global_data.irq[0] = dma_info->dma_irq[0]; 858 dma_global_data.irq[1] = dma_info->dma_irq[1]; 859 dma_global_data.assigned[0] = 0; 860 dma_global_data.assigned[1] = 0; 861 862 initialized = 1; 863 return 1; 864} 865EXPORT_SYMBOL_GPL(fsl_dma_configure); 866 867static int __init fsl_soc_platform_init(void) 868{ 869 return snd_soc_register_platform(&fsl_soc_platform); 870} 871module_init(fsl_soc_platform_init); 872 873static void __exit fsl_soc_platform_exit(void) 874{ 875 snd_soc_unregister_platform(&fsl_soc_platform); 876} 877module_exit(fsl_soc_platform_exit); 878 879MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 880MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module"); 881MODULE_LICENSE("GPL"); 882