1/* 2 * wm8904.c -- WM8904 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/module.h> 15#include <linux/moduleparam.h> 16#include <linux/init.h> 17#include <linux/delay.h> 18#include <linux/pm.h> 19#include <linux/i2c.h> 20#include <linux/platform_device.h> 21#include <linux/regulator/consumer.h> 22#include <linux/slab.h> 23#include <sound/core.h> 24#include <sound/pcm.h> 25#include <sound/pcm_params.h> 26#include <sound/soc.h> 27#include <sound/soc-dapm.h> 28#include <sound/initval.h> 29#include <sound/tlv.h> 30#include <sound/wm8904.h> 31 32#include "wm8904.h" 33 34static struct snd_soc_codec *wm8904_codec; 35struct snd_soc_codec_device soc_codec_dev_wm8904; 36 37enum wm8904_type { 38 WM8904, 39 WM8912, 40}; 41 42#define WM8904_NUM_DCS_CHANNELS 4 43 44#define WM8904_NUM_SUPPLIES 5 45static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { 46 "DCVDD", 47 "DBVDD", 48 "AVDD", 49 "CPVDD", 50 "MICVDD", 51}; 52 53/* codec private data */ 54struct wm8904_priv { 55 struct snd_soc_codec codec; 56 u16 reg_cache[WM8904_MAX_REGISTER + 1]; 57 58 enum wm8904_type devtype; 59 60 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; 61 62 struct wm8904_pdata *pdata; 63 64 int deemph; 65 66 /* Platform provided DRC configuration */ 67 const char **drc_texts; 68 int drc_cfg; 69 struct soc_enum drc_enum; 70 71 /* Platform provided ReTune mobile configuration */ 72 int num_retune_mobile_texts; 73 const char **retune_mobile_texts; 74 int retune_mobile_cfg; 75 struct soc_enum retune_mobile_enum; 76 77 /* FLL setup */ 78 int fll_src; 79 int fll_fref; 80 int fll_fout; 81 82 /* Clocking configuration */ 83 unsigned int mclk_rate; 84 int sysclk_src; 85 unsigned int sysclk_rate; 86 87 int tdm_width; 88 int tdm_slots; 89 int bclk; 90 int fs; 91 92 /* DC servo configuration - cached offset values */ 93 int dcs_state[WM8904_NUM_DCS_CHANNELS]; 94}; 95 96static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = { 97 0x8904, /* R0 - SW Reset and ID */ 98 0x0000, /* R1 - Revision */ 99 0x0000, /* R2 */ 100 0x0000, /* R3 */ 101 0x0018, /* R4 - Bias Control 0 */ 102 0x0000, /* R5 - VMID Control 0 */ 103 0x0000, /* R6 - Mic Bias Control 0 */ 104 0x0000, /* R7 - Mic Bias Control 1 */ 105 0x0001, /* R8 - Analogue DAC 0 */ 106 0x9696, /* R9 - mic Filter Control */ 107 0x0001, /* R10 - Analogue ADC 0 */ 108 0x0000, /* R11 */ 109 0x0000, /* R12 - Power Management 0 */ 110 0x0000, /* R13 */ 111 0x0000, /* R14 - Power Management 2 */ 112 0x0000, /* R15 - Power Management 3 */ 113 0x0000, /* R16 */ 114 0x0000, /* R17 */ 115 0x0000, /* R18 - Power Management 6 */ 116 0x0000, /* R19 */ 117 0x945E, /* R20 - Clock Rates 0 */ 118 0x0C05, /* R21 - Clock Rates 1 */ 119 0x0006, /* R22 - Clock Rates 2 */ 120 0x0000, /* R23 */ 121 0x0050, /* R24 - Audio Interface 0 */ 122 0x000A, /* R25 - Audio Interface 1 */ 123 0x00E4, /* R26 - Audio Interface 2 */ 124 0x0040, /* R27 - Audio Interface 3 */ 125 0x0000, /* R28 */ 126 0x0000, /* R29 */ 127 0x00C0, /* R30 - DAC Digital Volume Left */ 128 0x00C0, /* R31 - DAC Digital Volume Right */ 129 0x0000, /* R32 - DAC Digital 0 */ 130 0x0008, /* R33 - DAC Digital 1 */ 131 0x0000, /* R34 */ 132 0x0000, /* R35 */ 133 0x00C0, /* R36 - ADC Digital Volume Left */ 134 0x00C0, /* R37 - ADC Digital Volume Right */ 135 0x0010, /* R38 - ADC Digital 0 */ 136 0x0000, /* R39 - Digital Microphone 0 */ 137 0x01AF, /* R40 - DRC 0 */ 138 0x3248, /* R41 - DRC 1 */ 139 0x0000, /* R42 - DRC 2 */ 140 0x0000, /* R43 - DRC 3 */ 141 0x0085, /* R44 - Analogue Left Input 0 */ 142 0x0085, /* R45 - Analogue Right Input 0 */ 143 0x0044, /* R46 - Analogue Left Input 1 */ 144 0x0044, /* R47 - Analogue Right Input 1 */ 145 0x0000, /* R48 */ 146 0x0000, /* R49 */ 147 0x0000, /* R50 */ 148 0x0000, /* R51 */ 149 0x0000, /* R52 */ 150 0x0000, /* R53 */ 151 0x0000, /* R54 */ 152 0x0000, /* R55 */ 153 0x0000, /* R56 */ 154 0x002D, /* R57 - Analogue OUT1 Left */ 155 0x002D, /* R58 - Analogue OUT1 Right */ 156 0x0039, /* R59 - Analogue OUT2 Left */ 157 0x0039, /* R60 - Analogue OUT2 Right */ 158 0x0000, /* R61 - Analogue OUT12 ZC */ 159 0x0000, /* R62 */ 160 0x0000, /* R63 */ 161 0x0000, /* R64 */ 162 0x0000, /* R65 */ 163 0x0000, /* R66 */ 164 0x0000, /* R67 - DC Servo 0 */ 165 0x0000, /* R68 - DC Servo 1 */ 166 0xAAAA, /* R69 - DC Servo 2 */ 167 0x0000, /* R70 */ 168 0xAAAA, /* R71 - DC Servo 4 */ 169 0xAAAA, /* R72 - DC Servo 5 */ 170 0x0000, /* R73 - DC Servo 6 */ 171 0x0000, /* R74 - DC Servo 7 */ 172 0x0000, /* R75 - DC Servo 8 */ 173 0x0000, /* R76 - DC Servo 9 */ 174 0x0000, /* R77 - DC Servo Readback 0 */ 175 0x0000, /* R78 */ 176 0x0000, /* R79 */ 177 0x0000, /* R80 */ 178 0x0000, /* R81 */ 179 0x0000, /* R82 */ 180 0x0000, /* R83 */ 181 0x0000, /* R84 */ 182 0x0000, /* R85 */ 183 0x0000, /* R86 */ 184 0x0000, /* R87 */ 185 0x0000, /* R88 */ 186 0x0000, /* R89 */ 187 0x0000, /* R90 - Analogue HP 0 */ 188 0x0000, /* R91 */ 189 0x0000, /* R92 */ 190 0x0000, /* R93 */ 191 0x0000, /* R94 - Analogue Lineout 0 */ 192 0x0000, /* R95 */ 193 0x0000, /* R96 */ 194 0x0000, /* R97 */ 195 0x0000, /* R98 - Charge Pump 0 */ 196 0x0000, /* R99 */ 197 0x0000, /* R100 */ 198 0x0000, /* R101 */ 199 0x0000, /* R102 */ 200 0x0000, /* R103 */ 201 0x0004, /* R104 - Class W 0 */ 202 0x0000, /* R105 */ 203 0x0000, /* R106 */ 204 0x0000, /* R107 */ 205 0x0000, /* R108 - Write Sequencer 0 */ 206 0x0000, /* R109 - Write Sequencer 1 */ 207 0x0000, /* R110 - Write Sequencer 2 */ 208 0x0000, /* R111 - Write Sequencer 3 */ 209 0x0000, /* R112 - Write Sequencer 4 */ 210 0x0000, /* R113 */ 211 0x0000, /* R114 */ 212 0x0000, /* R115 */ 213 0x0000, /* R116 - FLL Control 1 */ 214 0x0007, /* R117 - FLL Control 2 */ 215 0x0000, /* R118 - FLL Control 3 */ 216 0x2EE0, /* R119 - FLL Control 4 */ 217 0x0004, /* R120 - FLL Control 5 */ 218 0x0014, /* R121 - GPIO Control 1 */ 219 0x0010, /* R122 - GPIO Control 2 */ 220 0x0010, /* R123 - GPIO Control 3 */ 221 0x0000, /* R124 - GPIO Control 4 */ 222 0x0000, /* R125 */ 223 0x0000, /* R126 - Digital Pulls */ 224 0x0000, /* R127 - Interrupt Status */ 225 0xFFFF, /* R128 - Interrupt Status Mask */ 226 0x0000, /* R129 - Interrupt Polarity */ 227 0x0000, /* R130 - Interrupt Debounce */ 228 0x0000, /* R131 */ 229 0x0000, /* R132 */ 230 0x0000, /* R133 */ 231 0x0000, /* R134 - EQ1 */ 232 0x000C, /* R135 - EQ2 */ 233 0x000C, /* R136 - EQ3 */ 234 0x000C, /* R137 - EQ4 */ 235 0x000C, /* R138 - EQ5 */ 236 0x000C, /* R139 - EQ6 */ 237 0x0FCA, /* R140 - EQ7 */ 238 0x0400, /* R141 - EQ8 */ 239 0x00D8, /* R142 - EQ9 */ 240 0x1EB5, /* R143 - EQ10 */ 241 0xF145, /* R144 - EQ11 */ 242 0x0B75, /* R145 - EQ12 */ 243 0x01C5, /* R146 - EQ13 */ 244 0x1C58, /* R147 - EQ14 */ 245 0xF373, /* R148 - EQ15 */ 246 0x0A54, /* R149 - EQ16 */ 247 0x0558, /* R150 - EQ17 */ 248 0x168E, /* R151 - EQ18 */ 249 0xF829, /* R152 - EQ19 */ 250 0x07AD, /* R153 - EQ20 */ 251 0x1103, /* R154 - EQ21 */ 252 0x0564, /* R155 - EQ22 */ 253 0x0559, /* R156 - EQ23 */ 254 0x4000, /* R157 - EQ24 */ 255 0x0000, /* R158 */ 256 0x0000, /* R159 */ 257 0x0000, /* R160 */ 258 0x0000, /* R161 - Control Interface Test 1 */ 259 0x0000, /* R162 */ 260 0x0000, /* R163 */ 261 0x0000, /* R164 */ 262 0x0000, /* R165 */ 263 0x0000, /* R166 */ 264 0x0000, /* R167 */ 265 0x0000, /* R168 */ 266 0x0000, /* R169 */ 267 0x0000, /* R170 */ 268 0x0000, /* R171 */ 269 0x0000, /* R172 */ 270 0x0000, /* R173 */ 271 0x0000, /* R174 */ 272 0x0000, /* R175 */ 273 0x0000, /* R176 */ 274 0x0000, /* R177 */ 275 0x0000, /* R178 */ 276 0x0000, /* R179 */ 277 0x0000, /* R180 */ 278 0x0000, /* R181 */ 279 0x0000, /* R182 */ 280 0x0000, /* R183 */ 281 0x0000, /* R184 */ 282 0x0000, /* R185 */ 283 0x0000, /* R186 */ 284 0x0000, /* R187 */ 285 0x0000, /* R188 */ 286 0x0000, /* R189 */ 287 0x0000, /* R190 */ 288 0x0000, /* R191 */ 289 0x0000, /* R192 */ 290 0x0000, /* R193 */ 291 0x0000, /* R194 */ 292 0x0000, /* R195 */ 293 0x0000, /* R196 */ 294 0x0000, /* R197 */ 295 0x0000, /* R198 */ 296 0x0000, /* R199 */ 297 0x0000, /* R200 */ 298 0x0000, /* R201 */ 299 0x0000, /* R202 */ 300 0x0000, /* R203 */ 301 0x0000, /* R204 - Analogue Output Bias 0 */ 302 0x0000, /* R205 */ 303 0x0000, /* R206 */ 304 0x0000, /* R207 */ 305 0x0000, /* R208 */ 306 0x0000, /* R209 */ 307 0x0000, /* R210 */ 308 0x0000, /* R211 */ 309 0x0000, /* R212 */ 310 0x0000, /* R213 */ 311 0x0000, /* R214 */ 312 0x0000, /* R215 */ 313 0x0000, /* R216 */ 314 0x0000, /* R217 */ 315 0x0000, /* R218 */ 316 0x0000, /* R219 */ 317 0x0000, /* R220 */ 318 0x0000, /* R221 */ 319 0x0000, /* R222 */ 320 0x0000, /* R223 */ 321 0x0000, /* R224 */ 322 0x0000, /* R225 */ 323 0x0000, /* R226 */ 324 0x0000, /* R227 */ 325 0x0000, /* R228 */ 326 0x0000, /* R229 */ 327 0x0000, /* R230 */ 328 0x0000, /* R231 */ 329 0x0000, /* R232 */ 330 0x0000, /* R233 */ 331 0x0000, /* R234 */ 332 0x0000, /* R235 */ 333 0x0000, /* R236 */ 334 0x0000, /* R237 */ 335 0x0000, /* R238 */ 336 0x0000, /* R239 */ 337 0x0000, /* R240 */ 338 0x0000, /* R241 */ 339 0x0000, /* R242 */ 340 0x0000, /* R243 */ 341 0x0000, /* R244 */ 342 0x0000, /* R245 */ 343 0x0000, /* R246 */ 344 0x0000, /* R247 - FLL NCO Test 0 */ 345 0x0019, /* R248 - FLL NCO Test 1 */ 346}; 347 348static struct { 349 int readable; 350 int writable; 351 int vol; 352} wm8904_access[] = { 353 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */ 354 { 0x0000, 0x0000, 0 }, /* R1 - Revision */ 355 { 0x0000, 0x0000, 0 }, /* R2 */ 356 { 0x0000, 0x0000, 0 }, /* R3 */ 357 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */ 358 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */ 359 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */ 360 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */ 361 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */ 362 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */ 363 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */ 364 { 0x0000, 0x0000, 0 }, /* R11 */ 365 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */ 366 { 0x0000, 0x0000, 0 }, /* R13 */ 367 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */ 368 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */ 369 { 0x0000, 0x0000, 0 }, /* R16 */ 370 { 0x0000, 0x0000, 0 }, /* R17 */ 371 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */ 372 { 0x0000, 0x0000, 0 }, /* R19 */ 373 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */ 374 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */ 375 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */ 376 { 0x0000, 0x0000, 0 }, /* R23 */ 377 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */ 378 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */ 379 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */ 380 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */ 381 { 0x0000, 0x0000, 0 }, /* R28 */ 382 { 0x0000, 0x0000, 0 }, /* R29 */ 383 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */ 384 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */ 385 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */ 386 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */ 387 { 0x0000, 0x0000, 0 }, /* R34 */ 388 { 0x0000, 0x0000, 0 }, /* R35 */ 389 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */ 390 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */ 391 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */ 392 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */ 393 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */ 394 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */ 395 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */ 396 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */ 397 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */ 398 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */ 399 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */ 400 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */ 401 { 0x0000, 0x0000, 0 }, /* R48 */ 402 { 0x0000, 0x0000, 0 }, /* R49 */ 403 { 0x0000, 0x0000, 0 }, /* R50 */ 404 { 0x0000, 0x0000, 0 }, /* R51 */ 405 { 0x0000, 0x0000, 0 }, /* R52 */ 406 { 0x0000, 0x0000, 0 }, /* R53 */ 407 { 0x0000, 0x0000, 0 }, /* R54 */ 408 { 0x0000, 0x0000, 0 }, /* R55 */ 409 { 0x0000, 0x0000, 0 }, /* R56 */ 410 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */ 411 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */ 412 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */ 413 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */ 414 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */ 415 { 0x0000, 0x0000, 0 }, /* R62 */ 416 { 0x0000, 0x0000, 0 }, /* R63 */ 417 { 0x0000, 0x0000, 0 }, /* R64 */ 418 { 0x0000, 0x0000, 0 }, /* R65 */ 419 { 0x0000, 0x0000, 0 }, /* R66 */ 420 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */ 421 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */ 422 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */ 423 { 0x0000, 0x0000, 0 }, /* R70 */ 424 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */ 425 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */ 426 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */ 427 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */ 428 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */ 429 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */ 430 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */ 431 { 0x0000, 0x0000, 0 }, /* R78 */ 432 { 0x0000, 0x0000, 0 }, /* R79 */ 433 { 0x0000, 0x0000, 0 }, /* R80 */ 434 { 0x0000, 0x0000, 0 }, /* R81 */ 435 { 0x0000, 0x0000, 0 }, /* R82 */ 436 { 0x0000, 0x0000, 0 }, /* R83 */ 437 { 0x0000, 0x0000, 0 }, /* R84 */ 438 { 0x0000, 0x0000, 0 }, /* R85 */ 439 { 0x0000, 0x0000, 0 }, /* R86 */ 440 { 0x0000, 0x0000, 0 }, /* R87 */ 441 { 0x0000, 0x0000, 0 }, /* R88 */ 442 { 0x0000, 0x0000, 0 }, /* R89 */ 443 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */ 444 { 0x0000, 0x0000, 0 }, /* R91 */ 445 { 0x0000, 0x0000, 0 }, /* R92 */ 446 { 0x0000, 0x0000, 0 }, /* R93 */ 447 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */ 448 { 0x0000, 0x0000, 0 }, /* R95 */ 449 { 0x0000, 0x0000, 0 }, /* R96 */ 450 { 0x0000, 0x0000, 0 }, /* R97 */ 451 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */ 452 { 0x0000, 0x0000, 0 }, /* R99 */ 453 { 0x0000, 0x0000, 0 }, /* R100 */ 454 { 0x0000, 0x0000, 0 }, /* R101 */ 455 { 0x0000, 0x0000, 0 }, /* R102 */ 456 { 0x0000, 0x0000, 0 }, /* R103 */ 457 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */ 458 { 0x0000, 0x0000, 0 }, /* R105 */ 459 { 0x0000, 0x0000, 0 }, /* R106 */ 460 { 0x0000, 0x0000, 0 }, /* R107 */ 461 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */ 462 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */ 463 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */ 464 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */ 465 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */ 466 { 0x0000, 0x0000, 0 }, /* R113 */ 467 { 0x0000, 0x0000, 0 }, /* R114 */ 468 { 0x0000, 0x0000, 0 }, /* R115 */ 469 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */ 470 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */ 471 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */ 472 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */ 473 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */ 474 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */ 475 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */ 476 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */ 477 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */ 478 { 0x0000, 0x0000, 0 }, /* R125 */ 479 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */ 480 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */ 481 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */ 482 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */ 483 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */ 484 { 0x0000, 0x0000, 0 }, /* R131 */ 485 { 0x0000, 0x0000, 0 }, /* R132 */ 486 { 0x0000, 0x0000, 0 }, /* R133 */ 487 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */ 488 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */ 489 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */ 490 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */ 491 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */ 492 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */ 493 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */ 494 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */ 495 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */ 496 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */ 497 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */ 498 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */ 499 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */ 500 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */ 501 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */ 502 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */ 503 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */ 504 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */ 505 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */ 506 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */ 507 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */ 508 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */ 509 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */ 510 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */ 511 { 0x0000, 0x0000, 0 }, /* R158 */ 512 { 0x0000, 0x0000, 0 }, /* R159 */ 513 { 0x0000, 0x0000, 0 }, /* R160 */ 514 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */ 515 { 0x0000, 0x0000, 0 }, /* R162 */ 516 { 0x0000, 0x0000, 0 }, /* R163 */ 517 { 0x0000, 0x0000, 0 }, /* R164 */ 518 { 0x0000, 0x0000, 0 }, /* R165 */ 519 { 0x0000, 0x0000, 0 }, /* R166 */ 520 { 0x0000, 0x0000, 0 }, /* R167 */ 521 { 0x0000, 0x0000, 0 }, /* R168 */ 522 { 0x0000, 0x0000, 0 }, /* R169 */ 523 { 0x0000, 0x0000, 0 }, /* R170 */ 524 { 0x0000, 0x0000, 0 }, /* R171 */ 525 { 0x0000, 0x0000, 0 }, /* R172 */ 526 { 0x0000, 0x0000, 0 }, /* R173 */ 527 { 0x0000, 0x0000, 0 }, /* R174 */ 528 { 0x0000, 0x0000, 0 }, /* R175 */ 529 { 0x0000, 0x0000, 0 }, /* R176 */ 530 { 0x0000, 0x0000, 0 }, /* R177 */ 531 { 0x0000, 0x0000, 0 }, /* R178 */ 532 { 0x0000, 0x0000, 0 }, /* R179 */ 533 { 0x0000, 0x0000, 0 }, /* R180 */ 534 { 0x0000, 0x0000, 0 }, /* R181 */ 535 { 0x0000, 0x0000, 0 }, /* R182 */ 536 { 0x0000, 0x0000, 0 }, /* R183 */ 537 { 0x0000, 0x0000, 0 }, /* R184 */ 538 { 0x0000, 0x0000, 0 }, /* R185 */ 539 { 0x0000, 0x0000, 0 }, /* R186 */ 540 { 0x0000, 0x0000, 0 }, /* R187 */ 541 { 0x0000, 0x0000, 0 }, /* R188 */ 542 { 0x0000, 0x0000, 0 }, /* R189 */ 543 { 0x0000, 0x0000, 0 }, /* R190 */ 544 { 0x0000, 0x0000, 0 }, /* R191 */ 545 { 0x0000, 0x0000, 0 }, /* R192 */ 546 { 0x0000, 0x0000, 0 }, /* R193 */ 547 { 0x0000, 0x0000, 0 }, /* R194 */ 548 { 0x0000, 0x0000, 0 }, /* R195 */ 549 { 0x0000, 0x0000, 0 }, /* R196 */ 550 { 0x0000, 0x0000, 0 }, /* R197 */ 551 { 0x0000, 0x0000, 0 }, /* R198 */ 552 { 0x0000, 0x0000, 0 }, /* R199 */ 553 { 0x0000, 0x0000, 0 }, /* R200 */ 554 { 0x0000, 0x0000, 0 }, /* R201 */ 555 { 0x0000, 0x0000, 0 }, /* R202 */ 556 { 0x0000, 0x0000, 0 }, /* R203 */ 557 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */ 558 { 0x0000, 0x0000, 0 }, /* R205 */ 559 { 0x0000, 0x0000, 0 }, /* R206 */ 560 { 0x0000, 0x0000, 0 }, /* R207 */ 561 { 0x0000, 0x0000, 0 }, /* R208 */ 562 { 0x0000, 0x0000, 0 }, /* R209 */ 563 { 0x0000, 0x0000, 0 }, /* R210 */ 564 { 0x0000, 0x0000, 0 }, /* R211 */ 565 { 0x0000, 0x0000, 0 }, /* R212 */ 566 { 0x0000, 0x0000, 0 }, /* R213 */ 567 { 0x0000, 0x0000, 0 }, /* R214 */ 568 { 0x0000, 0x0000, 0 }, /* R215 */ 569 { 0x0000, 0x0000, 0 }, /* R216 */ 570 { 0x0000, 0x0000, 0 }, /* R217 */ 571 { 0x0000, 0x0000, 0 }, /* R218 */ 572 { 0x0000, 0x0000, 0 }, /* R219 */ 573 { 0x0000, 0x0000, 0 }, /* R220 */ 574 { 0x0000, 0x0000, 0 }, /* R221 */ 575 { 0x0000, 0x0000, 0 }, /* R222 */ 576 { 0x0000, 0x0000, 0 }, /* R223 */ 577 { 0x0000, 0x0000, 0 }, /* R224 */ 578 { 0x0000, 0x0000, 0 }, /* R225 */ 579 { 0x0000, 0x0000, 0 }, /* R226 */ 580 { 0x0000, 0x0000, 0 }, /* R227 */ 581 { 0x0000, 0x0000, 0 }, /* R228 */ 582 { 0x0000, 0x0000, 0 }, /* R229 */ 583 { 0x0000, 0x0000, 0 }, /* R230 */ 584 { 0x0000, 0x0000, 0 }, /* R231 */ 585 { 0x0000, 0x0000, 0 }, /* R232 */ 586 { 0x0000, 0x0000, 0 }, /* R233 */ 587 { 0x0000, 0x0000, 0 }, /* R234 */ 588 { 0x0000, 0x0000, 0 }, /* R235 */ 589 { 0x0000, 0x0000, 0 }, /* R236 */ 590 { 0x0000, 0x0000, 0 }, /* R237 */ 591 { 0x0000, 0x0000, 0 }, /* R238 */ 592 { 0x0000, 0x0000, 0 }, /* R239 */ 593 { 0x0000, 0x0000, 0 }, /* R240 */ 594 { 0x0000, 0x0000, 0 }, /* R241 */ 595 { 0x0000, 0x0000, 0 }, /* R242 */ 596 { 0x0000, 0x0000, 0 }, /* R243 */ 597 { 0x0000, 0x0000, 0 }, /* R244 */ 598 { 0x0000, 0x0000, 0 }, /* R245 */ 599 { 0x0000, 0x0000, 0 }, /* R246 */ 600 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */ 601 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */ 602}; 603 604static int wm8904_volatile_register(unsigned int reg) 605{ 606 return wm8904_access[reg].vol; 607} 608 609static int wm8904_reset(struct snd_soc_codec *codec) 610{ 611 return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0); 612} 613 614static int wm8904_configure_clocking(struct snd_soc_codec *codec) 615{ 616 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 617 unsigned int clock0, clock2, rate; 618 619 /* Gate the clock while we're updating to avoid misclocking */ 620 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 621 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 622 WM8904_SYSCLK_SRC, 0); 623 624 /* This should be done on init() for bypass paths */ 625 switch (wm8904->sysclk_src) { 626 case WM8904_CLK_MCLK: 627 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); 628 629 clock2 &= ~WM8904_SYSCLK_SRC; 630 rate = wm8904->mclk_rate; 631 632 /* Ensure the FLL is stopped */ 633 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 634 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 635 break; 636 637 case WM8904_CLK_FLL: 638 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 639 wm8904->fll_fout); 640 641 clock2 |= WM8904_SYSCLK_SRC; 642 rate = wm8904->fll_fout; 643 break; 644 645 default: 646 dev_err(codec->dev, "System clock not configured\n"); 647 return -EINVAL; 648 } 649 650 /* SYSCLK shouldn't be over 13.5MHz */ 651 if (rate > 13500000) { 652 clock0 = WM8904_MCLK_DIV; 653 wm8904->sysclk_rate = rate / 2; 654 } else { 655 clock0 = 0; 656 wm8904->sysclk_rate = rate; 657 } 658 659 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, 660 clock0); 661 662 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 663 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); 664 665 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); 666 667 return 0; 668} 669 670static void wm8904_set_drc(struct snd_soc_codec *codec) 671{ 672 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 673 struct wm8904_pdata *pdata = wm8904->pdata; 674 int save, i; 675 676 /* Save any enables; the configuration should clear them. */ 677 save = snd_soc_read(codec, WM8904_DRC_0); 678 679 for (i = 0; i < WM8904_DRC_REGS; i++) 680 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, 681 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); 682 683 /* Reenable the DRC */ 684 snd_soc_update_bits(codec, WM8904_DRC_0, 685 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); 686} 687 688static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 689 struct snd_ctl_elem_value *ucontrol) 690{ 691 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 692 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 693 struct wm8904_pdata *pdata = wm8904->pdata; 694 int value = ucontrol->value.integer.value[0]; 695 696 if (value >= pdata->num_drc_cfgs) 697 return -EINVAL; 698 699 wm8904->drc_cfg = value; 700 701 wm8904_set_drc(codec); 702 703 return 0; 704} 705 706static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 707 struct snd_ctl_elem_value *ucontrol) 708{ 709 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 710 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 711 712 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 713 714 return 0; 715} 716 717static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) 718{ 719 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 720 struct wm8904_pdata *pdata = wm8904->pdata; 721 int best, best_val, save, i, cfg; 722 723 if (!pdata || !wm8904->num_retune_mobile_texts) 724 return; 725 726 /* Find the version of the currently selected configuration 727 * with the nearest sample rate. */ 728 cfg = wm8904->retune_mobile_cfg; 729 best = 0; 730 best_val = INT_MAX; 731 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 732 if (strcmp(pdata->retune_mobile_cfgs[i].name, 733 wm8904->retune_mobile_texts[cfg]) == 0 && 734 abs(pdata->retune_mobile_cfgs[i].rate 735 - wm8904->fs) < best_val) { 736 best = i; 737 best_val = abs(pdata->retune_mobile_cfgs[i].rate 738 - wm8904->fs); 739 } 740 } 741 742 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", 743 pdata->retune_mobile_cfgs[best].name, 744 pdata->retune_mobile_cfgs[best].rate, 745 wm8904->fs); 746 747 /* The EQ will be disabled while reconfiguring it, remember the 748 * current configuration. 749 */ 750 save = snd_soc_read(codec, WM8904_EQ1); 751 752 for (i = 0; i < WM8904_EQ_REGS; i++) 753 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, 754 pdata->retune_mobile_cfgs[best].regs[i]); 755 756 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); 757} 758 759static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 760 struct snd_ctl_elem_value *ucontrol) 761{ 762 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 763 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 764 struct wm8904_pdata *pdata = wm8904->pdata; 765 int value = ucontrol->value.integer.value[0]; 766 767 if (value >= pdata->num_retune_mobile_cfgs) 768 return -EINVAL; 769 770 wm8904->retune_mobile_cfg = value; 771 772 wm8904_set_retune_mobile(codec); 773 774 return 0; 775} 776 777static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 778 struct snd_ctl_elem_value *ucontrol) 779{ 780 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 781 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 782 783 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 784 785 return 0; 786} 787 788static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 789 790static int wm8904_set_deemph(struct snd_soc_codec *codec) 791{ 792 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 793 int val, i, best; 794 795 /* If we're using deemphasis select the nearest available sample 796 * rate. 797 */ 798 if (wm8904->deemph) { 799 best = 1; 800 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 801 if (abs(deemph_settings[i] - wm8904->fs) < 802 abs(deemph_settings[best] - wm8904->fs)) 803 best = i; 804 } 805 806 val = best << WM8904_DEEMPH_SHIFT; 807 } else { 808 val = 0; 809 } 810 811 dev_dbg(codec->dev, "Set deemphasis %d\n", val); 812 813 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 814 WM8904_DEEMPH_MASK, val); 815} 816 817static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 818 struct snd_ctl_elem_value *ucontrol) 819{ 820 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 821 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 822 823 ucontrol->value.enumerated.item[0] = wm8904->deemph; 824 return 0; 825} 826 827static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 828 struct snd_ctl_elem_value *ucontrol) 829{ 830 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 831 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 832 int deemph = ucontrol->value.enumerated.item[0]; 833 834 if (deemph > 1) 835 return -EINVAL; 836 837 wm8904->deemph = deemph; 838 839 return wm8904_set_deemph(codec); 840} 841 842static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 843static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 844static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 845static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 846static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 847 848static const char *input_mode_text[] = { 849 "Single-Ended", "Differential Line", "Differential Mic" 850}; 851 852static const struct soc_enum lin_mode = 853 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 854 855static const struct soc_enum rin_mode = 856 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 857 858static const char *hpf_mode_text[] = { 859 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 860}; 861 862static const struct soc_enum hpf_mode = 863 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); 864 865static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { 866SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, 867 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), 868 869SOC_ENUM("Left Caputure Mode", lin_mode), 870SOC_ENUM("Right Capture Mode", rin_mode), 871 872/* No TLV since it depends on mode */ 873SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, 874 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), 875SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, 876 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0), 877 878SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), 879SOC_ENUM("High Pass Filter Mode", hpf_mode), 880 881SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0), 882}; 883 884static const char *drc_path_text[] = { 885 "ADC", "DAC" 886}; 887 888static const struct soc_enum drc_path = 889 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); 890 891static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { 892SOC_SINGLE_TLV("Digital Playback Boost Volume", 893 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), 894SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, 895 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 896 897SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, 898 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), 899SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, 900 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), 901SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, 902 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), 903 904SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, 905 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), 906SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, 907 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), 908SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, 909 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), 910 911SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), 912SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), 913SOC_ENUM("DRC Path", drc_path), 914SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), 915SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 916 wm8904_get_deemph, wm8904_put_deemph), 917}; 918 919static const struct snd_kcontrol_new wm8904_snd_controls[] = { 920SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, 921 sidetone_tlv), 922}; 923 924static const struct snd_kcontrol_new wm8904_eq_controls[] = { 925SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), 926SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), 927SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), 928SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), 929SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), 930}; 931 932static int cp_event(struct snd_soc_dapm_widget *w, 933 struct snd_kcontrol *kcontrol, int event) 934{ 935 BUG_ON(event != SND_SOC_DAPM_POST_PMU); 936 937 /* Maximum startup time */ 938 udelay(500); 939 940 return 0; 941} 942 943static int sysclk_event(struct snd_soc_dapm_widget *w, 944 struct snd_kcontrol *kcontrol, int event) 945{ 946 struct snd_soc_codec *codec = w->codec; 947 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 948 949 switch (event) { 950 case SND_SOC_DAPM_PRE_PMU: 951 /* If we're using the FLL then we only start it when 952 * required; we assume that the configuration has been 953 * done previously and all we need to do is kick it 954 * off. 955 */ 956 switch (wm8904->sysclk_src) { 957 case WM8904_CLK_FLL: 958 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 959 WM8904_FLL_OSC_ENA, 960 WM8904_FLL_OSC_ENA); 961 962 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 963 WM8904_FLL_ENA, 964 WM8904_FLL_ENA); 965 break; 966 967 default: 968 break; 969 } 970 break; 971 972 case SND_SOC_DAPM_POST_PMD: 973 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 974 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 975 break; 976 } 977 978 return 0; 979} 980 981static int out_pga_event(struct snd_soc_dapm_widget *w, 982 struct snd_kcontrol *kcontrol, int event) 983{ 984 struct snd_soc_codec *codec = w->codec; 985 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 986 int reg, val; 987 int dcs_mask; 988 int dcs_l, dcs_r; 989 int dcs_l_reg, dcs_r_reg; 990 int timeout; 991 int pwr_reg; 992 993 /* This code is shared between HP and LINEOUT; we do all our 994 * power management in stereo pairs to avoid latency issues so 995 * we reuse shift to identify which rather than strcmp() the 996 * name. */ 997 reg = w->shift; 998 999 switch (reg) { 1000 case WM8904_ANALOGUE_HP_0: 1001 pwr_reg = WM8904_POWER_MANAGEMENT_2; 1002 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; 1003 dcs_r_reg = WM8904_DC_SERVO_8; 1004 dcs_l_reg = WM8904_DC_SERVO_9; 1005 dcs_l = 0; 1006 dcs_r = 1; 1007 break; 1008 case WM8904_ANALOGUE_LINEOUT_0: 1009 pwr_reg = WM8904_POWER_MANAGEMENT_3; 1010 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; 1011 dcs_r_reg = WM8904_DC_SERVO_6; 1012 dcs_l_reg = WM8904_DC_SERVO_7; 1013 dcs_l = 2; 1014 dcs_r = 3; 1015 break; 1016 default: 1017 BUG(); 1018 return -EINVAL; 1019 } 1020 1021 switch (event) { 1022 case SND_SOC_DAPM_PRE_PMU: 1023 /* Power on the PGAs */ 1024 snd_soc_update_bits(codec, pwr_reg, 1025 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1026 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); 1027 1028 /* Power on the amplifier */ 1029 snd_soc_update_bits(codec, reg, 1030 WM8904_HPL_ENA | WM8904_HPR_ENA, 1031 WM8904_HPL_ENA | WM8904_HPR_ENA); 1032 1033 1034 /* Enable the first stage */ 1035 snd_soc_update_bits(codec, reg, 1036 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, 1037 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); 1038 1039 /* Power up the DC servo */ 1040 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1041 dcs_mask, dcs_mask); 1042 1043 /* Either calibrate the DC servo or restore cached state 1044 * if we have that. 1045 */ 1046 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { 1047 dev_dbg(codec->dev, "Restoring DC servo state\n"); 1048 1049 snd_soc_write(codec, dcs_l_reg, 1050 wm8904->dcs_state[dcs_l]); 1051 snd_soc_write(codec, dcs_r_reg, 1052 wm8904->dcs_state[dcs_r]); 1053 1054 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); 1055 1056 timeout = 20; 1057 } else { 1058 dev_dbg(codec->dev, "Calibrating DC servo\n"); 1059 1060 snd_soc_write(codec, WM8904_DC_SERVO_1, 1061 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); 1062 1063 timeout = 500; 1064 } 1065 1066 /* Wait for DC servo to complete */ 1067 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; 1068 do { 1069 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); 1070 if ((val & dcs_mask) == dcs_mask) 1071 break; 1072 1073 msleep(1); 1074 } while (--timeout); 1075 1076 if ((val & dcs_mask) != dcs_mask) 1077 dev_warn(codec->dev, "DC servo timed out\n"); 1078 else 1079 dev_dbg(codec->dev, "DC servo ready\n"); 1080 1081 /* Enable the output stage */ 1082 snd_soc_update_bits(codec, reg, 1083 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1084 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); 1085 break; 1086 1087 case SND_SOC_DAPM_POST_PMU: 1088 /* Unshort the output itself */ 1089 snd_soc_update_bits(codec, reg, 1090 WM8904_HPL_RMV_SHORT | 1091 WM8904_HPR_RMV_SHORT, 1092 WM8904_HPL_RMV_SHORT | 1093 WM8904_HPR_RMV_SHORT); 1094 1095 break; 1096 1097 case SND_SOC_DAPM_PRE_PMD: 1098 /* Short the output */ 1099 snd_soc_update_bits(codec, reg, 1100 WM8904_HPL_RMV_SHORT | 1101 WM8904_HPR_RMV_SHORT, 0); 1102 break; 1103 1104 case SND_SOC_DAPM_POST_PMD: 1105 /* Cache the DC servo configuration; this will be 1106 * invalidated if we change the configuration. */ 1107 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); 1108 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); 1109 1110 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1111 dcs_mask, 0); 1112 1113 /* Disable the amplifier input and output stages */ 1114 snd_soc_update_bits(codec, reg, 1115 WM8904_HPL_ENA | WM8904_HPR_ENA | 1116 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | 1117 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1118 0); 1119 1120 /* PGAs too */ 1121 snd_soc_update_bits(codec, pwr_reg, 1122 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1123 0); 1124 break; 1125 } 1126 1127 return 0; 1128} 1129 1130static const char *lin_text[] = { 1131 "IN1L", "IN2L", "IN3L" 1132}; 1133 1134static const struct soc_enum lin_enum = 1135 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); 1136 1137static const struct snd_kcontrol_new lin_mux = 1138 SOC_DAPM_ENUM("Left Capture Mux", lin_enum); 1139 1140static const struct soc_enum lin_inv_enum = 1141 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); 1142 1143static const struct snd_kcontrol_new lin_inv_mux = 1144 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); 1145 1146static const char *rin_text[] = { 1147 "IN1R", "IN2R", "IN3R" 1148}; 1149 1150static const struct soc_enum rin_enum = 1151 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); 1152 1153static const struct snd_kcontrol_new rin_mux = 1154 SOC_DAPM_ENUM("Right Capture Mux", rin_enum); 1155 1156static const struct soc_enum rin_inv_enum = 1157 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); 1158 1159static const struct snd_kcontrol_new rin_inv_mux = 1160 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); 1161 1162static const char *aif_text[] = { 1163 "Left", "Right" 1164}; 1165 1166static const struct soc_enum aifoutl_enum = 1167 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); 1168 1169static const struct snd_kcontrol_new aifoutl_mux = 1170 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 1171 1172static const struct soc_enum aifoutr_enum = 1173 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); 1174 1175static const struct snd_kcontrol_new aifoutr_mux = 1176 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 1177 1178static const struct soc_enum aifinl_enum = 1179 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); 1180 1181static const struct snd_kcontrol_new aifinl_mux = 1182 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 1183 1184static const struct soc_enum aifinr_enum = 1185 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); 1186 1187static const struct snd_kcontrol_new aifinr_mux = 1188 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 1189 1190static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { 1191SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, 1192 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1193SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), 1194SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), 1195}; 1196 1197static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { 1198SND_SOC_DAPM_INPUT("IN1L"), 1199SND_SOC_DAPM_INPUT("IN1R"), 1200SND_SOC_DAPM_INPUT("IN2L"), 1201SND_SOC_DAPM_INPUT("IN2R"), 1202SND_SOC_DAPM_INPUT("IN3L"), 1203SND_SOC_DAPM_INPUT("IN3R"), 1204 1205SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0), 1206 1207SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), 1208SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1209 &lin_inv_mux), 1210SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), 1211SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1212 &rin_inv_mux), 1213 1214SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, 1215 NULL, 0), 1216SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, 1217 NULL, 0), 1218 1219SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), 1220SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), 1221 1222SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 1223SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 1224 1225SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 1226SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 1227}; 1228 1229static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { 1230SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 1231SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 1232 1233SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 1234SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 1235 1236SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), 1237SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), 1238 1239SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, 1240 SND_SOC_DAPM_POST_PMU), 1241 1242SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1243SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1244 1245SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1246SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1247 1248SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, 1249 0, NULL, 0, out_pga_event, 1250 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1251 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1252SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, 1253 0, NULL, 0, out_pga_event, 1254 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1255 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1256 1257SND_SOC_DAPM_OUTPUT("HPOUTL"), 1258SND_SOC_DAPM_OUTPUT("HPOUTR"), 1259SND_SOC_DAPM_OUTPUT("LINEOUTL"), 1260SND_SOC_DAPM_OUTPUT("LINEOUTR"), 1261}; 1262 1263static const char *out_mux_text[] = { 1264 "DAC", "Bypass" 1265}; 1266 1267static const struct soc_enum hpl_enum = 1268 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); 1269 1270static const struct snd_kcontrol_new hpl_mux = 1271 SOC_DAPM_ENUM("HPL Mux", hpl_enum); 1272 1273static const struct soc_enum hpr_enum = 1274 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); 1275 1276static const struct snd_kcontrol_new hpr_mux = 1277 SOC_DAPM_ENUM("HPR Mux", hpr_enum); 1278 1279static const struct soc_enum linel_enum = 1280 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); 1281 1282static const struct snd_kcontrol_new linel_mux = 1283 SOC_DAPM_ENUM("LINEL Mux", linel_enum); 1284 1285static const struct soc_enum liner_enum = 1286 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); 1287 1288static const struct snd_kcontrol_new liner_mux = 1289 SOC_DAPM_ENUM("LINEL Mux", liner_enum); 1290 1291static const char *sidetone_text[] = { 1292 "None", "Left", "Right" 1293}; 1294 1295static const struct soc_enum dacl_sidetone_enum = 1296 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); 1297 1298static const struct snd_kcontrol_new dacl_sidetone_mux = 1299 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); 1300 1301static const struct soc_enum dacr_sidetone_enum = 1302 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); 1303 1304static const struct snd_kcontrol_new dacr_sidetone_mux = 1305 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); 1306 1307static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { 1308SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), 1309SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1310SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1311 1312SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), 1313SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), 1314 1315SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1316SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1317SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), 1318SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), 1319}; 1320 1321static const struct snd_soc_dapm_route core_intercon[] = { 1322 { "CLK_DSP", NULL, "SYSCLK" }, 1323 { "TOCLK", NULL, "SYSCLK" }, 1324}; 1325 1326static const struct snd_soc_dapm_route adc_intercon[] = { 1327 { "Left Capture Mux", "IN1L", "IN1L" }, 1328 { "Left Capture Mux", "IN2L", "IN2L" }, 1329 { "Left Capture Mux", "IN3L", "IN3L" }, 1330 1331 { "Left Capture Inverting Mux", "IN1L", "IN1L" }, 1332 { "Left Capture Inverting Mux", "IN2L", "IN2L" }, 1333 { "Left Capture Inverting Mux", "IN3L", "IN3L" }, 1334 1335 { "Right Capture Mux", "IN1R", "IN1R" }, 1336 { "Right Capture Mux", "IN2R", "IN2R" }, 1337 { "Right Capture Mux", "IN3R", "IN3R" }, 1338 1339 { "Right Capture Inverting Mux", "IN1R", "IN1R" }, 1340 { "Right Capture Inverting Mux", "IN2R", "IN2R" }, 1341 { "Right Capture Inverting Mux", "IN3R", "IN3R" }, 1342 1343 { "Left Capture PGA", NULL, "Left Capture Mux" }, 1344 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, 1345 1346 { "Right Capture PGA", NULL, "Right Capture Mux" }, 1347 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, 1348 1349 { "AIFOUTL", "Left", "ADCL" }, 1350 { "AIFOUTL", "Right", "ADCR" }, 1351 { "AIFOUTR", "Left", "ADCL" }, 1352 { "AIFOUTR", "Right", "ADCR" }, 1353 1354 { "ADCL", NULL, "CLK_DSP" }, 1355 { "ADCL", NULL, "Left Capture PGA" }, 1356 1357 { "ADCR", NULL, "CLK_DSP" }, 1358 { "ADCR", NULL, "Right Capture PGA" }, 1359}; 1360 1361static const struct snd_soc_dapm_route dac_intercon[] = { 1362 { "DACL", "Right", "AIFINR" }, 1363 { "DACL", "Left", "AIFINL" }, 1364 { "DACL", NULL, "CLK_DSP" }, 1365 1366 { "DACR", "Right", "AIFINR" }, 1367 { "DACR", "Left", "AIFINL" }, 1368 { "DACR", NULL, "CLK_DSP" }, 1369 1370 { "Charge pump", NULL, "SYSCLK" }, 1371 1372 { "Headphone Output", NULL, "HPL PGA" }, 1373 { "Headphone Output", NULL, "HPR PGA" }, 1374 { "Headphone Output", NULL, "Charge pump" }, 1375 { "Headphone Output", NULL, "TOCLK" }, 1376 1377 { "Line Output", NULL, "LINEL PGA" }, 1378 { "Line Output", NULL, "LINER PGA" }, 1379 { "Line Output", NULL, "Charge pump" }, 1380 { "Line Output", NULL, "TOCLK" }, 1381 1382 { "HPOUTL", NULL, "Headphone Output" }, 1383 { "HPOUTR", NULL, "Headphone Output" }, 1384 1385 { "LINEOUTL", NULL, "Line Output" }, 1386 { "LINEOUTR", NULL, "Line Output" }, 1387}; 1388 1389static const struct snd_soc_dapm_route wm8904_intercon[] = { 1390 { "Left Sidetone", "Left", "ADCL" }, 1391 { "Left Sidetone", "Right", "ADCR" }, 1392 { "DACL", NULL, "Left Sidetone" }, 1393 1394 { "Right Sidetone", "Left", "ADCL" }, 1395 { "Right Sidetone", "Right", "ADCR" }, 1396 { "DACR", NULL, "Right Sidetone" }, 1397 1398 { "Left Bypass", NULL, "Class G" }, 1399 { "Left Bypass", NULL, "Left Capture PGA" }, 1400 1401 { "Right Bypass", NULL, "Class G" }, 1402 { "Right Bypass", NULL, "Right Capture PGA" }, 1403 1404 { "HPL Mux", "DAC", "DACL" }, 1405 { "HPL Mux", "Bypass", "Left Bypass" }, 1406 1407 { "HPR Mux", "DAC", "DACR" }, 1408 { "HPR Mux", "Bypass", "Right Bypass" }, 1409 1410 { "LINEL Mux", "DAC", "DACL" }, 1411 { "LINEL Mux", "Bypass", "Left Bypass" }, 1412 1413 { "LINER Mux", "DAC", "DACR" }, 1414 { "LINER Mux", "Bypass", "Right Bypass" }, 1415 1416 { "HPL PGA", NULL, "HPL Mux" }, 1417 { "HPR PGA", NULL, "HPR Mux" }, 1418 1419 { "LINEL PGA", NULL, "LINEL Mux" }, 1420 { "LINER PGA", NULL, "LINER Mux" }, 1421}; 1422 1423static const struct snd_soc_dapm_route wm8912_intercon[] = { 1424 { "HPL PGA", NULL, "DACL" }, 1425 { "HPR PGA", NULL, "DACR" }, 1426 1427 { "LINEL PGA", NULL, "DACL" }, 1428 { "LINER PGA", NULL, "DACR" }, 1429}; 1430 1431static int wm8904_add_widgets(struct snd_soc_codec *codec) 1432{ 1433 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1434 1435 snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets, 1436 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1437 snd_soc_dapm_add_routes(codec, core_intercon, 1438 ARRAY_SIZE(core_intercon)); 1439 1440 switch (wm8904->devtype) { 1441 case WM8904: 1442 snd_soc_add_controls(codec, wm8904_adc_snd_controls, 1443 ARRAY_SIZE(wm8904_adc_snd_controls)); 1444 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1445 ARRAY_SIZE(wm8904_dac_snd_controls)); 1446 snd_soc_add_controls(codec, wm8904_snd_controls, 1447 ARRAY_SIZE(wm8904_snd_controls)); 1448 1449 snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets, 1450 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1451 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, 1452 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1453 snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets, 1454 ARRAY_SIZE(wm8904_dapm_widgets)); 1455 1456 snd_soc_dapm_add_routes(codec, core_intercon, 1457 ARRAY_SIZE(core_intercon)); 1458 snd_soc_dapm_add_routes(codec, adc_intercon, 1459 ARRAY_SIZE(adc_intercon)); 1460 snd_soc_dapm_add_routes(codec, dac_intercon, 1461 ARRAY_SIZE(dac_intercon)); 1462 snd_soc_dapm_add_routes(codec, wm8904_intercon, 1463 ARRAY_SIZE(wm8904_intercon)); 1464 break; 1465 1466 case WM8912: 1467 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1468 ARRAY_SIZE(wm8904_dac_snd_controls)); 1469 1470 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, 1471 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1472 1473 snd_soc_dapm_add_routes(codec, dac_intercon, 1474 ARRAY_SIZE(dac_intercon)); 1475 snd_soc_dapm_add_routes(codec, wm8912_intercon, 1476 ARRAY_SIZE(wm8912_intercon)); 1477 break; 1478 } 1479 1480 snd_soc_dapm_new_widgets(codec); 1481 return 0; 1482} 1483 1484static struct { 1485 int ratio; 1486 unsigned int clk_sys_rate; 1487} clk_sys_rates[] = { 1488 { 64, 0 }, 1489 { 128, 1 }, 1490 { 192, 2 }, 1491 { 256, 3 }, 1492 { 384, 4 }, 1493 { 512, 5 }, 1494 { 786, 6 }, 1495 { 1024, 7 }, 1496 { 1408, 8 }, 1497 { 1536, 9 }, 1498}; 1499 1500static struct { 1501 int rate; 1502 int sample_rate; 1503} sample_rates[] = { 1504 { 8000, 0 }, 1505 { 11025, 1 }, 1506 { 12000, 1 }, 1507 { 16000, 2 }, 1508 { 22050, 3 }, 1509 { 24000, 3 }, 1510 { 32000, 4 }, 1511 { 44100, 5 }, 1512 { 48000, 5 }, 1513}; 1514 1515static struct { 1516 int div; /* *10 due to .5s */ 1517 int bclk_div; 1518} bclk_divs[] = { 1519 { 10, 0 }, 1520 { 15, 1 }, 1521 { 20, 2 }, 1522 { 30, 3 }, 1523 { 40, 4 }, 1524 { 50, 5 }, 1525 { 55, 6 }, 1526 { 60, 7 }, 1527 { 80, 8 }, 1528 { 100, 9 }, 1529 { 110, 10 }, 1530 { 120, 11 }, 1531 { 160, 12 }, 1532 { 200, 13 }, 1533 { 220, 14 }, 1534 { 240, 16 }, 1535 { 200, 17 }, 1536 { 320, 18 }, 1537 { 440, 19 }, 1538 { 480, 20 }, 1539}; 1540 1541 1542static int wm8904_hw_params(struct snd_pcm_substream *substream, 1543 struct snd_pcm_hw_params *params, 1544 struct snd_soc_dai *dai) 1545{ 1546 struct snd_soc_codec *codec = dai->codec; 1547 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1548 int ret, i, best, best_val, cur_val; 1549 unsigned int aif1 = 0; 1550 unsigned int aif2 = 0; 1551 unsigned int aif3 = 0; 1552 unsigned int clock1 = 0; 1553 unsigned int dac_digital1 = 0; 1554 1555 /* What BCLK do we need? */ 1556 wm8904->fs = params_rate(params); 1557 if (wm8904->tdm_slots) { 1558 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1559 wm8904->tdm_slots, wm8904->tdm_width); 1560 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, 1561 wm8904->tdm_width, 2, 1562 wm8904->tdm_slots); 1563 } else { 1564 wm8904->bclk = snd_soc_params_to_bclk(params); 1565 } 1566 1567 switch (params_format(params)) { 1568 case SNDRV_PCM_FORMAT_S16_LE: 1569 break; 1570 case SNDRV_PCM_FORMAT_S20_3LE: 1571 aif1 |= 0x40; 1572 break; 1573 case SNDRV_PCM_FORMAT_S24_LE: 1574 aif1 |= 0x80; 1575 break; 1576 case SNDRV_PCM_FORMAT_S32_LE: 1577 aif1 |= 0xc0; 1578 break; 1579 default: 1580 return -EINVAL; 1581 } 1582 1583 1584 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); 1585 1586 ret = wm8904_configure_clocking(codec); 1587 if (ret != 0) 1588 return ret; 1589 1590 /* Select nearest CLK_SYS_RATE */ 1591 best = 0; 1592 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) 1593 - wm8904->fs); 1594 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1595 cur_val = abs((wm8904->sysclk_rate / 1596 clk_sys_rates[i].ratio) - wm8904->fs);; 1597 if (cur_val < best_val) { 1598 best = i; 1599 best_val = cur_val; 1600 } 1601 } 1602 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1603 clk_sys_rates[best].ratio); 1604 clock1 |= (clk_sys_rates[best].clk_sys_rate 1605 << WM8904_CLK_SYS_RATE_SHIFT); 1606 1607 /* SAMPLE_RATE */ 1608 best = 0; 1609 best_val = abs(wm8904->fs - sample_rates[0].rate); 1610 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1611 /* Closest match */ 1612 cur_val = abs(wm8904->fs - sample_rates[i].rate); 1613 if (cur_val < best_val) { 1614 best = i; 1615 best_val = cur_val; 1616 } 1617 } 1618 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1619 sample_rates[best].rate); 1620 clock1 |= (sample_rates[best].sample_rate 1621 << WM8904_SAMPLE_RATE_SHIFT); 1622 1623 /* Enable sloping stopband filter for low sample rates */ 1624 if (wm8904->fs <= 24000) 1625 dac_digital1 |= WM8904_DAC_SB_FILT; 1626 1627 /* BCLK_DIV */ 1628 best = 0; 1629 best_val = INT_MAX; 1630 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1631 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) 1632 - wm8904->bclk; 1633 if (cur_val < 0) /* Table is sorted */ 1634 break; 1635 if (cur_val < best_val) { 1636 best = i; 1637 best_val = cur_val; 1638 } 1639 } 1640 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; 1641 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1642 bclk_divs[best].div, wm8904->bclk); 1643 aif2 |= bclk_divs[best].bclk_div; 1644 1645 /* LRCLK is a simple fraction of BCLK */ 1646 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); 1647 aif3 |= wm8904->bclk / wm8904->fs; 1648 1649 /* Apply the settings */ 1650 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 1651 WM8904_DAC_SB_FILT, dac_digital1); 1652 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1653 WM8904_AIF_WL_MASK, aif1); 1654 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, 1655 WM8904_BCLK_DIV_MASK, aif2); 1656 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1657 WM8904_LRCLK_RATE_MASK, aif3); 1658 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, 1659 WM8904_SAMPLE_RATE_MASK | 1660 WM8904_CLK_SYS_RATE_MASK, clock1); 1661 1662 /* Update filters for the new settings */ 1663 wm8904_set_retune_mobile(codec); 1664 wm8904_set_deemph(codec); 1665 1666 return 0; 1667} 1668 1669 1670static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1671 unsigned int freq, int dir) 1672{ 1673 struct snd_soc_codec *codec = dai->codec; 1674 struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); 1675 1676 switch (clk_id) { 1677 case WM8904_CLK_MCLK: 1678 priv->sysclk_src = clk_id; 1679 priv->mclk_rate = freq; 1680 break; 1681 1682 case WM8904_CLK_FLL: 1683 priv->sysclk_src = clk_id; 1684 break; 1685 1686 default: 1687 return -EINVAL; 1688 } 1689 1690 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1691 1692 wm8904_configure_clocking(codec); 1693 1694 return 0; 1695} 1696 1697static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1698{ 1699 struct snd_soc_codec *codec = dai->codec; 1700 unsigned int aif1 = 0; 1701 unsigned int aif3 = 0; 1702 1703 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1704 case SND_SOC_DAIFMT_CBS_CFS: 1705 break; 1706 case SND_SOC_DAIFMT_CBS_CFM: 1707 aif3 |= WM8904_LRCLK_DIR; 1708 break; 1709 case SND_SOC_DAIFMT_CBM_CFS: 1710 aif1 |= WM8904_BCLK_DIR; 1711 break; 1712 case SND_SOC_DAIFMT_CBM_CFM: 1713 aif1 |= WM8904_BCLK_DIR; 1714 aif3 |= WM8904_LRCLK_DIR; 1715 break; 1716 default: 1717 return -EINVAL; 1718 } 1719 1720 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1721 case SND_SOC_DAIFMT_DSP_B: 1722 aif1 |= WM8904_AIF_LRCLK_INV; 1723 case SND_SOC_DAIFMT_DSP_A: 1724 aif1 |= 0x3; 1725 break; 1726 case SND_SOC_DAIFMT_I2S: 1727 aif1 |= 0x2; 1728 break; 1729 case SND_SOC_DAIFMT_RIGHT_J: 1730 break; 1731 case SND_SOC_DAIFMT_LEFT_J: 1732 aif1 |= 0x1; 1733 break; 1734 default: 1735 return -EINVAL; 1736 } 1737 1738 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1739 case SND_SOC_DAIFMT_DSP_A: 1740 case SND_SOC_DAIFMT_DSP_B: 1741 /* frame inversion not valid for DSP modes */ 1742 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1743 case SND_SOC_DAIFMT_NB_NF: 1744 break; 1745 case SND_SOC_DAIFMT_IB_NF: 1746 aif1 |= WM8904_AIF_BCLK_INV; 1747 break; 1748 default: 1749 return -EINVAL; 1750 } 1751 break; 1752 1753 case SND_SOC_DAIFMT_I2S: 1754 case SND_SOC_DAIFMT_RIGHT_J: 1755 case SND_SOC_DAIFMT_LEFT_J: 1756 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1757 case SND_SOC_DAIFMT_NB_NF: 1758 break; 1759 case SND_SOC_DAIFMT_IB_IF: 1760 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; 1761 break; 1762 case SND_SOC_DAIFMT_IB_NF: 1763 aif1 |= WM8904_AIF_BCLK_INV; 1764 break; 1765 case SND_SOC_DAIFMT_NB_IF: 1766 aif1 |= WM8904_AIF_LRCLK_INV; 1767 break; 1768 default: 1769 return -EINVAL; 1770 } 1771 break; 1772 default: 1773 return -EINVAL; 1774 } 1775 1776 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1777 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | 1778 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); 1779 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1780 WM8904_LRCLK_DIR, aif3); 1781 1782 return 0; 1783} 1784 1785 1786static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1787 unsigned int rx_mask, int slots, int slot_width) 1788{ 1789 struct snd_soc_codec *codec = dai->codec; 1790 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1791 int aif1 = 0; 1792 1793 /* Don't need to validate anything if we're turning off TDM */ 1794 if (slots == 0) 1795 goto out; 1796 1797 /* Note that we allow configurations we can't handle ourselves - 1798 * for example, we can generate clocks for slots 2 and up even if 1799 * we can't use those slots ourselves. 1800 */ 1801 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; 1802 1803 switch (rx_mask) { 1804 case 3: 1805 break; 1806 case 0xc: 1807 aif1 |= WM8904_AIFADC_TDM_CHAN; 1808 break; 1809 default: 1810 return -EINVAL; 1811 } 1812 1813 1814 switch (tx_mask) { 1815 case 3: 1816 break; 1817 case 0xc: 1818 aif1 |= WM8904_AIFDAC_TDM_CHAN; 1819 break; 1820 default: 1821 return -EINVAL; 1822 } 1823 1824out: 1825 wm8904->tdm_width = slot_width; 1826 wm8904->tdm_slots = slots / 2; 1827 1828 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1829 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | 1830 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); 1831 1832 return 0; 1833} 1834 1835struct _fll_div { 1836 u16 fll_fratio; 1837 u16 fll_outdiv; 1838 u16 fll_clk_ref_div; 1839 u16 n; 1840 u16 k; 1841}; 1842 1843/* The size in bits of the FLL divide multiplied by 10 1844 * to allow rounding later */ 1845#define FIXED_FLL_SIZE ((1 << 16) * 10) 1846 1847static struct { 1848 unsigned int min; 1849 unsigned int max; 1850 u16 fll_fratio; 1851 int ratio; 1852} fll_fratios[] = { 1853 { 0, 64000, 4, 16 }, 1854 { 64000, 128000, 3, 8 }, 1855 { 128000, 256000, 2, 4 }, 1856 { 256000, 1000000, 1, 2 }, 1857 { 1000000, 13500000, 0, 1 }, 1858}; 1859 1860static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1861 unsigned int Fout) 1862{ 1863 u64 Kpart; 1864 unsigned int K, Ndiv, Nmod, target; 1865 unsigned int div; 1866 int i; 1867 1868 /* Fref must be <=13.5MHz */ 1869 div = 1; 1870 fll_div->fll_clk_ref_div = 0; 1871 while ((Fref / div) > 13500000) { 1872 div *= 2; 1873 fll_div->fll_clk_ref_div++; 1874 1875 if (div > 8) { 1876 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1877 Fref); 1878 return -EINVAL; 1879 } 1880 } 1881 1882 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 1883 1884 /* Apply the division for our remaining calculations */ 1885 Fref /= div; 1886 1887 /* Fvco should be 90-100MHz; don't check the upper bound */ 1888 div = 4; 1889 while (Fout * div < 90000000) { 1890 div++; 1891 if (div > 64) { 1892 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1893 Fout); 1894 return -EINVAL; 1895 } 1896 } 1897 target = Fout * div; 1898 fll_div->fll_outdiv = div - 1; 1899 1900 pr_debug("Fvco=%dHz\n", target); 1901 1902 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 1903 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1904 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1905 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1906 target /= fll_fratios[i].ratio; 1907 break; 1908 } 1909 } 1910 if (i == ARRAY_SIZE(fll_fratios)) { 1911 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1912 return -EINVAL; 1913 } 1914 1915 /* Now, calculate N.K */ 1916 Ndiv = target / Fref; 1917 1918 fll_div->n = Ndiv; 1919 Nmod = target % Fref; 1920 pr_debug("Nmod=%d\n", Nmod); 1921 1922 /* Calculate fractional part - scale up so we can round. */ 1923 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1924 1925 do_div(Kpart, Fref); 1926 1927 K = Kpart & 0xFFFFFFFF; 1928 1929 if ((K % 10) >= 5) 1930 K += 5; 1931 1932 /* Move down to proper range now rounding is done */ 1933 fll_div->k = K / 10; 1934 1935 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 1936 fll_div->n, fll_div->k, 1937 fll_div->fll_fratio, fll_div->fll_outdiv, 1938 fll_div->fll_clk_ref_div); 1939 1940 return 0; 1941} 1942 1943static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 1944 unsigned int Fref, unsigned int Fout) 1945{ 1946 struct snd_soc_codec *codec = dai->codec; 1947 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1948 struct _fll_div fll_div; 1949 int ret, val; 1950 int clock2, fll1; 1951 1952 /* Any change? */ 1953 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && 1954 Fout == wm8904->fll_fout) 1955 return 0; 1956 1957 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 1958 1959 if (Fout == 0) { 1960 dev_dbg(codec->dev, "FLL disabled\n"); 1961 1962 wm8904->fll_fref = 0; 1963 wm8904->fll_fout = 0; 1964 1965 /* Gate SYSCLK to avoid glitches */ 1966 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 1967 WM8904_CLK_SYS_ENA, 0); 1968 1969 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 1970 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1971 1972 goto out; 1973 } 1974 1975 /* Validate the FLL ID */ 1976 switch (source) { 1977 case WM8904_FLL_MCLK: 1978 case WM8904_FLL_LRCLK: 1979 case WM8904_FLL_BCLK: 1980 ret = fll_factors(&fll_div, Fref, Fout); 1981 if (ret != 0) 1982 return ret; 1983 break; 1984 1985 case WM8904_FLL_FREE_RUNNING: 1986 dev_dbg(codec->dev, "Using free running FLL\n"); 1987 /* Force 12MHz and output/4 for now */ 1988 Fout = 12000000; 1989 Fref = 12000000; 1990 1991 memset(&fll_div, 0, sizeof(fll_div)); 1992 fll_div.fll_outdiv = 3; 1993 break; 1994 1995 default: 1996 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 1997 return -EINVAL; 1998 } 1999 2000 /* Save current state then disable the FLL and SYSCLK to avoid 2001 * misclocking */ 2002 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); 2003 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 2004 WM8904_CLK_SYS_ENA, 0); 2005 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2006 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 2007 2008 /* Unlock forced oscilator control to switch it on/off */ 2009 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2010 WM8904_USER_KEY, WM8904_USER_KEY); 2011 2012 if (fll_id == WM8904_FLL_FREE_RUNNING) { 2013 val = WM8904_FLL_FRC_NCO; 2014 } else { 2015 val = 0; 2016 } 2017 2018 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, 2019 val); 2020 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2021 WM8904_USER_KEY, 0); 2022 2023 switch (fll_id) { 2024 case WM8904_FLL_MCLK: 2025 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2026 WM8904_FLL_CLK_REF_SRC_MASK, 0); 2027 break; 2028 2029 case WM8904_FLL_LRCLK: 2030 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2031 WM8904_FLL_CLK_REF_SRC_MASK, 1); 2032 break; 2033 2034 case WM8904_FLL_BCLK: 2035 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2036 WM8904_FLL_CLK_REF_SRC_MASK, 2); 2037 break; 2038 } 2039 2040 if (fll_div.k) 2041 val = WM8904_FLL_FRACN_ENA; 2042 else 2043 val = 0; 2044 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2045 WM8904_FLL_FRACN_ENA, val); 2046 2047 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, 2048 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, 2049 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | 2050 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); 2051 2052 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); 2053 2054 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, 2055 fll_div.n << WM8904_FLL_N_SHIFT); 2056 2057 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2058 WM8904_FLL_CLK_REF_DIV_MASK, 2059 fll_div.fll_clk_ref_div 2060 << WM8904_FLL_CLK_REF_DIV_SHIFT); 2061 2062 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2063 2064 wm8904->fll_fref = Fref; 2065 wm8904->fll_fout = Fout; 2066 wm8904->fll_src = source; 2067 2068 /* Enable the FLL if it was previously active */ 2069 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2070 WM8904_FLL_OSC_ENA, fll1); 2071 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2072 WM8904_FLL_ENA, fll1); 2073 2074out: 2075 /* Reenable SYSCLK if it was previously active */ 2076 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 2077 WM8904_CLK_SYS_ENA, clock2); 2078 2079 return 0; 2080} 2081 2082static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) 2083{ 2084 struct snd_soc_codec *codec = codec_dai->codec; 2085 int val; 2086 2087 if (mute) 2088 val = WM8904_DAC_MUTE; 2089 else 2090 val = 0; 2091 2092 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); 2093 2094 return 0; 2095} 2096 2097static void wm8904_sync_cache(struct snd_soc_codec *codec) 2098{ 2099 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2100 int i; 2101 2102 if (!codec->cache_sync) 2103 return; 2104 2105 codec->cache_only = 0; 2106 2107 /* Sync back cached values if they're different from the 2108 * hardware default. 2109 */ 2110 for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) { 2111 if (!wm8904_access[i].writable) 2112 continue; 2113 2114 if (wm8904->reg_cache[i] == wm8904_reg[i]) 2115 continue; 2116 2117 snd_soc_write(codec, i, wm8904->reg_cache[i]); 2118 } 2119 2120 codec->cache_sync = 0; 2121} 2122 2123static int wm8904_set_bias_level(struct snd_soc_codec *codec, 2124 enum snd_soc_bias_level level) 2125{ 2126 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2127 int ret; 2128 2129 switch (level) { 2130 case SND_SOC_BIAS_ON: 2131 break; 2132 2133 case SND_SOC_BIAS_PREPARE: 2134 /* VMID resistance 2*50k */ 2135 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2136 WM8904_VMID_RES_MASK, 2137 0x1 << WM8904_VMID_RES_SHIFT); 2138 2139 /* Normal bias current */ 2140 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2141 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); 2142 break; 2143 2144 case SND_SOC_BIAS_STANDBY: 2145 if (codec->bias_level == SND_SOC_BIAS_OFF) { 2146 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2147 wm8904->supplies); 2148 if (ret != 0) { 2149 dev_err(codec->dev, 2150 "Failed to enable supplies: %d\n", 2151 ret); 2152 return ret; 2153 } 2154 2155 wm8904_sync_cache(codec); 2156 2157 /* Enable bias */ 2158 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2159 WM8904_BIAS_ENA, WM8904_BIAS_ENA); 2160 2161 /* Enable VMID, VMID buffering, 2*5k resistance */ 2162 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2163 WM8904_VMID_ENA | 2164 WM8904_VMID_RES_MASK, 2165 WM8904_VMID_ENA | 2166 0x3 << WM8904_VMID_RES_SHIFT); 2167 2168 /* Let VMID ramp */ 2169 msleep(1); 2170 } 2171 2172 /* Maintain VMID with 2*250k */ 2173 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2174 WM8904_VMID_RES_MASK, 2175 0x2 << WM8904_VMID_RES_SHIFT); 2176 2177 /* Bias current *0.5 */ 2178 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2179 WM8904_ISEL_MASK, 0); 2180 break; 2181 2182 case SND_SOC_BIAS_OFF: 2183 /* Turn off VMID */ 2184 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2185 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); 2186 2187 /* Stop bias generation */ 2188 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2189 WM8904_BIAS_ENA, 0); 2190 2191#ifdef CONFIG_REGULATOR 2192 /* Post 2.6.34 we will be able to get a callback when 2193 * the regulators are disabled which we can use but 2194 * for now just assume that the power will be cut if 2195 * the regulator API is in use. 2196 */ 2197 codec->cache_sync = 1; 2198#endif 2199 2200 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 2201 wm8904->supplies); 2202 break; 2203 } 2204 codec->bias_level = level; 2205 return 0; 2206} 2207 2208#define WM8904_RATES SNDRV_PCM_RATE_8000_96000 2209 2210#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2211 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2212 2213static struct snd_soc_dai_ops wm8904_dai_ops = { 2214 .set_sysclk = wm8904_set_sysclk, 2215 .set_fmt = wm8904_set_fmt, 2216 .set_tdm_slot = wm8904_set_tdm_slot, 2217 .set_pll = wm8904_set_fll, 2218 .hw_params = wm8904_hw_params, 2219 .digital_mute = wm8904_digital_mute, 2220}; 2221 2222struct snd_soc_dai wm8904_dai = { 2223 .name = "WM8904", 2224 .playback = { 2225 .stream_name = "Playback", 2226 .channels_min = 2, 2227 .channels_max = 2, 2228 .rates = WM8904_RATES, 2229 .formats = WM8904_FORMATS, 2230 }, 2231 .capture = { 2232 .stream_name = "Capture", 2233 .channels_min = 2, 2234 .channels_max = 2, 2235 .rates = WM8904_RATES, 2236 .formats = WM8904_FORMATS, 2237 }, 2238 .ops = &wm8904_dai_ops, 2239 .symmetric_rates = 1, 2240}; 2241EXPORT_SYMBOL_GPL(wm8904_dai); 2242 2243#ifdef CONFIG_PM 2244static int wm8904_suspend(struct platform_device *pdev, pm_message_t state) 2245{ 2246 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2247 struct snd_soc_codec *codec = socdev->card->codec; 2248 2249 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); 2250 2251 return 0; 2252} 2253 2254static int wm8904_resume(struct platform_device *pdev) 2255{ 2256 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2257 struct snd_soc_codec *codec = socdev->card->codec; 2258 2259 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2260 2261 return 0; 2262} 2263#else 2264#define wm8904_suspend NULL 2265#define wm8904_resume NULL 2266#endif 2267 2268static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904) 2269{ 2270 struct snd_soc_codec *codec = &wm8904->codec; 2271 struct wm8904_pdata *pdata = wm8904->pdata; 2272 struct snd_kcontrol_new control = 2273 SOC_ENUM_EXT("EQ Mode", 2274 wm8904->retune_mobile_enum, 2275 wm8904_get_retune_mobile_enum, 2276 wm8904_put_retune_mobile_enum); 2277 int ret, i, j; 2278 const char **t; 2279 2280 /* We need an array of texts for the enum API but the number 2281 * of texts is likely to be less than the number of 2282 * configurations due to the sample rate dependency of the 2283 * configurations. */ 2284 wm8904->num_retune_mobile_texts = 0; 2285 wm8904->retune_mobile_texts = NULL; 2286 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2287 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { 2288 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2289 wm8904->retune_mobile_texts[j]) == 0) 2290 break; 2291 } 2292 2293 if (j != wm8904->num_retune_mobile_texts) 2294 continue; 2295 2296 /* Expand the array... */ 2297 t = krealloc(wm8904->retune_mobile_texts, 2298 sizeof(char *) * 2299 (wm8904->num_retune_mobile_texts + 1), 2300 GFP_KERNEL); 2301 if (t == NULL) 2302 continue; 2303 2304 /* ...store the new entry... */ 2305 t[wm8904->num_retune_mobile_texts] = 2306 pdata->retune_mobile_cfgs[i].name; 2307 2308 /* ...and remember the new version. */ 2309 wm8904->num_retune_mobile_texts++; 2310 wm8904->retune_mobile_texts = t; 2311 } 2312 2313 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2314 wm8904->num_retune_mobile_texts); 2315 2316 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; 2317 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; 2318 2319 ret = snd_soc_add_controls(&wm8904->codec, &control, 1); 2320 if (ret != 0) 2321 dev_err(wm8904->codec.dev, 2322 "Failed to add ReTune Mobile control: %d\n", ret); 2323} 2324 2325static void wm8904_handle_pdata(struct wm8904_priv *wm8904) 2326{ 2327 struct snd_soc_codec *codec = &wm8904->codec; 2328 struct wm8904_pdata *pdata = wm8904->pdata; 2329 int ret, i; 2330 2331 if (!pdata) { 2332 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls, 2333 ARRAY_SIZE(wm8904_eq_controls)); 2334 return; 2335 } 2336 2337 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2338 2339 if (pdata->num_drc_cfgs) { 2340 struct snd_kcontrol_new control = 2341 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, 2342 wm8904_get_drc_enum, wm8904_put_drc_enum); 2343 2344 /* We need an array of texts for the enum API */ 2345 wm8904->drc_texts = kmalloc(sizeof(char *) 2346 * pdata->num_drc_cfgs, GFP_KERNEL); 2347 if (!wm8904->drc_texts) { 2348 dev_err(wm8904->codec.dev, 2349 "Failed to allocate %d DRC config texts\n", 2350 pdata->num_drc_cfgs); 2351 return; 2352 } 2353 2354 for (i = 0; i < pdata->num_drc_cfgs; i++) 2355 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; 2356 2357 wm8904->drc_enum.max = pdata->num_drc_cfgs; 2358 wm8904->drc_enum.texts = wm8904->drc_texts; 2359 2360 ret = snd_soc_add_controls(&wm8904->codec, &control, 1); 2361 if (ret != 0) 2362 dev_err(wm8904->codec.dev, 2363 "Failed to add DRC mode control: %d\n", ret); 2364 2365 wm8904_set_drc(codec); 2366 } 2367 2368 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2369 pdata->num_retune_mobile_cfgs); 2370 2371 if (pdata->num_retune_mobile_cfgs) 2372 wm8904_handle_retune_mobile_pdata(wm8904); 2373 else 2374 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls, 2375 ARRAY_SIZE(wm8904_eq_controls)); 2376} 2377 2378static int wm8904_probe(struct platform_device *pdev) 2379{ 2380 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2381 struct snd_soc_codec *codec; 2382 int ret = 0; 2383 2384 if (wm8904_codec == NULL) { 2385 dev_err(&pdev->dev, "Codec device not registered\n"); 2386 return -ENODEV; 2387 } 2388 2389 socdev->card->codec = wm8904_codec; 2390 codec = wm8904_codec; 2391 2392 /* register pcms */ 2393 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 2394 if (ret < 0) { 2395 dev_err(codec->dev, "failed to create pcms: %d\n", ret); 2396 goto pcm_err; 2397 } 2398 2399 wm8904_handle_pdata(snd_soc_codec_get_drvdata(codec)); 2400 2401 wm8904_add_widgets(codec); 2402 2403 return ret; 2404 2405pcm_err: 2406 return ret; 2407} 2408 2409static int wm8904_remove(struct platform_device *pdev) 2410{ 2411 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2412 2413 snd_soc_free_pcms(socdev); 2414 snd_soc_dapm_free(socdev); 2415 2416 return 0; 2417} 2418 2419struct snd_soc_codec_device soc_codec_dev_wm8904 = { 2420 .probe = wm8904_probe, 2421 .remove = wm8904_remove, 2422 .suspend = wm8904_suspend, 2423 .resume = wm8904_resume, 2424}; 2425EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904); 2426 2427static int wm8904_register(struct wm8904_priv *wm8904, 2428 enum snd_soc_control_type control) 2429{ 2430 struct wm8904_pdata *pdata = wm8904->pdata; 2431 int ret; 2432 struct snd_soc_codec *codec = &wm8904->codec; 2433 int i; 2434 2435 if (wm8904_codec) { 2436 dev_err(codec->dev, "Another WM8904 is registered\n"); 2437 ret = -EINVAL; 2438 goto err; 2439 } 2440 2441 mutex_init(&codec->mutex); 2442 INIT_LIST_HEAD(&codec->dapm_widgets); 2443 INIT_LIST_HEAD(&codec->dapm_paths); 2444 2445 snd_soc_codec_set_drvdata(codec, wm8904); 2446 codec->name = "WM8904"; 2447 codec->owner = THIS_MODULE; 2448 codec->bias_level = SND_SOC_BIAS_OFF; 2449 codec->set_bias_level = wm8904_set_bias_level; 2450 codec->dai = &wm8904_dai; 2451 codec->num_dai = 1; 2452 codec->reg_cache_size = WM8904_MAX_REGISTER; 2453 codec->reg_cache = &wm8904->reg_cache; 2454 codec->volatile_register = wm8904_volatile_register; 2455 codec->cache_sync = 1; 2456 codec->idle_bias_off = 1; 2457 2458 switch (wm8904->devtype) { 2459 case WM8904: 2460 break; 2461 case WM8912: 2462 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); 2463 break; 2464 default: 2465 dev_err(codec->dev, "Unknown device type %d\n", 2466 wm8904->devtype); 2467 ret = -EINVAL; 2468 goto err; 2469 } 2470 2471 memcpy(codec->reg_cache, wm8904_reg, sizeof(wm8904_reg)); 2472 2473 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control); 2474 if (ret != 0) { 2475 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2476 goto err; 2477 } 2478 2479 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) 2480 wm8904->supplies[i].supply = wm8904_supply_names[i]; 2481 2482 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), 2483 wm8904->supplies); 2484 if (ret != 0) { 2485 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2486 goto err; 2487 } 2488 2489 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2490 wm8904->supplies); 2491 if (ret != 0) { 2492 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2493 goto err_get; 2494 } 2495 2496 ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID); 2497 if (ret < 0) { 2498 dev_err(codec->dev, "Failed to read ID register\n"); 2499 goto err_enable; 2500 } 2501 if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) { 2502 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); 2503 ret = -EINVAL; 2504 goto err_enable; 2505 } 2506 2507 ret = snd_soc_read(codec, WM8904_REVISION); 2508 if (ret < 0) { 2509 dev_err(codec->dev, "Failed to read device revision: %d\n", 2510 ret); 2511 goto err_enable; 2512 } 2513 dev_info(codec->dev, "revision %c\n", ret + 'A'); 2514 2515 ret = wm8904_reset(codec); 2516 if (ret < 0) { 2517 dev_err(codec->dev, "Failed to issue reset\n"); 2518 goto err_enable; 2519 } 2520 2521 wm8904_dai.dev = codec->dev; 2522 2523 /* Change some default settings - latch VU and enable ZC */ 2524 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; 2525 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; 2526 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; 2527 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; 2528 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | 2529 WM8904_HPOUTLZC; 2530 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | 2531 WM8904_HPOUTRZC; 2532 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | 2533 WM8904_LINEOUTLZC; 2534 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | 2535 WM8904_LINEOUTRZC; 2536 wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; 2537 2538 /* Apply configuration from the platform data. */ 2539 if (wm8904->pdata) { 2540 for (i = 0; i < WM8904_GPIO_REGS; i++) { 2541 if (!pdata->gpio_cfg[i]) 2542 continue; 2543 2544 wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i] 2545 = pdata->gpio_cfg[i] & 0xffff; 2546 } 2547 2548 /* Zero is the default value for these anyway */ 2549 for (i = 0; i < WM8904_MIC_REGS; i++) 2550 wm8904->reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] 2551 = pdata->mic_cfg[i]; 2552 } 2553 2554 /* Set Class W by default - this will be managed by the Class 2555 * G widget at runtime where bypass paths are available. 2556 */ 2557 wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; 2558 2559 /* Use normal bias source */ 2560 wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; 2561 2562 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2563 2564 /* Bias level configuration will have done an extra enable */ 2565 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2566 2567 wm8904_codec = codec; 2568 2569 ret = snd_soc_register_codec(codec); 2570 if (ret != 0) { 2571 dev_err(codec->dev, "Failed to register codec: %d\n", ret); 2572 goto err_enable; 2573 } 2574 2575 ret = snd_soc_register_dai(&wm8904_dai); 2576 if (ret != 0) { 2577 dev_err(codec->dev, "Failed to register DAI: %d\n", ret); 2578 goto err_codec; 2579 } 2580 2581 return 0; 2582 2583err_codec: 2584 snd_soc_unregister_codec(codec); 2585err_enable: 2586 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2587err_get: 2588 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2589err: 2590 kfree(wm8904); 2591 return ret; 2592} 2593 2594static void wm8904_unregister(struct wm8904_priv *wm8904) 2595{ 2596 wm8904_set_bias_level(&wm8904->codec, SND_SOC_BIAS_OFF); 2597 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2598 snd_soc_unregister_dai(&wm8904_dai); 2599 snd_soc_unregister_codec(&wm8904->codec); 2600 kfree(wm8904); 2601 wm8904_codec = NULL; 2602} 2603 2604#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2605static __devinit int wm8904_i2c_probe(struct i2c_client *i2c, 2606 const struct i2c_device_id *id) 2607{ 2608 struct wm8904_priv *wm8904; 2609 struct snd_soc_codec *codec; 2610 2611 wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL); 2612 if (wm8904 == NULL) 2613 return -ENOMEM; 2614 2615 codec = &wm8904->codec; 2616 codec->hw_write = (hw_write_t)i2c_master_send; 2617 2618 wm8904->devtype = id->driver_data; 2619 2620 i2c_set_clientdata(i2c, wm8904); 2621 codec->control_data = i2c; 2622 wm8904->pdata = i2c->dev.platform_data; 2623 2624 codec->dev = &i2c->dev; 2625 2626 return wm8904_register(wm8904, SND_SOC_I2C); 2627} 2628 2629static __devexit int wm8904_i2c_remove(struct i2c_client *client) 2630{ 2631 struct wm8904_priv *wm8904 = i2c_get_clientdata(client); 2632 wm8904_unregister(wm8904); 2633 return 0; 2634} 2635 2636static const struct i2c_device_id wm8904_i2c_id[] = { 2637 { "wm8904", WM8904 }, 2638 { "wm8912", WM8912 }, 2639 { } 2640}; 2641MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); 2642 2643static struct i2c_driver wm8904_i2c_driver = { 2644 .driver = { 2645 .name = "WM8904", 2646 .owner = THIS_MODULE, 2647 }, 2648 .probe = wm8904_i2c_probe, 2649 .remove = __devexit_p(wm8904_i2c_remove), 2650 .id_table = wm8904_i2c_id, 2651}; 2652#endif 2653 2654static int __init wm8904_modinit(void) 2655{ 2656 int ret; 2657#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2658 ret = i2c_add_driver(&wm8904_i2c_driver); 2659 if (ret != 0) { 2660 printk(KERN_ERR "Failed to register WM8904 I2C driver: %d\n", 2661 ret); 2662 } 2663#endif 2664 return 0; 2665} 2666module_init(wm8904_modinit); 2667 2668static void __exit wm8904_exit(void) 2669{ 2670#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2671 i2c_del_driver(&wm8904_i2c_driver); 2672#endif 2673} 2674module_exit(wm8904_exit); 2675 2676MODULE_DESCRIPTION("ASoC WM8904 driver"); 2677MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2678MODULE_LICENSE("GPL"); 2679