1/* 2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com> 9 * 10 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC 11 * codec model. 12 * 13 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org> 14 * Copyright 2005 Openedhand Ltd. 15 */ 16 17#include <linux/module.h> 18#include <linux/init.h> 19#include <linux/types.h> 20#include <linux/slab.h> 21#include <linux/errno.h> 22#include <linux/gpio.h> 23#include <linux/delay.h> 24#include <linux/i2c.h> 25#include <linux/workqueue.h> 26#include <sound/core.h> 27#include <sound/control.h> 28#include <sound/initval.h> 29#include <sound/soc.h> 30#include <sound/soc-dapm.h> 31#include <sound/tlv.h> 32#include <sound/uda1380.h> 33 34#include "uda1380.h" 35 36static struct snd_soc_codec *uda1380_codec; 37 38/* codec private data */ 39struct uda1380_priv { 40 struct snd_soc_codec codec; 41 u16 reg_cache[UDA1380_CACHEREGNUM]; 42 unsigned int dac_clk; 43 struct work_struct work; 44}; 45 46/* 47 * uda1380 register cache 48 */ 49static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = { 50 0x0502, 0x0000, 0x0000, 0x3f3f, 51 0x0202, 0x0000, 0x0000, 0x0000, 52 0x0000, 0x0000, 0x0000, 0x0000, 53 0x0000, 0x0000, 0x0000, 0x0000, 54 0x0000, 0xff00, 0x0000, 0x4800, 55 0x0000, 0x0000, 0x0000, 0x0000, 56 0x0000, 0x0000, 0x0000, 0x0000, 57 0x0000, 0x0000, 0x0000, 0x0000, 58 0x0000, 0x8000, 0x0002, 0x0000, 59}; 60 61static unsigned long uda1380_cache_dirty; 62 63/* 64 * read uda1380 register cache 65 */ 66static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec, 67 unsigned int reg) 68{ 69 u16 *cache = codec->reg_cache; 70 if (reg == UDA1380_RESET) 71 return 0; 72 if (reg >= UDA1380_CACHEREGNUM) 73 return -1; 74 return cache[reg]; 75} 76 77/* 78 * write uda1380 register cache 79 */ 80static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec, 81 u16 reg, unsigned int value) 82{ 83 u16 *cache = codec->reg_cache; 84 85 if (reg >= UDA1380_CACHEREGNUM) 86 return; 87 if ((reg >= 0x10) && (cache[reg] != value)) 88 set_bit(reg - 0x10, &uda1380_cache_dirty); 89 cache[reg] = value; 90} 91 92/* 93 * write to the UDA1380 register space 94 */ 95static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg, 96 unsigned int value) 97{ 98 u8 data[3]; 99 100 /* data is 101 * data[0] is register offset 102 * data[1] is MS byte 103 * data[2] is LS byte 104 */ 105 data[0] = reg; 106 data[1] = (value & 0xff00) >> 8; 107 data[2] = value & 0x00ff; 108 109 uda1380_write_reg_cache(codec, reg, value); 110 111 /* the interpolator & decimator regs must only be written when the 112 * codec DAI is active. 113 */ 114 if (!codec->active && (reg >= UDA1380_MVOL)) 115 return 0; 116 pr_debug("uda1380: hw write %x val %x\n", reg, value); 117 if (codec->hw_write(codec->control_data, data, 3) == 3) { 118 unsigned int val; 119 i2c_master_send(codec->control_data, data, 1); 120 i2c_master_recv(codec->control_data, data, 2); 121 val = (data[0]<<8) | data[1]; 122 if (val != value) { 123 pr_debug("uda1380: READ BACK VAL %x\n", 124 (data[0]<<8) | data[1]); 125 return -EIO; 126 } 127 if (reg >= 0x10) 128 clear_bit(reg - 0x10, &uda1380_cache_dirty); 129 return 0; 130 } else 131 return -EIO; 132} 133 134#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0) 135 136static void uda1380_flush_work(struct work_struct *work) 137{ 138 int bit, reg; 139 140 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) { 141 reg = 0x10 + bit; 142 pr_debug("uda1380: flush reg %x val %x:\n", reg, 143 uda1380_read_reg_cache(uda1380_codec, reg)); 144 uda1380_write(uda1380_codec, reg, 145 uda1380_read_reg_cache(uda1380_codec, reg)); 146 clear_bit(bit, &uda1380_cache_dirty); 147 } 148} 149 150/* declarations of ALSA reg_elem_REAL controls */ 151static const char *uda1380_deemp[] = { 152 "None", 153 "32kHz", 154 "44.1kHz", 155 "48kHz", 156 "96kHz", 157}; 158static const char *uda1380_input_sel[] = { 159 "Line", 160 "Mic + Line R", 161 "Line L", 162 "Mic", 163}; 164static const char *uda1380_output_sel[] = { 165 "DAC", 166 "Analog Mixer", 167}; 168static const char *uda1380_spf_mode[] = { 169 "Flat", 170 "Minimum1", 171 "Minimum2", 172 "Maximum" 173}; 174static const char *uda1380_capture_sel[] = { 175 "ADC", 176 "Digital Mixer" 177}; 178static const char *uda1380_sel_ns[] = { 179 "3rd-order", 180 "5th-order" 181}; 182static const char *uda1380_mix_control[] = { 183 "off", 184 "PCM only", 185 "before sound processing", 186 "after sound processing" 187}; 188static const char *uda1380_sdet_setting[] = { 189 "3200", 190 "4800", 191 "9600", 192 "19200" 193}; 194static const char *uda1380_os_setting[] = { 195 "single-speed", 196 "double-speed (no mixing)", 197 "quad-speed (no mixing)" 198}; 199 200static const struct soc_enum uda1380_deemp_enum[] = { 201 SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp), 202 SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp), 203}; 204static const struct soc_enum uda1380_input_sel_enum = 205 SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */ 206static const struct soc_enum uda1380_output_sel_enum = 207 SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */ 208static const struct soc_enum uda1380_spf_enum = 209 SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */ 210static const struct soc_enum uda1380_capture_sel_enum = 211 SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */ 212static const struct soc_enum uda1380_sel_ns_enum = 213 SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */ 214static const struct soc_enum uda1380_mix_enum = 215 SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */ 216static const struct soc_enum uda1380_sdet_enum = 217 SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */ 218static const struct soc_enum uda1380_os_enum = 219 SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */ 220 221/* 222 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB) 223 */ 224static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1); 225 226/* 227 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored), 228 * from -66 dB in 0.5 dB steps (2 dB steps, really) and 229 * from -52 dB in 0.25 dB steps 230 */ 231static const unsigned int mvol_tlv[] = { 232 TLV_DB_RANGE_HEAD(3), 233 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1), 234 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0), 235 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0), 236}; 237 238/* 239 * from -72 dB in 1.5 dB steps (6 dB steps really), 240 * from -66 dB in 0.75 dB steps (3 dB steps really), 241 * from -60 dB in 0.5 dB steps (2 dB steps really) and 242 * from -46 dB in 0.25 dB steps 243 */ 244static const unsigned int vc_tlv[] = { 245 TLV_DB_RANGE_HEAD(4), 246 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1), 247 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0), 248 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0), 249 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0), 250}; 251 252/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */ 253static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0); 254 255/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts 256 * off at 18 dB max) */ 257static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0); 258 259/* from -63 to 24 dB in 0.5 dB steps (-128...48) */ 260static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1); 261 262/* from 0 to 24 dB in 3 dB steps */ 263static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0); 264 265/* from 0 to 30 dB in 2 dB steps */ 266static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0); 267 268static const struct snd_kcontrol_new uda1380_snd_controls[] = { 269 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */ 270 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */ 271 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */ 272 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */ 273 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */ 274 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */ 275 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */ 276/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */ 277 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */ 278 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */ 279 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */ 280 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */ 281 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */ 282 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */ 283 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */ 284 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */ 285 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */ 286 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */ 287 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */ 288/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */ 289 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */ 290 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */ 291 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */ 292 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */ 293 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */ 294 SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */ 295 SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */ 296 /* -5.5, -8, -11.5, -14 dBFS */ 297 SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0), 298}; 299 300/* Input mux */ 301static const struct snd_kcontrol_new uda1380_input_mux_control = 302 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum); 303 304/* Output mux */ 305static const struct snd_kcontrol_new uda1380_output_mux_control = 306 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum); 307 308/* Capture mux */ 309static const struct snd_kcontrol_new uda1380_capture_mux_control = 310 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum); 311 312 313static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = { 314 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, 315 &uda1380_input_mux_control), 316 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0, 317 &uda1380_output_mux_control), 318 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, 319 &uda1380_capture_mux_control), 320 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0), 321 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0), 322 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0), 323 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0), 324 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0), 325 SND_SOC_DAPM_INPUT("VINM"), 326 SND_SOC_DAPM_INPUT("VINL"), 327 SND_SOC_DAPM_INPUT("VINR"), 328 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0), 329 SND_SOC_DAPM_OUTPUT("VOUTLHP"), 330 SND_SOC_DAPM_OUTPUT("VOUTRHP"), 331 SND_SOC_DAPM_OUTPUT("VOUTL"), 332 SND_SOC_DAPM_OUTPUT("VOUTR"), 333 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0), 334 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0), 335}; 336 337static const struct snd_soc_dapm_route audio_map[] = { 338 339 /* output mux */ 340 {"HeadPhone Driver", NULL, "Output Mux"}, 341 {"VOUTR", NULL, "Output Mux"}, 342 {"VOUTL", NULL, "Output Mux"}, 343 344 {"Analog Mixer", NULL, "VINR"}, 345 {"Analog Mixer", NULL, "VINL"}, 346 {"Analog Mixer", NULL, "DAC"}, 347 348 {"Output Mux", "DAC", "DAC"}, 349 {"Output Mux", "Analog Mixer", "Analog Mixer"}, 350 351 /* {"DAC", "Digital Mixer", "I2S" } */ 352 353 /* headphone driver */ 354 {"VOUTLHP", NULL, "HeadPhone Driver"}, 355 {"VOUTRHP", NULL, "HeadPhone Driver"}, 356 357 /* input mux */ 358 {"Left ADC", NULL, "Input Mux"}, 359 {"Input Mux", "Mic", "Mic LNA"}, 360 {"Input Mux", "Mic + Line R", "Mic LNA"}, 361 {"Input Mux", "Line L", "Left PGA"}, 362 {"Input Mux", "Line", "Left PGA"}, 363 364 /* right input */ 365 {"Right ADC", "Mic + Line R", "Right PGA"}, 366 {"Right ADC", "Line", "Right PGA"}, 367 368 /* inputs */ 369 {"Mic LNA", NULL, "VINM"}, 370 {"Left PGA", NULL, "VINL"}, 371 {"Right PGA", NULL, "VINR"}, 372}; 373 374static int uda1380_add_widgets(struct snd_soc_codec *codec) 375{ 376 snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets, 377 ARRAY_SIZE(uda1380_dapm_widgets)); 378 379 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 380 381 return 0; 382} 383 384static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai, 385 unsigned int fmt) 386{ 387 struct snd_soc_codec *codec = codec_dai->codec; 388 int iface; 389 390 /* set up DAI based upon fmt */ 391 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); 392 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK); 393 394 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 395 case SND_SOC_DAIFMT_I2S: 396 iface |= R01_SFORI_I2S | R01_SFORO_I2S; 397 break; 398 case SND_SOC_DAIFMT_LSB: 399 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16; 400 break; 401 case SND_SOC_DAIFMT_MSB: 402 iface |= R01_SFORI_MSB | R01_SFORO_MSB; 403 } 404 405 /* DATAI is slave only, so in single-link mode, this has to be slave */ 406 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) 407 return -EINVAL; 408 409 uda1380_write(codec, UDA1380_IFACE, iface); 410 411 return 0; 412} 413 414static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai, 415 unsigned int fmt) 416{ 417 struct snd_soc_codec *codec = codec_dai->codec; 418 int iface; 419 420 /* set up DAI based upon fmt */ 421 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); 422 iface &= ~R01_SFORI_MASK; 423 424 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 425 case SND_SOC_DAIFMT_I2S: 426 iface |= R01_SFORI_I2S; 427 break; 428 case SND_SOC_DAIFMT_LSB: 429 iface |= R01_SFORI_LSB16; 430 break; 431 case SND_SOC_DAIFMT_MSB: 432 iface |= R01_SFORI_MSB; 433 } 434 435 /* DATAI is slave only, so this has to be slave */ 436 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) 437 return -EINVAL; 438 439 uda1380_write(codec, UDA1380_IFACE, iface); 440 441 return 0; 442} 443 444static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai, 445 unsigned int fmt) 446{ 447 struct snd_soc_codec *codec = codec_dai->codec; 448 int iface; 449 450 /* set up DAI based upon fmt */ 451 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); 452 iface &= ~(R01_SIM | R01_SFORO_MASK); 453 454 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 455 case SND_SOC_DAIFMT_I2S: 456 iface |= R01_SFORO_I2S; 457 break; 458 case SND_SOC_DAIFMT_LSB: 459 iface |= R01_SFORO_LSB16; 460 break; 461 case SND_SOC_DAIFMT_MSB: 462 iface |= R01_SFORO_MSB; 463 } 464 465 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM) 466 iface |= R01_SIM; 467 468 uda1380_write(codec, UDA1380_IFACE, iface); 469 470 return 0; 471} 472 473static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd, 474 struct snd_soc_dai *dai) 475{ 476 struct snd_soc_pcm_runtime *rtd = substream->private_data; 477 struct snd_soc_device *socdev = rtd->socdev; 478 struct snd_soc_codec *codec = socdev->card->codec; 479 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec); 480 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER); 481 482 switch (cmd) { 483 case SNDRV_PCM_TRIGGER_START: 484 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 485 uda1380_write_reg_cache(codec, UDA1380_MIXER, 486 mixer & ~R14_SILENCE); 487 schedule_work(&uda1380->work); 488 break; 489 case SNDRV_PCM_TRIGGER_STOP: 490 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 491 uda1380_write_reg_cache(codec, UDA1380_MIXER, 492 mixer | R14_SILENCE); 493 schedule_work(&uda1380->work); 494 break; 495 } 496 return 0; 497} 498 499static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream, 500 struct snd_pcm_hw_params *params, 501 struct snd_soc_dai *dai) 502{ 503 struct snd_soc_pcm_runtime *rtd = substream->private_data; 504 struct snd_soc_device *socdev = rtd->socdev; 505 struct snd_soc_codec *codec = socdev->card->codec; 506 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK); 507 508 /* set WSPLL power and divider if running from this clock */ 509 if (clk & R00_DAC_CLK) { 510 int rate = params_rate(params); 511 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM); 512 clk &= ~0x3; /* clear SEL_LOOP_DIV */ 513 switch (rate) { 514 case 6250 ... 12500: 515 clk |= 0x0; 516 break; 517 case 12501 ... 25000: 518 clk |= 0x1; 519 break; 520 case 25001 ... 50000: 521 clk |= 0x2; 522 break; 523 case 50001 ... 100000: 524 clk |= 0x3; 525 break; 526 } 527 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm); 528 } 529 530 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 531 clk |= R00_EN_DAC | R00_EN_INT; 532 else 533 clk |= R00_EN_ADC | R00_EN_DEC; 534 535 uda1380_write(codec, UDA1380_CLK, clk); 536 return 0; 537} 538 539static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream, 540 struct snd_soc_dai *dai) 541{ 542 struct snd_soc_pcm_runtime *rtd = substream->private_data; 543 struct snd_soc_device *socdev = rtd->socdev; 544 struct snd_soc_codec *codec = socdev->card->codec; 545 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK); 546 547 /* shut down WSPLL power if running from this clock */ 548 if (clk & R00_DAC_CLK) { 549 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM); 550 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm); 551 } 552 553 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 554 clk &= ~(R00_EN_DAC | R00_EN_INT); 555 else 556 clk &= ~(R00_EN_ADC | R00_EN_DEC); 557 558 uda1380_write(codec, UDA1380_CLK, clk); 559} 560 561static int uda1380_set_bias_level(struct snd_soc_codec *codec, 562 enum snd_soc_bias_level level) 563{ 564 int pm = uda1380_read_reg_cache(codec, UDA1380_PM); 565 566 switch (level) { 567 case SND_SOC_BIAS_ON: 568 case SND_SOC_BIAS_PREPARE: 569 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm); 570 break; 571 case SND_SOC_BIAS_STANDBY: 572 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS); 573 break; 574 case SND_SOC_BIAS_OFF: 575 uda1380_write(codec, UDA1380_PM, 0x0); 576 break; 577 } 578 codec->bias_level = level; 579 return 0; 580} 581 582#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 583 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ 584 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 585 586static struct snd_soc_dai_ops uda1380_dai_ops = { 587 .hw_params = uda1380_pcm_hw_params, 588 .shutdown = uda1380_pcm_shutdown, 589 .trigger = uda1380_trigger, 590 .set_fmt = uda1380_set_dai_fmt_both, 591}; 592 593static struct snd_soc_dai_ops uda1380_dai_ops_playback = { 594 .hw_params = uda1380_pcm_hw_params, 595 .shutdown = uda1380_pcm_shutdown, 596 .trigger = uda1380_trigger, 597 .set_fmt = uda1380_set_dai_fmt_playback, 598}; 599 600static struct snd_soc_dai_ops uda1380_dai_ops_capture = { 601 .hw_params = uda1380_pcm_hw_params, 602 .shutdown = uda1380_pcm_shutdown, 603 .trigger = uda1380_trigger, 604 .set_fmt = uda1380_set_dai_fmt_capture, 605}; 606 607struct snd_soc_dai uda1380_dai[] = { 608{ 609 .name = "UDA1380", 610 .playback = { 611 .stream_name = "Playback", 612 .channels_min = 1, 613 .channels_max = 2, 614 .rates = UDA1380_RATES, 615 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 616 .capture = { 617 .stream_name = "Capture", 618 .channels_min = 1, 619 .channels_max = 2, 620 .rates = UDA1380_RATES, 621 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 622 .ops = &uda1380_dai_ops, 623}, 624{ /* playback only - dual interface */ 625 .name = "UDA1380", 626 .playback = { 627 .stream_name = "Playback", 628 .channels_min = 1, 629 .channels_max = 2, 630 .rates = UDA1380_RATES, 631 .formats = SNDRV_PCM_FMTBIT_S16_LE, 632 }, 633 .ops = &uda1380_dai_ops_playback, 634}, 635{ /* capture only - dual interface*/ 636 .name = "UDA1380", 637 .capture = { 638 .stream_name = "Capture", 639 .channels_min = 1, 640 .channels_max = 2, 641 .rates = UDA1380_RATES, 642 .formats = SNDRV_PCM_FMTBIT_S16_LE, 643 }, 644 .ops = &uda1380_dai_ops_capture, 645}, 646}; 647EXPORT_SYMBOL_GPL(uda1380_dai); 648 649static int uda1380_suspend(struct platform_device *pdev, pm_message_t state) 650{ 651 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 652 struct snd_soc_codec *codec = socdev->card->codec; 653 654 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF); 655 return 0; 656} 657 658static int uda1380_resume(struct platform_device *pdev) 659{ 660 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 661 struct snd_soc_codec *codec = socdev->card->codec; 662 int i; 663 u8 data[2]; 664 u16 *cache = codec->reg_cache; 665 666 /* Sync reg_cache with the hardware */ 667 for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) { 668 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); 669 data[1] = cache[i] & 0x00ff; 670 codec->hw_write(codec->control_data, data, 2); 671 } 672 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 673 return 0; 674} 675 676static int uda1380_probe(struct platform_device *pdev) 677{ 678 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 679 struct snd_soc_codec *codec; 680 struct uda1380_platform_data *pdata; 681 int ret = 0; 682 683 if (uda1380_codec == NULL) { 684 dev_err(&pdev->dev, "Codec device not registered\n"); 685 return -ENODEV; 686 } 687 688 socdev->card->codec = uda1380_codec; 689 codec = uda1380_codec; 690 pdata = codec->dev->platform_data; 691 692 /* register pcms */ 693 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 694 if (ret < 0) { 695 dev_err(codec->dev, "failed to create pcms: %d\n", ret); 696 goto pcm_err; 697 } 698 699 /* power on device */ 700 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 701 /* set clock input */ 702 switch (pdata->dac_clk) { 703 case UDA1380_DAC_CLK_SYSCLK: 704 uda1380_write(codec, UDA1380_CLK, 0); 705 break; 706 case UDA1380_DAC_CLK_WSPLL: 707 uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK); 708 break; 709 } 710 711 snd_soc_add_controls(codec, uda1380_snd_controls, 712 ARRAY_SIZE(uda1380_snd_controls)); 713 uda1380_add_widgets(codec); 714 715 return ret; 716 717pcm_err: 718 return ret; 719} 720 721/* power down chip */ 722static int uda1380_remove(struct platform_device *pdev) 723{ 724 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 725 struct snd_soc_codec *codec = socdev->card->codec; 726 727 if (codec->control_data) 728 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF); 729 730 snd_soc_free_pcms(socdev); 731 snd_soc_dapm_free(socdev); 732 733 return 0; 734} 735 736struct snd_soc_codec_device soc_codec_dev_uda1380 = { 737 .probe = uda1380_probe, 738 .remove = uda1380_remove, 739 .suspend = uda1380_suspend, 740 .resume = uda1380_resume, 741}; 742EXPORT_SYMBOL_GPL(soc_codec_dev_uda1380); 743 744static int uda1380_register(struct uda1380_priv *uda1380) 745{ 746 int ret, i; 747 struct snd_soc_codec *codec = &uda1380->codec; 748 struct uda1380_platform_data *pdata = codec->dev->platform_data; 749 750 if (uda1380_codec) { 751 dev_err(codec->dev, "Another UDA1380 is registered\n"); 752 return -EINVAL; 753 } 754 755 if (!pdata || !pdata->gpio_power || !pdata->gpio_reset) 756 return -EINVAL; 757 758 ret = gpio_request(pdata->gpio_power, "uda1380 power"); 759 if (ret) 760 goto err_out; 761 ret = gpio_request(pdata->gpio_reset, "uda1380 reset"); 762 if (ret) 763 goto err_gpio; 764 765 gpio_direction_output(pdata->gpio_power, 1); 766 767 /* we may need to have the clock running here - pH5 */ 768 gpio_direction_output(pdata->gpio_reset, 1); 769 udelay(5); 770 gpio_set_value(pdata->gpio_reset, 0); 771 772 mutex_init(&codec->mutex); 773 INIT_LIST_HEAD(&codec->dapm_widgets); 774 INIT_LIST_HEAD(&codec->dapm_paths); 775 776 snd_soc_codec_set_drvdata(codec, uda1380); 777 codec->name = "UDA1380"; 778 codec->owner = THIS_MODULE; 779 codec->read = uda1380_read_reg_cache; 780 codec->write = uda1380_write; 781 codec->bias_level = SND_SOC_BIAS_OFF; 782 codec->set_bias_level = uda1380_set_bias_level; 783 codec->dai = uda1380_dai; 784 codec->num_dai = ARRAY_SIZE(uda1380_dai); 785 codec->reg_cache_size = ARRAY_SIZE(uda1380_reg); 786 codec->reg_cache = &uda1380->reg_cache; 787 codec->reg_cache_step = 1; 788 789 memcpy(codec->reg_cache, uda1380_reg, sizeof(uda1380_reg)); 790 791 ret = uda1380_reset(codec); 792 if (ret < 0) { 793 dev_err(codec->dev, "Failed to issue reset\n"); 794 goto err_reset; 795 } 796 797 INIT_WORK(&uda1380->work, uda1380_flush_work); 798 799 for (i = 0; i < ARRAY_SIZE(uda1380_dai); i++) 800 uda1380_dai[i].dev = codec->dev; 801 802 uda1380_codec = codec; 803 804 ret = snd_soc_register_codec(codec); 805 if (ret != 0) { 806 dev_err(codec->dev, "Failed to register codec: %d\n", ret); 807 goto err_reset; 808 } 809 810 ret = snd_soc_register_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai)); 811 if (ret != 0) { 812 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); 813 goto err_dai; 814 } 815 816 return 0; 817 818err_dai: 819 snd_soc_unregister_codec(codec); 820err_reset: 821 gpio_set_value(pdata->gpio_power, 0); 822 gpio_free(pdata->gpio_reset); 823err_gpio: 824 gpio_free(pdata->gpio_power); 825err_out: 826 return ret; 827} 828 829static void uda1380_unregister(struct uda1380_priv *uda1380) 830{ 831 struct snd_soc_codec *codec = &uda1380->codec; 832 struct uda1380_platform_data *pdata = codec->dev->platform_data; 833 834 snd_soc_unregister_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai)); 835 snd_soc_unregister_codec(&uda1380->codec); 836 837 gpio_set_value(pdata->gpio_power, 0); 838 gpio_free(pdata->gpio_reset); 839 gpio_free(pdata->gpio_power); 840 841 kfree(uda1380); 842 uda1380_codec = NULL; 843} 844 845#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 846static __devinit int uda1380_i2c_probe(struct i2c_client *i2c, 847 const struct i2c_device_id *id) 848{ 849 struct uda1380_priv *uda1380; 850 struct snd_soc_codec *codec; 851 int ret; 852 853 uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL); 854 if (uda1380 == NULL) 855 return -ENOMEM; 856 857 codec = &uda1380->codec; 858 codec->hw_write = (hw_write_t)i2c_master_send; 859 860 i2c_set_clientdata(i2c, uda1380); 861 codec->control_data = i2c; 862 863 codec->dev = &i2c->dev; 864 865 ret = uda1380_register(uda1380); 866 if (ret != 0) 867 kfree(uda1380); 868 869 return ret; 870} 871 872static int __devexit uda1380_i2c_remove(struct i2c_client *i2c) 873{ 874 struct uda1380_priv *uda1380 = i2c_get_clientdata(i2c); 875 uda1380_unregister(uda1380); 876 return 0; 877} 878 879static const struct i2c_device_id uda1380_i2c_id[] = { 880 { "uda1380", 0 }, 881 { } 882}; 883MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id); 884 885static struct i2c_driver uda1380_i2c_driver = { 886 .driver = { 887 .name = "UDA1380 I2C Codec", 888 .owner = THIS_MODULE, 889 }, 890 .probe = uda1380_i2c_probe, 891 .remove = __devexit_p(uda1380_i2c_remove), 892 .id_table = uda1380_i2c_id, 893}; 894#endif 895 896static int __init uda1380_modinit(void) 897{ 898 int ret; 899#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 900 ret = i2c_add_driver(&uda1380_i2c_driver); 901 if (ret != 0) 902 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret); 903#endif 904 return 0; 905} 906module_init(uda1380_modinit); 907 908static void __exit uda1380_exit(void) 909{ 910#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 911 i2c_del_driver(&uda1380_i2c_driver); 912#endif 913} 914module_exit(uda1380_exit); 915 916MODULE_AUTHOR("Giorgio Padrin"); 917MODULE_DESCRIPTION("Audio support for codec Philips UDA1380"); 918MODULE_LICENSE("GPL"); 919