1/* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 is as follows: 19 * aic32 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35#include <linux/module.h> 36#include <linux/moduleparam.h> 37#include <linux/init.h> 38#include <linux/delay.h> 39#include <linux/pm.h> 40#include <linux/i2c.h> 41#include <linux/gpio.h> 42#include <linux/regulator/consumer.h> 43#include <linux/platform_device.h> 44#include <linux/slab.h> 45#include <sound/core.h> 46#include <sound/pcm.h> 47#include <sound/pcm_params.h> 48#include <sound/soc.h> 49#include <sound/soc-dapm.h> 50#include <sound/initval.h> 51#include <sound/tlv.h> 52#include <sound/tlv320aic3x.h> 53 54#include "tlv320aic3x.h" 55 56#define AIC3X_NUM_SUPPLIES 4 57static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 58 "IOVDD", /* I/O Voltage */ 59 "DVDD", /* Digital Core Voltage */ 60 "AVDD", /* Analog DAC Voltage */ 61 "DRVDD", /* ADC Analog and Output Driver Voltage */ 62}; 63 64/* codec private data */ 65struct aic3x_priv { 66 struct snd_soc_codec codec; 67 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 68 unsigned int sysclk; 69 int master; 70 int gpio_reset; 71}; 72 73/* 74 * AIC3X register cache 75 * We can't read the AIC3X register space when we are 76 * using 2 wire for device control, so we cache them instead. 77 * There is no point in caching the reset register 78 */ 79static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 80 0x00, 0x00, 0x00, 0x10, /* 0 */ 81 0x04, 0x00, 0x00, 0x00, /* 4 */ 82 0x00, 0x00, 0x00, 0x01, /* 8 */ 83 0x00, 0x00, 0x00, 0x80, /* 12 */ 84 0x80, 0xff, 0xff, 0x78, /* 16 */ 85 0x78, 0x78, 0x78, 0x78, /* 20 */ 86 0x78, 0x00, 0x00, 0xfe, /* 24 */ 87 0x00, 0x00, 0xfe, 0x00, /* 28 */ 88 0x18, 0x18, 0x00, 0x00, /* 32 */ 89 0x00, 0x00, 0x00, 0x00, /* 36 */ 90 0x00, 0x00, 0x00, 0x80, /* 40 */ 91 0x80, 0x00, 0x00, 0x00, /* 44 */ 92 0x00, 0x00, 0x00, 0x04, /* 48 */ 93 0x00, 0x00, 0x00, 0x00, /* 52 */ 94 0x00, 0x00, 0x04, 0x00, /* 56 */ 95 0x00, 0x00, 0x00, 0x00, /* 60 */ 96 0x00, 0x04, 0x00, 0x00, /* 64 */ 97 0x00, 0x00, 0x00, 0x00, /* 68 */ 98 0x04, 0x00, 0x00, 0x00, /* 72 */ 99 0x00, 0x00, 0x00, 0x00, /* 76 */ 100 0x00, 0x00, 0x00, 0x00, /* 80 */ 101 0x00, 0x00, 0x00, 0x00, /* 84 */ 102 0x00, 0x00, 0x00, 0x00, /* 88 */ 103 0x00, 0x00, 0x00, 0x00, /* 92 */ 104 0x00, 0x00, 0x00, 0x00, /* 96 */ 105 0x00, 0x00, 0x02, /* 100 */ 106}; 107 108/* 109 * read aic3x register cache 110 */ 111static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec, 112 unsigned int reg) 113{ 114 u8 *cache = codec->reg_cache; 115 if (reg >= AIC3X_CACHEREGNUM) 116 return -1; 117 return cache[reg]; 118} 119 120/* 121 * write aic3x register cache 122 */ 123static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec, 124 u8 reg, u8 value) 125{ 126 u8 *cache = codec->reg_cache; 127 if (reg >= AIC3X_CACHEREGNUM) 128 return; 129 cache[reg] = value; 130} 131 132/* 133 * write to the aic3x register space 134 */ 135static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg, 136 unsigned int value) 137{ 138 u8 data[2]; 139 140 /* data is 141 * D15..D8 aic3x register offset 142 * D7...D0 register data 143 */ 144 data[0] = reg & 0xff; 145 data[1] = value & 0xff; 146 147 aic3x_write_reg_cache(codec, data[0], data[1]); 148 if (codec->hw_write(codec->control_data, data, 2) == 2) 149 return 0; 150 else 151 return -EIO; 152} 153 154/* 155 * read from the aic3x register space 156 */ 157static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, 158 u8 *value) 159{ 160 *value = reg & 0xff; 161 162 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]); 163 164 aic3x_write_reg_cache(codec, reg, *value); 165 return 0; 166} 167 168#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 169{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 170 .info = snd_soc_info_volsw, \ 171 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ 172 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } 173 174/* 175 * All input lines are connected when !0xf and disconnected with 0xf bit field, 176 * so we have to use specific dapm_put call for input mixer 177 */ 178static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 179 struct snd_ctl_elem_value *ucontrol) 180{ 181 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 182 struct soc_mixer_control *mc = 183 (struct soc_mixer_control *)kcontrol->private_value; 184 unsigned int reg = mc->reg; 185 unsigned int shift = mc->shift; 186 int max = mc->max; 187 unsigned int mask = (1 << fls(max)) - 1; 188 unsigned int invert = mc->invert; 189 unsigned short val, val_mask; 190 int ret; 191 struct snd_soc_dapm_path *path; 192 int found = 0; 193 194 val = (ucontrol->value.integer.value[0] & mask); 195 196 mask = 0xf; 197 if (val) 198 val = mask; 199 200 if (invert) 201 val = mask - val; 202 val_mask = mask << shift; 203 val = val << shift; 204 205 mutex_lock(&widget->codec->mutex); 206 207 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 208 /* find dapm widget path assoc with kcontrol */ 209 list_for_each_entry(path, &widget->codec->dapm_paths, list) { 210 if (path->kcontrol != kcontrol) 211 continue; 212 213 /* found, now check type */ 214 found = 1; 215 if (val) 216 /* new connection */ 217 path->connect = invert ? 0 : 1; 218 else 219 /* old connection must be powered down */ 220 path->connect = invert ? 1 : 0; 221 break; 222 } 223 224 if (found) 225 snd_soc_dapm_sync(widget->codec); 226 } 227 228 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); 229 230 mutex_unlock(&widget->codec->mutex); 231 return ret; 232} 233 234static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 235static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 236static const char *aic3x_left_hpcom_mux[] = 237 { "differential of HPLOUT", "constant VCM", "single-ended" }; 238static const char *aic3x_right_hpcom_mux[] = 239 { "differential of HPROUT", "constant VCM", "single-ended", 240 "differential of HPLCOM", "external feedback" }; 241static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 242static const char *aic3x_adc_hpf[] = 243 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 244 245#define LDAC_ENUM 0 246#define RDAC_ENUM 1 247#define LHPCOM_ENUM 2 248#define RHPCOM_ENUM 3 249#define LINE1L_ENUM 4 250#define LINE1R_ENUM 5 251#define LINE2L_ENUM 6 252#define LINE2R_ENUM 7 253#define ADC_HPF_ENUM 8 254 255static const struct soc_enum aic3x_enum[] = { 256 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 257 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 258 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 259 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 260 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 261 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 262 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 263 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 264 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 265}; 266 267/* 268 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 269 */ 270static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 271/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 272static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 273/* 274 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 275 * Step size is approximately 0.5 dB over most of the scale but increasing 276 * near the very low levels. 277 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 278 * but having increasing dB difference below that (and where it doesn't count 279 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 280 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 281 */ 282static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 283 284static const struct snd_kcontrol_new aic3x_snd_controls[] = { 285 /* Output */ 286 SOC_DOUBLE_R_TLV("PCM Playback Volume", 287 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 288 289 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 290 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 291 0, 118, 1, output_stage_tlv), 292 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0), 293 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0), 294 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume", 295 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL, 296 0, 118, 1, output_stage_tlv), 297 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume", 298 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 299 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume", 300 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 301 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume", 302 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL, 303 0, 118, 1, output_stage_tlv), 304 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume", 305 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL, 306 0, 118, 1, output_stage_tlv), 307 308 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 309 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 310 0, 118, 1, output_stage_tlv), 311 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 312 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume", 313 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 314 0, 118, 1, output_stage_tlv), 315 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume", 316 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 317 0, 118, 1, output_stage_tlv), 318 319 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 320 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 321 0, 118, 1, output_stage_tlv), 322 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 323 0x01, 0), 324 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume", 325 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 326 0, 118, 1, output_stage_tlv), 327 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume", 328 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 329 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume", 330 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 331 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume", 332 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 333 0, 118, 1, output_stage_tlv), 334 335 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 336 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 337 0, 118, 1, output_stage_tlv), 338 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 339 0x01, 0), 340 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume", 341 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 342 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume", 343 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 344 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume", 345 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 346 0, 118, 1, output_stage_tlv), 347 348 /* 349 * Note: enable Automatic input Gain Controller with care. It can 350 * adjust PGA to max value when ADC is on and will never go back. 351 */ 352 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 353 354 /* Input */ 355 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 356 0, 119, 0, adc_tlv), 357 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 358 359 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 360}; 361 362/* Left DAC Mux */ 363static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 364SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 365 366/* Right DAC Mux */ 367static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 368SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 369 370/* Left HPCOM Mux */ 371static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 372SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 373 374/* Right HPCOM Mux */ 375static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 376SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 377 378/* Left DAC_L1 Mixer */ 379static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = { 380 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 381 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 382 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 383 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 384 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 385}; 386 387/* Right DAC_R1 Mixer */ 388static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = { 389 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 390 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 391 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 392 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 393 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 394}; 395 396/* Left PGA Mixer */ 397static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 398 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 399 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 400 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 401 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 402 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 403}; 404 405/* Right PGA Mixer */ 406static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 407 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 408 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 409 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 410 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 411 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 412}; 413 414/* Left Line1 Mux */ 415static const struct snd_kcontrol_new aic3x_left_line1_mux_controls = 416SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]); 417 418/* Right Line1 Mux */ 419static const struct snd_kcontrol_new aic3x_right_line1_mux_controls = 420SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]); 421 422/* Left Line2 Mux */ 423static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 424SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 425 426/* Right Line2 Mux */ 427static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 428SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 429 430/* Left PGA Bypass Mixer */ 431static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = { 432 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 433 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 434 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 435 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 436 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 437 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 438 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 439}; 440 441/* Right PGA Bypass Mixer */ 442static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = { 443 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 444 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 445 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 446 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 447 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 448 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 449 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 450}; 451 452/* Left Line2 Bypass Mixer */ 453static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = { 454 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 455 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 456 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 457 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 458 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 459}; 460 461/* Right Line2 Bypass Mixer */ 462static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = { 463 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 464 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 465 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 466 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 467 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 468}; 469 470static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 471 /* Left DAC to Left Outputs */ 472 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 473 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 474 &aic3x_left_dac_mux_controls), 475 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0, 476 &aic3x_left_dac_mixer_controls[0], 477 ARRAY_SIZE(aic3x_left_dac_mixer_controls)), 478 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 479 &aic3x_left_hpcom_mux_controls), 480 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 481 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 482 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 483 484 /* Right DAC to Right Outputs */ 485 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 486 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 487 &aic3x_right_dac_mux_controls), 488 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0, 489 &aic3x_right_dac_mixer_controls[0], 490 ARRAY_SIZE(aic3x_right_dac_mixer_controls)), 491 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 492 &aic3x_right_hpcom_mux_controls), 493 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 494 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 495 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 496 497 /* Mono Output */ 498 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 499 500 /* Inputs to Left ADC */ 501 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 502 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 503 &aic3x_left_pga_mixer_controls[0], 504 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 505 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 506 &aic3x_left_line1_mux_controls), 507 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 508 &aic3x_left_line1_mux_controls), 509 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 510 &aic3x_left_line2_mux_controls), 511 512 /* Inputs to Right ADC */ 513 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 514 LINE1R_2_RADC_CTRL, 2, 0), 515 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 516 &aic3x_right_pga_mixer_controls[0], 517 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 518 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 519 &aic3x_right_line1_mux_controls), 520 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 521 &aic3x_right_line1_mux_controls), 522 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 523 &aic3x_right_line2_mux_controls), 524 525 /* 526 * Not a real mic bias widget but similar function. This is for dynamic 527 * control of GPIO1 digital mic modulator clock output function when 528 * using digital mic. 529 */ 530 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 531 AIC3X_GPIO1_REG, 4, 0xf, 532 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 533 AIC3X_GPIO1_FUNC_DISABLED), 534 535 /* 536 * Also similar function like mic bias. Selects digital mic with 537 * configurable oversampling rate instead of ADC converter. 538 */ 539 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 540 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 541 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 542 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 543 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 544 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 545 546 /* Mic Bias */ 547 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", 548 MICBIAS_CTRL, 6, 3, 1, 0), 549 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", 550 MICBIAS_CTRL, 6, 3, 2, 0), 551 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", 552 MICBIAS_CTRL, 6, 3, 3, 0), 553 554 /* Left PGA to Left Output bypass */ 555 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, 556 &aic3x_left_pga_bp_mixer_controls[0], 557 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)), 558 559 /* Right PGA to Right Output bypass */ 560 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, 561 &aic3x_right_pga_bp_mixer_controls[0], 562 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)), 563 564 /* Left Line2 to Left Output bypass */ 565 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, 566 &aic3x_left_line2_bp_mixer_controls[0], 567 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)), 568 569 /* Right Line2 to Right Output bypass */ 570 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, 571 &aic3x_right_line2_bp_mixer_controls[0], 572 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)), 573 574 SND_SOC_DAPM_OUTPUT("LLOUT"), 575 SND_SOC_DAPM_OUTPUT("RLOUT"), 576 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 577 SND_SOC_DAPM_OUTPUT("HPLOUT"), 578 SND_SOC_DAPM_OUTPUT("HPROUT"), 579 SND_SOC_DAPM_OUTPUT("HPLCOM"), 580 SND_SOC_DAPM_OUTPUT("HPRCOM"), 581 582 SND_SOC_DAPM_INPUT("MIC3L"), 583 SND_SOC_DAPM_INPUT("MIC3R"), 584 SND_SOC_DAPM_INPUT("LINE1L"), 585 SND_SOC_DAPM_INPUT("LINE1R"), 586 SND_SOC_DAPM_INPUT("LINE2L"), 587 SND_SOC_DAPM_INPUT("LINE2R"), 588}; 589 590static const struct snd_soc_dapm_route intercon[] = { 591 /* Left Output */ 592 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 593 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 594 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 595 596 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"}, 597 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"}, 598 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"}, 599 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"}, 600 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"}, 601 {"Left Line Out", NULL, "Left DAC Mux"}, 602 {"Left HP Out", NULL, "Left DAC Mux"}, 603 604 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"}, 605 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"}, 606 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"}, 607 608 {"Left Line Out", NULL, "Left DAC_L1 Mixer"}, 609 {"Mono Out", NULL, "Left DAC_L1 Mixer"}, 610 {"Left HP Out", NULL, "Left DAC_L1 Mixer"}, 611 {"Left HP Com", NULL, "Left HPCOM Mux"}, 612 613 {"LLOUT", NULL, "Left Line Out"}, 614 {"LLOUT", NULL, "Left Line Out"}, 615 {"HPLOUT", NULL, "Left HP Out"}, 616 {"HPLCOM", NULL, "Left HP Com"}, 617 618 /* Right Output */ 619 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 620 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 621 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 622 623 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"}, 624 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"}, 625 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"}, 626 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"}, 627 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"}, 628 {"Right Line Out", NULL, "Right DAC Mux"}, 629 {"Right HP Out", NULL, "Right DAC Mux"}, 630 631 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"}, 632 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"}, 633 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"}, 634 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"}, 635 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"}, 636 637 {"Right Line Out", NULL, "Right DAC_R1 Mixer"}, 638 {"Mono Out", NULL, "Right DAC_R1 Mixer"}, 639 {"Right HP Out", NULL, "Right DAC_R1 Mixer"}, 640 {"Right HP Com", NULL, "Right HPCOM Mux"}, 641 642 {"RLOUT", NULL, "Right Line Out"}, 643 {"RLOUT", NULL, "Right Line Out"}, 644 {"HPROUT", NULL, "Right HP Out"}, 645 {"HPRCOM", NULL, "Right HP Com"}, 646 647 /* Mono Output */ 648 {"MONO_LOUT", NULL, "Mono Out"}, 649 {"MONO_LOUT", NULL, "Mono Out"}, 650 651 /* Left Input */ 652 {"Left Line1L Mux", "single-ended", "LINE1L"}, 653 {"Left Line1L Mux", "differential", "LINE1L"}, 654 655 {"Left Line2L Mux", "single-ended", "LINE2L"}, 656 {"Left Line2L Mux", "differential", "LINE2L"}, 657 658 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 659 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 660 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 661 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 662 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 663 664 {"Left ADC", NULL, "Left PGA Mixer"}, 665 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 666 667 /* Right Input */ 668 {"Right Line1R Mux", "single-ended", "LINE1R"}, 669 {"Right Line1R Mux", "differential", "LINE1R"}, 670 671 {"Right Line2R Mux", "single-ended", "LINE2R"}, 672 {"Right Line2R Mux", "differential", "LINE2R"}, 673 674 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 675 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 676 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 677 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 678 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 679 680 {"Right ADC", NULL, "Right PGA Mixer"}, 681 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 682 683 /* Left PGA Bypass */ 684 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"}, 685 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"}, 686 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"}, 687 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"}, 688 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"}, 689 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"}, 690 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"}, 691 692 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"}, 693 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"}, 694 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"}, 695 696 {"Left Line Out", NULL, "Left PGA Bypass Mixer"}, 697 {"Mono Out", NULL, "Left PGA Bypass Mixer"}, 698 {"Left HP Out", NULL, "Left PGA Bypass Mixer"}, 699 700 /* Right PGA Bypass */ 701 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"}, 702 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"}, 703 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"}, 704 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"}, 705 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"}, 706 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"}, 707 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"}, 708 709 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"}, 710 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"}, 711 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"}, 712 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"}, 713 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"}, 714 715 {"Right Line Out", NULL, "Right PGA Bypass Mixer"}, 716 {"Mono Out", NULL, "Right PGA Bypass Mixer"}, 717 {"Right HP Out", NULL, "Right PGA Bypass Mixer"}, 718 719 /* Left Line2 Bypass */ 720 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"}, 721 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"}, 722 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"}, 723 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"}, 724 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"}, 725 726 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"}, 727 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"}, 728 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"}, 729 730 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"}, 731 {"Mono Out", NULL, "Left Line2 Bypass Mixer"}, 732 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"}, 733 734 /* Right Line2 Bypass */ 735 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"}, 736 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"}, 737 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"}, 738 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"}, 739 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"}, 740 741 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"}, 742 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"}, 743 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"}, 744 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"}, 745 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"}, 746 747 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"}, 748 {"Mono Out", NULL, "Right Line2 Bypass Mixer"}, 749 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"}, 750 751 /* 752 * Logical path between digital mic enable and GPIO1 modulator clock 753 * output function 754 */ 755 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 756 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 757 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 758}; 759 760static int aic3x_add_widgets(struct snd_soc_codec *codec) 761{ 762 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, 763 ARRAY_SIZE(aic3x_dapm_widgets)); 764 765 /* set up audio path interconnects */ 766 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 767 768 return 0; 769} 770 771static int aic3x_hw_params(struct snd_pcm_substream *substream, 772 struct snd_pcm_hw_params *params, 773 struct snd_soc_dai *dai) 774{ 775 struct snd_soc_pcm_runtime *rtd = substream->private_data; 776 struct snd_soc_device *socdev = rtd->socdev; 777 struct snd_soc_codec *codec = socdev->card->codec; 778 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 779 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 780 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 781 u16 d, pll_d = 1; 782 u8 reg; 783 int clk; 784 785 /* select data word length */ 786 data = 787 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 788 switch (params_format(params)) { 789 case SNDRV_PCM_FORMAT_S16_LE: 790 break; 791 case SNDRV_PCM_FORMAT_S20_3LE: 792 data |= (0x01 << 4); 793 break; 794 case SNDRV_PCM_FORMAT_S24_LE: 795 data |= (0x02 << 4); 796 break; 797 case SNDRV_PCM_FORMAT_S32_LE: 798 data |= (0x03 << 4); 799 break; 800 } 801 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data); 802 803 /* Fsref can be 44100 or 48000 */ 804 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 805 806 /* Try to find a value for Q which allows us to bypass the PLL and 807 * generate CODEC_CLK directly. */ 808 for (pll_q = 2; pll_q < 18; pll_q++) 809 if (aic3x->sysclk / (128 * pll_q) == fsref) { 810 bypass_pll = 1; 811 break; 812 } 813 814 if (bypass_pll) { 815 pll_q &= 0xf; 816 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 817 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 818 /* disable PLL if it is bypassed */ 819 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 820 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE); 821 822 } else { 823 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 824 /* enable PLL when it is used */ 825 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 826 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE); 827 } 828 829 /* Route Left DAC to left channel input and 830 * right DAC to right channel input */ 831 data = (LDAC2LCH | RDAC2RCH); 832 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 833 if (params_rate(params) >= 64000) 834 data |= DUAL_RATE_MODE; 835 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 836 837 /* codec sample rate select */ 838 data = (fsref * 20) / params_rate(params); 839 if (params_rate(params) < 64000) 840 data /= 2; 841 data /= 5; 842 data -= 2; 843 data |= (data << 4); 844 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 845 846 if (bypass_pll) 847 return 0; 848 849 /* Use PLL, compute apropriate setup for j, d, r and p, the closest 850 * one wins the game. Try with d==0 first, next with d!=0. 851 * Constraints for j are according to the datasheet. 852 * The sysclk is divided by 1000 to prevent integer overflows. 853 */ 854 855 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 856 857 for (r = 1; r <= 16; r++) 858 for (p = 1; p <= 8; p++) { 859 for (j = 4; j <= 55; j++) { 860 /* This is actually 1000*((j+(d/10000))*r)/p 861 * The term had to be converted to get 862 * rid of the division by 10000; d = 0 here 863 */ 864 int tmp_clk = (1000 * j * r) / p; 865 866 /* Check whether this values get closer than 867 * the best ones we had before 868 */ 869 if (abs(codec_clk - tmp_clk) < 870 abs(codec_clk - last_clk)) { 871 pll_j = j; pll_d = 0; 872 pll_r = r; pll_p = p; 873 last_clk = tmp_clk; 874 } 875 876 /* Early exit for exact matches */ 877 if (tmp_clk == codec_clk) 878 goto found; 879 } 880 } 881 882 /* try with d != 0 */ 883 for (p = 1; p <= 8; p++) { 884 j = codec_clk * p / 1000; 885 886 if (j < 4 || j > 11) 887 continue; 888 889 /* do not use codec_clk here since we'd loose precision */ 890 d = ((2048 * p * fsref) - j * aic3x->sysclk) 891 * 100 / (aic3x->sysclk/100); 892 893 clk = (10000 * j + d) / (10 * p); 894 895 /* check whether this values get closer than the best 896 * ones we had before */ 897 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 898 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 899 last_clk = clk; 900 } 901 902 /* Early exit for exact matches */ 903 if (clk == codec_clk) 904 goto found; 905 } 906 907 if (last_clk == 0) { 908 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 909 return -EINVAL; 910 } 911 912found: 913 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 914 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT)); 915 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT); 916 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 917 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT); 918 aic3x_write(codec, AIC3X_PLL_PROGD_REG, 919 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 920 921 return 0; 922} 923 924static int aic3x_mute(struct snd_soc_dai *dai, int mute) 925{ 926 struct snd_soc_codec *codec = dai->codec; 927 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON; 928 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON; 929 930 if (mute) { 931 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 932 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 933 } else { 934 aic3x_write(codec, LDAC_VOL, ldac_reg); 935 aic3x_write(codec, RDAC_VOL, rdac_reg); 936 } 937 938 return 0; 939} 940 941static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 942 int clk_id, unsigned int freq, int dir) 943{ 944 struct snd_soc_codec *codec = codec_dai->codec; 945 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 946 947 aic3x->sysclk = freq; 948 return 0; 949} 950 951static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 952 unsigned int fmt) 953{ 954 struct snd_soc_codec *codec = codec_dai->codec; 955 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 956 u8 iface_areg, iface_breg; 957 int delay = 0; 958 959 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 960 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 961 962 /* set master/slave audio interface */ 963 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 964 case SND_SOC_DAIFMT_CBM_CFM: 965 aic3x->master = 1; 966 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 967 break; 968 case SND_SOC_DAIFMT_CBS_CFS: 969 aic3x->master = 0; 970 break; 971 default: 972 return -EINVAL; 973 } 974 975 /* 976 * match both interface format and signal polarities since they 977 * are fixed 978 */ 979 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 980 SND_SOC_DAIFMT_INV_MASK)) { 981 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 982 break; 983 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 984 delay = 1; 985 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 986 iface_breg |= (0x01 << 6); 987 break; 988 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 989 iface_breg |= (0x02 << 6); 990 break; 991 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 992 iface_breg |= (0x03 << 6); 993 break; 994 default: 995 return -EINVAL; 996 } 997 998 /* set iface */ 999 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1000 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1001 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1002 1003 return 0; 1004} 1005 1006static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1007 enum snd_soc_bias_level level) 1008{ 1009 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1010 u8 reg; 1011 1012 switch (level) { 1013 case SND_SOC_BIAS_ON: 1014 break; 1015 case SND_SOC_BIAS_PREPARE: 1016 if (aic3x->master) { 1017 /* enable pll */ 1018 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 1019 aic3x_write(codec, AIC3X_PLL_PROGA_REG, 1020 reg | PLL_ENABLE); 1021 } 1022 break; 1023 case SND_SOC_BIAS_STANDBY: 1024 /* fall through and disable pll */ 1025 case SND_SOC_BIAS_OFF: 1026 if (aic3x->master) { 1027 /* disable pll */ 1028 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 1029 aic3x_write(codec, AIC3X_PLL_PROGA_REG, 1030 reg & ~PLL_ENABLE); 1031 } 1032 break; 1033 } 1034 codec->bias_level = level; 1035 1036 return 0; 1037} 1038 1039void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) 1040{ 1041 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1042 u8 bit = gpio ? 3: 0; 1043 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit); 1044 aic3x_write(codec, reg, val | (!!state << bit)); 1045} 1046EXPORT_SYMBOL_GPL(aic3x_set_gpio); 1047 1048int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio) 1049{ 1050 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1051 u8 val, bit = gpio ? 2: 1; 1052 1053 aic3x_read(codec, reg, &val); 1054 return (val >> bit) & 1; 1055} 1056EXPORT_SYMBOL_GPL(aic3x_get_gpio); 1057 1058void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, 1059 int headset_debounce, int button_debounce) 1060{ 1061 u8 val; 1062 1063 val = ((detect & AIC3X_HEADSET_DETECT_MASK) 1064 << AIC3X_HEADSET_DETECT_SHIFT) | 1065 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK) 1066 << AIC3X_HEADSET_DEBOUNCE_SHIFT) | 1067 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK) 1068 << AIC3X_BUTTON_DEBOUNCE_SHIFT); 1069 1070 if (detect & AIC3X_HEADSET_DETECT_MASK) 1071 val |= AIC3X_HEADSET_DETECT_ENABLED; 1072 1073 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val); 1074} 1075EXPORT_SYMBOL_GPL(aic3x_set_headset_detection); 1076 1077int aic3x_headset_detected(struct snd_soc_codec *codec) 1078{ 1079 u8 val; 1080 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1081 return (val >> 4) & 1; 1082} 1083EXPORT_SYMBOL_GPL(aic3x_headset_detected); 1084 1085int aic3x_button_pressed(struct snd_soc_codec *codec) 1086{ 1087 u8 val; 1088 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1089 return (val >> 5) & 1; 1090} 1091EXPORT_SYMBOL_GPL(aic3x_button_pressed); 1092 1093#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1094#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1095 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1096 1097static struct snd_soc_dai_ops aic3x_dai_ops = { 1098 .hw_params = aic3x_hw_params, 1099 .digital_mute = aic3x_mute, 1100 .set_sysclk = aic3x_set_dai_sysclk, 1101 .set_fmt = aic3x_set_dai_fmt, 1102}; 1103 1104struct snd_soc_dai aic3x_dai = { 1105 .name = "tlv320aic3x", 1106 .playback = { 1107 .stream_name = "Playback", 1108 .channels_min = 1, 1109 .channels_max = 2, 1110 .rates = AIC3X_RATES, 1111 .formats = AIC3X_FORMATS,}, 1112 .capture = { 1113 .stream_name = "Capture", 1114 .channels_min = 1, 1115 .channels_max = 2, 1116 .rates = AIC3X_RATES, 1117 .formats = AIC3X_FORMATS,}, 1118 .ops = &aic3x_dai_ops, 1119}; 1120EXPORT_SYMBOL_GPL(aic3x_dai); 1121 1122static int aic3x_suspend(struct platform_device *pdev, pm_message_t state) 1123{ 1124 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1125 struct snd_soc_codec *codec = socdev->card->codec; 1126 1127 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1128 1129 return 0; 1130} 1131 1132static int aic3x_resume(struct platform_device *pdev) 1133{ 1134 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1135 struct snd_soc_codec *codec = socdev->card->codec; 1136 int i; 1137 u8 data[2]; 1138 u8 *cache = codec->reg_cache; 1139 1140 /* Sync reg_cache with the hardware */ 1141 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) { 1142 data[0] = i; 1143 data[1] = cache[i]; 1144 codec->hw_write(codec->control_data, data, 2); 1145 } 1146 1147 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1148 1149 return 0; 1150} 1151 1152/* 1153 * initialise the AIC3X driver 1154 * register the mixer and dsp interfaces with the kernel 1155 */ 1156static int aic3x_init(struct snd_soc_codec *codec) 1157{ 1158 int reg; 1159 1160 mutex_init(&codec->mutex); 1161 INIT_LIST_HEAD(&codec->dapm_widgets); 1162 INIT_LIST_HEAD(&codec->dapm_paths); 1163 1164 codec->name = "tlv320aic3x"; 1165 codec->owner = THIS_MODULE; 1166 codec->read = aic3x_read_reg_cache; 1167 codec->write = aic3x_write; 1168 codec->set_bias_level = aic3x_set_bias_level; 1169 codec->dai = &aic3x_dai; 1170 codec->num_dai = 1; 1171 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg); 1172 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL); 1173 if (codec->reg_cache == NULL) 1174 return -ENOMEM; 1175 1176 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1177 aic3x_write(codec, AIC3X_RESET, SOFT_RESET); 1178 1179 /* DAC default volume and mute */ 1180 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1181 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1182 1183 /* DAC to HP default volume and route to Output mixer */ 1184 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1185 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1186 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1187 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1188 /* DAC to Line Out default volume and route to Output mixer */ 1189 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1190 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1191 /* DAC to Mono Line Out default volume and route to Output mixer */ 1192 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1193 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1194 1195 /* unmute all outputs */ 1196 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); 1197 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE); 1198 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); 1199 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE); 1200 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); 1201 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE); 1202 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); 1203 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE); 1204 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); 1205 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE); 1206 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); 1207 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE); 1208 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); 1209 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE); 1210 1211 /* ADC default volume and unmute */ 1212 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN); 1213 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN); 1214 /* By default route Line1 to ADC PGA mixer */ 1215 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1216 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1217 1218 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1219 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1220 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1221 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1222 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1223 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1224 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1225 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1226 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1227 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1228 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1229 1230 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1231 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1232 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1233 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1234 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1235 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1236 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1237 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1238 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1239 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1240 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1241 1242 /* off, with power on */ 1243 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1244 1245 return 0; 1246} 1247 1248static struct snd_soc_codec *aic3x_codec; 1249 1250static int aic3x_register(struct snd_soc_codec *codec) 1251{ 1252 int ret; 1253 1254 ret = aic3x_init(codec); 1255 if (ret < 0) { 1256 dev_err(codec->dev, "Failed to initialise device\n"); 1257 return ret; 1258 } 1259 1260 aic3x_codec = codec; 1261 1262 ret = snd_soc_register_codec(codec); 1263 if (ret) { 1264 dev_err(codec->dev, "Failed to register codec\n"); 1265 return ret; 1266 } 1267 1268 ret = snd_soc_register_dai(&aic3x_dai); 1269 if (ret) { 1270 dev_err(codec->dev, "Failed to register dai\n"); 1271 snd_soc_unregister_codec(codec); 1272 return ret; 1273 } 1274 1275 return 0; 1276} 1277 1278static int aic3x_unregister(struct aic3x_priv *aic3x) 1279{ 1280 aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF); 1281 1282 snd_soc_unregister_dai(&aic3x_dai); 1283 snd_soc_unregister_codec(&aic3x->codec); 1284 1285 if (aic3x->gpio_reset >= 0) { 1286 gpio_set_value(aic3x->gpio_reset, 0); 1287 gpio_free(aic3x->gpio_reset); 1288 } 1289 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1290 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1291 1292 kfree(aic3x); 1293 aic3x_codec = NULL; 1294 1295 return 0; 1296} 1297 1298#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1299/* 1300 * AIC3X 2 wire address can be up to 4 devices with device addresses 1301 * 0x18, 0x19, 0x1A, 0x1B 1302 */ 1303 1304/* 1305 * If the i2c layer weren't so broken, we could pass this kind of data 1306 * around 1307 */ 1308static int aic3x_i2c_probe(struct i2c_client *i2c, 1309 const struct i2c_device_id *id) 1310{ 1311 struct snd_soc_codec *codec; 1312 struct aic3x_priv *aic3x; 1313 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1314 int ret, i; 1315 1316 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); 1317 if (aic3x == NULL) { 1318 dev_err(&i2c->dev, "failed to create private data\n"); 1319 return -ENOMEM; 1320 } 1321 1322 codec = &aic3x->codec; 1323 codec->dev = &i2c->dev; 1324 snd_soc_codec_set_drvdata(codec, aic3x); 1325 codec->control_data = i2c; 1326 codec->hw_write = (hw_write_t) i2c_master_send; 1327 1328 i2c_set_clientdata(i2c, aic3x); 1329 1330 aic3x->gpio_reset = -1; 1331 if (pdata && pdata->gpio_reset >= 0) { 1332 ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset"); 1333 if (ret != 0) 1334 goto err_gpio; 1335 aic3x->gpio_reset = pdata->gpio_reset; 1336 gpio_direction_output(aic3x->gpio_reset, 0); 1337 } 1338 1339 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1340 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1341 1342 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), 1343 aic3x->supplies); 1344 if (ret != 0) { 1345 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1346 goto err_get; 1347 } 1348 1349 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1350 aic3x->supplies); 1351 if (ret != 0) { 1352 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 1353 goto err_enable; 1354 } 1355 1356 if (aic3x->gpio_reset >= 0) { 1357 udelay(1); 1358 gpio_set_value(aic3x->gpio_reset, 1); 1359 } 1360 1361 return aic3x_register(codec); 1362 1363err_enable: 1364 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1365err_get: 1366 if (aic3x->gpio_reset >= 0) 1367 gpio_free(aic3x->gpio_reset); 1368err_gpio: 1369 kfree(aic3x); 1370 return ret; 1371} 1372 1373static int aic3x_i2c_remove(struct i2c_client *client) 1374{ 1375 struct aic3x_priv *aic3x = i2c_get_clientdata(client); 1376 1377 return aic3x_unregister(aic3x); 1378} 1379 1380static const struct i2c_device_id aic3x_i2c_id[] = { 1381 { "tlv320aic3x", 0 }, 1382 { "tlv320aic33", 0 }, 1383 { } 1384}; 1385MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1386 1387/* machine i2c codec control layer */ 1388static struct i2c_driver aic3x_i2c_driver = { 1389 .driver = { 1390 .name = "aic3x I2C Codec", 1391 .owner = THIS_MODULE, 1392 }, 1393 .probe = aic3x_i2c_probe, 1394 .remove = aic3x_i2c_remove, 1395 .id_table = aic3x_i2c_id, 1396}; 1397 1398static inline void aic3x_i2c_init(void) 1399{ 1400 int ret; 1401 1402 ret = i2c_add_driver(&aic3x_i2c_driver); 1403 if (ret) 1404 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n", 1405 __func__, ret); 1406} 1407 1408static inline void aic3x_i2c_exit(void) 1409{ 1410 i2c_del_driver(&aic3x_i2c_driver); 1411} 1412#else 1413static inline void aic3x_i2c_init(void) { } 1414static inline void aic3x_i2c_exit(void) { } 1415#endif 1416 1417static int aic3x_probe(struct platform_device *pdev) 1418{ 1419 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1420 struct aic3x_setup_data *setup; 1421 struct snd_soc_codec *codec; 1422 int ret = 0; 1423 1424 codec = aic3x_codec; 1425 if (!codec) { 1426 dev_err(&pdev->dev, "Codec not registered\n"); 1427 return -ENODEV; 1428 } 1429 1430 socdev->card->codec = codec; 1431 setup = socdev->codec_data; 1432 1433 if (setup) { 1434 /* setup GPIO functions */ 1435 aic3x_write(codec, AIC3X_GPIO1_REG, 1436 (setup->gpio_func[0] & 0xf) << 4); 1437 aic3x_write(codec, AIC3X_GPIO2_REG, 1438 (setup->gpio_func[1] & 0xf) << 4); 1439 } 1440 1441 /* register pcms */ 1442 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1443 if (ret < 0) { 1444 printk(KERN_ERR "aic3x: failed to create pcms\n"); 1445 goto pcm_err; 1446 } 1447 1448 snd_soc_add_controls(codec, aic3x_snd_controls, 1449 ARRAY_SIZE(aic3x_snd_controls)); 1450 1451 aic3x_add_widgets(codec); 1452 1453 return ret; 1454 1455pcm_err: 1456 kfree(codec->reg_cache); 1457 return ret; 1458} 1459 1460static int aic3x_remove(struct platform_device *pdev) 1461{ 1462 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1463 struct snd_soc_codec *codec = socdev->card->codec; 1464 1465 /* power down chip */ 1466 if (codec->control_data) 1467 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1468 1469 snd_soc_free_pcms(socdev); 1470 snd_soc_dapm_free(socdev); 1471 1472 kfree(codec->reg_cache); 1473 1474 return 0; 1475} 1476 1477struct snd_soc_codec_device soc_codec_dev_aic3x = { 1478 .probe = aic3x_probe, 1479 .remove = aic3x_remove, 1480 .suspend = aic3x_suspend, 1481 .resume = aic3x_resume, 1482}; 1483EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x); 1484 1485static int __init aic3x_modinit(void) 1486{ 1487 aic3x_i2c_init(); 1488 1489 return 0; 1490} 1491module_init(aic3x_modinit); 1492 1493static void __exit aic3x_exit(void) 1494{ 1495 aic3x_i2c_exit(); 1496} 1497module_exit(aic3x_exit); 1498 1499MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1500MODULE_AUTHOR("Vladimir Barinov"); 1501MODULE_LICENSE("GPL"); 1502