1/* 2 * include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994 3 * 4 * Copyright 2009 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15#ifndef __MFD_WM8994_REGISTERS_H__ 16#define __MFD_WM8994_REGISTERS_H__ 17 18/* 19 * Register values. 20 */ 21#define WM8994_SOFTWARE_RESET 0x00 22#define WM8994_POWER_MANAGEMENT_1 0x01 23#define WM8994_POWER_MANAGEMENT_2 0x02 24#define WM8994_POWER_MANAGEMENT_3 0x03 25#define WM8994_POWER_MANAGEMENT_4 0x04 26#define WM8994_POWER_MANAGEMENT_5 0x05 27#define WM8994_POWER_MANAGEMENT_6 0x06 28#define WM8994_INPUT_MIXER_1 0x15 29#define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18 30#define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19 31#define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A 32#define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B 33#define WM8994_LEFT_OUTPUT_VOLUME 0x1C 34#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D 35#define WM8994_LINE_OUTPUTS_VOLUME 0x1E 36#define WM8994_HPOUT2_VOLUME 0x1F 37#define WM8994_LEFT_OPGA_VOLUME 0x20 38#define WM8994_RIGHT_OPGA_VOLUME 0x21 39#define WM8994_SPKMIXL_ATTENUATION 0x22 40#define WM8994_SPKMIXR_ATTENUATION 0x23 41#define WM8994_SPKOUT_MIXERS 0x24 42#define WM8994_CLASSD 0x25 43#define WM8994_SPEAKER_VOLUME_LEFT 0x26 44#define WM8994_SPEAKER_VOLUME_RIGHT 0x27 45#define WM8994_INPUT_MIXER_2 0x28 46#define WM8994_INPUT_MIXER_3 0x29 47#define WM8994_INPUT_MIXER_4 0x2A 48#define WM8994_INPUT_MIXER_5 0x2B 49#define WM8994_INPUT_MIXER_6 0x2C 50#define WM8994_OUTPUT_MIXER_1 0x2D 51#define WM8994_OUTPUT_MIXER_2 0x2E 52#define WM8994_OUTPUT_MIXER_3 0x2F 53#define WM8994_OUTPUT_MIXER_4 0x30 54#define WM8994_OUTPUT_MIXER_5 0x31 55#define WM8994_OUTPUT_MIXER_6 0x32 56#define WM8994_HPOUT2_MIXER 0x33 57#define WM8994_LINE_MIXER_1 0x34 58#define WM8994_LINE_MIXER_2 0x35 59#define WM8994_SPEAKER_MIXER 0x36 60#define WM8994_ADDITIONAL_CONTROL 0x37 61#define WM8994_ANTIPOP_1 0x38 62#define WM8994_ANTIPOP_2 0x39 63#define WM8994_MICBIAS 0x3A 64#define WM8994_LDO_1 0x3B 65#define WM8994_LDO_2 0x3C 66#define WM8994_CHARGE_PUMP_1 0x4C 67#define WM8994_CLASS_W_1 0x51 68#define WM8994_DC_SERVO_1 0x54 69#define WM8994_DC_SERVO_2 0x55 70#define WM8994_DC_SERVO_4 0x57 71#define WM8994_DC_SERVO_READBACK 0x58 72#define WM8994_ANALOGUE_HP_1 0x60 73#define WM8994_CHIP_REVISION 0x100 74#define WM8994_CONTROL_INTERFACE 0x101 75#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110 76#define WM8994_WRITE_SEQUENCER_CTRL_2 0x111 77#define WM8994_AIF1_CLOCKING_1 0x200 78#define WM8994_AIF1_CLOCKING_2 0x201 79#define WM8994_AIF2_CLOCKING_1 0x204 80#define WM8994_AIF2_CLOCKING_2 0x205 81#define WM8994_CLOCKING_1 0x208 82#define WM8994_CLOCKING_2 0x209 83#define WM8994_AIF1_RATE 0x210 84#define WM8994_AIF2_RATE 0x211 85#define WM8994_RATE_STATUS 0x212 86#define WM8994_FLL1_CONTROL_1 0x220 87#define WM8994_FLL1_CONTROL_2 0x221 88#define WM8994_FLL1_CONTROL_3 0x222 89#define WM8994_FLL1_CONTROL_4 0x223 90#define WM8994_FLL1_CONTROL_5 0x224 91#define WM8994_FLL2_CONTROL_1 0x240 92#define WM8994_FLL2_CONTROL_2 0x241 93#define WM8994_FLL2_CONTROL_3 0x242 94#define WM8994_FLL2_CONTROL_4 0x243 95#define WM8994_FLL2_CONTROL_5 0x244 96#define WM8994_AIF1_CONTROL_1 0x300 97#define WM8994_AIF1_CONTROL_2 0x301 98#define WM8994_AIF1_MASTER_SLAVE 0x302 99#define WM8994_AIF1_BCLK 0x303 100#define WM8994_AIF1ADC_LRCLK 0x304 101#define WM8994_AIF1DAC_LRCLK 0x305 102#define WM8994_AIF1DAC_DATA 0x306 103#define WM8994_AIF1ADC_DATA 0x307 104#define WM8994_AIF2_CONTROL_1 0x310 105#define WM8994_AIF2_CONTROL_2 0x311 106#define WM8994_AIF2_MASTER_SLAVE 0x312 107#define WM8994_AIF2_BCLK 0x313 108#define WM8994_AIF2ADC_LRCLK 0x314 109#define WM8994_AIF2DAC_LRCLK 0x315 110#define WM8994_AIF2DAC_DATA 0x316 111#define WM8994_AIF2ADC_DATA 0x317 112#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400 113#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401 114#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402 115#define WM8994_AIF1_DAC1_RIGHT_VOLUME 0x403 116#define WM8994_AIF1_ADC2_LEFT_VOLUME 0x404 117#define WM8994_AIF1_ADC2_RIGHT_VOLUME 0x405 118#define WM8994_AIF1_DAC2_LEFT_VOLUME 0x406 119#define WM8994_AIF1_DAC2_RIGHT_VOLUME 0x407 120#define WM8994_AIF1_ADC1_FILTERS 0x410 121#define WM8994_AIF1_ADC2_FILTERS 0x411 122#define WM8994_AIF1_DAC1_FILTERS_1 0x420 123#define WM8994_AIF1_DAC1_FILTERS_2 0x421 124#define WM8994_AIF1_DAC2_FILTERS_1 0x422 125#define WM8994_AIF1_DAC2_FILTERS_2 0x423 126#define WM8994_AIF1_DRC1_1 0x440 127#define WM8994_AIF1_DRC1_2 0x441 128#define WM8994_AIF1_DRC1_3 0x442 129#define WM8994_AIF1_DRC1_4 0x443 130#define WM8994_AIF1_DRC1_5 0x444 131#define WM8994_AIF1_DRC2_1 0x450 132#define WM8994_AIF1_DRC2_2 0x451 133#define WM8994_AIF1_DRC2_3 0x452 134#define WM8994_AIF1_DRC2_4 0x453 135#define WM8994_AIF1_DRC2_5 0x454 136#define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480 137#define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481 138#define WM8994_AIF1_DAC1_EQ_BAND_1_A 0x482 139#define WM8994_AIF1_DAC1_EQ_BAND_1_B 0x483 140#define WM8994_AIF1_DAC1_EQ_BAND_1_PG 0x484 141#define WM8994_AIF1_DAC1_EQ_BAND_2_A 0x485 142#define WM8994_AIF1_DAC1_EQ_BAND_2_B 0x486 143#define WM8994_AIF1_DAC1_EQ_BAND_2_C 0x487 144#define WM8994_AIF1_DAC1_EQ_BAND_2_PG 0x488 145#define WM8994_AIF1_DAC1_EQ_BAND_3_A 0x489 146#define WM8994_AIF1_DAC1_EQ_BAND_3_B 0x48A 147#define WM8994_AIF1_DAC1_EQ_BAND_3_C 0x48B 148#define WM8994_AIF1_DAC1_EQ_BAND_3_PG 0x48C 149#define WM8994_AIF1_DAC1_EQ_BAND_4_A 0x48D 150#define WM8994_AIF1_DAC1_EQ_BAND_4_B 0x48E 151#define WM8994_AIF1_DAC1_EQ_BAND_4_C 0x48F 152#define WM8994_AIF1_DAC1_EQ_BAND_4_PG 0x490 153#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491 154#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492 155#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493 156#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0 157#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1 158#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2 159#define WM8994_AIF1_DAC2_EQ_BAND_1_B 0x4A3 160#define WM8994_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 161#define WM8994_AIF1_DAC2_EQ_BAND_2_A 0x4A5 162#define WM8994_AIF1_DAC2_EQ_BAND_2_B 0x4A6 163#define WM8994_AIF1_DAC2_EQ_BAND_2_C 0x4A7 164#define WM8994_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 165#define WM8994_AIF1_DAC2_EQ_BAND_3_A 0x4A9 166#define WM8994_AIF1_DAC2_EQ_BAND_3_B 0x4AA 167#define WM8994_AIF1_DAC2_EQ_BAND_3_C 0x4AB 168#define WM8994_AIF1_DAC2_EQ_BAND_3_PG 0x4AC 169#define WM8994_AIF1_DAC2_EQ_BAND_4_A 0x4AD 170#define WM8994_AIF1_DAC2_EQ_BAND_4_B 0x4AE 171#define WM8994_AIF1_DAC2_EQ_BAND_4_C 0x4AF 172#define WM8994_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 173#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1 174#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2 175#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 176#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500 177#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501 178#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 179#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 180#define WM8994_AIF2_ADC_FILTERS 0x510 181#define WM8994_AIF2_DAC_FILTERS_1 0x520 182#define WM8994_AIF2_DAC_FILTERS_2 0x521 183#define WM8994_AIF2_DRC_1 0x540 184#define WM8994_AIF2_DRC_2 0x541 185#define WM8994_AIF2_DRC_3 0x542 186#define WM8994_AIF2_DRC_4 0x543 187#define WM8994_AIF2_DRC_5 0x544 188#define WM8994_AIF2_EQ_GAINS_1 0x580 189#define WM8994_AIF2_EQ_GAINS_2 0x581 190#define WM8994_AIF2_EQ_BAND_1_A 0x582 191#define WM8994_AIF2_EQ_BAND_1_B 0x583 192#define WM8994_AIF2_EQ_BAND_1_PG 0x584 193#define WM8994_AIF2_EQ_BAND_2_A 0x585 194#define WM8994_AIF2_EQ_BAND_2_B 0x586 195#define WM8994_AIF2_EQ_BAND_2_C 0x587 196#define WM8994_AIF2_EQ_BAND_2_PG 0x588 197#define WM8994_AIF2_EQ_BAND_3_A 0x589 198#define WM8994_AIF2_EQ_BAND_3_B 0x58A 199#define WM8994_AIF2_EQ_BAND_3_C 0x58B 200#define WM8994_AIF2_EQ_BAND_3_PG 0x58C 201#define WM8994_AIF2_EQ_BAND_4_A 0x58D 202#define WM8994_AIF2_EQ_BAND_4_B 0x58E 203#define WM8994_AIF2_EQ_BAND_4_C 0x58F 204#define WM8994_AIF2_EQ_BAND_4_PG 0x590 205#define WM8994_AIF2_EQ_BAND_5_A 0x591 206#define WM8994_AIF2_EQ_BAND_5_B 0x592 207#define WM8994_AIF2_EQ_BAND_5_PG 0x593 208#define WM8994_DAC1_MIXER_VOLUMES 0x600 209#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 210#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 211#define WM8994_DAC2_MIXER_VOLUMES 0x603 212#define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604 213#define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605 214#define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 215#define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 216#define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 217#define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 218#define WM8994_DAC1_LEFT_VOLUME 0x610 219#define WM8994_DAC1_RIGHT_VOLUME 0x611 220#define WM8994_DAC2_LEFT_VOLUME 0x612 221#define WM8994_DAC2_RIGHT_VOLUME 0x613 222#define WM8994_DAC_SOFTMUTE 0x614 223#define WM8994_OVERSAMPLING 0x620 224#define WM8994_SIDETONE 0x621 225#define WM8994_GPIO_1 0x700 226#define WM8994_GPIO_2 0x701 227#define WM8994_GPIO_3 0x702 228#define WM8994_GPIO_4 0x703 229#define WM8994_GPIO_5 0x704 230#define WM8994_GPIO_6 0x705 231#define WM8994_GPIO_7 0x706 232#define WM8994_GPIO_8 0x707 233#define WM8994_GPIO_9 0x708 234#define WM8994_GPIO_10 0x709 235#define WM8994_GPIO_11 0x70A 236#define WM8994_PULL_CONTROL_1 0x720 237#define WM8994_PULL_CONTROL_2 0x721 238#define WM8994_INTERRUPT_STATUS_1 0x730 239#define WM8994_INTERRUPT_STATUS_2 0x731 240#define WM8994_INTERRUPT_RAW_STATUS_2 0x732 241#define WM8994_INTERRUPT_STATUS_1_MASK 0x738 242#define WM8994_INTERRUPT_STATUS_2_MASK 0x739 243#define WM8994_INTERRUPT_CONTROL 0x740 244#define WM8994_IRQ_DEBOUNCE 0x748 245#define WM8994_WRITE_SEQUENCER_0 0x3000 246#define WM8994_WRITE_SEQUENCER_1 0x3001 247#define WM8994_WRITE_SEQUENCER_2 0x3002 248#define WM8994_WRITE_SEQUENCER_3 0x3003 249#define WM8994_WRITE_SEQUENCER_4 0x3004 250#define WM8994_WRITE_SEQUENCER_5 0x3005 251#define WM8994_WRITE_SEQUENCER_6 0x3006 252#define WM8994_WRITE_SEQUENCER_7 0x3007 253#define WM8994_WRITE_SEQUENCER_8 0x3008 254#define WM8994_WRITE_SEQUENCER_9 0x3009 255#define WM8994_WRITE_SEQUENCER_10 0x300A 256#define WM8994_WRITE_SEQUENCER_11 0x300B 257#define WM8994_WRITE_SEQUENCER_12 0x300C 258#define WM8994_WRITE_SEQUENCER_13 0x300D 259#define WM8994_WRITE_SEQUENCER_14 0x300E 260#define WM8994_WRITE_SEQUENCER_15 0x300F 261#define WM8994_WRITE_SEQUENCER_16 0x3010 262#define WM8994_WRITE_SEQUENCER_17 0x3011 263#define WM8994_WRITE_SEQUENCER_18 0x3012 264#define WM8994_WRITE_SEQUENCER_19 0x3013 265#define WM8994_WRITE_SEQUENCER_20 0x3014 266#define WM8994_WRITE_SEQUENCER_21 0x3015 267#define WM8994_WRITE_SEQUENCER_22 0x3016 268#define WM8994_WRITE_SEQUENCER_23 0x3017 269#define WM8994_WRITE_SEQUENCER_24 0x3018 270#define WM8994_WRITE_SEQUENCER_25 0x3019 271#define WM8994_WRITE_SEQUENCER_26 0x301A 272#define WM8994_WRITE_SEQUENCER_27 0x301B 273#define WM8994_WRITE_SEQUENCER_28 0x301C 274#define WM8994_WRITE_SEQUENCER_29 0x301D 275#define WM8994_WRITE_SEQUENCER_30 0x301E 276#define WM8994_WRITE_SEQUENCER_31 0x301F 277#define WM8994_WRITE_SEQUENCER_32 0x3020 278#define WM8994_WRITE_SEQUENCER_33 0x3021 279#define WM8994_WRITE_SEQUENCER_34 0x3022 280#define WM8994_WRITE_SEQUENCER_35 0x3023 281#define WM8994_WRITE_SEQUENCER_36 0x3024 282#define WM8994_WRITE_SEQUENCER_37 0x3025 283#define WM8994_WRITE_SEQUENCER_38 0x3026 284#define WM8994_WRITE_SEQUENCER_39 0x3027 285#define WM8994_WRITE_SEQUENCER_40 0x3028 286#define WM8994_WRITE_SEQUENCER_41 0x3029 287#define WM8994_WRITE_SEQUENCER_42 0x302A 288#define WM8994_WRITE_SEQUENCER_43 0x302B 289#define WM8994_WRITE_SEQUENCER_44 0x302C 290#define WM8994_WRITE_SEQUENCER_45 0x302D 291#define WM8994_WRITE_SEQUENCER_46 0x302E 292#define WM8994_WRITE_SEQUENCER_47 0x302F 293#define WM8994_WRITE_SEQUENCER_48 0x3030 294#define WM8994_WRITE_SEQUENCER_49 0x3031 295#define WM8994_WRITE_SEQUENCER_50 0x3032 296#define WM8994_WRITE_SEQUENCER_51 0x3033 297#define WM8994_WRITE_SEQUENCER_52 0x3034 298#define WM8994_WRITE_SEQUENCER_53 0x3035 299#define WM8994_WRITE_SEQUENCER_54 0x3036 300#define WM8994_WRITE_SEQUENCER_55 0x3037 301#define WM8994_WRITE_SEQUENCER_56 0x3038 302#define WM8994_WRITE_SEQUENCER_57 0x3039 303#define WM8994_WRITE_SEQUENCER_58 0x303A 304#define WM8994_WRITE_SEQUENCER_59 0x303B 305#define WM8994_WRITE_SEQUENCER_60 0x303C 306#define WM8994_WRITE_SEQUENCER_61 0x303D 307#define WM8994_WRITE_SEQUENCER_62 0x303E 308#define WM8994_WRITE_SEQUENCER_63 0x303F 309#define WM8994_WRITE_SEQUENCER_64 0x3040 310#define WM8994_WRITE_SEQUENCER_65 0x3041 311#define WM8994_WRITE_SEQUENCER_66 0x3042 312#define WM8994_WRITE_SEQUENCER_67 0x3043 313#define WM8994_WRITE_SEQUENCER_68 0x3044 314#define WM8994_WRITE_SEQUENCER_69 0x3045 315#define WM8994_WRITE_SEQUENCER_70 0x3046 316#define WM8994_WRITE_SEQUENCER_71 0x3047 317#define WM8994_WRITE_SEQUENCER_72 0x3048 318#define WM8994_WRITE_SEQUENCER_73 0x3049 319#define WM8994_WRITE_SEQUENCER_74 0x304A 320#define WM8994_WRITE_SEQUENCER_75 0x304B 321#define WM8994_WRITE_SEQUENCER_76 0x304C 322#define WM8994_WRITE_SEQUENCER_77 0x304D 323#define WM8994_WRITE_SEQUENCER_78 0x304E 324#define WM8994_WRITE_SEQUENCER_79 0x304F 325#define WM8994_WRITE_SEQUENCER_80 0x3050 326#define WM8994_WRITE_SEQUENCER_81 0x3051 327#define WM8994_WRITE_SEQUENCER_82 0x3052 328#define WM8994_WRITE_SEQUENCER_83 0x3053 329#define WM8994_WRITE_SEQUENCER_84 0x3054 330#define WM8994_WRITE_SEQUENCER_85 0x3055 331#define WM8994_WRITE_SEQUENCER_86 0x3056 332#define WM8994_WRITE_SEQUENCER_87 0x3057 333#define WM8994_WRITE_SEQUENCER_88 0x3058 334#define WM8994_WRITE_SEQUENCER_89 0x3059 335#define WM8994_WRITE_SEQUENCER_90 0x305A 336#define WM8994_WRITE_SEQUENCER_91 0x305B 337#define WM8994_WRITE_SEQUENCER_92 0x305C 338#define WM8994_WRITE_SEQUENCER_93 0x305D 339#define WM8994_WRITE_SEQUENCER_94 0x305E 340#define WM8994_WRITE_SEQUENCER_95 0x305F 341#define WM8994_WRITE_SEQUENCER_96 0x3060 342#define WM8994_WRITE_SEQUENCER_97 0x3061 343#define WM8994_WRITE_SEQUENCER_98 0x3062 344#define WM8994_WRITE_SEQUENCER_99 0x3063 345#define WM8994_WRITE_SEQUENCER_100 0x3064 346#define WM8994_WRITE_SEQUENCER_101 0x3065 347#define WM8994_WRITE_SEQUENCER_102 0x3066 348#define WM8994_WRITE_SEQUENCER_103 0x3067 349#define WM8994_WRITE_SEQUENCER_104 0x3068 350#define WM8994_WRITE_SEQUENCER_105 0x3069 351#define WM8994_WRITE_SEQUENCER_106 0x306A 352#define WM8994_WRITE_SEQUENCER_107 0x306B 353#define WM8994_WRITE_SEQUENCER_108 0x306C 354#define WM8994_WRITE_SEQUENCER_109 0x306D 355#define WM8994_WRITE_SEQUENCER_110 0x306E 356#define WM8994_WRITE_SEQUENCER_111 0x306F 357#define WM8994_WRITE_SEQUENCER_112 0x3070 358#define WM8994_WRITE_SEQUENCER_113 0x3071 359#define WM8994_WRITE_SEQUENCER_114 0x3072 360#define WM8994_WRITE_SEQUENCER_115 0x3073 361#define WM8994_WRITE_SEQUENCER_116 0x3074 362#define WM8994_WRITE_SEQUENCER_117 0x3075 363#define WM8994_WRITE_SEQUENCER_118 0x3076 364#define WM8994_WRITE_SEQUENCER_119 0x3077 365#define WM8994_WRITE_SEQUENCER_120 0x3078 366#define WM8994_WRITE_SEQUENCER_121 0x3079 367#define WM8994_WRITE_SEQUENCER_122 0x307A 368#define WM8994_WRITE_SEQUENCER_123 0x307B 369#define WM8994_WRITE_SEQUENCER_124 0x307C 370#define WM8994_WRITE_SEQUENCER_125 0x307D 371#define WM8994_WRITE_SEQUENCER_126 0x307E 372#define WM8994_WRITE_SEQUENCER_127 0x307F 373#define WM8994_WRITE_SEQUENCER_128 0x3080 374#define WM8994_WRITE_SEQUENCER_129 0x3081 375#define WM8994_WRITE_SEQUENCER_130 0x3082 376#define WM8994_WRITE_SEQUENCER_131 0x3083 377#define WM8994_WRITE_SEQUENCER_132 0x3084 378#define WM8994_WRITE_SEQUENCER_133 0x3085 379#define WM8994_WRITE_SEQUENCER_134 0x3086 380#define WM8994_WRITE_SEQUENCER_135 0x3087 381#define WM8994_WRITE_SEQUENCER_136 0x3088 382#define WM8994_WRITE_SEQUENCER_137 0x3089 383#define WM8994_WRITE_SEQUENCER_138 0x308A 384#define WM8994_WRITE_SEQUENCER_139 0x308B 385#define WM8994_WRITE_SEQUENCER_140 0x308C 386#define WM8994_WRITE_SEQUENCER_141 0x308D 387#define WM8994_WRITE_SEQUENCER_142 0x308E 388#define WM8994_WRITE_SEQUENCER_143 0x308F 389#define WM8994_WRITE_SEQUENCER_144 0x3090 390#define WM8994_WRITE_SEQUENCER_145 0x3091 391#define WM8994_WRITE_SEQUENCER_146 0x3092 392#define WM8994_WRITE_SEQUENCER_147 0x3093 393#define WM8994_WRITE_SEQUENCER_148 0x3094 394#define WM8994_WRITE_SEQUENCER_149 0x3095 395#define WM8994_WRITE_SEQUENCER_150 0x3096 396#define WM8994_WRITE_SEQUENCER_151 0x3097 397#define WM8994_WRITE_SEQUENCER_152 0x3098 398#define WM8994_WRITE_SEQUENCER_153 0x3099 399#define WM8994_WRITE_SEQUENCER_154 0x309A 400#define WM8994_WRITE_SEQUENCER_155 0x309B 401#define WM8994_WRITE_SEQUENCER_156 0x309C 402#define WM8994_WRITE_SEQUENCER_157 0x309D 403#define WM8994_WRITE_SEQUENCER_158 0x309E 404#define WM8994_WRITE_SEQUENCER_159 0x309F 405#define WM8994_WRITE_SEQUENCER_160 0x30A0 406#define WM8994_WRITE_SEQUENCER_161 0x30A1 407#define WM8994_WRITE_SEQUENCER_162 0x30A2 408#define WM8994_WRITE_SEQUENCER_163 0x30A3 409#define WM8994_WRITE_SEQUENCER_164 0x30A4 410#define WM8994_WRITE_SEQUENCER_165 0x30A5 411#define WM8994_WRITE_SEQUENCER_166 0x30A6 412#define WM8994_WRITE_SEQUENCER_167 0x30A7 413#define WM8994_WRITE_SEQUENCER_168 0x30A8 414#define WM8994_WRITE_SEQUENCER_169 0x30A9 415#define WM8994_WRITE_SEQUENCER_170 0x30AA 416#define WM8994_WRITE_SEQUENCER_171 0x30AB 417#define WM8994_WRITE_SEQUENCER_172 0x30AC 418#define WM8994_WRITE_SEQUENCER_173 0x30AD 419#define WM8994_WRITE_SEQUENCER_174 0x30AE 420#define WM8994_WRITE_SEQUENCER_175 0x30AF 421#define WM8994_WRITE_SEQUENCER_176 0x30B0 422#define WM8994_WRITE_SEQUENCER_177 0x30B1 423#define WM8994_WRITE_SEQUENCER_178 0x30B2 424#define WM8994_WRITE_SEQUENCER_179 0x30B3 425#define WM8994_WRITE_SEQUENCER_180 0x30B4 426#define WM8994_WRITE_SEQUENCER_181 0x30B5 427#define WM8994_WRITE_SEQUENCER_182 0x30B6 428#define WM8994_WRITE_SEQUENCER_183 0x30B7 429#define WM8994_WRITE_SEQUENCER_184 0x30B8 430#define WM8994_WRITE_SEQUENCER_185 0x30B9 431#define WM8994_WRITE_SEQUENCER_186 0x30BA 432#define WM8994_WRITE_SEQUENCER_187 0x30BB 433#define WM8994_WRITE_SEQUENCER_188 0x30BC 434#define WM8994_WRITE_SEQUENCER_189 0x30BD 435#define WM8994_WRITE_SEQUENCER_190 0x30BE 436#define WM8994_WRITE_SEQUENCER_191 0x30BF 437#define WM8994_WRITE_SEQUENCER_192 0x30C0 438#define WM8994_WRITE_SEQUENCER_193 0x30C1 439#define WM8994_WRITE_SEQUENCER_194 0x30C2 440#define WM8994_WRITE_SEQUENCER_195 0x30C3 441#define WM8994_WRITE_SEQUENCER_196 0x30C4 442#define WM8994_WRITE_SEQUENCER_197 0x30C5 443#define WM8994_WRITE_SEQUENCER_198 0x30C6 444#define WM8994_WRITE_SEQUENCER_199 0x30C7 445#define WM8994_WRITE_SEQUENCER_200 0x30C8 446#define WM8994_WRITE_SEQUENCER_201 0x30C9 447#define WM8994_WRITE_SEQUENCER_202 0x30CA 448#define WM8994_WRITE_SEQUENCER_203 0x30CB 449#define WM8994_WRITE_SEQUENCER_204 0x30CC 450#define WM8994_WRITE_SEQUENCER_205 0x30CD 451#define WM8994_WRITE_SEQUENCER_206 0x30CE 452#define WM8994_WRITE_SEQUENCER_207 0x30CF 453#define WM8994_WRITE_SEQUENCER_208 0x30D0 454#define WM8994_WRITE_SEQUENCER_209 0x30D1 455#define WM8994_WRITE_SEQUENCER_210 0x30D2 456#define WM8994_WRITE_SEQUENCER_211 0x30D3 457#define WM8994_WRITE_SEQUENCER_212 0x30D4 458#define WM8994_WRITE_SEQUENCER_213 0x30D5 459#define WM8994_WRITE_SEQUENCER_214 0x30D6 460#define WM8994_WRITE_SEQUENCER_215 0x30D7 461#define WM8994_WRITE_SEQUENCER_216 0x30D8 462#define WM8994_WRITE_SEQUENCER_217 0x30D9 463#define WM8994_WRITE_SEQUENCER_218 0x30DA 464#define WM8994_WRITE_SEQUENCER_219 0x30DB 465#define WM8994_WRITE_SEQUENCER_220 0x30DC 466#define WM8994_WRITE_SEQUENCER_221 0x30DD 467#define WM8994_WRITE_SEQUENCER_222 0x30DE 468#define WM8994_WRITE_SEQUENCER_223 0x30DF 469#define WM8994_WRITE_SEQUENCER_224 0x30E0 470#define WM8994_WRITE_SEQUENCER_225 0x30E1 471#define WM8994_WRITE_SEQUENCER_226 0x30E2 472#define WM8994_WRITE_SEQUENCER_227 0x30E3 473#define WM8994_WRITE_SEQUENCER_228 0x30E4 474#define WM8994_WRITE_SEQUENCER_229 0x30E5 475#define WM8994_WRITE_SEQUENCER_230 0x30E6 476#define WM8994_WRITE_SEQUENCER_231 0x30E7 477#define WM8994_WRITE_SEQUENCER_232 0x30E8 478#define WM8994_WRITE_SEQUENCER_233 0x30E9 479#define WM8994_WRITE_SEQUENCER_234 0x30EA 480#define WM8994_WRITE_SEQUENCER_235 0x30EB 481#define WM8994_WRITE_SEQUENCER_236 0x30EC 482#define WM8994_WRITE_SEQUENCER_237 0x30ED 483#define WM8994_WRITE_SEQUENCER_238 0x30EE 484#define WM8994_WRITE_SEQUENCER_239 0x30EF 485#define WM8994_WRITE_SEQUENCER_240 0x30F0 486#define WM8994_WRITE_SEQUENCER_241 0x30F1 487#define WM8994_WRITE_SEQUENCER_242 0x30F2 488#define WM8994_WRITE_SEQUENCER_243 0x30F3 489#define WM8994_WRITE_SEQUENCER_244 0x30F4 490#define WM8994_WRITE_SEQUENCER_245 0x30F5 491#define WM8994_WRITE_SEQUENCER_246 0x30F6 492#define WM8994_WRITE_SEQUENCER_247 0x30F7 493#define WM8994_WRITE_SEQUENCER_248 0x30F8 494#define WM8994_WRITE_SEQUENCER_249 0x30F9 495#define WM8994_WRITE_SEQUENCER_250 0x30FA 496#define WM8994_WRITE_SEQUENCER_251 0x30FB 497#define WM8994_WRITE_SEQUENCER_252 0x30FC 498#define WM8994_WRITE_SEQUENCER_253 0x30FD 499#define WM8994_WRITE_SEQUENCER_254 0x30FE 500#define WM8994_WRITE_SEQUENCER_255 0x30FF 501#define WM8994_WRITE_SEQUENCER_256 0x3100 502#define WM8994_WRITE_SEQUENCER_257 0x3101 503#define WM8994_WRITE_SEQUENCER_258 0x3102 504#define WM8994_WRITE_SEQUENCER_259 0x3103 505#define WM8994_WRITE_SEQUENCER_260 0x3104 506#define WM8994_WRITE_SEQUENCER_261 0x3105 507#define WM8994_WRITE_SEQUENCER_262 0x3106 508#define WM8994_WRITE_SEQUENCER_263 0x3107 509#define WM8994_WRITE_SEQUENCER_264 0x3108 510#define WM8994_WRITE_SEQUENCER_265 0x3109 511#define WM8994_WRITE_SEQUENCER_266 0x310A 512#define WM8994_WRITE_SEQUENCER_267 0x310B 513#define WM8994_WRITE_SEQUENCER_268 0x310C 514#define WM8994_WRITE_SEQUENCER_269 0x310D 515#define WM8994_WRITE_SEQUENCER_270 0x310E 516#define WM8994_WRITE_SEQUENCER_271 0x310F 517#define WM8994_WRITE_SEQUENCER_272 0x3110 518#define WM8994_WRITE_SEQUENCER_273 0x3111 519#define WM8994_WRITE_SEQUENCER_274 0x3112 520#define WM8994_WRITE_SEQUENCER_275 0x3113 521#define WM8994_WRITE_SEQUENCER_276 0x3114 522#define WM8994_WRITE_SEQUENCER_277 0x3115 523#define WM8994_WRITE_SEQUENCER_278 0x3116 524#define WM8994_WRITE_SEQUENCER_279 0x3117 525#define WM8994_WRITE_SEQUENCER_280 0x3118 526#define WM8994_WRITE_SEQUENCER_281 0x3119 527#define WM8994_WRITE_SEQUENCER_282 0x311A 528#define WM8994_WRITE_SEQUENCER_283 0x311B 529#define WM8994_WRITE_SEQUENCER_284 0x311C 530#define WM8994_WRITE_SEQUENCER_285 0x311D 531#define WM8994_WRITE_SEQUENCER_286 0x311E 532#define WM8994_WRITE_SEQUENCER_287 0x311F 533#define WM8994_WRITE_SEQUENCER_288 0x3120 534#define WM8994_WRITE_SEQUENCER_289 0x3121 535#define WM8994_WRITE_SEQUENCER_290 0x3122 536#define WM8994_WRITE_SEQUENCER_291 0x3123 537#define WM8994_WRITE_SEQUENCER_292 0x3124 538#define WM8994_WRITE_SEQUENCER_293 0x3125 539#define WM8994_WRITE_SEQUENCER_294 0x3126 540#define WM8994_WRITE_SEQUENCER_295 0x3127 541#define WM8994_WRITE_SEQUENCER_296 0x3128 542#define WM8994_WRITE_SEQUENCER_297 0x3129 543#define WM8994_WRITE_SEQUENCER_298 0x312A 544#define WM8994_WRITE_SEQUENCER_299 0x312B 545#define WM8994_WRITE_SEQUENCER_300 0x312C 546#define WM8994_WRITE_SEQUENCER_301 0x312D 547#define WM8994_WRITE_SEQUENCER_302 0x312E 548#define WM8994_WRITE_SEQUENCER_303 0x312F 549#define WM8994_WRITE_SEQUENCER_304 0x3130 550#define WM8994_WRITE_SEQUENCER_305 0x3131 551#define WM8994_WRITE_SEQUENCER_306 0x3132 552#define WM8994_WRITE_SEQUENCER_307 0x3133 553#define WM8994_WRITE_SEQUENCER_308 0x3134 554#define WM8994_WRITE_SEQUENCER_309 0x3135 555#define WM8994_WRITE_SEQUENCER_310 0x3136 556#define WM8994_WRITE_SEQUENCER_311 0x3137 557#define WM8994_WRITE_SEQUENCER_312 0x3138 558#define WM8994_WRITE_SEQUENCER_313 0x3139 559#define WM8994_WRITE_SEQUENCER_314 0x313A 560#define WM8994_WRITE_SEQUENCER_315 0x313B 561#define WM8994_WRITE_SEQUENCER_316 0x313C 562#define WM8994_WRITE_SEQUENCER_317 0x313D 563#define WM8994_WRITE_SEQUENCER_318 0x313E 564#define WM8994_WRITE_SEQUENCER_319 0x313F 565#define WM8994_WRITE_SEQUENCER_320 0x3140 566#define WM8994_WRITE_SEQUENCER_321 0x3141 567#define WM8994_WRITE_SEQUENCER_322 0x3142 568#define WM8994_WRITE_SEQUENCER_323 0x3143 569#define WM8994_WRITE_SEQUENCER_324 0x3144 570#define WM8994_WRITE_SEQUENCER_325 0x3145 571#define WM8994_WRITE_SEQUENCER_326 0x3146 572#define WM8994_WRITE_SEQUENCER_327 0x3147 573#define WM8994_WRITE_SEQUENCER_328 0x3148 574#define WM8994_WRITE_SEQUENCER_329 0x3149 575#define WM8994_WRITE_SEQUENCER_330 0x314A 576#define WM8994_WRITE_SEQUENCER_331 0x314B 577#define WM8994_WRITE_SEQUENCER_332 0x314C 578#define WM8994_WRITE_SEQUENCER_333 0x314D 579#define WM8994_WRITE_SEQUENCER_334 0x314E 580#define WM8994_WRITE_SEQUENCER_335 0x314F 581#define WM8994_WRITE_SEQUENCER_336 0x3150 582#define WM8994_WRITE_SEQUENCER_337 0x3151 583#define WM8994_WRITE_SEQUENCER_338 0x3152 584#define WM8994_WRITE_SEQUENCER_339 0x3153 585#define WM8994_WRITE_SEQUENCER_340 0x3154 586#define WM8994_WRITE_SEQUENCER_341 0x3155 587#define WM8994_WRITE_SEQUENCER_342 0x3156 588#define WM8994_WRITE_SEQUENCER_343 0x3157 589#define WM8994_WRITE_SEQUENCER_344 0x3158 590#define WM8994_WRITE_SEQUENCER_345 0x3159 591#define WM8994_WRITE_SEQUENCER_346 0x315A 592#define WM8994_WRITE_SEQUENCER_347 0x315B 593#define WM8994_WRITE_SEQUENCER_348 0x315C 594#define WM8994_WRITE_SEQUENCER_349 0x315D 595#define WM8994_WRITE_SEQUENCER_350 0x315E 596#define WM8994_WRITE_SEQUENCER_351 0x315F 597#define WM8994_WRITE_SEQUENCER_352 0x3160 598#define WM8994_WRITE_SEQUENCER_353 0x3161 599#define WM8994_WRITE_SEQUENCER_354 0x3162 600#define WM8994_WRITE_SEQUENCER_355 0x3163 601#define WM8994_WRITE_SEQUENCER_356 0x3164 602#define WM8994_WRITE_SEQUENCER_357 0x3165 603#define WM8994_WRITE_SEQUENCER_358 0x3166 604#define WM8994_WRITE_SEQUENCER_359 0x3167 605#define WM8994_WRITE_SEQUENCER_360 0x3168 606#define WM8994_WRITE_SEQUENCER_361 0x3169 607#define WM8994_WRITE_SEQUENCER_362 0x316A 608#define WM8994_WRITE_SEQUENCER_363 0x316B 609#define WM8994_WRITE_SEQUENCER_364 0x316C 610#define WM8994_WRITE_SEQUENCER_365 0x316D 611#define WM8994_WRITE_SEQUENCER_366 0x316E 612#define WM8994_WRITE_SEQUENCER_367 0x316F 613#define WM8994_WRITE_SEQUENCER_368 0x3170 614#define WM8994_WRITE_SEQUENCER_369 0x3171 615#define WM8994_WRITE_SEQUENCER_370 0x3172 616#define WM8994_WRITE_SEQUENCER_371 0x3173 617#define WM8994_WRITE_SEQUENCER_372 0x3174 618#define WM8994_WRITE_SEQUENCER_373 0x3175 619#define WM8994_WRITE_SEQUENCER_374 0x3176 620#define WM8994_WRITE_SEQUENCER_375 0x3177 621#define WM8994_WRITE_SEQUENCER_376 0x3178 622#define WM8994_WRITE_SEQUENCER_377 0x3179 623#define WM8994_WRITE_SEQUENCER_378 0x317A 624#define WM8994_WRITE_SEQUENCER_379 0x317B 625#define WM8994_WRITE_SEQUENCER_380 0x317C 626#define WM8994_WRITE_SEQUENCER_381 0x317D 627#define WM8994_WRITE_SEQUENCER_382 0x317E 628#define WM8994_WRITE_SEQUENCER_383 0x317F 629#define WM8994_WRITE_SEQUENCER_384 0x3180 630#define WM8994_WRITE_SEQUENCER_385 0x3181 631#define WM8994_WRITE_SEQUENCER_386 0x3182 632#define WM8994_WRITE_SEQUENCER_387 0x3183 633#define WM8994_WRITE_SEQUENCER_388 0x3184 634#define WM8994_WRITE_SEQUENCER_389 0x3185 635#define WM8994_WRITE_SEQUENCER_390 0x3186 636#define WM8994_WRITE_SEQUENCER_391 0x3187 637#define WM8994_WRITE_SEQUENCER_392 0x3188 638#define WM8994_WRITE_SEQUENCER_393 0x3189 639#define WM8994_WRITE_SEQUENCER_394 0x318A 640#define WM8994_WRITE_SEQUENCER_395 0x318B 641#define WM8994_WRITE_SEQUENCER_396 0x318C 642#define WM8994_WRITE_SEQUENCER_397 0x318D 643#define WM8994_WRITE_SEQUENCER_398 0x318E 644#define WM8994_WRITE_SEQUENCER_399 0x318F 645#define WM8994_WRITE_SEQUENCER_400 0x3190 646#define WM8994_WRITE_SEQUENCER_401 0x3191 647#define WM8994_WRITE_SEQUENCER_402 0x3192 648#define WM8994_WRITE_SEQUENCER_403 0x3193 649#define WM8994_WRITE_SEQUENCER_404 0x3194 650#define WM8994_WRITE_SEQUENCER_405 0x3195 651#define WM8994_WRITE_SEQUENCER_406 0x3196 652#define WM8994_WRITE_SEQUENCER_407 0x3197 653#define WM8994_WRITE_SEQUENCER_408 0x3198 654#define WM8994_WRITE_SEQUENCER_409 0x3199 655#define WM8994_WRITE_SEQUENCER_410 0x319A 656#define WM8994_WRITE_SEQUENCER_411 0x319B 657#define WM8994_WRITE_SEQUENCER_412 0x319C 658#define WM8994_WRITE_SEQUENCER_413 0x319D 659#define WM8994_WRITE_SEQUENCER_414 0x319E 660#define WM8994_WRITE_SEQUENCER_415 0x319F 661#define WM8994_WRITE_SEQUENCER_416 0x31A0 662#define WM8994_WRITE_SEQUENCER_417 0x31A1 663#define WM8994_WRITE_SEQUENCER_418 0x31A2 664#define WM8994_WRITE_SEQUENCER_419 0x31A3 665#define WM8994_WRITE_SEQUENCER_420 0x31A4 666#define WM8994_WRITE_SEQUENCER_421 0x31A5 667#define WM8994_WRITE_SEQUENCER_422 0x31A6 668#define WM8994_WRITE_SEQUENCER_423 0x31A7 669#define WM8994_WRITE_SEQUENCER_424 0x31A8 670#define WM8994_WRITE_SEQUENCER_425 0x31A9 671#define WM8994_WRITE_SEQUENCER_426 0x31AA 672#define WM8994_WRITE_SEQUENCER_427 0x31AB 673#define WM8994_WRITE_SEQUENCER_428 0x31AC 674#define WM8994_WRITE_SEQUENCER_429 0x31AD 675#define WM8994_WRITE_SEQUENCER_430 0x31AE 676#define WM8994_WRITE_SEQUENCER_431 0x31AF 677#define WM8994_WRITE_SEQUENCER_432 0x31B0 678#define WM8994_WRITE_SEQUENCER_433 0x31B1 679#define WM8994_WRITE_SEQUENCER_434 0x31B2 680#define WM8994_WRITE_SEQUENCER_435 0x31B3 681#define WM8994_WRITE_SEQUENCER_436 0x31B4 682#define WM8994_WRITE_SEQUENCER_437 0x31B5 683#define WM8994_WRITE_SEQUENCER_438 0x31B6 684#define WM8994_WRITE_SEQUENCER_439 0x31B7 685#define WM8994_WRITE_SEQUENCER_440 0x31B8 686#define WM8994_WRITE_SEQUENCER_441 0x31B9 687#define WM8994_WRITE_SEQUENCER_442 0x31BA 688#define WM8994_WRITE_SEQUENCER_443 0x31BB 689#define WM8994_WRITE_SEQUENCER_444 0x31BC 690#define WM8994_WRITE_SEQUENCER_445 0x31BD 691#define WM8994_WRITE_SEQUENCER_446 0x31BE 692#define WM8994_WRITE_SEQUENCER_447 0x31BF 693#define WM8994_WRITE_SEQUENCER_448 0x31C0 694#define WM8994_WRITE_SEQUENCER_449 0x31C1 695#define WM8994_WRITE_SEQUENCER_450 0x31C2 696#define WM8994_WRITE_SEQUENCER_451 0x31C3 697#define WM8994_WRITE_SEQUENCER_452 0x31C4 698#define WM8994_WRITE_SEQUENCER_453 0x31C5 699#define WM8994_WRITE_SEQUENCER_454 0x31C6 700#define WM8994_WRITE_SEQUENCER_455 0x31C7 701#define WM8994_WRITE_SEQUENCER_456 0x31C8 702#define WM8994_WRITE_SEQUENCER_457 0x31C9 703#define WM8994_WRITE_SEQUENCER_458 0x31CA 704#define WM8994_WRITE_SEQUENCER_459 0x31CB 705#define WM8994_WRITE_SEQUENCER_460 0x31CC 706#define WM8994_WRITE_SEQUENCER_461 0x31CD 707#define WM8994_WRITE_SEQUENCER_462 0x31CE 708#define WM8994_WRITE_SEQUENCER_463 0x31CF 709#define WM8994_WRITE_SEQUENCER_464 0x31D0 710#define WM8994_WRITE_SEQUENCER_465 0x31D1 711#define WM8994_WRITE_SEQUENCER_466 0x31D2 712#define WM8994_WRITE_SEQUENCER_467 0x31D3 713#define WM8994_WRITE_SEQUENCER_468 0x31D4 714#define WM8994_WRITE_SEQUENCER_469 0x31D5 715#define WM8994_WRITE_SEQUENCER_470 0x31D6 716#define WM8994_WRITE_SEQUENCER_471 0x31D7 717#define WM8994_WRITE_SEQUENCER_472 0x31D8 718#define WM8994_WRITE_SEQUENCER_473 0x31D9 719#define WM8994_WRITE_SEQUENCER_474 0x31DA 720#define WM8994_WRITE_SEQUENCER_475 0x31DB 721#define WM8994_WRITE_SEQUENCER_476 0x31DC 722#define WM8994_WRITE_SEQUENCER_477 0x31DD 723#define WM8994_WRITE_SEQUENCER_478 0x31DE 724#define WM8994_WRITE_SEQUENCER_479 0x31DF 725#define WM8994_WRITE_SEQUENCER_480 0x31E0 726#define WM8994_WRITE_SEQUENCER_481 0x31E1 727#define WM8994_WRITE_SEQUENCER_482 0x31E2 728#define WM8994_WRITE_SEQUENCER_483 0x31E3 729#define WM8994_WRITE_SEQUENCER_484 0x31E4 730#define WM8994_WRITE_SEQUENCER_485 0x31E5 731#define WM8994_WRITE_SEQUENCER_486 0x31E6 732#define WM8994_WRITE_SEQUENCER_487 0x31E7 733#define WM8994_WRITE_SEQUENCER_488 0x31E8 734#define WM8994_WRITE_SEQUENCER_489 0x31E9 735#define WM8994_WRITE_SEQUENCER_490 0x31EA 736#define WM8994_WRITE_SEQUENCER_491 0x31EB 737#define WM8994_WRITE_SEQUENCER_492 0x31EC 738#define WM8994_WRITE_SEQUENCER_493 0x31ED 739#define WM8994_WRITE_SEQUENCER_494 0x31EE 740#define WM8994_WRITE_SEQUENCER_495 0x31EF 741#define WM8994_WRITE_SEQUENCER_496 0x31F0 742#define WM8994_WRITE_SEQUENCER_497 0x31F1 743#define WM8994_WRITE_SEQUENCER_498 0x31F2 744#define WM8994_WRITE_SEQUENCER_499 0x31F3 745#define WM8994_WRITE_SEQUENCER_500 0x31F4 746#define WM8994_WRITE_SEQUENCER_501 0x31F5 747#define WM8994_WRITE_SEQUENCER_502 0x31F6 748#define WM8994_WRITE_SEQUENCER_503 0x31F7 749#define WM8994_WRITE_SEQUENCER_504 0x31F8 750#define WM8994_WRITE_SEQUENCER_505 0x31F9 751#define WM8994_WRITE_SEQUENCER_506 0x31FA 752#define WM8994_WRITE_SEQUENCER_507 0x31FB 753#define WM8994_WRITE_SEQUENCER_508 0x31FC 754#define WM8994_WRITE_SEQUENCER_509 0x31FD 755#define WM8994_WRITE_SEQUENCER_510 0x31FE 756#define WM8994_WRITE_SEQUENCER_511 0x31FF 757 758#define WM8994_REGISTER_COUNT 736 759#define WM8994_MAX_REGISTER 0x31FF 760#define WM8994_MAX_CACHED_REGISTER 0x749 761 762/* 763 * Field Definitions. 764 */ 765 766/* 767 * R0 (0x00) - Software Reset 768 */ 769#define WM8994_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 770#define WM8994_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 771#define WM8994_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 772 773/* 774 * R1 (0x01) - Power Management (1) 775 */ 776#define WM8994_SPKOUTR_ENA 0x2000 /* SPKOUTR_ENA */ 777#define WM8994_SPKOUTR_ENA_MASK 0x2000 /* SPKOUTR_ENA */ 778#define WM8994_SPKOUTR_ENA_SHIFT 13 /* SPKOUTR_ENA */ 779#define WM8994_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */ 780#define WM8994_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */ 781#define WM8994_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */ 782#define WM8994_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */ 783#define WM8994_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */ 784#define WM8994_HPOUT2_ENA 0x0800 /* HPOUT2_ENA */ 785#define WM8994_HPOUT2_ENA_MASK 0x0800 /* HPOUT2_ENA */ 786#define WM8994_HPOUT2_ENA_SHIFT 11 /* HPOUT2_ENA */ 787#define WM8994_HPOUT2_ENA_WIDTH 1 /* HPOUT2_ENA */ 788#define WM8994_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */ 789#define WM8994_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */ 790#define WM8994_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */ 791#define WM8994_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 792#define WM8994_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */ 793#define WM8994_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */ 794#define WM8994_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */ 795#define WM8994_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 796#define WM8994_MICB2_ENA 0x0020 /* MICB2_ENA */ 797#define WM8994_MICB2_ENA_MASK 0x0020 /* MICB2_ENA */ 798#define WM8994_MICB2_ENA_SHIFT 5 /* MICB2_ENA */ 799#define WM8994_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 800#define WM8994_MICB1_ENA 0x0010 /* MICB1_ENA */ 801#define WM8994_MICB1_ENA_MASK 0x0010 /* MICB1_ENA */ 802#define WM8994_MICB1_ENA_SHIFT 4 /* MICB1_ENA */ 803#define WM8994_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 804#define WM8994_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */ 805#define WM8994_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */ 806#define WM8994_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */ 807#define WM8994_BIAS_ENA 0x0001 /* BIAS_ENA */ 808#define WM8994_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 809#define WM8994_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 810#define WM8994_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 811 812/* 813 * R2 (0x02) - Power Management (2) 814 */ 815#define WM8994_TSHUT_ENA 0x4000 /* TSHUT_ENA */ 816#define WM8994_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */ 817#define WM8994_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */ 818#define WM8994_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */ 819#define WM8994_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ 820#define WM8994_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */ 821#define WM8994_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */ 822#define WM8994_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */ 823#define WM8994_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 824#define WM8994_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 825#define WM8994_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 826#define WM8994_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 827#define WM8994_MIXINL_ENA 0x0200 /* MIXINL_ENA */ 828#define WM8994_MIXINL_ENA_MASK 0x0200 /* MIXINL_ENA */ 829#define WM8994_MIXINL_ENA_SHIFT 9 /* MIXINL_ENA */ 830#define WM8994_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */ 831#define WM8994_MIXINR_ENA 0x0100 /* MIXINR_ENA */ 832#define WM8994_MIXINR_ENA_MASK 0x0100 /* MIXINR_ENA */ 833#define WM8994_MIXINR_ENA_SHIFT 8 /* MIXINR_ENA */ 834#define WM8994_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */ 835#define WM8994_IN2L_ENA 0x0080 /* IN2L_ENA */ 836#define WM8994_IN2L_ENA_MASK 0x0080 /* IN2L_ENA */ 837#define WM8994_IN2L_ENA_SHIFT 7 /* IN2L_ENA */ 838#define WM8994_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 839#define WM8994_IN1L_ENA 0x0040 /* IN1L_ENA */ 840#define WM8994_IN1L_ENA_MASK 0x0040 /* IN1L_ENA */ 841#define WM8994_IN1L_ENA_SHIFT 6 /* IN1L_ENA */ 842#define WM8994_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 843#define WM8994_IN2R_ENA 0x0020 /* IN2R_ENA */ 844#define WM8994_IN2R_ENA_MASK 0x0020 /* IN2R_ENA */ 845#define WM8994_IN2R_ENA_SHIFT 5 /* IN2R_ENA */ 846#define WM8994_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 847#define WM8994_IN1R_ENA 0x0010 /* IN1R_ENA */ 848#define WM8994_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ 849#define WM8994_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ 850#define WM8994_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 851 852/* 853 * R3 (0x03) - Power Management (3) 854 */ 855#define WM8994_LINEOUT1N_ENA 0x2000 /* LINEOUT1N_ENA */ 856#define WM8994_LINEOUT1N_ENA_MASK 0x2000 /* LINEOUT1N_ENA */ 857#define WM8994_LINEOUT1N_ENA_SHIFT 13 /* LINEOUT1N_ENA */ 858#define WM8994_LINEOUT1N_ENA_WIDTH 1 /* LINEOUT1N_ENA */ 859#define WM8994_LINEOUT1P_ENA 0x1000 /* LINEOUT1P_ENA */ 860#define WM8994_LINEOUT1P_ENA_MASK 0x1000 /* LINEOUT1P_ENA */ 861#define WM8994_LINEOUT1P_ENA_SHIFT 12 /* LINEOUT1P_ENA */ 862#define WM8994_LINEOUT1P_ENA_WIDTH 1 /* LINEOUT1P_ENA */ 863#define WM8994_LINEOUT2N_ENA 0x0800 /* LINEOUT2N_ENA */ 864#define WM8994_LINEOUT2N_ENA_MASK 0x0800 /* LINEOUT2N_ENA */ 865#define WM8994_LINEOUT2N_ENA_SHIFT 11 /* LINEOUT2N_ENA */ 866#define WM8994_LINEOUT2N_ENA_WIDTH 1 /* LINEOUT2N_ENA */ 867#define WM8994_LINEOUT2P_ENA 0x0400 /* LINEOUT2P_ENA */ 868#define WM8994_LINEOUT2P_ENA_MASK 0x0400 /* LINEOUT2P_ENA */ 869#define WM8994_LINEOUT2P_ENA_SHIFT 10 /* LINEOUT2P_ENA */ 870#define WM8994_LINEOUT2P_ENA_WIDTH 1 /* LINEOUT2P_ENA */ 871#define WM8994_SPKRVOL_ENA 0x0200 /* SPKRVOL_ENA */ 872#define WM8994_SPKRVOL_ENA_MASK 0x0200 /* SPKRVOL_ENA */ 873#define WM8994_SPKRVOL_ENA_SHIFT 9 /* SPKRVOL_ENA */ 874#define WM8994_SPKRVOL_ENA_WIDTH 1 /* SPKRVOL_ENA */ 875#define WM8994_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */ 876#define WM8994_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */ 877#define WM8994_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */ 878#define WM8994_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */ 879#define WM8994_MIXOUTLVOL_ENA 0x0080 /* MIXOUTLVOL_ENA */ 880#define WM8994_MIXOUTLVOL_ENA_MASK 0x0080 /* MIXOUTLVOL_ENA */ 881#define WM8994_MIXOUTLVOL_ENA_SHIFT 7 /* MIXOUTLVOL_ENA */ 882#define WM8994_MIXOUTLVOL_ENA_WIDTH 1 /* MIXOUTLVOL_ENA */ 883#define WM8994_MIXOUTRVOL_ENA 0x0040 /* MIXOUTRVOL_ENA */ 884#define WM8994_MIXOUTRVOL_ENA_MASK 0x0040 /* MIXOUTRVOL_ENA */ 885#define WM8994_MIXOUTRVOL_ENA_SHIFT 6 /* MIXOUTRVOL_ENA */ 886#define WM8994_MIXOUTRVOL_ENA_WIDTH 1 /* MIXOUTRVOL_ENA */ 887#define WM8994_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */ 888#define WM8994_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */ 889#define WM8994_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */ 890#define WM8994_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */ 891#define WM8994_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */ 892#define WM8994_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */ 893#define WM8994_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */ 894#define WM8994_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */ 895 896/* 897 * R4 (0x04) - Power Management (4) 898 */ 899#define WM8994_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ 900#define WM8994_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ 901#define WM8994_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ 902#define WM8994_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ 903#define WM8994_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ 904#define WM8994_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ 905#define WM8994_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ 906#define WM8994_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ 907#define WM8994_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ 908#define WM8994_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ 909#define WM8994_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ 910#define WM8994_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ 911#define WM8994_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ 912#define WM8994_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ 913#define WM8994_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ 914#define WM8994_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ 915#define WM8994_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ 916#define WM8994_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ 917#define WM8994_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ 918#define WM8994_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ 919#define WM8994_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ 920#define WM8994_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ 921#define WM8994_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ 922#define WM8994_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ 923#define WM8994_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 924#define WM8994_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 925#define WM8994_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 926#define WM8994_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 927#define WM8994_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 928#define WM8994_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 929#define WM8994_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 930#define WM8994_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 931#define WM8994_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 932#define WM8994_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 933#define WM8994_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 934#define WM8994_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 935#define WM8994_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 936#define WM8994_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 937#define WM8994_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 938#define WM8994_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 939#define WM8994_ADCL_ENA 0x0002 /* ADCL_ENA */ 940#define WM8994_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 941#define WM8994_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 942#define WM8994_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 943#define WM8994_ADCR_ENA 0x0001 /* ADCR_ENA */ 944#define WM8994_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 945#define WM8994_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 946#define WM8994_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 947 948/* 949 * R5 (0x05) - Power Management (5) 950 */ 951#define WM8994_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ 952#define WM8994_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ 953#define WM8994_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ 954#define WM8994_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ 955#define WM8994_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ 956#define WM8994_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ 957#define WM8994_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ 958#define WM8994_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ 959#define WM8994_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ 960#define WM8994_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ 961#define WM8994_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ 962#define WM8994_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ 963#define WM8994_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ 964#define WM8994_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ 965#define WM8994_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ 966#define WM8994_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ 967#define WM8994_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ 968#define WM8994_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ 969#define WM8994_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ 970#define WM8994_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ 971#define WM8994_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ 972#define WM8994_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ 973#define WM8994_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ 974#define WM8994_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ 975#define WM8994_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 976#define WM8994_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 977#define WM8994_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 978#define WM8994_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 979#define WM8994_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 980#define WM8994_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 981#define WM8994_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 982#define WM8994_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 983#define WM8994_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 984#define WM8994_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 985#define WM8994_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 986#define WM8994_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 987#define WM8994_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 988#define WM8994_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 989#define WM8994_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 990#define WM8994_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 991 992/* 993 * R6 (0x06) - Power Management (6) 994 */ 995#define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */ 996#define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ 997#define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ 998#define WM8994_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 999#define WM8994_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ 1000#define WM8994_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ 1001#define WM8994_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ 1002#define WM8994_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ 1003#define WM8994_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ 1004#define WM8994_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ 1005#define WM8994_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ 1006#define WM8994_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ 1007#define WM8994_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ 1008#define WM8994_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ 1009#define WM8994_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ 1010#define WM8994_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ 1011#define WM8994_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ 1012#define WM8994_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ 1013#define WM8994_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ 1014 1015/* 1016 * R21 (0x15) - Input Mixer (1) 1017 */ 1018#define WM8994_IN1RP_MIXINR_BOOST 0x0100 /* IN1RP_MIXINR_BOOST */ 1019#define WM8994_IN1RP_MIXINR_BOOST_MASK 0x0100 /* IN1RP_MIXINR_BOOST */ 1020#define WM8994_IN1RP_MIXINR_BOOST_SHIFT 8 /* IN1RP_MIXINR_BOOST */ 1021#define WM8994_IN1RP_MIXINR_BOOST_WIDTH 1 /* IN1RP_MIXINR_BOOST */ 1022#define WM8994_IN1LP_MIXINL_BOOST 0x0080 /* IN1LP_MIXINL_BOOST */ 1023#define WM8994_IN1LP_MIXINL_BOOST_MASK 0x0080 /* IN1LP_MIXINL_BOOST */ 1024#define WM8994_IN1LP_MIXINL_BOOST_SHIFT 7 /* IN1LP_MIXINL_BOOST */ 1025#define WM8994_IN1LP_MIXINL_BOOST_WIDTH 1 /* IN1LP_MIXINL_BOOST */ 1026#define WM8994_INPUTS_CLAMP 0x0040 /* INPUTS_CLAMP */ 1027#define WM8994_INPUTS_CLAMP_MASK 0x0040 /* INPUTS_CLAMP */ 1028#define WM8994_INPUTS_CLAMP_SHIFT 6 /* INPUTS_CLAMP */ 1029#define WM8994_INPUTS_CLAMP_WIDTH 1 /* INPUTS_CLAMP */ 1030 1031/* 1032 * R24 (0x18) - Left Line Input 1&2 Volume 1033 */ 1034#define WM8994_IN1_VU 0x0100 /* IN1_VU */ 1035#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */ 1036#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */ 1037#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */ 1038#define WM8994_IN1L_MUTE 0x0080 /* IN1L_MUTE */ 1039#define WM8994_IN1L_MUTE_MASK 0x0080 /* IN1L_MUTE */ 1040#define WM8994_IN1L_MUTE_SHIFT 7 /* IN1L_MUTE */ 1041#define WM8994_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 1042#define WM8994_IN1L_ZC 0x0040 /* IN1L_ZC */ 1043#define WM8994_IN1L_ZC_MASK 0x0040 /* IN1L_ZC */ 1044#define WM8994_IN1L_ZC_SHIFT 6 /* IN1L_ZC */ 1045#define WM8994_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 1046#define WM8994_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 1047#define WM8994_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 1048#define WM8994_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 1049 1050/* 1051 * R25 (0x19) - Left Line Input 3&4 Volume 1052 */ 1053#define WM8994_IN2_VU 0x0100 /* IN2_VU */ 1054#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */ 1055#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */ 1056#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */ 1057#define WM8994_IN2L_MUTE 0x0080 /* IN2L_MUTE */ 1058#define WM8994_IN2L_MUTE_MASK 0x0080 /* IN2L_MUTE */ 1059#define WM8994_IN2L_MUTE_SHIFT 7 /* IN2L_MUTE */ 1060#define WM8994_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 1061#define WM8994_IN2L_ZC 0x0040 /* IN2L_ZC */ 1062#define WM8994_IN2L_ZC_MASK 0x0040 /* IN2L_ZC */ 1063#define WM8994_IN2L_ZC_SHIFT 6 /* IN2L_ZC */ 1064#define WM8994_IN2L_ZC_WIDTH 1 /* IN2L_ZC */ 1065#define WM8994_IN2L_VOL_MASK 0x001F /* IN2L_VOL - [4:0] */ 1066#define WM8994_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [4:0] */ 1067#define WM8994_IN2L_VOL_WIDTH 5 /* IN2L_VOL - [4:0] */ 1068 1069/* 1070 * R26 (0x1A) - Right Line Input 1&2 Volume 1071 */ 1072#define WM8994_IN1_VU 0x0100 /* IN1_VU */ 1073#define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */ 1074#define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */ 1075#define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */ 1076#define WM8994_IN1R_MUTE 0x0080 /* IN1R_MUTE */ 1077#define WM8994_IN1R_MUTE_MASK 0x0080 /* IN1R_MUTE */ 1078#define WM8994_IN1R_MUTE_SHIFT 7 /* IN1R_MUTE */ 1079#define WM8994_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 1080#define WM8994_IN1R_ZC 0x0040 /* IN1R_ZC */ 1081#define WM8994_IN1R_ZC_MASK 0x0040 /* IN1R_ZC */ 1082#define WM8994_IN1R_ZC_SHIFT 6 /* IN1R_ZC */ 1083#define WM8994_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 1084#define WM8994_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 1085#define WM8994_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 1086#define WM8994_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 1087 1088/* 1089 * R27 (0x1B) - Right Line Input 3&4 Volume 1090 */ 1091#define WM8994_IN2_VU 0x0100 /* IN2_VU */ 1092#define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */ 1093#define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */ 1094#define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */ 1095#define WM8994_IN2R_MUTE 0x0080 /* IN2R_MUTE */ 1096#define WM8994_IN2R_MUTE_MASK 0x0080 /* IN2R_MUTE */ 1097#define WM8994_IN2R_MUTE_SHIFT 7 /* IN2R_MUTE */ 1098#define WM8994_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 1099#define WM8994_IN2R_ZC 0x0040 /* IN2R_ZC */ 1100#define WM8994_IN2R_ZC_MASK 0x0040 /* IN2R_ZC */ 1101#define WM8994_IN2R_ZC_SHIFT 6 /* IN2R_ZC */ 1102#define WM8994_IN2R_ZC_WIDTH 1 /* IN2R_ZC */ 1103#define WM8994_IN2R_VOL_MASK 0x001F /* IN2R_VOL - [4:0] */ 1104#define WM8994_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [4:0] */ 1105#define WM8994_IN2R_VOL_WIDTH 5 /* IN2R_VOL - [4:0] */ 1106 1107/* 1108 * R28 (0x1C) - Left Output Volume 1109 */ 1110#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 1111#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 1112#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 1113#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 1114#define WM8994_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ 1115#define WM8994_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ 1116#define WM8994_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ 1117#define WM8994_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 1118#define WM8994_HPOUT1L_MUTE_N 0x0040 /* HPOUT1L_MUTE_N */ 1119#define WM8994_HPOUT1L_MUTE_N_MASK 0x0040 /* HPOUT1L_MUTE_N */ 1120#define WM8994_HPOUT1L_MUTE_N_SHIFT 6 /* HPOUT1L_MUTE_N */ 1121#define WM8994_HPOUT1L_MUTE_N_WIDTH 1 /* HPOUT1L_MUTE_N */ 1122#define WM8994_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */ 1123#define WM8994_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */ 1124#define WM8994_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */ 1125 1126/* 1127 * R29 (0x1D) - Right Output Volume 1128 */ 1129#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 1130#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 1131#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 1132#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 1133#define WM8994_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ 1134#define WM8994_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ 1135#define WM8994_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ 1136#define WM8994_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 1137#define WM8994_HPOUT1R_MUTE_N 0x0040 /* HPOUT1R_MUTE_N */ 1138#define WM8994_HPOUT1R_MUTE_N_MASK 0x0040 /* HPOUT1R_MUTE_N */ 1139#define WM8994_HPOUT1R_MUTE_N_SHIFT 6 /* HPOUT1R_MUTE_N */ 1140#define WM8994_HPOUT1R_MUTE_N_WIDTH 1 /* HPOUT1R_MUTE_N */ 1141#define WM8994_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */ 1142#define WM8994_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */ 1143#define WM8994_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */ 1144 1145/* 1146 * R30 (0x1E) - Line Outputs Volume 1147 */ 1148#define WM8994_LINEOUT1N_MUTE 0x0040 /* LINEOUT1N_MUTE */ 1149#define WM8994_LINEOUT1N_MUTE_MASK 0x0040 /* LINEOUT1N_MUTE */ 1150#define WM8994_LINEOUT1N_MUTE_SHIFT 6 /* LINEOUT1N_MUTE */ 1151#define WM8994_LINEOUT1N_MUTE_WIDTH 1 /* LINEOUT1N_MUTE */ 1152#define WM8994_LINEOUT1P_MUTE 0x0020 /* LINEOUT1P_MUTE */ 1153#define WM8994_LINEOUT1P_MUTE_MASK 0x0020 /* LINEOUT1P_MUTE */ 1154#define WM8994_LINEOUT1P_MUTE_SHIFT 5 /* LINEOUT1P_MUTE */ 1155#define WM8994_LINEOUT1P_MUTE_WIDTH 1 /* LINEOUT1P_MUTE */ 1156#define WM8994_LINEOUT1_VOL 0x0010 /* LINEOUT1_VOL */ 1157#define WM8994_LINEOUT1_VOL_MASK 0x0010 /* LINEOUT1_VOL */ 1158#define WM8994_LINEOUT1_VOL_SHIFT 4 /* LINEOUT1_VOL */ 1159#define WM8994_LINEOUT1_VOL_WIDTH 1 /* LINEOUT1_VOL */ 1160#define WM8994_LINEOUT2N_MUTE 0x0004 /* LINEOUT2N_MUTE */ 1161#define WM8994_LINEOUT2N_MUTE_MASK 0x0004 /* LINEOUT2N_MUTE */ 1162#define WM8994_LINEOUT2N_MUTE_SHIFT 2 /* LINEOUT2N_MUTE */ 1163#define WM8994_LINEOUT2N_MUTE_WIDTH 1 /* LINEOUT2N_MUTE */ 1164#define WM8994_LINEOUT2P_MUTE 0x0002 /* LINEOUT2P_MUTE */ 1165#define WM8994_LINEOUT2P_MUTE_MASK 0x0002 /* LINEOUT2P_MUTE */ 1166#define WM8994_LINEOUT2P_MUTE_SHIFT 1 /* LINEOUT2P_MUTE */ 1167#define WM8994_LINEOUT2P_MUTE_WIDTH 1 /* LINEOUT2P_MUTE */ 1168#define WM8994_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */ 1169#define WM8994_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */ 1170#define WM8994_LINEOUT2_VOL_SHIFT 0 /* LINEOUT2_VOL */ 1171#define WM8994_LINEOUT2_VOL_WIDTH 1 /* LINEOUT2_VOL */ 1172 1173/* 1174 * R31 (0x1F) - HPOUT2 Volume 1175 */ 1176#define WM8994_HPOUT2_MUTE 0x0020 /* HPOUT2_MUTE */ 1177#define WM8994_HPOUT2_MUTE_MASK 0x0020 /* HPOUT2_MUTE */ 1178#define WM8994_HPOUT2_MUTE_SHIFT 5 /* HPOUT2_MUTE */ 1179#define WM8994_HPOUT2_MUTE_WIDTH 1 /* HPOUT2_MUTE */ 1180#define WM8994_HPOUT2_VOL 0x0010 /* HPOUT2_VOL */ 1181#define WM8994_HPOUT2_VOL_MASK 0x0010 /* HPOUT2_VOL */ 1182#define WM8994_HPOUT2_VOL_SHIFT 4 /* HPOUT2_VOL */ 1183#define WM8994_HPOUT2_VOL_WIDTH 1 /* HPOUT2_VOL */ 1184 1185/* 1186 * R32 (0x20) - Left OPGA Volume 1187 */ 1188#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */ 1189#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */ 1190#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */ 1191#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */ 1192#define WM8994_MIXOUTL_ZC 0x0080 /* MIXOUTL_ZC */ 1193#define WM8994_MIXOUTL_ZC_MASK 0x0080 /* MIXOUTL_ZC */ 1194#define WM8994_MIXOUTL_ZC_SHIFT 7 /* MIXOUTL_ZC */ 1195#define WM8994_MIXOUTL_ZC_WIDTH 1 /* MIXOUTL_ZC */ 1196#define WM8994_MIXOUTL_MUTE_N 0x0040 /* MIXOUTL_MUTE_N */ 1197#define WM8994_MIXOUTL_MUTE_N_MASK 0x0040 /* MIXOUTL_MUTE_N */ 1198#define WM8994_MIXOUTL_MUTE_N_SHIFT 6 /* MIXOUTL_MUTE_N */ 1199#define WM8994_MIXOUTL_MUTE_N_WIDTH 1 /* MIXOUTL_MUTE_N */ 1200#define WM8994_MIXOUTL_VOL_MASK 0x003F /* MIXOUTL_VOL - [5:0] */ 1201#define WM8994_MIXOUTL_VOL_SHIFT 0 /* MIXOUTL_VOL - [5:0] */ 1202#define WM8994_MIXOUTL_VOL_WIDTH 6 /* MIXOUTL_VOL - [5:0] */ 1203 1204/* 1205 * R33 (0x21) - Right OPGA Volume 1206 */ 1207#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */ 1208#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */ 1209#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */ 1210#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */ 1211#define WM8994_MIXOUTR_ZC 0x0080 /* MIXOUTR_ZC */ 1212#define WM8994_MIXOUTR_ZC_MASK 0x0080 /* MIXOUTR_ZC */ 1213#define WM8994_MIXOUTR_ZC_SHIFT 7 /* MIXOUTR_ZC */ 1214#define WM8994_MIXOUTR_ZC_WIDTH 1 /* MIXOUTR_ZC */ 1215#define WM8994_MIXOUTR_MUTE_N 0x0040 /* MIXOUTR_MUTE_N */ 1216#define WM8994_MIXOUTR_MUTE_N_MASK 0x0040 /* MIXOUTR_MUTE_N */ 1217#define WM8994_MIXOUTR_MUTE_N_SHIFT 6 /* MIXOUTR_MUTE_N */ 1218#define WM8994_MIXOUTR_MUTE_N_WIDTH 1 /* MIXOUTR_MUTE_N */ 1219#define WM8994_MIXOUTR_VOL_MASK 0x003F /* MIXOUTR_VOL - [5:0] */ 1220#define WM8994_MIXOUTR_VOL_SHIFT 0 /* MIXOUTR_VOL - [5:0] */ 1221#define WM8994_MIXOUTR_VOL_WIDTH 6 /* MIXOUTR_VOL - [5:0] */ 1222 1223/* 1224 * R34 (0x22) - SPKMIXL Attenuation 1225 */ 1226#define WM8994_DAC2L_SPKMIXL_VOL 0x0040 /* DAC2L_SPKMIXL_VOL */ 1227#define WM8994_DAC2L_SPKMIXL_VOL_MASK 0x0040 /* DAC2L_SPKMIXL_VOL */ 1228#define WM8994_DAC2L_SPKMIXL_VOL_SHIFT 6 /* DAC2L_SPKMIXL_VOL */ 1229#define WM8994_DAC2L_SPKMIXL_VOL_WIDTH 1 /* DAC2L_SPKMIXL_VOL */ 1230#define WM8994_MIXINL_SPKMIXL_VOL 0x0020 /* MIXINL_SPKMIXL_VOL */ 1231#define WM8994_MIXINL_SPKMIXL_VOL_MASK 0x0020 /* MIXINL_SPKMIXL_VOL */ 1232#define WM8994_MIXINL_SPKMIXL_VOL_SHIFT 5 /* MIXINL_SPKMIXL_VOL */ 1233#define WM8994_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */ 1234#define WM8994_IN1LP_SPKMIXL_VOL 0x0010 /* IN1LP_SPKMIXL_VOL */ 1235#define WM8994_IN1LP_SPKMIXL_VOL_MASK 0x0010 /* IN1LP_SPKMIXL_VOL */ 1236#define WM8994_IN1LP_SPKMIXL_VOL_SHIFT 4 /* IN1LP_SPKMIXL_VOL */ 1237#define WM8994_IN1LP_SPKMIXL_VOL_WIDTH 1 /* IN1LP_SPKMIXL_VOL */ 1238#define WM8994_MIXOUTL_SPKMIXL_VOL 0x0008 /* MIXOUTL_SPKMIXL_VOL */ 1239#define WM8994_MIXOUTL_SPKMIXL_VOL_MASK 0x0008 /* MIXOUTL_SPKMIXL_VOL */ 1240#define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT 3 /* MIXOUTL_SPKMIXL_VOL */ 1241#define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH 1 /* MIXOUTL_SPKMIXL_VOL */ 1242#define WM8994_DAC1L_SPKMIXL_VOL 0x0004 /* DAC1L_SPKMIXL_VOL */ 1243#define WM8994_DAC1L_SPKMIXL_VOL_MASK 0x0004 /* DAC1L_SPKMIXL_VOL */ 1244#define WM8994_DAC1L_SPKMIXL_VOL_SHIFT 2 /* DAC1L_SPKMIXL_VOL */ 1245#define WM8994_DAC1L_SPKMIXL_VOL_WIDTH 1 /* DAC1L_SPKMIXL_VOL */ 1246#define WM8994_SPKMIXL_VOL_MASK 0x0003 /* SPKMIXL_VOL - [1:0] */ 1247#define WM8994_SPKMIXL_VOL_SHIFT 0 /* SPKMIXL_VOL - [1:0] */ 1248#define WM8994_SPKMIXL_VOL_WIDTH 2 /* SPKMIXL_VOL - [1:0] */ 1249 1250/* 1251 * R35 (0x23) - SPKMIXR Attenuation 1252 */ 1253#define WM8994_SPKOUT_CLASSAB 0x0100 /* SPKOUT_CLASSAB */ 1254#define WM8994_SPKOUT_CLASSAB_MASK 0x0100 /* SPKOUT_CLASSAB */ 1255#define WM8994_SPKOUT_CLASSAB_SHIFT 8 /* SPKOUT_CLASSAB */ 1256#define WM8994_SPKOUT_CLASSAB_WIDTH 1 /* SPKOUT_CLASSAB */ 1257#define WM8994_DAC2R_SPKMIXR_VOL 0x0040 /* DAC2R_SPKMIXR_VOL */ 1258#define WM8994_DAC2R_SPKMIXR_VOL_MASK 0x0040 /* DAC2R_SPKMIXR_VOL */ 1259#define WM8994_DAC2R_SPKMIXR_VOL_SHIFT 6 /* DAC2R_SPKMIXR_VOL */ 1260#define WM8994_DAC2R_SPKMIXR_VOL_WIDTH 1 /* DAC2R_SPKMIXR_VOL */ 1261#define WM8994_MIXINR_SPKMIXR_VOL 0x0020 /* MIXINR_SPKMIXR_VOL */ 1262#define WM8994_MIXINR_SPKMIXR_VOL_MASK 0x0020 /* MIXINR_SPKMIXR_VOL */ 1263#define WM8994_MIXINR_SPKMIXR_VOL_SHIFT 5 /* MIXINR_SPKMIXR_VOL */ 1264#define WM8994_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */ 1265#define WM8994_IN1RP_SPKMIXR_VOL 0x0010 /* IN1RP_SPKMIXR_VOL */ 1266#define WM8994_IN1RP_SPKMIXR_VOL_MASK 0x0010 /* IN1RP_SPKMIXR_VOL */ 1267#define WM8994_IN1RP_SPKMIXR_VOL_SHIFT 4 /* IN1RP_SPKMIXR_VOL */ 1268#define WM8994_IN1RP_SPKMIXR_VOL_WIDTH 1 /* IN1RP_SPKMIXR_VOL */ 1269#define WM8994_MIXOUTR_SPKMIXR_VOL 0x0008 /* MIXOUTR_SPKMIXR_VOL */ 1270#define WM8994_MIXOUTR_SPKMIXR_VOL_MASK 0x0008 /* MIXOUTR_SPKMIXR_VOL */ 1271#define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT 3 /* MIXOUTR_SPKMIXR_VOL */ 1272#define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH 1 /* MIXOUTR_SPKMIXR_VOL */ 1273#define WM8994_DAC1R_SPKMIXR_VOL 0x0004 /* DAC1R_SPKMIXR_VOL */ 1274#define WM8994_DAC1R_SPKMIXR_VOL_MASK 0x0004 /* DAC1R_SPKMIXR_VOL */ 1275#define WM8994_DAC1R_SPKMIXR_VOL_SHIFT 2 /* DAC1R_SPKMIXR_VOL */ 1276#define WM8994_DAC1R_SPKMIXR_VOL_WIDTH 1 /* DAC1R_SPKMIXR_VOL */ 1277#define WM8994_SPKMIXR_VOL_MASK 0x0003 /* SPKMIXR_VOL - [1:0] */ 1278#define WM8994_SPKMIXR_VOL_SHIFT 0 /* SPKMIXR_VOL - [1:0] */ 1279#define WM8994_SPKMIXR_VOL_WIDTH 2 /* SPKMIXR_VOL - [1:0] */ 1280 1281/* 1282 * R36 (0x24) - SPKOUT Mixers 1283 */ 1284#define WM8994_IN2LRP_TO_SPKOUTL 0x0020 /* IN2LRP_TO_SPKOUTL */ 1285#define WM8994_IN2LRP_TO_SPKOUTL_MASK 0x0020 /* IN2LRP_TO_SPKOUTL */ 1286#define WM8994_IN2LRP_TO_SPKOUTL_SHIFT 5 /* IN2LRP_TO_SPKOUTL */ 1287#define WM8994_IN2LRP_TO_SPKOUTL_WIDTH 1 /* IN2LRP_TO_SPKOUTL */ 1288#define WM8994_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */ 1289#define WM8994_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */ 1290#define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */ 1291#define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */ 1292#define WM8994_SPKMIXR_TO_SPKOUTL 0x0008 /* SPKMIXR_TO_SPKOUTL */ 1293#define WM8994_SPKMIXR_TO_SPKOUTL_MASK 0x0008 /* SPKMIXR_TO_SPKOUTL */ 1294#define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT 3 /* SPKMIXR_TO_SPKOUTL */ 1295#define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH 1 /* SPKMIXR_TO_SPKOUTL */ 1296#define WM8994_IN2LRP_TO_SPKOUTR 0x0004 /* IN2LRP_TO_SPKOUTR */ 1297#define WM8994_IN2LRP_TO_SPKOUTR_MASK 0x0004 /* IN2LRP_TO_SPKOUTR */ 1298#define WM8994_IN2LRP_TO_SPKOUTR_SHIFT 2 /* IN2LRP_TO_SPKOUTR */ 1299#define WM8994_IN2LRP_TO_SPKOUTR_WIDTH 1 /* IN2LRP_TO_SPKOUTR */ 1300#define WM8994_SPKMIXL_TO_SPKOUTR 0x0002 /* SPKMIXL_TO_SPKOUTR */ 1301#define WM8994_SPKMIXL_TO_SPKOUTR_MASK 0x0002 /* SPKMIXL_TO_SPKOUTR */ 1302#define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT 1 /* SPKMIXL_TO_SPKOUTR */ 1303#define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH 1 /* SPKMIXL_TO_SPKOUTR */ 1304#define WM8994_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */ 1305#define WM8994_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */ 1306#define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT 0 /* SPKMIXR_TO_SPKOUTR */ 1307#define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH 1 /* SPKMIXR_TO_SPKOUTR */ 1308 1309/* 1310 * R37 (0x25) - ClassD 1311 */ 1312#define WM8994_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */ 1313#define WM8994_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */ 1314#define WM8994_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */ 1315#define WM8994_SPKOUTR_BOOST_MASK 0x0007 /* SPKOUTR_BOOST - [2:0] */ 1316#define WM8994_SPKOUTR_BOOST_SHIFT 0 /* SPKOUTR_BOOST - [2:0] */ 1317#define WM8994_SPKOUTR_BOOST_WIDTH 3 /* SPKOUTR_BOOST - [2:0] */ 1318 1319/* 1320 * R38 (0x26) - Speaker Volume Left 1321 */ 1322#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 1323#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 1324#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 1325#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 1326#define WM8994_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */ 1327#define WM8994_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */ 1328#define WM8994_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */ 1329#define WM8994_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */ 1330#define WM8994_SPKOUTL_MUTE_N 0x0040 /* SPKOUTL_MUTE_N */ 1331#define WM8994_SPKOUTL_MUTE_N_MASK 0x0040 /* SPKOUTL_MUTE_N */ 1332#define WM8994_SPKOUTL_MUTE_N_SHIFT 6 /* SPKOUTL_MUTE_N */ 1333#define WM8994_SPKOUTL_MUTE_N_WIDTH 1 /* SPKOUTL_MUTE_N */ 1334#define WM8994_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */ 1335#define WM8994_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */ 1336#define WM8994_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */ 1337 1338/* 1339 * R39 (0x27) - Speaker Volume Right 1340 */ 1341#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 1342#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 1343#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 1344#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 1345#define WM8994_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */ 1346#define WM8994_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */ 1347#define WM8994_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */ 1348#define WM8994_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */ 1349#define WM8994_SPKOUTR_MUTE_N 0x0040 /* SPKOUTR_MUTE_N */ 1350#define WM8994_SPKOUTR_MUTE_N_MASK 0x0040 /* SPKOUTR_MUTE_N */ 1351#define WM8994_SPKOUTR_MUTE_N_SHIFT 6 /* SPKOUTR_MUTE_N */ 1352#define WM8994_SPKOUTR_MUTE_N_WIDTH 1 /* SPKOUTR_MUTE_N */ 1353#define WM8994_SPKOUTR_VOL_MASK 0x003F /* SPKOUTR_VOL - [5:0] */ 1354#define WM8994_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [5:0] */ 1355#define WM8994_SPKOUTR_VOL_WIDTH 6 /* SPKOUTR_VOL - [5:0] */ 1356 1357/* 1358 * R40 (0x28) - Input Mixer (2) 1359 */ 1360#define WM8994_IN2LP_TO_IN2L 0x0080 /* IN2LP_TO_IN2L */ 1361#define WM8994_IN2LP_TO_IN2L_MASK 0x0080 /* IN2LP_TO_IN2L */ 1362#define WM8994_IN2LP_TO_IN2L_SHIFT 7 /* IN2LP_TO_IN2L */ 1363#define WM8994_IN2LP_TO_IN2L_WIDTH 1 /* IN2LP_TO_IN2L */ 1364#define WM8994_IN2LN_TO_IN2L 0x0040 /* IN2LN_TO_IN2L */ 1365#define WM8994_IN2LN_TO_IN2L_MASK 0x0040 /* IN2LN_TO_IN2L */ 1366#define WM8994_IN2LN_TO_IN2L_SHIFT 6 /* IN2LN_TO_IN2L */ 1367#define WM8994_IN2LN_TO_IN2L_WIDTH 1 /* IN2LN_TO_IN2L */ 1368#define WM8994_IN1LP_TO_IN1L 0x0020 /* IN1LP_TO_IN1L */ 1369#define WM8994_IN1LP_TO_IN1L_MASK 0x0020 /* IN1LP_TO_IN1L */ 1370#define WM8994_IN1LP_TO_IN1L_SHIFT 5 /* IN1LP_TO_IN1L */ 1371#define WM8994_IN1LP_TO_IN1L_WIDTH 1 /* IN1LP_TO_IN1L */ 1372#define WM8994_IN1LN_TO_IN1L 0x0010 /* IN1LN_TO_IN1L */ 1373#define WM8994_IN1LN_TO_IN1L_MASK 0x0010 /* IN1LN_TO_IN1L */ 1374#define WM8994_IN1LN_TO_IN1L_SHIFT 4 /* IN1LN_TO_IN1L */ 1375#define WM8994_IN1LN_TO_IN1L_WIDTH 1 /* IN1LN_TO_IN1L */ 1376#define WM8994_IN2RP_TO_IN2R 0x0008 /* IN2RP_TO_IN2R */ 1377#define WM8994_IN2RP_TO_IN2R_MASK 0x0008 /* IN2RP_TO_IN2R */ 1378#define WM8994_IN2RP_TO_IN2R_SHIFT 3 /* IN2RP_TO_IN2R */ 1379#define WM8994_IN2RP_TO_IN2R_WIDTH 1 /* IN2RP_TO_IN2R */ 1380#define WM8994_IN2RN_TO_IN2R 0x0004 /* IN2RN_TO_IN2R */ 1381#define WM8994_IN2RN_TO_IN2R_MASK 0x0004 /* IN2RN_TO_IN2R */ 1382#define WM8994_IN2RN_TO_IN2R_SHIFT 2 /* IN2RN_TO_IN2R */ 1383#define WM8994_IN2RN_TO_IN2R_WIDTH 1 /* IN2RN_TO_IN2R */ 1384#define WM8994_IN1RP_TO_IN1R 0x0002 /* IN1RP_TO_IN1R */ 1385#define WM8994_IN1RP_TO_IN1R_MASK 0x0002 /* IN1RP_TO_IN1R */ 1386#define WM8994_IN1RP_TO_IN1R_SHIFT 1 /* IN1RP_TO_IN1R */ 1387#define WM8994_IN1RP_TO_IN1R_WIDTH 1 /* IN1RP_TO_IN1R */ 1388#define WM8994_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */ 1389#define WM8994_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */ 1390#define WM8994_IN1RN_TO_IN1R_SHIFT 0 /* IN1RN_TO_IN1R */ 1391#define WM8994_IN1RN_TO_IN1R_WIDTH 1 /* IN1RN_TO_IN1R */ 1392 1393/* 1394 * R41 (0x29) - Input Mixer (3) 1395 */ 1396#define WM8994_IN2L_TO_MIXINL 0x0100 /* IN2L_TO_MIXINL */ 1397#define WM8994_IN2L_TO_MIXINL_MASK 0x0100 /* IN2L_TO_MIXINL */ 1398#define WM8994_IN2L_TO_MIXINL_SHIFT 8 /* IN2L_TO_MIXINL */ 1399#define WM8994_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */ 1400#define WM8994_IN2L_MIXINL_VOL 0x0080 /* IN2L_MIXINL_VOL */ 1401#define WM8994_IN2L_MIXINL_VOL_MASK 0x0080 /* IN2L_MIXINL_VOL */ 1402#define WM8994_IN2L_MIXINL_VOL_SHIFT 7 /* IN2L_MIXINL_VOL */ 1403#define WM8994_IN2L_MIXINL_VOL_WIDTH 1 /* IN2L_MIXINL_VOL */ 1404#define WM8994_IN1L_TO_MIXINL 0x0020 /* IN1L_TO_MIXINL */ 1405#define WM8994_IN1L_TO_MIXINL_MASK 0x0020 /* IN1L_TO_MIXINL */ 1406#define WM8994_IN1L_TO_MIXINL_SHIFT 5 /* IN1L_TO_MIXINL */ 1407#define WM8994_IN1L_TO_MIXINL_WIDTH 1 /* IN1L_TO_MIXINL */ 1408#define WM8994_IN1L_MIXINL_VOL 0x0010 /* IN1L_MIXINL_VOL */ 1409#define WM8994_IN1L_MIXINL_VOL_MASK 0x0010 /* IN1L_MIXINL_VOL */ 1410#define WM8994_IN1L_MIXINL_VOL_SHIFT 4 /* IN1L_MIXINL_VOL */ 1411#define WM8994_IN1L_MIXINL_VOL_WIDTH 1 /* IN1L_MIXINL_VOL */ 1412#define WM8994_MIXOUTL_MIXINL_VOL_MASK 0x0007 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1413#define WM8994_MIXOUTL_MIXINL_VOL_SHIFT 0 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1414#define WM8994_MIXOUTL_MIXINL_VOL_WIDTH 3 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1415 1416/* 1417 * R42 (0x2A) - Input Mixer (4) 1418 */ 1419#define WM8994_IN2R_TO_MIXINR 0x0100 /* IN2R_TO_MIXINR */ 1420#define WM8994_IN2R_TO_MIXINR_MASK 0x0100 /* IN2R_TO_MIXINR */ 1421#define WM8994_IN2R_TO_MIXINR_SHIFT 8 /* IN2R_TO_MIXINR */ 1422#define WM8994_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */ 1423#define WM8994_IN2R_MIXINR_VOL 0x0080 /* IN2R_MIXINR_VOL */ 1424#define WM8994_IN2R_MIXINR_VOL_MASK 0x0080 /* IN2R_MIXINR_VOL */ 1425#define WM8994_IN2R_MIXINR_VOL_SHIFT 7 /* IN2R_MIXINR_VOL */ 1426#define WM8994_IN2R_MIXINR_VOL_WIDTH 1 /* IN2R_MIXINR_VOL */ 1427#define WM8994_IN1R_TO_MIXINR 0x0020 /* IN1R_TO_MIXINR */ 1428#define WM8994_IN1R_TO_MIXINR_MASK 0x0020 /* IN1R_TO_MIXINR */ 1429#define WM8994_IN1R_TO_MIXINR_SHIFT 5 /* IN1R_TO_MIXINR */ 1430#define WM8994_IN1R_TO_MIXINR_WIDTH 1 /* IN1R_TO_MIXINR */ 1431#define WM8994_IN1R_MIXINR_VOL 0x0010 /* IN1R_MIXINR_VOL */ 1432#define WM8994_IN1R_MIXINR_VOL_MASK 0x0010 /* IN1R_MIXINR_VOL */ 1433#define WM8994_IN1R_MIXINR_VOL_SHIFT 4 /* IN1R_MIXINR_VOL */ 1434#define WM8994_IN1R_MIXINR_VOL_WIDTH 1 /* IN1R_MIXINR_VOL */ 1435#define WM8994_MIXOUTR_MIXINR_VOL_MASK 0x0007 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1436#define WM8994_MIXOUTR_MIXINR_VOL_SHIFT 0 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1437#define WM8994_MIXOUTR_MIXINR_VOL_WIDTH 3 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1438 1439/* 1440 * R43 (0x2B) - Input Mixer (5) 1441 */ 1442#define WM8994_IN1LP_MIXINL_VOL_MASK 0x01C0 /* IN1LP_MIXINL_VOL - [8:6] */ 1443#define WM8994_IN1LP_MIXINL_VOL_SHIFT 6 /* IN1LP_MIXINL_VOL - [8:6] */ 1444#define WM8994_IN1LP_MIXINL_VOL_WIDTH 3 /* IN1LP_MIXINL_VOL - [8:6] */ 1445#define WM8994_IN2LRP_MIXINL_VOL_MASK 0x0007 /* IN2LRP_MIXINL_VOL - [2:0] */ 1446#define WM8994_IN2LRP_MIXINL_VOL_SHIFT 0 /* IN2LRP_MIXINL_VOL - [2:0] */ 1447#define WM8994_IN2LRP_MIXINL_VOL_WIDTH 3 /* IN2LRP_MIXINL_VOL - [2:0] */ 1448 1449/* 1450 * R44 (0x2C) - Input Mixer (6) 1451 */ 1452#define WM8994_IN1RP_MIXINR_VOL_MASK 0x01C0 /* IN1RP_MIXINR_VOL - [8:6] */ 1453#define WM8994_IN1RP_MIXINR_VOL_SHIFT 6 /* IN1RP_MIXINR_VOL - [8:6] */ 1454#define WM8994_IN1RP_MIXINR_VOL_WIDTH 3 /* IN1RP_MIXINR_VOL - [8:6] */ 1455#define WM8994_IN2LRP_MIXINR_VOL_MASK 0x0007 /* IN2LRP_MIXINR_VOL - [2:0] */ 1456#define WM8994_IN2LRP_MIXINR_VOL_SHIFT 0 /* IN2LRP_MIXINR_VOL - [2:0] */ 1457#define WM8994_IN2LRP_MIXINR_VOL_WIDTH 3 /* IN2LRP_MIXINR_VOL - [2:0] */ 1458 1459/* 1460 * R45 (0x2D) - Output Mixer (1) 1461 */ 1462#define WM8994_DAC1L_TO_HPOUT1L 0x0100 /* DAC1L_TO_HPOUT1L */ 1463#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 /* DAC1L_TO_HPOUT1L */ 1464#define WM8994_DAC1L_TO_HPOUT1L_SHIFT 8 /* DAC1L_TO_HPOUT1L */ 1465#define WM8994_DAC1L_TO_HPOUT1L_WIDTH 1 /* DAC1L_TO_HPOUT1L */ 1466#define WM8994_MIXINR_TO_MIXOUTL 0x0080 /* MIXINR_TO_MIXOUTL */ 1467#define WM8994_MIXINR_TO_MIXOUTL_MASK 0x0080 /* MIXINR_TO_MIXOUTL */ 1468#define WM8994_MIXINR_TO_MIXOUTL_SHIFT 7 /* MIXINR_TO_MIXOUTL */ 1469#define WM8994_MIXINR_TO_MIXOUTL_WIDTH 1 /* MIXINR_TO_MIXOUTL */ 1470#define WM8994_MIXINL_TO_MIXOUTL 0x0040 /* MIXINL_TO_MIXOUTL */ 1471#define WM8994_MIXINL_TO_MIXOUTL_MASK 0x0040 /* MIXINL_TO_MIXOUTL */ 1472#define WM8994_MIXINL_TO_MIXOUTL_SHIFT 6 /* MIXINL_TO_MIXOUTL */ 1473#define WM8994_MIXINL_TO_MIXOUTL_WIDTH 1 /* MIXINL_TO_MIXOUTL */ 1474#define WM8994_IN2RN_TO_MIXOUTL 0x0020 /* IN2RN_TO_MIXOUTL */ 1475#define WM8994_IN2RN_TO_MIXOUTL_MASK 0x0020 /* IN2RN_TO_MIXOUTL */ 1476#define WM8994_IN2RN_TO_MIXOUTL_SHIFT 5 /* IN2RN_TO_MIXOUTL */ 1477#define WM8994_IN2RN_TO_MIXOUTL_WIDTH 1 /* IN2RN_TO_MIXOUTL */ 1478#define WM8994_IN2LN_TO_MIXOUTL 0x0010 /* IN2LN_TO_MIXOUTL */ 1479#define WM8994_IN2LN_TO_MIXOUTL_MASK 0x0010 /* IN2LN_TO_MIXOUTL */ 1480#define WM8994_IN2LN_TO_MIXOUTL_SHIFT 4 /* IN2LN_TO_MIXOUTL */ 1481#define WM8994_IN2LN_TO_MIXOUTL_WIDTH 1 /* IN2LN_TO_MIXOUTL */ 1482#define WM8994_IN1R_TO_MIXOUTL 0x0008 /* IN1R_TO_MIXOUTL */ 1483#define WM8994_IN1R_TO_MIXOUTL_MASK 0x0008 /* IN1R_TO_MIXOUTL */ 1484#define WM8994_IN1R_TO_MIXOUTL_SHIFT 3 /* IN1R_TO_MIXOUTL */ 1485#define WM8994_IN1R_TO_MIXOUTL_WIDTH 1 /* IN1R_TO_MIXOUTL */ 1486#define WM8994_IN1L_TO_MIXOUTL 0x0004 /* IN1L_TO_MIXOUTL */ 1487#define WM8994_IN1L_TO_MIXOUTL_MASK 0x0004 /* IN1L_TO_MIXOUTL */ 1488#define WM8994_IN1L_TO_MIXOUTL_SHIFT 2 /* IN1L_TO_MIXOUTL */ 1489#define WM8994_IN1L_TO_MIXOUTL_WIDTH 1 /* IN1L_TO_MIXOUTL */ 1490#define WM8994_IN2LP_TO_MIXOUTL 0x0002 /* IN2LP_TO_MIXOUTL */ 1491#define WM8994_IN2LP_TO_MIXOUTL_MASK 0x0002 /* IN2LP_TO_MIXOUTL */ 1492#define WM8994_IN2LP_TO_MIXOUTL_SHIFT 1 /* IN2LP_TO_MIXOUTL */ 1493#define WM8994_IN2LP_TO_MIXOUTL_WIDTH 1 /* IN2LP_TO_MIXOUTL */ 1494#define WM8994_DAC1L_TO_MIXOUTL 0x0001 /* DAC1L_TO_MIXOUTL */ 1495#define WM8994_DAC1L_TO_MIXOUTL_MASK 0x0001 /* DAC1L_TO_MIXOUTL */ 1496#define WM8994_DAC1L_TO_MIXOUTL_SHIFT 0 /* DAC1L_TO_MIXOUTL */ 1497#define WM8994_DAC1L_TO_MIXOUTL_WIDTH 1 /* DAC1L_TO_MIXOUTL */ 1498 1499/* 1500 * R46 (0x2E) - Output Mixer (2) 1501 */ 1502#define WM8994_DAC1R_TO_HPOUT1R 0x0100 /* DAC1R_TO_HPOUT1R */ 1503#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 /* DAC1R_TO_HPOUT1R */ 1504#define WM8994_DAC1R_TO_HPOUT1R_SHIFT 8 /* DAC1R_TO_HPOUT1R */ 1505#define WM8994_DAC1R_TO_HPOUT1R_WIDTH 1 /* DAC1R_TO_HPOUT1R */ 1506#define WM8994_MIXINL_TO_MIXOUTR 0x0080 /* MIXINL_TO_MIXOUTR */ 1507#define WM8994_MIXINL_TO_MIXOUTR_MASK 0x0080 /* MIXINL_TO_MIXOUTR */ 1508#define WM8994_MIXINL_TO_MIXOUTR_SHIFT 7 /* MIXINL_TO_MIXOUTR */ 1509#define WM8994_MIXINL_TO_MIXOUTR_WIDTH 1 /* MIXINL_TO_MIXOUTR */ 1510#define WM8994_MIXINR_TO_MIXOUTR 0x0040 /* MIXINR_TO_MIXOUTR */ 1511#define WM8994_MIXINR_TO_MIXOUTR_MASK 0x0040 /* MIXINR_TO_MIXOUTR */ 1512#define WM8994_MIXINR_TO_MIXOUTR_SHIFT 6 /* MIXINR_TO_MIXOUTR */ 1513#define WM8994_MIXINR_TO_MIXOUTR_WIDTH 1 /* MIXINR_TO_MIXOUTR */ 1514#define WM8994_IN2LN_TO_MIXOUTR 0x0020 /* IN2LN_TO_MIXOUTR */ 1515#define WM8994_IN2LN_TO_MIXOUTR_MASK 0x0020 /* IN2LN_TO_MIXOUTR */ 1516#define WM8994_IN2LN_TO_MIXOUTR_SHIFT 5 /* IN2LN_TO_MIXOUTR */ 1517#define WM8994_IN2LN_TO_MIXOUTR_WIDTH 1 /* IN2LN_TO_MIXOUTR */ 1518#define WM8994_IN2RN_TO_MIXOUTR 0x0010 /* IN2RN_TO_MIXOUTR */ 1519#define WM8994_IN2RN_TO_MIXOUTR_MASK 0x0010 /* IN2RN_TO_MIXOUTR */ 1520#define WM8994_IN2RN_TO_MIXOUTR_SHIFT 4 /* IN2RN_TO_MIXOUTR */ 1521#define WM8994_IN2RN_TO_MIXOUTR_WIDTH 1 /* IN2RN_TO_MIXOUTR */ 1522#define WM8994_IN1L_TO_MIXOUTR 0x0008 /* IN1L_TO_MIXOUTR */ 1523#define WM8994_IN1L_TO_MIXOUTR_MASK 0x0008 /* IN1L_TO_MIXOUTR */ 1524#define WM8994_IN1L_TO_MIXOUTR_SHIFT 3 /* IN1L_TO_MIXOUTR */ 1525#define WM8994_IN1L_TO_MIXOUTR_WIDTH 1 /* IN1L_TO_MIXOUTR */ 1526#define WM8994_IN1R_TO_MIXOUTR 0x0004 /* IN1R_TO_MIXOUTR */ 1527#define WM8994_IN1R_TO_MIXOUTR_MASK 0x0004 /* IN1R_TO_MIXOUTR */ 1528#define WM8994_IN1R_TO_MIXOUTR_SHIFT 2 /* IN1R_TO_MIXOUTR */ 1529#define WM8994_IN1R_TO_MIXOUTR_WIDTH 1 /* IN1R_TO_MIXOUTR */ 1530#define WM8994_IN2RP_TO_MIXOUTR 0x0002 /* IN2RP_TO_MIXOUTR */ 1531#define WM8994_IN2RP_TO_MIXOUTR_MASK 0x0002 /* IN2RP_TO_MIXOUTR */ 1532#define WM8994_IN2RP_TO_MIXOUTR_SHIFT 1 /* IN2RP_TO_MIXOUTR */ 1533#define WM8994_IN2RP_TO_MIXOUTR_WIDTH 1 /* IN2RP_TO_MIXOUTR */ 1534#define WM8994_DAC1R_TO_MIXOUTR 0x0001 /* DAC1R_TO_MIXOUTR */ 1535#define WM8994_DAC1R_TO_MIXOUTR_MASK 0x0001 /* DAC1R_TO_MIXOUTR */ 1536#define WM8994_DAC1R_TO_MIXOUTR_SHIFT 0 /* DAC1R_TO_MIXOUTR */ 1537#define WM8994_DAC1R_TO_MIXOUTR_WIDTH 1 /* DAC1R_TO_MIXOUTR */ 1538 1539/* 1540 * R47 (0x2F) - Output Mixer (3) 1541 */ 1542#define WM8994_IN2LP_MIXOUTL_VOL_MASK 0x0E00 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1543#define WM8994_IN2LP_MIXOUTL_VOL_SHIFT 9 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1544#define WM8994_IN2LP_MIXOUTL_VOL_WIDTH 3 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1545#define WM8994_IN2LN_MIXOUTL_VOL_MASK 0x01C0 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1546#define WM8994_IN2LN_MIXOUTL_VOL_SHIFT 6 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1547#define WM8994_IN2LN_MIXOUTL_VOL_WIDTH 3 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1548#define WM8994_IN1R_MIXOUTL_VOL_MASK 0x0038 /* IN1R_MIXOUTL_VOL - [5:3] */ 1549#define WM8994_IN1R_MIXOUTL_VOL_SHIFT 3 /* IN1R_MIXOUTL_VOL - [5:3] */ 1550#define WM8994_IN1R_MIXOUTL_VOL_WIDTH 3 /* IN1R_MIXOUTL_VOL - [5:3] */ 1551#define WM8994_IN1L_MIXOUTL_VOL_MASK 0x0007 /* IN1L_MIXOUTL_VOL - [2:0] */ 1552#define WM8994_IN1L_MIXOUTL_VOL_SHIFT 0 /* IN1L_MIXOUTL_VOL - [2:0] */ 1553#define WM8994_IN1L_MIXOUTL_VOL_WIDTH 3 /* IN1L_MIXOUTL_VOL - [2:0] */ 1554 1555/* 1556 * R48 (0x30) - Output Mixer (4) 1557 */ 1558#define WM8994_IN2RP_MIXOUTR_VOL_MASK 0x0E00 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1559#define WM8994_IN2RP_MIXOUTR_VOL_SHIFT 9 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1560#define WM8994_IN2RP_MIXOUTR_VOL_WIDTH 3 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1561#define WM8994_IN2RN_MIXOUTR_VOL_MASK 0x01C0 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1562#define WM8994_IN2RN_MIXOUTR_VOL_SHIFT 6 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1563#define WM8994_IN2RN_MIXOUTR_VOL_WIDTH 3 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1564#define WM8994_IN1L_MIXOUTR_VOL_MASK 0x0038 /* IN1L_MIXOUTR_VOL - [5:3] */ 1565#define WM8994_IN1L_MIXOUTR_VOL_SHIFT 3 /* IN1L_MIXOUTR_VOL - [5:3] */ 1566#define WM8994_IN1L_MIXOUTR_VOL_WIDTH 3 /* IN1L_MIXOUTR_VOL - [5:3] */ 1567#define WM8994_IN1R_MIXOUTR_VOL_MASK 0x0007 /* IN1R_MIXOUTR_VOL - [2:0] */ 1568#define WM8994_IN1R_MIXOUTR_VOL_SHIFT 0 /* IN1R_MIXOUTR_VOL - [2:0] */ 1569#define WM8994_IN1R_MIXOUTR_VOL_WIDTH 3 /* IN1R_MIXOUTR_VOL - [2:0] */ 1570 1571/* 1572 * R49 (0x31) - Output Mixer (5) 1573 */ 1574#define WM8994_DAC1L_MIXOUTL_VOL_MASK 0x0E00 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1575#define WM8994_DAC1L_MIXOUTL_VOL_SHIFT 9 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1576#define WM8994_DAC1L_MIXOUTL_VOL_WIDTH 3 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1577#define WM8994_IN2RN_MIXOUTL_VOL_MASK 0x01C0 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1578#define WM8994_IN2RN_MIXOUTL_VOL_SHIFT 6 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1579#define WM8994_IN2RN_MIXOUTL_VOL_WIDTH 3 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1580#define WM8994_MIXINR_MIXOUTL_VOL_MASK 0x0038 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1581#define WM8994_MIXINR_MIXOUTL_VOL_SHIFT 3 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1582#define WM8994_MIXINR_MIXOUTL_VOL_WIDTH 3 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1583#define WM8994_MIXINL_MIXOUTL_VOL_MASK 0x0007 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1584#define WM8994_MIXINL_MIXOUTL_VOL_SHIFT 0 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1585#define WM8994_MIXINL_MIXOUTL_VOL_WIDTH 3 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1586 1587/* 1588 * R50 (0x32) - Output Mixer (6) 1589 */ 1590#define WM8994_DAC1R_MIXOUTR_VOL_MASK 0x0E00 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1591#define WM8994_DAC1R_MIXOUTR_VOL_SHIFT 9 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1592#define WM8994_DAC1R_MIXOUTR_VOL_WIDTH 3 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1593#define WM8994_IN2LN_MIXOUTR_VOL_MASK 0x01C0 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1594#define WM8994_IN2LN_MIXOUTR_VOL_SHIFT 6 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1595#define WM8994_IN2LN_MIXOUTR_VOL_WIDTH 3 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1596#define WM8994_MIXINL_MIXOUTR_VOL_MASK 0x0038 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1597#define WM8994_MIXINL_MIXOUTR_VOL_SHIFT 3 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1598#define WM8994_MIXINL_MIXOUTR_VOL_WIDTH 3 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1599#define WM8994_MIXINR_MIXOUTR_VOL_MASK 0x0007 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1600#define WM8994_MIXINR_MIXOUTR_VOL_SHIFT 0 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1601#define WM8994_MIXINR_MIXOUTR_VOL_WIDTH 3 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1602 1603/* 1604 * R51 (0x33) - HPOUT2 Mixer 1605 */ 1606#define WM8994_IN2LRP_TO_HPOUT2 0x0020 /* IN2LRP_TO_HPOUT2 */ 1607#define WM8994_IN2LRP_TO_HPOUT2_MASK 0x0020 /* IN2LRP_TO_HPOUT2 */ 1608#define WM8994_IN2LRP_TO_HPOUT2_SHIFT 5 /* IN2LRP_TO_HPOUT2 */ 1609#define WM8994_IN2LRP_TO_HPOUT2_WIDTH 1 /* IN2LRP_TO_HPOUT2 */ 1610#define WM8994_MIXOUTLVOL_TO_HPOUT2 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */ 1611#define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */ 1612#define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT 4 /* MIXOUTLVOL_TO_HPOUT2 */ 1613#define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTLVOL_TO_HPOUT2 */ 1614#define WM8994_MIXOUTRVOL_TO_HPOUT2 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */ 1615#define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */ 1616#define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT 3 /* MIXOUTRVOL_TO_HPOUT2 */ 1617#define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTRVOL_TO_HPOUT2 */ 1618 1619/* 1620 * R52 (0x34) - Line Mixer (1) 1621 */ 1622#define WM8994_MIXOUTL_TO_LINEOUT1N 0x0040 /* MIXOUTL_TO_LINEOUT1N */ 1623#define WM8994_MIXOUTL_TO_LINEOUT1N_MASK 0x0040 /* MIXOUTL_TO_LINEOUT1N */ 1624#define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT 6 /* MIXOUTL_TO_LINEOUT1N */ 1625#define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH 1 /* MIXOUTL_TO_LINEOUT1N */ 1626#define WM8994_MIXOUTR_TO_LINEOUT1N 0x0020 /* MIXOUTR_TO_LINEOUT1N */ 1627#define WM8994_MIXOUTR_TO_LINEOUT1N_MASK 0x0020 /* MIXOUTR_TO_LINEOUT1N */ 1628#define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT 5 /* MIXOUTR_TO_LINEOUT1N */ 1629#define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH 1 /* MIXOUTR_TO_LINEOUT1N */ 1630#define WM8994_LINEOUT1_MODE 0x0010 /* LINEOUT1_MODE */ 1631#define WM8994_LINEOUT1_MODE_MASK 0x0010 /* LINEOUT1_MODE */ 1632#define WM8994_LINEOUT1_MODE_SHIFT 4 /* LINEOUT1_MODE */ 1633#define WM8994_LINEOUT1_MODE_WIDTH 1 /* LINEOUT1_MODE */ 1634#define WM8994_IN1R_TO_LINEOUT1P 0x0004 /* IN1R_TO_LINEOUT1P */ 1635#define WM8994_IN1R_TO_LINEOUT1P_MASK 0x0004 /* IN1R_TO_LINEOUT1P */ 1636#define WM8994_IN1R_TO_LINEOUT1P_SHIFT 2 /* IN1R_TO_LINEOUT1P */ 1637#define WM8994_IN1R_TO_LINEOUT1P_WIDTH 1 /* IN1R_TO_LINEOUT1P */ 1638#define WM8994_IN1L_TO_LINEOUT1P 0x0002 /* IN1L_TO_LINEOUT1P */ 1639#define WM8994_IN1L_TO_LINEOUT1P_MASK 0x0002 /* IN1L_TO_LINEOUT1P */ 1640#define WM8994_IN1L_TO_LINEOUT1P_SHIFT 1 /* IN1L_TO_LINEOUT1P */ 1641#define WM8994_IN1L_TO_LINEOUT1P_WIDTH 1 /* IN1L_TO_LINEOUT1P */ 1642#define WM8994_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */ 1643#define WM8994_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */ 1644#define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT 0 /* MIXOUTL_TO_LINEOUT1P */ 1645#define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH 1 /* MIXOUTL_TO_LINEOUT1P */ 1646 1647/* 1648 * R53 (0x35) - Line Mixer (2) 1649 */ 1650#define WM8994_MIXOUTR_TO_LINEOUT2N 0x0040 /* MIXOUTR_TO_LINEOUT2N */ 1651#define WM8994_MIXOUTR_TO_LINEOUT2N_MASK 0x0040 /* MIXOUTR_TO_LINEOUT2N */ 1652#define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT 6 /* MIXOUTR_TO_LINEOUT2N */ 1653#define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH 1 /* MIXOUTR_TO_LINEOUT2N */ 1654#define WM8994_MIXOUTL_TO_LINEOUT2N 0x0020 /* MIXOUTL_TO_LINEOUT2N */ 1655#define WM8994_MIXOUTL_TO_LINEOUT2N_MASK 0x0020 /* MIXOUTL_TO_LINEOUT2N */ 1656#define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT 5 /* MIXOUTL_TO_LINEOUT2N */ 1657#define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH 1 /* MIXOUTL_TO_LINEOUT2N */ 1658#define WM8994_LINEOUT2_MODE 0x0010 /* LINEOUT2_MODE */ 1659#define WM8994_LINEOUT2_MODE_MASK 0x0010 /* LINEOUT2_MODE */ 1660#define WM8994_LINEOUT2_MODE_SHIFT 4 /* LINEOUT2_MODE */ 1661#define WM8994_LINEOUT2_MODE_WIDTH 1 /* LINEOUT2_MODE */ 1662#define WM8994_IN1L_TO_LINEOUT2P 0x0004 /* IN1L_TO_LINEOUT2P */ 1663#define WM8994_IN1L_TO_LINEOUT2P_MASK 0x0004 /* IN1L_TO_LINEOUT2P */ 1664#define WM8994_IN1L_TO_LINEOUT2P_SHIFT 2 /* IN1L_TO_LINEOUT2P */ 1665#define WM8994_IN1L_TO_LINEOUT2P_WIDTH 1 /* IN1L_TO_LINEOUT2P */ 1666#define WM8994_IN1R_TO_LINEOUT2P 0x0002 /* IN1R_TO_LINEOUT2P */ 1667#define WM8994_IN1R_TO_LINEOUT2P_MASK 0x0002 /* IN1R_TO_LINEOUT2P */ 1668#define WM8994_IN1R_TO_LINEOUT2P_SHIFT 1 /* IN1R_TO_LINEOUT2P */ 1669#define WM8994_IN1R_TO_LINEOUT2P_WIDTH 1 /* IN1R_TO_LINEOUT2P */ 1670#define WM8994_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */ 1671#define WM8994_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */ 1672#define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT 0 /* MIXOUTR_TO_LINEOUT2P */ 1673#define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH 1 /* MIXOUTR_TO_LINEOUT2P */ 1674 1675/* 1676 * R54 (0x36) - Speaker Mixer 1677 */ 1678#define WM8994_DAC2L_TO_SPKMIXL 0x0200 /* DAC2L_TO_SPKMIXL */ 1679#define WM8994_DAC2L_TO_SPKMIXL_MASK 0x0200 /* DAC2L_TO_SPKMIXL */ 1680#define WM8994_DAC2L_TO_SPKMIXL_SHIFT 9 /* DAC2L_TO_SPKMIXL */ 1681#define WM8994_DAC2L_TO_SPKMIXL_WIDTH 1 /* DAC2L_TO_SPKMIXL */ 1682#define WM8994_DAC2R_TO_SPKMIXR 0x0100 /* DAC2R_TO_SPKMIXR */ 1683#define WM8994_DAC2R_TO_SPKMIXR_MASK 0x0100 /* DAC2R_TO_SPKMIXR */ 1684#define WM8994_DAC2R_TO_SPKMIXR_SHIFT 8 /* DAC2R_TO_SPKMIXR */ 1685#define WM8994_DAC2R_TO_SPKMIXR_WIDTH 1 /* DAC2R_TO_SPKMIXR */ 1686#define WM8994_MIXINL_TO_SPKMIXL 0x0080 /* MIXINL_TO_SPKMIXL */ 1687#define WM8994_MIXINL_TO_SPKMIXL_MASK 0x0080 /* MIXINL_TO_SPKMIXL */ 1688#define WM8994_MIXINL_TO_SPKMIXL_SHIFT 7 /* MIXINL_TO_SPKMIXL */ 1689#define WM8994_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */ 1690#define WM8994_MIXINR_TO_SPKMIXR 0x0040 /* MIXINR_TO_SPKMIXR */ 1691#define WM8994_MIXINR_TO_SPKMIXR_MASK 0x0040 /* MIXINR_TO_SPKMIXR */ 1692#define WM8994_MIXINR_TO_SPKMIXR_SHIFT 6 /* MIXINR_TO_SPKMIXR */ 1693#define WM8994_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */ 1694#define WM8994_IN1LP_TO_SPKMIXL 0x0020 /* IN1LP_TO_SPKMIXL */ 1695#define WM8994_IN1LP_TO_SPKMIXL_MASK 0x0020 /* IN1LP_TO_SPKMIXL */ 1696#define WM8994_IN1LP_TO_SPKMIXL_SHIFT 5 /* IN1LP_TO_SPKMIXL */ 1697#define WM8994_IN1LP_TO_SPKMIXL_WIDTH 1 /* IN1LP_TO_SPKMIXL */ 1698#define WM8994_IN1RP_TO_SPKMIXR 0x0010 /* IN1RP_TO_SPKMIXR */ 1699#define WM8994_IN1RP_TO_SPKMIXR_MASK 0x0010 /* IN1RP_TO_SPKMIXR */ 1700#define WM8994_IN1RP_TO_SPKMIXR_SHIFT 4 /* IN1RP_TO_SPKMIXR */ 1701#define WM8994_IN1RP_TO_SPKMIXR_WIDTH 1 /* IN1RP_TO_SPKMIXR */ 1702#define WM8994_MIXOUTL_TO_SPKMIXL 0x0008 /* MIXOUTL_TO_SPKMIXL */ 1703#define WM8994_MIXOUTL_TO_SPKMIXL_MASK 0x0008 /* MIXOUTL_TO_SPKMIXL */ 1704#define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT 3 /* MIXOUTL_TO_SPKMIXL */ 1705#define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH 1 /* MIXOUTL_TO_SPKMIXL */ 1706#define WM8994_MIXOUTR_TO_SPKMIXR 0x0004 /* MIXOUTR_TO_SPKMIXR */ 1707#define WM8994_MIXOUTR_TO_SPKMIXR_MASK 0x0004 /* MIXOUTR_TO_SPKMIXR */ 1708#define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT 2 /* MIXOUTR_TO_SPKMIXR */ 1709#define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH 1 /* MIXOUTR_TO_SPKMIXR */ 1710#define WM8994_DAC1L_TO_SPKMIXL 0x0002 /* DAC1L_TO_SPKMIXL */ 1711#define WM8994_DAC1L_TO_SPKMIXL_MASK 0x0002 /* DAC1L_TO_SPKMIXL */ 1712#define WM8994_DAC1L_TO_SPKMIXL_SHIFT 1 /* DAC1L_TO_SPKMIXL */ 1713#define WM8994_DAC1L_TO_SPKMIXL_WIDTH 1 /* DAC1L_TO_SPKMIXL */ 1714#define WM8994_DAC1R_TO_SPKMIXR 0x0001 /* DAC1R_TO_SPKMIXR */ 1715#define WM8994_DAC1R_TO_SPKMIXR_MASK 0x0001 /* DAC1R_TO_SPKMIXR */ 1716#define WM8994_DAC1R_TO_SPKMIXR_SHIFT 0 /* DAC1R_TO_SPKMIXR */ 1717#define WM8994_DAC1R_TO_SPKMIXR_WIDTH 1 /* DAC1R_TO_SPKMIXR */ 1718 1719/* 1720 * R55 (0x37) - Additional Control 1721 */ 1722#define WM8994_LINEOUT1_FB 0x0080 /* LINEOUT1_FB */ 1723#define WM8994_LINEOUT1_FB_MASK 0x0080 /* LINEOUT1_FB */ 1724#define WM8994_LINEOUT1_FB_SHIFT 7 /* LINEOUT1_FB */ 1725#define WM8994_LINEOUT1_FB_WIDTH 1 /* LINEOUT1_FB */ 1726#define WM8994_LINEOUT2_FB 0x0040 /* LINEOUT2_FB */ 1727#define WM8994_LINEOUT2_FB_MASK 0x0040 /* LINEOUT2_FB */ 1728#define WM8994_LINEOUT2_FB_SHIFT 6 /* LINEOUT2_FB */ 1729#define WM8994_LINEOUT2_FB_WIDTH 1 /* LINEOUT2_FB */ 1730#define WM8994_VROI 0x0001 /* VROI */ 1731#define WM8994_VROI_MASK 0x0001 /* VROI */ 1732#define WM8994_VROI_SHIFT 0 /* VROI */ 1733#define WM8994_VROI_WIDTH 1 /* VROI */ 1734 1735/* 1736 * R56 (0x38) - AntiPOP (1) 1737 */ 1738#define WM8994_LINEOUT_VMID_BUF_ENA 0x0080 /* LINEOUT_VMID_BUF_ENA */ 1739#define WM8994_LINEOUT_VMID_BUF_ENA_MASK 0x0080 /* LINEOUT_VMID_BUF_ENA */ 1740#define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT 7 /* LINEOUT_VMID_BUF_ENA */ 1741#define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH 1 /* LINEOUT_VMID_BUF_ENA */ 1742#define WM8994_HPOUT2_IN_ENA 0x0040 /* HPOUT2_IN_ENA */ 1743#define WM8994_HPOUT2_IN_ENA_MASK 0x0040 /* HPOUT2_IN_ENA */ 1744#define WM8994_HPOUT2_IN_ENA_SHIFT 6 /* HPOUT2_IN_ENA */ 1745#define WM8994_HPOUT2_IN_ENA_WIDTH 1 /* HPOUT2_IN_ENA */ 1746#define WM8994_LINEOUT1_DISCH 0x0020 /* LINEOUT1_DISCH */ 1747#define WM8994_LINEOUT1_DISCH_MASK 0x0020 /* LINEOUT1_DISCH */ 1748#define WM8994_LINEOUT1_DISCH_SHIFT 5 /* LINEOUT1_DISCH */ 1749#define WM8994_LINEOUT1_DISCH_WIDTH 1 /* LINEOUT1_DISCH */ 1750#define WM8994_LINEOUT2_DISCH 0x0010 /* LINEOUT2_DISCH */ 1751#define WM8994_LINEOUT2_DISCH_MASK 0x0010 /* LINEOUT2_DISCH */ 1752#define WM8994_LINEOUT2_DISCH_SHIFT 4 /* LINEOUT2_DISCH */ 1753#define WM8994_LINEOUT2_DISCH_WIDTH 1 /* LINEOUT2_DISCH */ 1754 1755/* 1756 * R57 (0x39) - AntiPOP (2) 1757 */ 1758#define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */ 1759#define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */ 1760#define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */ 1761#define WM8994_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1762#define WM8994_MICB1_DISCH 0x0080 /* MICB1_DISCH */ 1763#define WM8994_MICB1_DISCH_MASK 0x0080 /* MICB1_DISCH */ 1764#define WM8994_MICB1_DISCH_SHIFT 7 /* MICB1_DISCH */ 1765#define WM8994_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1766#define WM8994_VMID_RAMP_MASK 0x0060 /* VMID_RAMP - [6:5] */ 1767#define WM8994_VMID_RAMP_SHIFT 5 /* VMID_RAMP - [6:5] */ 1768#define WM8994_VMID_RAMP_WIDTH 2 /* VMID_RAMP - [6:5] */ 1769#define WM8994_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */ 1770#define WM8994_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */ 1771#define WM8994_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */ 1772#define WM8994_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 1773#define WM8994_STARTUP_BIAS_ENA 0x0004 /* STARTUP_BIAS_ENA */ 1774#define WM8994_STARTUP_BIAS_ENA_MASK 0x0004 /* STARTUP_BIAS_ENA */ 1775#define WM8994_STARTUP_BIAS_ENA_SHIFT 2 /* STARTUP_BIAS_ENA */ 1776#define WM8994_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 1777#define WM8994_BIAS_SRC 0x0002 /* BIAS_SRC */ 1778#define WM8994_BIAS_SRC_MASK 0x0002 /* BIAS_SRC */ 1779#define WM8994_BIAS_SRC_SHIFT 1 /* BIAS_SRC */ 1780#define WM8994_BIAS_SRC_WIDTH 1 /* BIAS_SRC */ 1781#define WM8994_VMID_DISCH 0x0001 /* VMID_DISCH */ 1782#define WM8994_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */ 1783#define WM8994_VMID_DISCH_SHIFT 0 /* VMID_DISCH */ 1784#define WM8994_VMID_DISCH_WIDTH 1 /* VMID_DISCH */ 1785 1786/* 1787 * R58 (0x3A) - MICBIAS 1788 */ 1789#define WM8994_MICD_SCTHR_MASK 0x00C0 /* MICD_SCTHR - [7:6] */ 1790#define WM8994_MICD_SCTHR_SHIFT 6 /* MICD_SCTHR - [7:6] */ 1791#define WM8994_MICD_SCTHR_WIDTH 2 /* MICD_SCTHR - [7:6] */ 1792#define WM8994_MICD_THR_MASK 0x0038 /* MICD_THR - [5:3] */ 1793#define WM8994_MICD_THR_SHIFT 3 /* MICD_THR - [5:3] */ 1794#define WM8994_MICD_THR_WIDTH 3 /* MICD_THR - [5:3] */ 1795#define WM8994_MICD_ENA 0x0004 /* MICD_ENA */ 1796#define WM8994_MICD_ENA_MASK 0x0004 /* MICD_ENA */ 1797#define WM8994_MICD_ENA_SHIFT 2 /* MICD_ENA */ 1798#define WM8994_MICD_ENA_WIDTH 1 /* MICD_ENA */ 1799#define WM8994_MICB2_LVL 0x0002 /* MICB2_LVL */ 1800#define WM8994_MICB2_LVL_MASK 0x0002 /* MICB2_LVL */ 1801#define WM8994_MICB2_LVL_SHIFT 1 /* MICB2_LVL */ 1802#define WM8994_MICB2_LVL_WIDTH 1 /* MICB2_LVL */ 1803#define WM8994_MICB1_LVL 0x0001 /* MICB1_LVL */ 1804#define WM8994_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */ 1805#define WM8994_MICB1_LVL_SHIFT 0 /* MICB1_LVL */ 1806#define WM8994_MICB1_LVL_WIDTH 1 /* MICB1_LVL */ 1807 1808/* 1809 * R59 (0x3B) - LDO 1 1810 */ 1811#define WM8994_LDO1_VSEL_MASK 0x000E /* LDO1_VSEL - [3:1] */ 1812#define WM8994_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [3:1] */ 1813#define WM8994_LDO1_VSEL_WIDTH 3 /* LDO1_VSEL - [3:1] */ 1814#define WM8994_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 1815#define WM8994_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 1816#define WM8994_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 1817#define WM8994_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 1818 1819/* 1820 * R60 (0x3C) - LDO 2 1821 */ 1822#define WM8994_LDO2_VSEL_MASK 0x0006 /* LDO2_VSEL - [2:1] */ 1823#define WM8994_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [2:1] */ 1824#define WM8994_LDO2_VSEL_WIDTH 2 /* LDO2_VSEL - [2:1] */ 1825#define WM8994_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 1826#define WM8994_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 1827#define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 1828#define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 1829 1830/* 1831 * R76 (0x4C) - Charge Pump (1) 1832 */ 1833#define WM8994_CP_ENA 0x8000 /* CP_ENA */ 1834#define WM8994_CP_ENA_MASK 0x8000 /* CP_ENA */ 1835#define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */ 1836#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */ 1837 1838/* 1839 * R81 (0x51) - Class W (1) 1840 */ 1841#define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ 1842#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ 1843#define WM8994_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ 1844#define WM8994_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 1845#define WM8994_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 1846#define WM8994_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 1847#define WM8994_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 1848 1849/* 1850 * R84 (0x54) - DC Servo (1) 1851 */ 1852#define WM8994_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 1853#define WM8994_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 1854#define WM8994_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 1855#define WM8994_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 1856#define WM8994_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 1857#define WM8994_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 1858#define WM8994_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 1859#define WM8994_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 1860#define WM8994_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 1861#define WM8994_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 1862#define WM8994_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 1863#define WM8994_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 1864#define WM8994_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 1865#define WM8994_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 1866#define WM8994_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 1867#define WM8994_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 1868#define WM8994_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 1869#define WM8994_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 1870#define WM8994_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 1871#define WM8994_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 1872#define WM8994_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 1873#define WM8994_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 1874#define WM8994_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 1875#define WM8994_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 1876#define WM8994_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */ 1877#define WM8994_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */ 1878#define WM8994_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */ 1879#define WM8994_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 1880#define WM8994_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */ 1881#define WM8994_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */ 1882#define WM8994_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */ 1883#define WM8994_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 1884#define WM8994_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 1885#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 1886#define WM8994_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 1887#define WM8994_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 1888#define WM8994_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 1889#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 1890#define WM8994_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 1891#define WM8994_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 1892 1893/* 1894 * R85 (0x55) - DC Servo (2) 1895 */ 1896#define WM8994_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */ 1897#define WM8994_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */ 1898#define WM8994_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */ 1899#define WM8994_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 1900#define WM8994_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1901#define WM8994_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1902 1903/* 1904 * R87 (0x57) - DC Servo (4) 1905 */ 1906#define WM8994_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1907#define WM8994_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1908#define WM8994_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1909#define WM8994_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 1910#define WM8994_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1911#define WM8994_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1912 1913/* 1914 * R88 (0x58) - DC Servo Readback 1915 */ 1916#define WM8994_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */ 1917#define WM8994_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */ 1918#define WM8994_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */ 1919#define WM8994_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */ 1920#define WM8994_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */ 1921#define WM8994_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */ 1922#define WM8994_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */ 1923#define WM8994_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */ 1924#define WM8994_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */ 1925 1926/* 1927 * R96 (0x60) - Analogue HP (1) 1928 */ 1929#define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 1930#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 1931#define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 1932#define WM8994_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 1933#define WM8994_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 1934#define WM8994_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 1935#define WM8994_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 1936#define WM8994_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 1937#define WM8994_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 1938#define WM8994_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 1939#define WM8994_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 1940#define WM8994_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 1941#define WM8994_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 1942#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 1943#define WM8994_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 1944#define WM8994_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 1945#define WM8994_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 1946#define WM8994_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 1947#define WM8994_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 1948#define WM8994_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 1949#define WM8994_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 1950#define WM8994_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 1951#define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 1952#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 1953 1954/* 1955 * R256 (0x100) - Chip Revision 1956 */ 1957#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 1958#define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 1959#define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 1960 1961/* 1962 * R257 (0x101) - Control Interface 1963 */ 1964#define WM8994_SPI_CONTRD 0x0040 /* SPI_CONTRD */ 1965#define WM8994_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ 1966#define WM8994_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ 1967#define WM8994_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ 1968#define WM8994_SPI_4WIRE 0x0020 /* SPI_4WIRE */ 1969#define WM8994_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ 1970#define WM8994_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ 1971#define WM8994_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 1972#define WM8994_SPI_CFG 0x0010 /* SPI_CFG */ 1973#define WM8994_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 1974#define WM8994_SPI_CFG_SHIFT 4 /* SPI_CFG */ 1975#define WM8994_SPI_CFG_WIDTH 1 /* SPI_CFG */ 1976#define WM8994_AUTO_INC 0x0004 /* AUTO_INC */ 1977#define WM8994_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 1978#define WM8994_AUTO_INC_SHIFT 2 /* AUTO_INC */ 1979#define WM8994_AUTO_INC_WIDTH 1 /* AUTO_INC */ 1980 1981/* 1982 * R272 (0x110) - Write Sequencer Ctrl (1) 1983 */ 1984#define WM8994_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 1985#define WM8994_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 1986#define WM8994_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 1987#define WM8994_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1988#define WM8994_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1989#define WM8994_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1990#define WM8994_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1991#define WM8994_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1992#define WM8994_WSEQ_START 0x0100 /* WSEQ_START */ 1993#define WM8994_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1994#define WM8994_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1995#define WM8994_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1996#define WM8994_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 1997#define WM8994_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 1998#define WM8994_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 1999 2000/* 2001 * R273 (0x111) - Write Sequencer Ctrl (2) 2002 */ 2003#define WM8994_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 2004#define WM8994_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 2005#define WM8994_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 2006#define WM8994_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 2007#define WM8994_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 2008#define WM8994_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 2009#define WM8994_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 2010 2011/* 2012 * R512 (0x200) - AIF1 Clocking (1) 2013 */ 2014#define WM8994_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ 2015#define WM8994_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ 2016#define WM8994_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ 2017#define WM8994_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ 2018#define WM8994_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ 2019#define WM8994_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ 2020#define WM8994_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ 2021#define WM8994_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ 2022#define WM8994_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ 2023#define WM8994_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ 2024#define WM8994_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ 2025#define WM8994_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ 2026#define WM8994_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ 2027#define WM8994_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ 2028#define WM8994_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ 2029 2030/* 2031 * R513 (0x201) - AIF1 Clocking (2) 2032 */ 2033#define WM8994_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ 2034#define WM8994_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ 2035#define WM8994_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ 2036#define WM8994_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ 2037#define WM8994_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ 2038#define WM8994_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ 2039 2040/* 2041 * R516 (0x204) - AIF2 Clocking (1) 2042 */ 2043#define WM8994_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ 2044#define WM8994_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ 2045#define WM8994_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ 2046#define WM8994_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ 2047#define WM8994_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ 2048#define WM8994_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ 2049#define WM8994_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ 2050#define WM8994_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ 2051#define WM8994_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ 2052#define WM8994_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ 2053#define WM8994_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ 2054#define WM8994_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ 2055#define WM8994_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ 2056#define WM8994_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ 2057#define WM8994_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ 2058 2059/* 2060 * R517 (0x205) - AIF2 Clocking (2) 2061 */ 2062#define WM8994_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ 2063#define WM8994_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ 2064#define WM8994_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ 2065#define WM8994_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ 2066#define WM8994_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ 2067#define WM8994_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ 2068 2069/* 2070 * R520 (0x208) - Clocking (1) 2071 */ 2072#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 2073#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 2074#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 2075#define WM8994_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 2076#define WM8994_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ 2077#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ 2078#define WM8994_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ 2079#define WM8994_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ 2080#define WM8994_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ 2081#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ 2082#define WM8994_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ 2083#define WM8994_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ 2084#define WM8994_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 2085#define WM8994_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 2086#define WM8994_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 2087#define WM8994_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 2088#define WM8994_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ 2089#define WM8994_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ 2090#define WM8994_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ 2091#define WM8994_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 2092 2093/* 2094 * R521 (0x209) - Clocking (2) 2095 */ 2096#define WM8994_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 2097#define WM8994_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 2098#define WM8994_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 2099#define WM8994_DBCLK_DIV_MASK 0x0070 /* DBCLK_DIV - [6:4] */ 2100#define WM8994_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [6:4] */ 2101#define WM8994_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [6:4] */ 2102#define WM8994_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 2103#define WM8994_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 2104#define WM8994_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 2105 2106/* 2107 * R528 (0x210) - AIF1 Rate 2108 */ 2109#define WM8994_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ 2110#define WM8994_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ 2111#define WM8994_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ 2112#define WM8994_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ 2113#define WM8994_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ 2114#define WM8994_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ 2115 2116/* 2117 * R529 (0x211) - AIF2 Rate 2118 */ 2119#define WM8994_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ 2120#define WM8994_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ 2121#define WM8994_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ 2122#define WM8994_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ 2123#define WM8994_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ 2124#define WM8994_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ 2125 2126/* 2127 * R530 (0x212) - Rate Status 2128 */ 2129#define WM8994_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ 2130#define WM8994_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ 2131#define WM8994_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ 2132 2133/* 2134 * R544 (0x220) - FLL1 Control (1) 2135 */ 2136#define WM8994_FLL1_FRAC 0x0004 /* FLL1_FRAC */ 2137#define WM8994_FLL1_FRAC_MASK 0x0004 /* FLL1_FRAC */ 2138#define WM8994_FLL1_FRAC_SHIFT 2 /* FLL1_FRAC */ 2139#define WM8994_FLL1_FRAC_WIDTH 1 /* FLL1_FRAC */ 2140#define WM8994_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ 2141#define WM8994_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ 2142#define WM8994_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ 2143#define WM8994_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ 2144#define WM8994_FLL1_ENA 0x0001 /* FLL1_ENA */ 2145#define WM8994_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 2146#define WM8994_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 2147#define WM8994_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 2148 2149/* 2150 * R545 (0x221) - FLL1 Control (2) 2151 */ 2152#define WM8994_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 2153#define WM8994_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 2154#define WM8994_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 2155#define WM8994_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ 2156#define WM8994_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ 2157#define WM8994_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ 2158#define WM8994_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 2159#define WM8994_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 2160#define WM8994_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 2161 2162/* 2163 * R546 (0x222) - FLL1 Control (3) 2164 */ 2165#define WM8994_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ 2166#define WM8994_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ 2167#define WM8994_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ 2168 2169/* 2170 * R547 (0x223) - FLL1 Control (4) 2171 */ 2172#define WM8994_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ 2173#define WM8994_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ 2174#define WM8994_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ 2175#define WM8994_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ 2176#define WM8994_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ 2177#define WM8994_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ 2178 2179/* 2180 * R548 (0x224) - FLL1 Control (5) 2181 */ 2182#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 2183#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 2184#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 2185#define WM8994_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ 2186#define WM8994_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ 2187#define WM8994_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ 2188#define WM8994_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ 2189#define WM8994_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ 2190#define WM8994_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ 2191#define WM8994_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ 2192#define WM8994_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ 2193#define WM8994_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ 2194#define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 2195 2196/* 2197 * R576 (0x240) - FLL2 Control (1) 2198 */ 2199#define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */ 2200#define WM8994_FLL2_FRAC_MASK 0x0004 /* FLL2_FRAC */ 2201#define WM8994_FLL2_FRAC_SHIFT 2 /* FLL2_FRAC */ 2202#define WM8994_FLL2_FRAC_WIDTH 1 /* FLL2_FRAC */ 2203#define WM8994_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ 2204#define WM8994_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ 2205#define WM8994_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ 2206#define WM8994_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ 2207#define WM8994_FLL2_ENA 0x0001 /* FLL2_ENA */ 2208#define WM8994_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 2209#define WM8994_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 2210#define WM8994_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 2211 2212/* 2213 * R577 (0x241) - FLL2 Control (2) 2214 */ 2215#define WM8994_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 2216#define WM8994_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 2217#define WM8994_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 2218#define WM8994_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ 2219#define WM8994_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ 2220#define WM8994_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ 2221#define WM8994_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 2222#define WM8994_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 2223#define WM8994_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 2224 2225/* 2226 * R578 (0x242) - FLL2 Control (3) 2227 */ 2228#define WM8994_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ 2229#define WM8994_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ 2230#define WM8994_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ 2231 2232/* 2233 * R579 (0x243) - FLL2 Control (4) 2234 */ 2235#define WM8994_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ 2236#define WM8994_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ 2237#define WM8994_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ 2238#define WM8994_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ 2239#define WM8994_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ 2240#define WM8994_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ 2241 2242/* 2243 * R580 (0x244) - FLL2 Control (5) 2244 */ 2245#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 2246#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 2247#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 2248#define WM8994_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ 2249#define WM8994_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ 2250#define WM8994_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ 2251#define WM8994_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ 2252#define WM8994_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ 2253#define WM8994_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ 2254#define WM8994_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ 2255#define WM8994_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ 2256#define WM8994_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ 2257#define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 2258 2259/* 2260 * R768 (0x300) - AIF1 Control (1) 2261 */ 2262#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 2263#define WM8994_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ 2264#define WM8994_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ 2265#define WM8994_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ 2266#define WM8994_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ 2267#define WM8994_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ 2268#define WM8994_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ 2269#define WM8994_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ 2270#define WM8994_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ 2271#define WM8994_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ 2272#define WM8994_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ 2273#define WM8994_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ 2274#define WM8994_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ 2275#define WM8994_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ 2276#define WM8994_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ 2277#define WM8994_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 2278#define WM8994_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ 2279#define WM8994_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ 2280#define WM8994_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ 2281#define WM8994_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 2282#define WM8994_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ 2283#define WM8994_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ 2284#define WM8994_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ 2285#define WM8994_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ 2286#define WM8994_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ 2287#define WM8994_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ 2288 2289/* 2290 * R769 (0x301) - AIF1 Control (2) 2291 */ 2292#define WM8994_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ 2293#define WM8994_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ 2294#define WM8994_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ 2295#define WM8994_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ 2296#define WM8994_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ 2297#define WM8994_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ 2298#define WM8994_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ 2299#define WM8994_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ 2300#define WM8994_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ 2301#define WM8994_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ 2302#define WM8994_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ 2303#define WM8994_AIF1_MONO 0x0100 /* AIF1_MONO */ 2304#define WM8994_AIF1_MONO_MASK 0x0100 /* AIF1_MONO */ 2305#define WM8994_AIF1_MONO_SHIFT 8 /* AIF1_MONO */ 2306#define WM8994_AIF1_MONO_WIDTH 1 /* AIF1_MONO */ 2307#define WM8994_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ 2308#define WM8994_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ 2309#define WM8994_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ 2310#define WM8994_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ 2311#define WM8994_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ 2312#define WM8994_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ 2313#define WM8994_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ 2314#define WM8994_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ 2315#define WM8994_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ 2316#define WM8994_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ 2317#define WM8994_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ 2318#define WM8994_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ 2319#define WM8994_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ 2320#define WM8994_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ 2321#define WM8994_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ 2322#define WM8994_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ 2323#define WM8994_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ 2324#define WM8994_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ 2325#define WM8994_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ 2326#define WM8994_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ 2327 2328/* 2329 * R770 (0x302) - AIF1 Master/Slave 2330 */ 2331#define WM8994_AIF1_TRI 0x8000 /* AIF1_TRI */ 2332#define WM8994_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ 2333#define WM8994_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ 2334#define WM8994_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 2335#define WM8994_AIF1_MSTR 0x4000 /* AIF1_MSTR */ 2336#define WM8994_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ 2337#define WM8994_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ 2338#define WM8994_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ 2339#define WM8994_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ 2340#define WM8994_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ 2341#define WM8994_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ 2342#define WM8994_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ 2343#define WM8994_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ 2344#define WM8994_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ 2345#define WM8994_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ 2346#define WM8994_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ 2347 2348/* 2349 * R771 (0x303) - AIF1 BCLK 2350 */ 2351#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 /* AIF1_BCLK_DIV - [8:4] */ 2352#define WM8994_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [8:4] */ 2353#define WM8994_AIF1_BCLK_DIV_WIDTH 5 /* AIF1_BCLK_DIV - [8:4] */ 2354 2355/* 2356 * R772 (0x304) - AIF1ADC LRCLK 2357 */ 2358#define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ 2359#define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ 2360#define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ 2361#define WM8994_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ 2362#define WM8994_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ 2363#define WM8994_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ 2364#define WM8994_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ 2365 2366/* 2367 * R773 (0x305) - AIF1DAC LRCLK 2368 */ 2369#define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ 2370#define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ 2371#define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ 2372#define WM8994_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ 2373#define WM8994_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ 2374#define WM8994_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ 2375#define WM8994_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ 2376 2377/* 2378 * R774 (0x306) - AIF1DAC Data 2379 */ 2380#define WM8994_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ 2381#define WM8994_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ 2382#define WM8994_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ 2383#define WM8994_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ 2384#define WM8994_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ 2385#define WM8994_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ 2386#define WM8994_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ 2387#define WM8994_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ 2388 2389/* 2390 * R775 (0x307) - AIF1ADC Data 2391 */ 2392#define WM8994_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ 2393#define WM8994_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ 2394#define WM8994_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ 2395#define WM8994_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ 2396#define WM8994_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ 2397#define WM8994_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ 2398#define WM8994_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ 2399#define WM8994_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ 2400 2401/* 2402 * R784 (0x310) - AIF2 Control (1) 2403 */ 2404#define WM8994_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ 2405#define WM8994_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ 2406#define WM8994_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ 2407#define WM8994_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ 2408#define WM8994_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ 2409#define WM8994_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ 2410#define WM8994_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ 2411#define WM8994_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ 2412#define WM8994_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ 2413#define WM8994_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ 2414#define WM8994_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ 2415#define WM8994_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ 2416#define WM8994_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ 2417#define WM8994_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ 2418#define WM8994_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ 2419#define WM8994_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ 2420#define WM8994_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ 2421#define WM8994_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ 2422#define WM8994_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ 2423#define WM8994_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2424#define WM8994_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ 2425#define WM8994_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ 2426#define WM8994_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ 2427#define WM8994_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ 2428#define WM8994_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ 2429#define WM8994_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ 2430#define WM8994_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ 2431#define WM8994_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ 2432#define WM8994_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ 2433#define WM8994_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ 2434 2435/* 2436 * R785 (0x311) - AIF2 Control (2) 2437 */ 2438#define WM8994_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ 2439#define WM8994_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ 2440#define WM8994_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ 2441#define WM8994_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ 2442#define WM8994_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ 2443#define WM8994_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ 2444#define WM8994_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ 2445#define WM8994_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ 2446#define WM8994_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ 2447#define WM8994_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ 2448#define WM8994_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ 2449#define WM8994_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ 2450#define WM8994_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ 2451#define WM8994_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ 2452#define WM8994_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ 2453#define WM8994_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ 2454#define WM8994_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ 2455#define WM8994_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ 2456#define WM8994_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ 2457#define WM8994_AIF2_MONO 0x0100 /* AIF2_MONO */ 2458#define WM8994_AIF2_MONO_MASK 0x0100 /* AIF2_MONO */ 2459#define WM8994_AIF2_MONO_SHIFT 8 /* AIF2_MONO */ 2460#define WM8994_AIF2_MONO_WIDTH 1 /* AIF2_MONO */ 2461#define WM8994_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ 2462#define WM8994_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ 2463#define WM8994_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ 2464#define WM8994_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ 2465#define WM8994_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ 2466#define WM8994_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ 2467#define WM8994_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ 2468#define WM8994_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ 2469#define WM8994_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ 2470#define WM8994_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ 2471#define WM8994_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ 2472#define WM8994_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ 2473#define WM8994_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ 2474#define WM8994_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ 2475#define WM8994_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ 2476#define WM8994_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ 2477#define WM8994_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ 2478#define WM8994_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ 2479#define WM8994_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ 2480#define WM8994_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ 2481 2482/* 2483 * R786 (0x312) - AIF2 Master/Slave 2484 */ 2485#define WM8994_AIF2_TRI 0x8000 /* AIF2_TRI */ 2486#define WM8994_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ 2487#define WM8994_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ 2488#define WM8994_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2489#define WM8994_AIF2_MSTR 0x4000 /* AIF2_MSTR */ 2490#define WM8994_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ 2491#define WM8994_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ 2492#define WM8994_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ 2493#define WM8994_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ 2494#define WM8994_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ 2495#define WM8994_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ 2496#define WM8994_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ 2497#define WM8994_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ 2498#define WM8994_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ 2499#define WM8994_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ 2500#define WM8994_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ 2501 2502/* 2503 * R787 (0x313) - AIF2 BCLK 2504 */ 2505#define WM8994_AIF2_BCLK_DIV_MASK 0x01F0 /* AIF2_BCLK_DIV - [8:4] */ 2506#define WM8994_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [8:4] */ 2507#define WM8994_AIF2_BCLK_DIV_WIDTH 5 /* AIF2_BCLK_DIV - [8:4] */ 2508 2509/* 2510 * R788 (0x314) - AIF2ADC LRCLK 2511 */ 2512#define WM8994_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ 2513#define WM8994_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ 2514#define WM8994_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ 2515#define WM8994_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ 2516#define WM8994_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ 2517#define WM8994_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ 2518#define WM8994_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ 2519 2520/* 2521 * R789 (0x315) - AIF2DAC LRCLK 2522 */ 2523#define WM8994_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ 2524#define WM8994_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ 2525#define WM8994_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ 2526#define WM8994_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ 2527#define WM8994_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ 2528#define WM8994_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ 2529#define WM8994_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ 2530 2531/* 2532 * R790 (0x316) - AIF2DAC Data 2533 */ 2534#define WM8994_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ 2535#define WM8994_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ 2536#define WM8994_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ 2537#define WM8994_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ 2538#define WM8994_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ 2539#define WM8994_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ 2540#define WM8994_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ 2541#define WM8994_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ 2542 2543/* 2544 * R791 (0x317) - AIF2ADC Data 2545 */ 2546#define WM8994_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ 2547#define WM8994_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ 2548#define WM8994_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ 2549#define WM8994_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ 2550#define WM8994_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ 2551#define WM8994_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ 2552#define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ 2553#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ 2554 2555/* 2556 * R1024 (0x400) - AIF1 ADC1 Left Volume 2557 */ 2558#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2559#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2560#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2561#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2562#define WM8994_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ 2563#define WM8994_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ 2564#define WM8994_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ 2565 2566/* 2567 * R1025 (0x401) - AIF1 ADC1 Right Volume 2568 */ 2569#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2570#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2571#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2572#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2573#define WM8994_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ 2574#define WM8994_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ 2575#define WM8994_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ 2576 2577/* 2578 * R1026 (0x402) - AIF1 DAC1 Left Volume 2579 */ 2580#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2581#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2582#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2583#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2584#define WM8994_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ 2585#define WM8994_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ 2586#define WM8994_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ 2587 2588/* 2589 * R1027 (0x403) - AIF1 DAC1 Right Volume 2590 */ 2591#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2592#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2593#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2594#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2595#define WM8994_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ 2596#define WM8994_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ 2597#define WM8994_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ 2598 2599/* 2600 * R1028 (0x404) - AIF1 ADC2 Left Volume 2601 */ 2602#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2603#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2604#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2605#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2606#define WM8994_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ 2607#define WM8994_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ 2608#define WM8994_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ 2609 2610/* 2611 * R1029 (0x405) - AIF1 ADC2 Right Volume 2612 */ 2613#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2614#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2615#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2616#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2617#define WM8994_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ 2618#define WM8994_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ 2619#define WM8994_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ 2620 2621/* 2622 * R1030 (0x406) - AIF1 DAC2 Left Volume 2623 */ 2624#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2625#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2626#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2627#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2628#define WM8994_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ 2629#define WM8994_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ 2630#define WM8994_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ 2631 2632/* 2633 * R1031 (0x407) - AIF1 DAC2 Right Volume 2634 */ 2635#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2636#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2637#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2638#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2639#define WM8994_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ 2640#define WM8994_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ 2641#define WM8994_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ 2642 2643/* 2644 * R1040 (0x410) - AIF1 ADC1 Filters 2645 */ 2646#define WM8994_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ 2647#define WM8994_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ 2648#define WM8994_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ 2649#define WM8994_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ 2650#define WM8994_AIF1ADC1_HPF_CUT_MASK 0x6000 /* AIF1ADC1_HPF_CUT - [14:13] */ 2651#define WM8994_AIF1ADC1_HPF_CUT_SHIFT 13 /* AIF1ADC1_HPF_CUT - [14:13] */ 2652#define WM8994_AIF1ADC1_HPF_CUT_WIDTH 2 /* AIF1ADC1_HPF_CUT - [14:13] */ 2653#define WM8994_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ 2654#define WM8994_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ 2655#define WM8994_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ 2656#define WM8994_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ 2657#define WM8994_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ 2658#define WM8994_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ 2659#define WM8994_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ 2660#define WM8994_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ 2661 2662/* 2663 * R1041 (0x411) - AIF1 ADC2 Filters 2664 */ 2665#define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */ 2666#define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */ 2667#define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */ 2668#define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ 2669#define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ 2670#define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ 2671#define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ 2672#define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ 2673#define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ 2674#define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ 2675#define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ 2676 2677/* 2678 * R1056 (0x420) - AIF1 DAC1 Filters (1) 2679 */ 2680#define WM8994_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ 2681#define WM8994_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ 2682#define WM8994_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ 2683#define WM8994_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ 2684#define WM8994_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ 2685#define WM8994_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ 2686#define WM8994_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ 2687#define WM8994_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ 2688#define WM8994_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ 2689#define WM8994_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ 2690#define WM8994_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ 2691#define WM8994_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ 2692#define WM8994_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2693#define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2694#define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ 2695#define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ 2696#define WM8994_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ 2697#define WM8994_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ 2698#define WM8994_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ 2699 2700/* 2701 * R1057 (0x421) - AIF1 DAC1 Filters (2) 2702 */ 2703#define WM8994_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ 2704#define WM8994_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ 2705#define WM8994_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ 2706#define WM8994_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ 2707#define WM8994_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ 2708#define WM8994_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ 2709#define WM8994_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ 2710 2711/* 2712 * R1058 (0x422) - AIF1 DAC2 Filters (1) 2713 */ 2714#define WM8994_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ 2715#define WM8994_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ 2716#define WM8994_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ 2717#define WM8994_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ 2718#define WM8994_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ 2719#define WM8994_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ 2720#define WM8994_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ 2721#define WM8994_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ 2722#define WM8994_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ 2723#define WM8994_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ 2724#define WM8994_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ 2725#define WM8994_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ 2726#define WM8994_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2727#define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2728#define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ 2729#define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ 2730#define WM8994_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ 2731#define WM8994_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ 2732#define WM8994_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ 2733 2734/* 2735 * R1059 (0x423) - AIF1 DAC2 Filters (2) 2736 */ 2737#define WM8994_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ 2738#define WM8994_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ 2739#define WM8994_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ 2740#define WM8994_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ 2741#define WM8994_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ 2742#define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ 2743#define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ 2744 2745/* 2746 * R1088 (0x440) - AIF1 DRC1 (1) 2747 */ 2748#define WM8994_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2749#define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2750#define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2751#define WM8994_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2752#define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2753#define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2754#define WM8994_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ 2755#define WM8994_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ 2756#define WM8994_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ 2757#define WM8994_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ 2758#define WM8994_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2759#define WM8994_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2760#define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ 2761#define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ 2762#define WM8994_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ 2763#define WM8994_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ 2764#define WM8994_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ 2765#define WM8994_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ 2766#define WM8994_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2767#define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2768#define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ 2769#define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ 2770#define WM8994_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ 2771#define WM8994_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ 2772#define WM8994_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ 2773#define WM8994_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ 2774#define WM8994_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ 2775#define WM8994_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ 2776#define WM8994_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ 2777#define WM8994_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ 2778#define WM8994_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ 2779#define WM8994_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ 2780#define WM8994_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ 2781#define WM8994_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ 2782#define WM8994_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ 2783#define WM8994_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ 2784#define WM8994_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ 2785#define WM8994_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ 2786#define WM8994_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ 2787#define WM8994_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ 2788#define WM8994_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ 2789#define WM8994_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ 2790 2791/* 2792 * R1089 (0x441) - AIF1 DRC1 (2) 2793 */ 2794#define WM8994_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ 2795#define WM8994_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ 2796#define WM8994_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ 2797#define WM8994_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ 2798#define WM8994_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ 2799#define WM8994_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ 2800#define WM8994_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ 2801#define WM8994_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ 2802#define WM8994_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ 2803#define WM8994_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ 2804#define WM8994_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ 2805#define WM8994_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ 2806 2807/* 2808 * R1090 (0x442) - AIF1 DRC1 (3) 2809 */ 2810#define WM8994_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2811#define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2812#define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2813#define WM8994_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ 2814#define WM8994_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ 2815#define WM8994_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ 2816#define WM8994_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ 2817#define WM8994_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ 2818#define WM8994_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ 2819#define WM8994_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ 2820#define WM8994_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ 2821#define WM8994_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ 2822#define WM8994_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ 2823#define WM8994_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ 2824#define WM8994_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ 2825#define WM8994_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ 2826#define WM8994_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ 2827#define WM8994_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ 2828 2829/* 2830 * R1091 (0x443) - AIF1 DRC1 (4) 2831 */ 2832#define WM8994_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ 2833#define WM8994_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ 2834#define WM8994_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ 2835#define WM8994_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ 2836#define WM8994_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ 2837#define WM8994_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ 2838 2839/* 2840 * R1092 (0x444) - AIF1 DRC1 (5) 2841 */ 2842#define WM8994_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2843#define WM8994_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2844#define WM8994_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2845#define WM8994_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ 2846#define WM8994_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ 2847#define WM8994_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ 2848 2849/* 2850 * R1104 (0x450) - AIF1 DRC2 (1) 2851 */ 2852#define WM8994_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2853#define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2854#define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2855#define WM8994_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2856#define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2857#define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2858#define WM8994_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ 2859#define WM8994_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ 2860#define WM8994_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ 2861#define WM8994_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ 2862#define WM8994_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 2863#define WM8994_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 2864#define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ 2865#define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ 2866#define WM8994_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ 2867#define WM8994_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ 2868#define WM8994_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ 2869#define WM8994_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ 2870#define WM8994_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 2871#define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 2872#define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ 2873#define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ 2874#define WM8994_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ 2875#define WM8994_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ 2876#define WM8994_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ 2877#define WM8994_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ 2878#define WM8994_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ 2879#define WM8994_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ 2880#define WM8994_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ 2881#define WM8994_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ 2882#define WM8994_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ 2883#define WM8994_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ 2884#define WM8994_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ 2885#define WM8994_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ 2886#define WM8994_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ 2887#define WM8994_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ 2888#define WM8994_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ 2889#define WM8994_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ 2890#define WM8994_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ 2891#define WM8994_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ 2892#define WM8994_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ 2893#define WM8994_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ 2894 2895/* 2896 * R1105 (0x451) - AIF1 DRC2 (2) 2897 */ 2898#define WM8994_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ 2899#define WM8994_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ 2900#define WM8994_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ 2901#define WM8994_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ 2902#define WM8994_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ 2903#define WM8994_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ 2904#define WM8994_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ 2905#define WM8994_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ 2906#define WM8994_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ 2907#define WM8994_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ 2908#define WM8994_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ 2909#define WM8994_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ 2910 2911/* 2912 * R1106 (0x452) - AIF1 DRC2 (3) 2913 */ 2914#define WM8994_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2915#define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2916#define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2917#define WM8994_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ 2918#define WM8994_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ 2919#define WM8994_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ 2920#define WM8994_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ 2921#define WM8994_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ 2922#define WM8994_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ 2923#define WM8994_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ 2924#define WM8994_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ 2925#define WM8994_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ 2926#define WM8994_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ 2927#define WM8994_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ 2928#define WM8994_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ 2929#define WM8994_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ 2930#define WM8994_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ 2931#define WM8994_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ 2932 2933/* 2934 * R1107 (0x453) - AIF1 DRC2 (4) 2935 */ 2936#define WM8994_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ 2937#define WM8994_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ 2938#define WM8994_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ 2939#define WM8994_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ 2940#define WM8994_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ 2941#define WM8994_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ 2942 2943/* 2944 * R1108 (0x454) - AIF1 DRC2 (5) 2945 */ 2946#define WM8994_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2947#define WM8994_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2948#define WM8994_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2949#define WM8994_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ 2950#define WM8994_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ 2951#define WM8994_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ 2952 2953/* 2954 * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) 2955 */ 2956#define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2957#define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2958#define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2959#define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2960#define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2961#define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2962#define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2963#define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2964#define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2965#define WM8994_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ 2966#define WM8994_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ 2967#define WM8994_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ 2968#define WM8994_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ 2969 2970/* 2971 * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) 2972 */ 2973#define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2974#define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2975#define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2976#define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2977#define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2978#define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2979 2980/* 2981 * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A 2982 */ 2983#define WM8994_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ 2984#define WM8994_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ 2985#define WM8994_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ 2986 2987/* 2988 * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B 2989 */ 2990#define WM8994_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ 2991#define WM8994_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ 2992#define WM8994_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ 2993 2994/* 2995 * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG 2996 */ 2997#define WM8994_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2998#define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2999#define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 3000 3001/* 3002 * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A 3003 */ 3004#define WM8994_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ 3005#define WM8994_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ 3006#define WM8994_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ 3007 3008/* 3009 * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B 3010 */ 3011#define WM8994_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ 3012#define WM8994_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ 3013#define WM8994_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ 3014 3015/* 3016 * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C 3017 */ 3018#define WM8994_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ 3019#define WM8994_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ 3020#define WM8994_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ 3021 3022/* 3023 * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG 3024 */ 3025#define WM8994_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3026#define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3027#define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3028 3029/* 3030 * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A 3031 */ 3032#define WM8994_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ 3033#define WM8994_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ 3034#define WM8994_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ 3035 3036/* 3037 * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B 3038 */ 3039#define WM8994_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ 3040#define WM8994_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ 3041#define WM8994_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ 3042 3043/* 3044 * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C 3045 */ 3046#define WM8994_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ 3047#define WM8994_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ 3048#define WM8994_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ 3049 3050/* 3051 * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG 3052 */ 3053#define WM8994_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3054#define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3055#define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3056 3057/* 3058 * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A 3059 */ 3060#define WM8994_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ 3061#define WM8994_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ 3062#define WM8994_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ 3063 3064/* 3065 * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B 3066 */ 3067#define WM8994_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ 3068#define WM8994_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ 3069#define WM8994_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ 3070 3071/* 3072 * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C 3073 */ 3074#define WM8994_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ 3075#define WM8994_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ 3076#define WM8994_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ 3077 3078/* 3079 * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG 3080 */ 3081#define WM8994_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3082#define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3083#define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3084 3085/* 3086 * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A 3087 */ 3088#define WM8994_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ 3089#define WM8994_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ 3090#define WM8994_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ 3091 3092/* 3093 * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B 3094 */ 3095#define WM8994_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ 3096#define WM8994_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ 3097#define WM8994_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ 3098 3099/* 3100 * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG 3101 */ 3102#define WM8994_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3103#define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3104#define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3105 3106/* 3107 * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) 3108 */ 3109#define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3110#define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3111#define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3112#define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3113#define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3114#define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3115#define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3116#define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3117#define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3118#define WM8994_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ 3119#define WM8994_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ 3120#define WM8994_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ 3121#define WM8994_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ 3122 3123/* 3124 * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) 3125 */ 3126#define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3127#define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3128#define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3129#define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3130#define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3131#define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3132 3133/* 3134 * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A 3135 */ 3136#define WM8994_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ 3137#define WM8994_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ 3138#define WM8994_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ 3139 3140/* 3141 * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B 3142 */ 3143#define WM8994_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ 3144#define WM8994_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ 3145#define WM8994_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ 3146 3147/* 3148 * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG 3149 */ 3150#define WM8994_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3151#define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3152#define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3153 3154/* 3155 * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A 3156 */ 3157#define WM8994_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ 3158#define WM8994_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ 3159#define WM8994_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ 3160 3161/* 3162 * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B 3163 */ 3164#define WM8994_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ 3165#define WM8994_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ 3166#define WM8994_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ 3167 3168/* 3169 * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C 3170 */ 3171#define WM8994_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ 3172#define WM8994_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ 3173#define WM8994_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ 3174 3175/* 3176 * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG 3177 */ 3178#define WM8994_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3179#define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3180#define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3181 3182/* 3183 * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A 3184 */ 3185#define WM8994_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ 3186#define WM8994_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ 3187#define WM8994_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ 3188 3189/* 3190 * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B 3191 */ 3192#define WM8994_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ 3193#define WM8994_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ 3194#define WM8994_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ 3195 3196/* 3197 * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C 3198 */ 3199#define WM8994_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ 3200#define WM8994_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ 3201#define WM8994_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ 3202 3203/* 3204 * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG 3205 */ 3206#define WM8994_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3207#define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3208#define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3209 3210/* 3211 * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A 3212 */ 3213#define WM8994_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ 3214#define WM8994_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ 3215#define WM8994_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ 3216 3217/* 3218 * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B 3219 */ 3220#define WM8994_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ 3221#define WM8994_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ 3222#define WM8994_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ 3223 3224/* 3225 * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C 3226 */ 3227#define WM8994_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ 3228#define WM8994_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ 3229#define WM8994_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ 3230 3231/* 3232 * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG 3233 */ 3234#define WM8994_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3235#define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3236#define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3237 3238/* 3239 * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A 3240 */ 3241#define WM8994_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ 3242#define WM8994_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ 3243#define WM8994_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ 3244 3245/* 3246 * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B 3247 */ 3248#define WM8994_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ 3249#define WM8994_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ 3250#define WM8994_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ 3251 3252/* 3253 * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG 3254 */ 3255#define WM8994_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3256#define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3257#define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3258 3259/* 3260 * R1280 (0x500) - AIF2 ADC Left Volume 3261 */ 3262#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 3263#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 3264#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 3265#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 3266#define WM8994_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ 3267#define WM8994_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ 3268#define WM8994_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ 3269 3270/* 3271 * R1281 (0x501) - AIF2 ADC Right Volume 3272 */ 3273#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 3274#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 3275#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 3276#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 3277#define WM8994_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ 3278#define WM8994_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ 3279#define WM8994_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ 3280 3281/* 3282 * R1282 (0x502) - AIF2 DAC Left Volume 3283 */ 3284#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 3285#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 3286#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 3287#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 3288#define WM8994_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ 3289#define WM8994_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ 3290#define WM8994_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ 3291 3292/* 3293 * R1283 (0x503) - AIF2 DAC Right Volume 3294 */ 3295#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 3296#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 3297#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 3298#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 3299#define WM8994_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ 3300#define WM8994_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ 3301#define WM8994_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ 3302 3303/* 3304 * R1296 (0x510) - AIF2 ADC Filters 3305 */ 3306#define WM8994_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ 3307#define WM8994_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ 3308#define WM8994_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ 3309#define WM8994_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ 3310#define WM8994_AIF2ADC_HPF_CUT_MASK 0x6000 /* AIF2ADC_HPF_CUT - [14:13] */ 3311#define WM8994_AIF2ADC_HPF_CUT_SHIFT 13 /* AIF2ADC_HPF_CUT - [14:13] */ 3312#define WM8994_AIF2ADC_HPF_CUT_WIDTH 2 /* AIF2ADC_HPF_CUT - [14:13] */ 3313#define WM8994_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ 3314#define WM8994_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ 3315#define WM8994_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ 3316#define WM8994_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ 3317#define WM8994_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ 3318#define WM8994_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ 3319#define WM8994_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ 3320#define WM8994_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ 3321 3322/* 3323 * R1312 (0x520) - AIF2 DAC Filters (1) 3324 */ 3325#define WM8994_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ 3326#define WM8994_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ 3327#define WM8994_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ 3328#define WM8994_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ 3329#define WM8994_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ 3330#define WM8994_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ 3331#define WM8994_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ 3332#define WM8994_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ 3333#define WM8994_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ 3334#define WM8994_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ 3335#define WM8994_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ 3336#define WM8994_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ 3337#define WM8994_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 3338#define WM8994_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 3339#define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ 3340#define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ 3341#define WM8994_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ 3342#define WM8994_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ 3343#define WM8994_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ 3344 3345/* 3346 * R1313 (0x521) - AIF2 DAC Filters (2) 3347 */ 3348#define WM8994_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ 3349#define WM8994_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ 3350#define WM8994_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ 3351#define WM8994_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ 3352#define WM8994_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ 3353#define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ 3354#define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ 3355 3356/* 3357 * R1344 (0x540) - AIF2 DRC (1) 3358 */ 3359#define WM8994_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3360#define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3361#define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3362#define WM8994_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3363#define WM8994_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3364#define WM8994_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3365#define WM8994_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ 3366#define WM8994_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ 3367#define WM8994_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ 3368#define WM8994_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ 3369#define WM8994_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ 3370#define WM8994_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ 3371#define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ 3372#define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ 3373#define WM8994_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ 3374#define WM8994_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ 3375#define WM8994_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ 3376#define WM8994_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ 3377#define WM8994_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 3378#define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 3379#define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ 3380#define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ 3381#define WM8994_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ 3382#define WM8994_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ 3383#define WM8994_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ 3384#define WM8994_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ 3385#define WM8994_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ 3386#define WM8994_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ 3387#define WM8994_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ 3388#define WM8994_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ 3389#define WM8994_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ 3390#define WM8994_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ 3391#define WM8994_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ 3392#define WM8994_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ 3393#define WM8994_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ 3394#define WM8994_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ 3395#define WM8994_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ 3396#define WM8994_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ 3397#define WM8994_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ 3398#define WM8994_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ 3399#define WM8994_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ 3400#define WM8994_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ 3401 3402/* 3403 * R1345 (0x541) - AIF2 DRC (2) 3404 */ 3405#define WM8994_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ 3406#define WM8994_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ 3407#define WM8994_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ 3408#define WM8994_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ 3409#define WM8994_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ 3410#define WM8994_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ 3411#define WM8994_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ 3412#define WM8994_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ 3413#define WM8994_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ 3414#define WM8994_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ 3415#define WM8994_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ 3416#define WM8994_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ 3417 3418/* 3419 * R1346 (0x542) - AIF2 DRC (3) 3420 */ 3421#define WM8994_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3422#define WM8994_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3423#define WM8994_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3424#define WM8994_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ 3425#define WM8994_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ 3426#define WM8994_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ 3427#define WM8994_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ 3428#define WM8994_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ 3429#define WM8994_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ 3430#define WM8994_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ 3431#define WM8994_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ 3432#define WM8994_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ 3433#define WM8994_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ 3434#define WM8994_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ 3435#define WM8994_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ 3436#define WM8994_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ 3437#define WM8994_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ 3438#define WM8994_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ 3439 3440/* 3441 * R1347 (0x543) - AIF2 DRC (4) 3442 */ 3443#define WM8994_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ 3444#define WM8994_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ 3445#define WM8994_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ 3446#define WM8994_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ 3447#define WM8994_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ 3448#define WM8994_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ 3449 3450/* 3451 * R1348 (0x544) - AIF2 DRC (5) 3452 */ 3453#define WM8994_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ 3454#define WM8994_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 3455#define WM8994_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 3456#define WM8994_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ 3457#define WM8994_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ 3458#define WM8994_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ 3459 3460/* 3461 * R1408 (0x580) - AIF2 EQ Gains (1) 3462 */ 3463#define WM8994_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3464#define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3465#define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3466#define WM8994_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3467#define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3468#define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3469#define WM8994_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3470#define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3471#define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3472#define WM8994_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ 3473#define WM8994_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ 3474#define WM8994_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ 3475#define WM8994_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ 3476 3477/* 3478 * R1409 (0x581) - AIF2 EQ Gains (2) 3479 */ 3480#define WM8994_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3481#define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3482#define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3483#define WM8994_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3484#define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3485#define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3486 3487/* 3488 * R1410 (0x582) - AIF2 EQ Band 1 A 3489 */ 3490#define WM8994_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ 3491#define WM8994_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ 3492#define WM8994_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ 3493 3494/* 3495 * R1411 (0x583) - AIF2 EQ Band 1 B 3496 */ 3497#define WM8994_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ 3498#define WM8994_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ 3499#define WM8994_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ 3500 3501/* 3502 * R1412 (0x584) - AIF2 EQ Band 1 PG 3503 */ 3504#define WM8994_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ 3505#define WM8994_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ 3506#define WM8994_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ 3507 3508/* 3509 * R1413 (0x585) - AIF2 EQ Band 2 A 3510 */ 3511#define WM8994_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ 3512#define WM8994_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ 3513#define WM8994_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ 3514 3515/* 3516 * R1414 (0x586) - AIF2 EQ Band 2 B 3517 */ 3518#define WM8994_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ 3519#define WM8994_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ 3520#define WM8994_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ 3521 3522/* 3523 * R1415 (0x587) - AIF2 EQ Band 2 C 3524 */ 3525#define WM8994_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ 3526#define WM8994_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ 3527#define WM8994_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ 3528 3529/* 3530 * R1416 (0x588) - AIF2 EQ Band 2 PG 3531 */ 3532#define WM8994_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ 3533#define WM8994_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3534#define WM8994_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3535 3536/* 3537 * R1417 (0x589) - AIF2 EQ Band 3 A 3538 */ 3539#define WM8994_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ 3540#define WM8994_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ 3541#define WM8994_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ 3542 3543/* 3544 * R1418 (0x58A) - AIF2 EQ Band 3 B 3545 */ 3546#define WM8994_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ 3547#define WM8994_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ 3548#define WM8994_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ 3549 3550/* 3551 * R1419 (0x58B) - AIF2 EQ Band 3 C 3552 */ 3553#define WM8994_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ 3554#define WM8994_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ 3555#define WM8994_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ 3556 3557/* 3558 * R1420 (0x58C) - AIF2 EQ Band 3 PG 3559 */ 3560#define WM8994_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ 3561#define WM8994_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3562#define WM8994_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3563 3564/* 3565 * R1421 (0x58D) - AIF2 EQ Band 4 A 3566 */ 3567#define WM8994_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ 3568#define WM8994_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ 3569#define WM8994_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ 3570 3571/* 3572 * R1422 (0x58E) - AIF2 EQ Band 4 B 3573 */ 3574#define WM8994_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ 3575#define WM8994_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ 3576#define WM8994_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ 3577 3578/* 3579 * R1423 (0x58F) - AIF2 EQ Band 4 C 3580 */ 3581#define WM8994_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ 3582#define WM8994_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ 3583#define WM8994_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ 3584 3585/* 3586 * R1424 (0x590) - AIF2 EQ Band 4 PG 3587 */ 3588#define WM8994_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ 3589#define WM8994_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3590#define WM8994_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3591 3592/* 3593 * R1425 (0x591) - AIF2 EQ Band 5 A 3594 */ 3595#define WM8994_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ 3596#define WM8994_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ 3597#define WM8994_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ 3598 3599/* 3600 * R1426 (0x592) - AIF2 EQ Band 5 B 3601 */ 3602#define WM8994_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ 3603#define WM8994_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ 3604#define WM8994_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ 3605 3606/* 3607 * R1427 (0x593) - AIF2 EQ Band 5 PG 3608 */ 3609#define WM8994_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ 3610#define WM8994_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3611#define WM8994_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3612 3613/* 3614 * R1536 (0x600) - DAC1 Mixer Volumes 3615 */ 3616#define WM8994_ADCR_DAC1_VOL_MASK 0x01E0 /* ADCR_DAC1_VOL - [8:5] */ 3617#define WM8994_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [8:5] */ 3618#define WM8994_ADCR_DAC1_VOL_WIDTH 4 /* ADCR_DAC1_VOL - [8:5] */ 3619#define WM8994_ADCL_DAC1_VOL_MASK 0x000F /* ADCL_DAC1_VOL - [3:0] */ 3620#define WM8994_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [3:0] */ 3621#define WM8994_ADCL_DAC1_VOL_WIDTH 4 /* ADCL_DAC1_VOL - [3:0] */ 3622 3623/* 3624 * R1537 (0x601) - DAC1 Left Mixer Routing 3625 */ 3626#define WM8994_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 3627#define WM8994_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 3628#define WM8994_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 3629#define WM8994_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 3630#define WM8994_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 3631#define WM8994_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 3632#define WM8994_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 3633#define WM8994_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 3634#define WM8994_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ 3635#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ 3636#define WM8994_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ 3637#define WM8994_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ 3638#define WM8994_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3639#define WM8994_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3640#define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ 3641#define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ 3642#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3643#define WM8994_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3644#define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ 3645#define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ 3646 3647/* 3648 * R1538 (0x602) - DAC1 Right Mixer Routing 3649 */ 3650#define WM8994_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 3651#define WM8994_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 3652#define WM8994_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 3653#define WM8994_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 3654#define WM8994_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 3655#define WM8994_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 3656#define WM8994_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 3657#define WM8994_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 3658#define WM8994_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ 3659#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ 3660#define WM8994_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ 3661#define WM8994_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ 3662#define WM8994_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3663#define WM8994_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3664#define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ 3665#define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ 3666#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3667#define WM8994_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3668#define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ 3669#define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ 3670 3671/* 3672 * R1539 (0x603) - DAC2 Mixer Volumes 3673 */ 3674#define WM8994_ADCR_DAC2_VOL_MASK 0x01E0 /* ADCR_DAC2_VOL - [8:5] */ 3675#define WM8994_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [8:5] */ 3676#define WM8994_ADCR_DAC2_VOL_WIDTH 4 /* ADCR_DAC2_VOL - [8:5] */ 3677#define WM8994_ADCL_DAC2_VOL_MASK 0x000F /* ADCL_DAC2_VOL - [3:0] */ 3678#define WM8994_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [3:0] */ 3679#define WM8994_ADCL_DAC2_VOL_WIDTH 4 /* ADCL_DAC2_VOL - [3:0] */ 3680 3681/* 3682 * R1540 (0x604) - DAC2 Left Mixer Routing 3683 */ 3684#define WM8994_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 3685#define WM8994_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 3686#define WM8994_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 3687#define WM8994_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 3688#define WM8994_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 3689#define WM8994_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 3690#define WM8994_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 3691#define WM8994_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 3692#define WM8994_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ 3693#define WM8994_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ 3694#define WM8994_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ 3695#define WM8994_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ 3696#define WM8994_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3697#define WM8994_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3698#define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ 3699#define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ 3700#define WM8994_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3701#define WM8994_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3702#define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ 3703#define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ 3704 3705/* 3706 * R1541 (0x605) - DAC2 Right Mixer Routing 3707 */ 3708#define WM8994_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 3709#define WM8994_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 3710#define WM8994_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 3711#define WM8994_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 3712#define WM8994_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 3713#define WM8994_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 3714#define WM8994_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 3715#define WM8994_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 3716#define WM8994_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ 3717#define WM8994_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ 3718#define WM8994_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ 3719#define WM8994_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ 3720#define WM8994_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3721#define WM8994_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3722#define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ 3723#define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ 3724#define WM8994_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3725#define WM8994_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3726#define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ 3727#define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ 3728 3729/* 3730 * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing 3731 */ 3732#define WM8994_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3733#define WM8994_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3734#define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ 3735#define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ 3736#define WM8994_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3737#define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3738#define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ 3739#define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ 3740 3741/* 3742 * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing 3743 */ 3744#define WM8994_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3745#define WM8994_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3746#define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ 3747#define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ 3748#define WM8994_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3749#define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3750#define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ 3751#define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ 3752 3753/* 3754 * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing 3755 */ 3756#define WM8994_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3757#define WM8994_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3758#define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ 3759#define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ 3760#define WM8994_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3761#define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3762#define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ 3763#define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ 3764 3765/* 3766 * R1545 (0x609) - AIF1 ADC2 Right mixer Routing 3767 */ 3768#define WM8994_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3769#define WM8994_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3770#define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ 3771#define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ 3772#define WM8994_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3773#define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3774#define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ 3775#define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ 3776 3777/* 3778 * R1552 (0x610) - DAC1 Left Volume 3779 */ 3780#define WM8994_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 3781#define WM8994_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 3782#define WM8994_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 3783#define WM8994_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 3784#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */ 3785#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 3786#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */ 3787#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */ 3788#define WM8994_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 3789#define WM8994_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 3790#define WM8994_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 3791 3792/* 3793 * R1553 (0x611) - DAC1 Right Volume 3794 */ 3795#define WM8994_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 3796#define WM8994_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 3797#define WM8994_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 3798#define WM8994_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 3799#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */ 3800#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 3801#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */ 3802#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */ 3803#define WM8994_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 3804#define WM8994_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 3805#define WM8994_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 3806 3807/* 3808 * R1554 (0x612) - DAC2 Left Volume 3809 */ 3810#define WM8994_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 3811#define WM8994_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 3812#define WM8994_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 3813#define WM8994_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 3814#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */ 3815#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 3816#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */ 3817#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */ 3818#define WM8994_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 3819#define WM8994_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 3820#define WM8994_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 3821 3822/* 3823 * R1555 (0x613) - DAC2 Right Volume 3824 */ 3825#define WM8994_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 3826#define WM8994_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 3827#define WM8994_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 3828#define WM8994_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 3829#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */ 3830#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 3831#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */ 3832#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */ 3833#define WM8994_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 3834#define WM8994_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 3835#define WM8994_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 3836 3837/* 3838 * R1556 (0x614) - DAC Softmute 3839 */ 3840#define WM8994_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 3841#define WM8994_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 3842#define WM8994_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 3843#define WM8994_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 3844#define WM8994_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 3845#define WM8994_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 3846#define WM8994_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 3847#define WM8994_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 3848 3849/* 3850 * R1568 (0x620) - Oversampling 3851 */ 3852#define WM8994_ADC_OSR128 0x0002 /* ADC_OSR128 */ 3853#define WM8994_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 3854#define WM8994_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 3855#define WM8994_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 3856#define WM8994_DAC_OSR128 0x0001 /* DAC_OSR128 */ 3857#define WM8994_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 3858#define WM8994_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 3859#define WM8994_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 3860 3861/* 3862 * R1569 (0x621) - Sidetone 3863 */ 3864#define WM8994_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 3865#define WM8994_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 3866#define WM8994_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 3867#define WM8994_ST_HPF 0x0040 /* ST_HPF */ 3868#define WM8994_ST_HPF_MASK 0x0040 /* ST_HPF */ 3869#define WM8994_ST_HPF_SHIFT 6 /* ST_HPF */ 3870#define WM8994_ST_HPF_WIDTH 1 /* ST_HPF */ 3871#define WM8994_STR_SEL 0x0002 /* STR_SEL */ 3872#define WM8994_STR_SEL_MASK 0x0002 /* STR_SEL */ 3873#define WM8994_STR_SEL_SHIFT 1 /* STR_SEL */ 3874#define WM8994_STR_SEL_WIDTH 1 /* STR_SEL */ 3875#define WM8994_STL_SEL 0x0001 /* STL_SEL */ 3876#define WM8994_STL_SEL_MASK 0x0001 /* STL_SEL */ 3877#define WM8994_STL_SEL_SHIFT 0 /* STL_SEL */ 3878#define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */ 3879 3880/* 3881 * R1824 (0x720) - Pull Control (1) 3882 */ 3883#define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */ 3884#define WM8994_DMICDAT2_PU_MASK 0x0800 /* DMICDAT2_PU */ 3885#define WM8994_DMICDAT2_PU_SHIFT 11 /* DMICDAT2_PU */ 3886#define WM8994_DMICDAT2_PU_WIDTH 1 /* DMICDAT2_PU */ 3887#define WM8994_DMICDAT2_PD 0x0400 /* DMICDAT2_PD */ 3888#define WM8994_DMICDAT2_PD_MASK 0x0400 /* DMICDAT2_PD */ 3889#define WM8994_DMICDAT2_PD_SHIFT 10 /* DMICDAT2_PD */ 3890#define WM8994_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3891#define WM8994_DMICDAT1_PU 0x0200 /* DMICDAT1_PU */ 3892#define WM8994_DMICDAT1_PU_MASK 0x0200 /* DMICDAT1_PU */ 3893#define WM8994_DMICDAT1_PU_SHIFT 9 /* DMICDAT1_PU */ 3894#define WM8994_DMICDAT1_PU_WIDTH 1 /* DMICDAT1_PU */ 3895#define WM8994_DMICDAT1_PD 0x0100 /* DMICDAT1_PD */ 3896#define WM8994_DMICDAT1_PD_MASK 0x0100 /* DMICDAT1_PD */ 3897#define WM8994_DMICDAT1_PD_SHIFT 8 /* DMICDAT1_PD */ 3898#define WM8994_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3899#define WM8994_MCLK1_PU 0x0080 /* MCLK1_PU */ 3900#define WM8994_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 3901#define WM8994_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 3902#define WM8994_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 3903#define WM8994_MCLK1_PD 0x0040 /* MCLK1_PD */ 3904#define WM8994_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 3905#define WM8994_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 3906#define WM8994_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3907#define WM8994_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 3908#define WM8994_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 3909#define WM8994_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 3910#define WM8994_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 3911#define WM8994_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 3912#define WM8994_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 3913#define WM8994_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 3914#define WM8994_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 3915#define WM8994_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 3916#define WM8994_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 3917#define WM8994_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 3918#define WM8994_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 3919#define WM8994_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 3920#define WM8994_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 3921#define WM8994_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 3922#define WM8994_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 3923#define WM8994_BCLK1_PU 0x0002 /* BCLK1_PU */ 3924#define WM8994_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 3925#define WM8994_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 3926#define WM8994_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 3927#define WM8994_BCLK1_PD 0x0001 /* BCLK1_PD */ 3928#define WM8994_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 3929#define WM8994_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 3930#define WM8994_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 3931 3932/* 3933 * R1825 (0x721) - Pull Control (2) 3934 */ 3935#define WM8994_CSNADDR_PD 0x0100 /* CSNADDR_PD */ 3936#define WM8994_CSNADDR_PD_MASK 0x0100 /* CSNADDR_PD */ 3937#define WM8994_CSNADDR_PD_SHIFT 8 /* CSNADDR_PD */ 3938#define WM8994_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ 3939#define WM8994_LDO2ENA_PD 0x0040 /* LDO2ENA_PD */ 3940#define WM8994_LDO2ENA_PD_MASK 0x0040 /* LDO2ENA_PD */ 3941#define WM8994_LDO2ENA_PD_SHIFT 6 /* LDO2ENA_PD */ 3942#define WM8994_LDO2ENA_PD_WIDTH 1 /* LDO2ENA_PD */ 3943#define WM8994_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ 3944#define WM8994_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ 3945#define WM8994_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ 3946#define WM8994_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3947#define WM8994_CIFMODE_PD 0x0004 /* CIFMODE_PD */ 3948#define WM8994_CIFMODE_PD_MASK 0x0004 /* CIFMODE_PD */ 3949#define WM8994_CIFMODE_PD_SHIFT 2 /* CIFMODE_PD */ 3950#define WM8994_CIFMODE_PD_WIDTH 1 /* CIFMODE_PD */ 3951#define WM8994_SPKMODE_PU 0x0002 /* SPKMODE_PU */ 3952#define WM8994_SPKMODE_PU_MASK 0x0002 /* SPKMODE_PU */ 3953#define WM8994_SPKMODE_PU_SHIFT 1 /* SPKMODE_PU */ 3954#define WM8994_SPKMODE_PU_WIDTH 1 /* SPKMODE_PU */ 3955 3956/* 3957 * R1840 (0x730) - Interrupt Status 1 3958 */ 3959#define WM8994_GP11_EINT 0x0400 /* GP11_EINT */ 3960#define WM8994_GP11_EINT_MASK 0x0400 /* GP11_EINT */ 3961#define WM8994_GP11_EINT_SHIFT 10 /* GP11_EINT */ 3962#define WM8994_GP11_EINT_WIDTH 1 /* GP11_EINT */ 3963#define WM8994_GP10_EINT 0x0200 /* GP10_EINT */ 3964#define WM8994_GP10_EINT_MASK 0x0200 /* GP10_EINT */ 3965#define WM8994_GP10_EINT_SHIFT 9 /* GP10_EINT */ 3966#define WM8994_GP10_EINT_WIDTH 1 /* GP10_EINT */ 3967#define WM8994_GP9_EINT 0x0100 /* GP9_EINT */ 3968#define WM8994_GP9_EINT_MASK 0x0100 /* GP9_EINT */ 3969#define WM8994_GP9_EINT_SHIFT 8 /* GP9_EINT */ 3970#define WM8994_GP9_EINT_WIDTH 1 /* GP9_EINT */ 3971#define WM8994_GP8_EINT 0x0080 /* GP8_EINT */ 3972#define WM8994_GP8_EINT_MASK 0x0080 /* GP8_EINT */ 3973#define WM8994_GP8_EINT_SHIFT 7 /* GP8_EINT */ 3974#define WM8994_GP8_EINT_WIDTH 1 /* GP8_EINT */ 3975#define WM8994_GP7_EINT 0x0040 /* GP7_EINT */ 3976#define WM8994_GP7_EINT_MASK 0x0040 /* GP7_EINT */ 3977#define WM8994_GP7_EINT_SHIFT 6 /* GP7_EINT */ 3978#define WM8994_GP7_EINT_WIDTH 1 /* GP7_EINT */ 3979#define WM8994_GP6_EINT 0x0020 /* GP6_EINT */ 3980#define WM8994_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3981#define WM8994_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3982#define WM8994_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3983#define WM8994_GP5_EINT 0x0010 /* GP5_EINT */ 3984#define WM8994_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3985#define WM8994_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3986#define WM8994_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3987#define WM8994_GP4_EINT 0x0008 /* GP4_EINT */ 3988#define WM8994_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3989#define WM8994_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3990#define WM8994_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3991#define WM8994_GP3_EINT 0x0004 /* GP3_EINT */ 3992#define WM8994_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3993#define WM8994_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3994#define WM8994_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3995#define WM8994_GP2_EINT 0x0002 /* GP2_EINT */ 3996#define WM8994_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3997#define WM8994_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3998#define WM8994_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3999#define WM8994_GP1_EINT 0x0001 /* GP1_EINT */ 4000#define WM8994_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 4001#define WM8994_GP1_EINT_SHIFT 0 /* GP1_EINT */ 4002#define WM8994_GP1_EINT_WIDTH 1 /* GP1_EINT */ 4003 4004/* 4005 * R1841 (0x731) - Interrupt Status 2 4006 */ 4007#define WM8994_TEMP_WARN_EINT 0x8000 /* TEMP_WARN_EINT */ 4008#define WM8994_TEMP_WARN_EINT_MASK 0x8000 /* TEMP_WARN_EINT */ 4009#define WM8994_TEMP_WARN_EINT_SHIFT 15 /* TEMP_WARN_EINT */ 4010#define WM8994_TEMP_WARN_EINT_WIDTH 1 /* TEMP_WARN_EINT */ 4011#define WM8994_DCS_DONE_EINT 0x4000 /* DCS_DONE_EINT */ 4012#define WM8994_DCS_DONE_EINT_MASK 0x4000 /* DCS_DONE_EINT */ 4013#define WM8994_DCS_DONE_EINT_SHIFT 14 /* DCS_DONE_EINT */ 4014#define WM8994_DCS_DONE_EINT_WIDTH 1 /* DCS_DONE_EINT */ 4015#define WM8994_WSEQ_DONE_EINT 0x2000 /* WSEQ_DONE_EINT */ 4016#define WM8994_WSEQ_DONE_EINT_MASK 0x2000 /* WSEQ_DONE_EINT */ 4017#define WM8994_WSEQ_DONE_EINT_SHIFT 13 /* WSEQ_DONE_EINT */ 4018#define WM8994_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 4019#define WM8994_FIFOS_ERR_EINT 0x1000 /* FIFOS_ERR_EINT */ 4020#define WM8994_FIFOS_ERR_EINT_MASK 0x1000 /* FIFOS_ERR_EINT */ 4021#define WM8994_FIFOS_ERR_EINT_SHIFT 12 /* FIFOS_ERR_EINT */ 4022#define WM8994_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 4023#define WM8994_AIF2DRC_SIG_DET_EINT 0x0800 /* AIF2DRC_SIG_DET_EINT */ 4024#define WM8994_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* AIF2DRC_SIG_DET_EINT */ 4025#define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* AIF2DRC_SIG_DET_EINT */ 4026#define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ 4027#define WM8994_AIF1DRC2_SIG_DET_EINT 0x0400 /* AIF1DRC2_SIG_DET_EINT */ 4028#define WM8994_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* AIF1DRC2_SIG_DET_EINT */ 4029#define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* AIF1DRC2_SIG_DET_EINT */ 4030#define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ 4031#define WM8994_AIF1DRC1_SIG_DET_EINT 0x0200 /* AIF1DRC1_SIG_DET_EINT */ 4032#define WM8994_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* AIF1DRC1_SIG_DET_EINT */ 4033#define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* AIF1DRC1_SIG_DET_EINT */ 4034#define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ 4035#define WM8994_SRC2_LOCK_EINT 0x0100 /* SRC2_LOCK_EINT */ 4036#define WM8994_SRC2_LOCK_EINT_MASK 0x0100 /* SRC2_LOCK_EINT */ 4037#define WM8994_SRC2_LOCK_EINT_SHIFT 8 /* SRC2_LOCK_EINT */ 4038#define WM8994_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ 4039#define WM8994_SRC1_LOCK_EINT 0x0080 /* SRC1_LOCK_EINT */ 4040#define WM8994_SRC1_LOCK_EINT_MASK 0x0080 /* SRC1_LOCK_EINT */ 4041#define WM8994_SRC1_LOCK_EINT_SHIFT 7 /* SRC1_LOCK_EINT */ 4042#define WM8994_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ 4043#define WM8994_FLL2_LOCK_EINT 0x0040 /* FLL2_LOCK_EINT */ 4044#define WM8994_FLL2_LOCK_EINT_MASK 0x0040 /* FLL2_LOCK_EINT */ 4045#define WM8994_FLL2_LOCK_EINT_SHIFT 6 /* FLL2_LOCK_EINT */ 4046#define WM8994_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 4047#define WM8994_FLL1_LOCK_EINT 0x0020 /* FLL1_LOCK_EINT */ 4048#define WM8994_FLL1_LOCK_EINT_MASK 0x0020 /* FLL1_LOCK_EINT */ 4049#define WM8994_FLL1_LOCK_EINT_SHIFT 5 /* FLL1_LOCK_EINT */ 4050#define WM8994_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 4051#define WM8994_MIC2_SHRT_EINT 0x0010 /* MIC2_SHRT_EINT */ 4052#define WM8994_MIC2_SHRT_EINT_MASK 0x0010 /* MIC2_SHRT_EINT */ 4053#define WM8994_MIC2_SHRT_EINT_SHIFT 4 /* MIC2_SHRT_EINT */ 4054#define WM8994_MIC2_SHRT_EINT_WIDTH 1 /* MIC2_SHRT_EINT */ 4055#define WM8994_MIC2_DET_EINT 0x0008 /* MIC2_DET_EINT */ 4056#define WM8994_MIC2_DET_EINT_MASK 0x0008 /* MIC2_DET_EINT */ 4057#define WM8994_MIC2_DET_EINT_SHIFT 3 /* MIC2_DET_EINT */ 4058#define WM8994_MIC2_DET_EINT_WIDTH 1 /* MIC2_DET_EINT */ 4059#define WM8994_MIC1_SHRT_EINT 0x0004 /* MIC1_SHRT_EINT */ 4060#define WM8994_MIC1_SHRT_EINT_MASK 0x0004 /* MIC1_SHRT_EINT */ 4061#define WM8994_MIC1_SHRT_EINT_SHIFT 2 /* MIC1_SHRT_EINT */ 4062#define WM8994_MIC1_SHRT_EINT_WIDTH 1 /* MIC1_SHRT_EINT */ 4063#define WM8994_MIC1_DET_EINT 0x0002 /* MIC1_DET_EINT */ 4064#define WM8994_MIC1_DET_EINT_MASK 0x0002 /* MIC1_DET_EINT */ 4065#define WM8994_MIC1_DET_EINT_SHIFT 1 /* MIC1_DET_EINT */ 4066#define WM8994_MIC1_DET_EINT_WIDTH 1 /* MIC1_DET_EINT */ 4067#define WM8994_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */ 4068#define WM8994_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */ 4069#define WM8994_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */ 4070#define WM8994_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */ 4071 4072/* 4073 * R1842 (0x732) - Interrupt Raw Status 2 4074 */ 4075#define WM8994_TEMP_WARN_STS 0x8000 /* TEMP_WARN_STS */ 4076#define WM8994_TEMP_WARN_STS_MASK 0x8000 /* TEMP_WARN_STS */ 4077#define WM8994_TEMP_WARN_STS_SHIFT 15 /* TEMP_WARN_STS */ 4078#define WM8994_TEMP_WARN_STS_WIDTH 1 /* TEMP_WARN_STS */ 4079#define WM8994_DCS_DONE_STS 0x4000 /* DCS_DONE_STS */ 4080#define WM8994_DCS_DONE_STS_MASK 0x4000 /* DCS_DONE_STS */ 4081#define WM8994_DCS_DONE_STS_SHIFT 14 /* DCS_DONE_STS */ 4082#define WM8994_DCS_DONE_STS_WIDTH 1 /* DCS_DONE_STS */ 4083#define WM8994_WSEQ_DONE_STS 0x2000 /* WSEQ_DONE_STS */ 4084#define WM8994_WSEQ_DONE_STS_MASK 0x2000 /* WSEQ_DONE_STS */ 4085#define WM8994_WSEQ_DONE_STS_SHIFT 13 /* WSEQ_DONE_STS */ 4086#define WM8994_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 4087#define WM8994_FIFOS_ERR_STS 0x1000 /* FIFOS_ERR_STS */ 4088#define WM8994_FIFOS_ERR_STS_MASK 0x1000 /* FIFOS_ERR_STS */ 4089#define WM8994_FIFOS_ERR_STS_SHIFT 12 /* FIFOS_ERR_STS */ 4090#define WM8994_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 4091#define WM8994_AIF2DRC_SIG_DET_STS 0x0800 /* AIF2DRC_SIG_DET_STS */ 4092#define WM8994_AIF2DRC_SIG_DET_STS_MASK 0x0800 /* AIF2DRC_SIG_DET_STS */ 4093#define WM8994_AIF2DRC_SIG_DET_STS_SHIFT 11 /* AIF2DRC_SIG_DET_STS */ 4094#define WM8994_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ 4095#define WM8994_AIF1DRC2_SIG_DET_STS 0x0400 /* AIF1DRC2_SIG_DET_STS */ 4096#define WM8994_AIF1DRC2_SIG_DET_STS_MASK 0x0400 /* AIF1DRC2_SIG_DET_STS */ 4097#define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT 10 /* AIF1DRC2_SIG_DET_STS */ 4098#define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ 4099#define WM8994_AIF1DRC1_SIG_DET_STS 0x0200 /* AIF1DRC1_SIG_DET_STS */ 4100#define WM8994_AIF1DRC1_SIG_DET_STS_MASK 0x0200 /* AIF1DRC1_SIG_DET_STS */ 4101#define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT 9 /* AIF1DRC1_SIG_DET_STS */ 4102#define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ 4103#define WM8994_SRC2_LOCK_STS 0x0100 /* SRC2_LOCK_STS */ 4104#define WM8994_SRC2_LOCK_STS_MASK 0x0100 /* SRC2_LOCK_STS */ 4105#define WM8994_SRC2_LOCK_STS_SHIFT 8 /* SRC2_LOCK_STS */ 4106#define WM8994_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ 4107#define WM8994_SRC1_LOCK_STS 0x0080 /* SRC1_LOCK_STS */ 4108#define WM8994_SRC1_LOCK_STS_MASK 0x0080 /* SRC1_LOCK_STS */ 4109#define WM8994_SRC1_LOCK_STS_SHIFT 7 /* SRC1_LOCK_STS */ 4110#define WM8994_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ 4111#define WM8994_FLL2_LOCK_STS 0x0040 /* FLL2_LOCK_STS */ 4112#define WM8994_FLL2_LOCK_STS_MASK 0x0040 /* FLL2_LOCK_STS */ 4113#define WM8994_FLL2_LOCK_STS_SHIFT 6 /* FLL2_LOCK_STS */ 4114#define WM8994_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 4115#define WM8994_FLL1_LOCK_STS 0x0020 /* FLL1_LOCK_STS */ 4116#define WM8994_FLL1_LOCK_STS_MASK 0x0020 /* FLL1_LOCK_STS */ 4117#define WM8994_FLL1_LOCK_STS_SHIFT 5 /* FLL1_LOCK_STS */ 4118#define WM8994_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 4119#define WM8994_MIC2_SHRT_STS 0x0010 /* MIC2_SHRT_STS */ 4120#define WM8994_MIC2_SHRT_STS_MASK 0x0010 /* MIC2_SHRT_STS */ 4121#define WM8994_MIC2_SHRT_STS_SHIFT 4 /* MIC2_SHRT_STS */ 4122#define WM8994_MIC2_SHRT_STS_WIDTH 1 /* MIC2_SHRT_STS */ 4123#define WM8994_MIC2_DET_STS 0x0008 /* MIC2_DET_STS */ 4124#define WM8994_MIC2_DET_STS_MASK 0x0008 /* MIC2_DET_STS */ 4125#define WM8994_MIC2_DET_STS_SHIFT 3 /* MIC2_DET_STS */ 4126#define WM8994_MIC2_DET_STS_WIDTH 1 /* MIC2_DET_STS */ 4127#define WM8994_MIC1_SHRT_STS 0x0004 /* MIC1_SHRT_STS */ 4128#define WM8994_MIC1_SHRT_STS_MASK 0x0004 /* MIC1_SHRT_STS */ 4129#define WM8994_MIC1_SHRT_STS_SHIFT 2 /* MIC1_SHRT_STS */ 4130#define WM8994_MIC1_SHRT_STS_WIDTH 1 /* MIC1_SHRT_STS */ 4131#define WM8994_MIC1_DET_STS 0x0002 /* MIC1_DET_STS */ 4132#define WM8994_MIC1_DET_STS_MASK 0x0002 /* MIC1_DET_STS */ 4133#define WM8994_MIC1_DET_STS_SHIFT 1 /* MIC1_DET_STS */ 4134#define WM8994_MIC1_DET_STS_WIDTH 1 /* MIC1_DET_STS */ 4135#define WM8994_TEMP_SHUT_STS 0x0001 /* TEMP_SHUT_STS */ 4136#define WM8994_TEMP_SHUT_STS_MASK 0x0001 /* TEMP_SHUT_STS */ 4137#define WM8994_TEMP_SHUT_STS_SHIFT 0 /* TEMP_SHUT_STS */ 4138#define WM8994_TEMP_SHUT_STS_WIDTH 1 /* TEMP_SHUT_STS */ 4139 4140/* 4141 * R1848 (0x738) - Interrupt Status 1 Mask 4142 */ 4143#define WM8994_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ 4144#define WM8994_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ 4145#define WM8994_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ 4146#define WM8994_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ 4147#define WM8994_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ 4148#define WM8994_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ 4149#define WM8994_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ 4150#define WM8994_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ 4151#define WM8994_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ 4152#define WM8994_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ 4153#define WM8994_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ 4154#define WM8994_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ 4155#define WM8994_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ 4156#define WM8994_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ 4157#define WM8994_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ 4158#define WM8994_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ 4159#define WM8994_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ 4160#define WM8994_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ 4161#define WM8994_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ 4162#define WM8994_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ 4163#define WM8994_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 4164#define WM8994_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 4165#define WM8994_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 4166#define WM8994_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 4167#define WM8994_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 4168#define WM8994_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 4169#define WM8994_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 4170#define WM8994_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 4171#define WM8994_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 4172#define WM8994_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 4173#define WM8994_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 4174#define WM8994_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 4175#define WM8994_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 4176#define WM8994_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 4177#define WM8994_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 4178#define WM8994_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 4179#define WM8994_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 4180#define WM8994_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 4181#define WM8994_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 4182#define WM8994_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 4183#define WM8994_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 4184#define WM8994_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 4185#define WM8994_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 4186#define WM8994_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 4187 4188/* 4189 * R1849 (0x739) - Interrupt Status 2 Mask 4190 */ 4191#define WM8994_IM_TEMP_WARN_EINT 0x8000 /* IM_TEMP_WARN_EINT */ 4192#define WM8994_IM_TEMP_WARN_EINT_MASK 0x8000 /* IM_TEMP_WARN_EINT */ 4193#define WM8994_IM_TEMP_WARN_EINT_SHIFT 15 /* IM_TEMP_WARN_EINT */ 4194#define WM8994_IM_TEMP_WARN_EINT_WIDTH 1 /* IM_TEMP_WARN_EINT */ 4195#define WM8994_IM_DCS_DONE_EINT 0x4000 /* IM_DCS_DONE_EINT */ 4196#define WM8994_IM_DCS_DONE_EINT_MASK 0x4000 /* IM_DCS_DONE_EINT */ 4197#define WM8994_IM_DCS_DONE_EINT_SHIFT 14 /* IM_DCS_DONE_EINT */ 4198#define WM8994_IM_DCS_DONE_EINT_WIDTH 1 /* IM_DCS_DONE_EINT */ 4199#define WM8994_IM_WSEQ_DONE_EINT 0x2000 /* IM_WSEQ_DONE_EINT */ 4200#define WM8994_IM_WSEQ_DONE_EINT_MASK 0x2000 /* IM_WSEQ_DONE_EINT */ 4201#define WM8994_IM_WSEQ_DONE_EINT_SHIFT 13 /* IM_WSEQ_DONE_EINT */ 4202#define WM8994_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 4203#define WM8994_IM_FIFOS_ERR_EINT 0x1000 /* IM_FIFOS_ERR_EINT */ 4204#define WM8994_IM_FIFOS_ERR_EINT_MASK 0x1000 /* IM_FIFOS_ERR_EINT */ 4205#define WM8994_IM_FIFOS_ERR_EINT_SHIFT 12 /* IM_FIFOS_ERR_EINT */ 4206#define WM8994_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 4207#define WM8994_IM_AIF2DRC_SIG_DET_EINT 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */ 4208#define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */ 4209#define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* IM_AIF2DRC_SIG_DET_EINT */ 4210#define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ 4211#define WM8994_IM_AIF1DRC2_SIG_DET_EINT 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */ 4212#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */ 4213#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* IM_AIF1DRC2_SIG_DET_EINT */ 4214#define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ 4215#define WM8994_IM_AIF1DRC1_SIG_DET_EINT 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */ 4216#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */ 4217#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* IM_AIF1DRC1_SIG_DET_EINT */ 4218#define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ 4219#define WM8994_IM_SRC2_LOCK_EINT 0x0100 /* IM_SRC2_LOCK_EINT */ 4220#define WM8994_IM_SRC2_LOCK_EINT_MASK 0x0100 /* IM_SRC2_LOCK_EINT */ 4221#define WM8994_IM_SRC2_LOCK_EINT_SHIFT 8 /* IM_SRC2_LOCK_EINT */ 4222#define WM8994_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ 4223#define WM8994_IM_SRC1_LOCK_EINT 0x0080 /* IM_SRC1_LOCK_EINT */ 4224#define WM8994_IM_SRC1_LOCK_EINT_MASK 0x0080 /* IM_SRC1_LOCK_EINT */ 4225#define WM8994_IM_SRC1_LOCK_EINT_SHIFT 7 /* IM_SRC1_LOCK_EINT */ 4226#define WM8994_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ 4227#define WM8994_IM_FLL2_LOCK_EINT 0x0040 /* IM_FLL2_LOCK_EINT */ 4228#define WM8994_IM_FLL2_LOCK_EINT_MASK 0x0040 /* IM_FLL2_LOCK_EINT */ 4229#define WM8994_IM_FLL2_LOCK_EINT_SHIFT 6 /* IM_FLL2_LOCK_EINT */ 4230#define WM8994_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 4231#define WM8994_IM_FLL1_LOCK_EINT 0x0020 /* IM_FLL1_LOCK_EINT */ 4232#define WM8994_IM_FLL1_LOCK_EINT_MASK 0x0020 /* IM_FLL1_LOCK_EINT */ 4233#define WM8994_IM_FLL1_LOCK_EINT_SHIFT 5 /* IM_FLL1_LOCK_EINT */ 4234#define WM8994_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 4235#define WM8994_IM_MIC2_SHRT_EINT 0x0010 /* IM_MIC2_SHRT_EINT */ 4236#define WM8994_IM_MIC2_SHRT_EINT_MASK 0x0010 /* IM_MIC2_SHRT_EINT */ 4237#define WM8994_IM_MIC2_SHRT_EINT_SHIFT 4 /* IM_MIC2_SHRT_EINT */ 4238#define WM8994_IM_MIC2_SHRT_EINT_WIDTH 1 /* IM_MIC2_SHRT_EINT */ 4239#define WM8994_IM_MIC2_DET_EINT 0x0008 /* IM_MIC2_DET_EINT */ 4240#define WM8994_IM_MIC2_DET_EINT_MASK 0x0008 /* IM_MIC2_DET_EINT */ 4241#define WM8994_IM_MIC2_DET_EINT_SHIFT 3 /* IM_MIC2_DET_EINT */ 4242#define WM8994_IM_MIC2_DET_EINT_WIDTH 1 /* IM_MIC2_DET_EINT */ 4243#define WM8994_IM_MIC1_SHRT_EINT 0x0004 /* IM_MIC1_SHRT_EINT */ 4244#define WM8994_IM_MIC1_SHRT_EINT_MASK 0x0004 /* IM_MIC1_SHRT_EINT */ 4245#define WM8994_IM_MIC1_SHRT_EINT_SHIFT 2 /* IM_MIC1_SHRT_EINT */ 4246#define WM8994_IM_MIC1_SHRT_EINT_WIDTH 1 /* IM_MIC1_SHRT_EINT */ 4247#define WM8994_IM_MIC1_DET_EINT 0x0002 /* IM_MIC1_DET_EINT */ 4248#define WM8994_IM_MIC1_DET_EINT_MASK 0x0002 /* IM_MIC1_DET_EINT */ 4249#define WM8994_IM_MIC1_DET_EINT_SHIFT 1 /* IM_MIC1_DET_EINT */ 4250#define WM8994_IM_MIC1_DET_EINT_WIDTH 1 /* IM_MIC1_DET_EINT */ 4251#define WM8994_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */ 4252#define WM8994_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */ 4253#define WM8994_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */ 4254#define WM8994_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */ 4255 4256/* 4257 * R1856 (0x740) - Interrupt Control 4258 */ 4259#define WM8994_IM_IRQ 0x0001 /* IM_IRQ */ 4260#define WM8994_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 4261#define WM8994_IM_IRQ_SHIFT 0 /* IM_IRQ */ 4262#define WM8994_IM_IRQ_WIDTH 1 /* IM_IRQ */ 4263 4264/* 4265 * R1864 (0x748) - IRQ Debounce 4266 */ 4267#define WM8994_TEMP_WARN_DB 0x0020 /* TEMP_WARN_DB */ 4268#define WM8994_TEMP_WARN_DB_MASK 0x0020 /* TEMP_WARN_DB */ 4269#define WM8994_TEMP_WARN_DB_SHIFT 5 /* TEMP_WARN_DB */ 4270#define WM8994_TEMP_WARN_DB_WIDTH 1 /* TEMP_WARN_DB */ 4271#define WM8994_MIC2_SHRT_DB 0x0010 /* MIC2_SHRT_DB */ 4272#define WM8994_MIC2_SHRT_DB_MASK 0x0010 /* MIC2_SHRT_DB */ 4273#define WM8994_MIC2_SHRT_DB_SHIFT 4 /* MIC2_SHRT_DB */ 4274#define WM8994_MIC2_SHRT_DB_WIDTH 1 /* MIC2_SHRT_DB */ 4275#define WM8994_MIC2_DET_DB 0x0008 /* MIC2_DET_DB */ 4276#define WM8994_MIC2_DET_DB_MASK 0x0008 /* MIC2_DET_DB */ 4277#define WM8994_MIC2_DET_DB_SHIFT 3 /* MIC2_DET_DB */ 4278#define WM8994_MIC2_DET_DB_WIDTH 1 /* MIC2_DET_DB */ 4279#define WM8994_MIC1_SHRT_DB 0x0004 /* MIC1_SHRT_DB */ 4280#define WM8994_MIC1_SHRT_DB_MASK 0x0004 /* MIC1_SHRT_DB */ 4281#define WM8994_MIC1_SHRT_DB_SHIFT 2 /* MIC1_SHRT_DB */ 4282#define WM8994_MIC1_SHRT_DB_WIDTH 1 /* MIC1_SHRT_DB */ 4283#define WM8994_MIC1_DET_DB 0x0002 /* MIC1_DET_DB */ 4284#define WM8994_MIC1_DET_DB_MASK 0x0002 /* MIC1_DET_DB */ 4285#define WM8994_MIC1_DET_DB_SHIFT 1 /* MIC1_DET_DB */ 4286#define WM8994_MIC1_DET_DB_WIDTH 1 /* MIC1_DET_DB */ 4287#define WM8994_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */ 4288#define WM8994_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */ 4289#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ 4290#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ 4291 4292#endif 4293