1/* 2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge 3 * 4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive for 8 * more details. 9 * 10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) 11 * which is based on the code of neofb. 12 */ 13 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/errno.h> 17#include <linux/string.h> 18#include <linux/mm.h> 19#include <linux/tty.h> 20#include <linux/delay.h> 21#include <linux/fb.h> 22#include <linux/svga.h> 23#include <linux/init.h> 24#include <linux/pci.h> 25#include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */ 26#include <video/vga.h> 27 28#ifdef CONFIG_MTRR 29#include <asm/mtrr.h> 30#endif 31 32struct s3fb_info { 33 int chip, rev, mclk_freq; 34 int mtrr_reg; 35 struct vgastate state; 36 struct mutex open_lock; 37 unsigned int ref_count; 38 u32 pseudo_palette[16]; 39}; 40 41 42/* ------------------------------------------------------------------------- */ 43 44static const struct svga_fb_format s3fb_formats[] = { 45 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 46 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 47 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0, 48 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 49 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, 50 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 51 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 52 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, 53 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, 54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, 55 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, 56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, 57 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, 59 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, 61 SVGA_FORMAT_END 62}; 63 64 65static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, 66 35000, 240000, 14318}; 67 68static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; 69 70static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", 71 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", 72 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge", 73 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", 74 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P", 75 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X"}; 76 77#define CHIP_UNKNOWN 0x00 78#define CHIP_732_TRIO32 0x01 79#define CHIP_764_TRIO64 0x02 80#define CHIP_765_TRIO64VP 0x03 81#define CHIP_767_TRIO64UVP 0x04 82#define CHIP_775_TRIO64V2_DX 0x05 83#define CHIP_785_TRIO64V2_GX 0x06 84#define CHIP_551_PLATO_PX 0x07 85#define CHIP_M65_AURORA64VP 0x08 86#define CHIP_325_VIRGE 0x09 87#define CHIP_988_VIRGE_VX 0x0A 88#define CHIP_375_VIRGE_DX 0x0B 89#define CHIP_385_VIRGE_GX 0x0C 90#define CHIP_356_VIRGE_GX2 0x0D 91#define CHIP_357_VIRGE_GX2P 0x0E 92#define CHIP_359_VIRGE_GX2P 0x0F 93#define CHIP_360_TRIO3D_1X 0x10 94#define CHIP_362_TRIO3D_2X 0x11 95#define CHIP_368_TRIO3D_2X 0x12 96 97#define CHIP_XXX_TRIO 0x80 98#define CHIP_XXX_TRIO64V2_DXGX 0x81 99#define CHIP_XXX_VIRGE_DXGX 0x82 100#define CHIP_36X_TRIO3D_1X_2X 0x83 101 102#define CHIP_UNDECIDED_FLAG 0x80 103#define CHIP_MASK 0xFF 104 105/* CRT timing register sets */ 106 107static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; 108static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; 109static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; 110static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; 111static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; 112static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; 113 114static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; 115static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; 116static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; 117static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; 118static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; 119static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; 120 121static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; 122static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; 123static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ 124 125static const struct svga_timing_regs s3_timing_regs = { 126 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, 127 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, 128 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, 129 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, 130}; 131 132 133/* ------------------------------------------------------------------------- */ 134 135/* Module parameters */ 136 137 138static char *mode_option __devinitdata = "640x480-8@60"; 139 140#ifdef CONFIG_MTRR 141static int mtrr __devinitdata = 1; 142#endif 143 144static int fasttext = 1; 145 146 147MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); 148MODULE_LICENSE("GPL"); 149MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); 150 151module_param(mode_option, charp, 0444); 152MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); 153module_param_named(mode, mode_option, charp, 0444); 154MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); 155 156#ifdef CONFIG_MTRR 157module_param(mtrr, int, 0444); 158MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); 159#endif 160 161module_param(fasttext, int, 0644); 162MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); 163 164 165/* ------------------------------------------------------------------------- */ 166 167/* Set font in S3 fast text mode */ 168 169static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) 170{ 171 const u8 *font = map->data; 172 u8 __iomem *fb = (u8 __iomem *) info->screen_base; 173 int i, c; 174 175 if ((map->width != 8) || (map->height != 16) || 176 (map->depth != 1) || (map->length != 256)) { 177 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", 178 info->node, map->width, map->height, map->depth, map->length); 179 return; 180 } 181 182 fb += 2; 183 for (i = 0; i < map->height; i++) { 184 for (c = 0; c < map->length; c++) { 185 fb_writeb(font[c * map->height + i], fb + c * 4); 186 } 187 fb += 1024; 188 } 189} 190 191static struct fb_tile_ops s3fb_tile_ops = { 192 .fb_settile = svga_settile, 193 .fb_tilecopy = svga_tilecopy, 194 .fb_tilefill = svga_tilefill, 195 .fb_tileblit = svga_tileblit, 196 .fb_tilecursor = svga_tilecursor, 197 .fb_get_tilemax = svga_get_tilemax, 198}; 199 200static struct fb_tile_ops s3fb_fast_tile_ops = { 201 .fb_settile = s3fb_settile_fast, 202 .fb_tilecopy = svga_tilecopy, 203 .fb_tilefill = svga_tilefill, 204 .fb_tileblit = svga_tileblit, 205 .fb_tilecursor = svga_tilecursor, 206 .fb_get_tilemax = svga_get_tilemax, 207}; 208 209 210/* ------------------------------------------------------------------------- */ 211 212/* image data is MSB-first, fb structure is MSB-first too */ 213static inline u32 expand_color(u32 c) 214{ 215 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; 216} 217 218/* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ 219static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) 220{ 221 u32 fg = expand_color(image->fg_color); 222 u32 bg = expand_color(image->bg_color); 223 const u8 *src1, *src; 224 u8 __iomem *dst1; 225 u32 __iomem *dst; 226 u32 val; 227 int x, y; 228 229 src1 = image->data; 230 dst1 = info->screen_base + (image->dy * info->fix.line_length) 231 + ((image->dx / 8) * 4); 232 233 for (y = 0; y < image->height; y++) { 234 src = src1; 235 dst = (u32 __iomem *) dst1; 236 for (x = 0; x < image->width; x += 8) { 237 val = *(src++) * 0x01010101; 238 val = (val & fg) | (~val & bg); 239 fb_writel(val, dst++); 240 } 241 src1 += image->width / 8; 242 dst1 += info->fix.line_length; 243 } 244 245} 246 247/* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ 248static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 249{ 250 u32 fg = expand_color(rect->color); 251 u8 __iomem *dst1; 252 u32 __iomem *dst; 253 int x, y; 254 255 dst1 = info->screen_base + (rect->dy * info->fix.line_length) 256 + ((rect->dx / 8) * 4); 257 258 for (y = 0; y < rect->height; y++) { 259 dst = (u32 __iomem *) dst1; 260 for (x = 0; x < rect->width; x += 8) { 261 fb_writel(fg, dst++); 262 } 263 dst1 += info->fix.line_length; 264 } 265} 266 267 268/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ 269static inline u32 expand_pixel(u32 c) 270{ 271 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | 272 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; 273} 274 275/* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ 276static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) 277{ 278 u32 fg = image->fg_color * 0x11111111; 279 u32 bg = image->bg_color * 0x11111111; 280 const u8 *src1, *src; 281 u8 __iomem *dst1; 282 u32 __iomem *dst; 283 u32 val; 284 int x, y; 285 286 src1 = image->data; 287 dst1 = info->screen_base + (image->dy * info->fix.line_length) 288 + ((image->dx / 8) * 4); 289 290 for (y = 0; y < image->height; y++) { 291 src = src1; 292 dst = (u32 __iomem *) dst1; 293 for (x = 0; x < image->width; x += 8) { 294 val = expand_pixel(*(src++)); 295 val = (val & fg) | (~val & bg); 296 fb_writel(val, dst++); 297 } 298 src1 += image->width / 8; 299 dst1 += info->fix.line_length; 300 } 301} 302 303static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) 304{ 305 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) 306 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { 307 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) 308 s3fb_iplan_imageblit(info, image); 309 else 310 s3fb_cfb4_imageblit(info, image); 311 } else 312 cfb_imageblit(info, image); 313} 314 315static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 316{ 317 if ((info->var.bits_per_pixel == 4) 318 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) 319 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) 320 s3fb_iplan_fillrect(info, rect); 321 else 322 cfb_fillrect(info, rect); 323} 324 325 326 327/* ------------------------------------------------------------------------- */ 328 329 330static void s3_set_pixclock(struct fb_info *info, u32 pixclock) 331{ 332 struct s3fb_info *par = info->par; 333 u16 m, n, r; 334 u8 regval; 335 int rv; 336 337 rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); 338 if (rv < 0) { 339 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); 340 return; 341 } 342 343 /* Set VGA misc register */ 344 regval = vga_r(NULL, VGA_MIS_R); 345 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); 346 347 /* Set S3 clock registers */ 348 if (par->chip == CHIP_360_TRIO3D_1X || 349 par->chip == CHIP_362_TRIO3D_2X || 350 par->chip == CHIP_368_TRIO3D_2X) { 351 vga_wseq(NULL, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ 352 vga_wseq(NULL, 0x29, r >> 2); /* remaining highest bit of r */ 353 } else 354 vga_wseq(NULL, 0x12, (n - 2) | (r << 5)); 355 vga_wseq(NULL, 0x13, m - 2); 356 357 udelay(1000); 358 359 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ 360 regval = vga_rseq (NULL, 0x15); /* | 0x80; */ 361 vga_wseq(NULL, 0x15, regval & ~(1<<5)); 362 vga_wseq(NULL, 0x15, regval | (1<<5)); 363 vga_wseq(NULL, 0x15, regval & ~(1<<5)); 364} 365 366 367/* Open framebuffer */ 368 369static int s3fb_open(struct fb_info *info, int user) 370{ 371 struct s3fb_info *par = info->par; 372 373 mutex_lock(&(par->open_lock)); 374 if (par->ref_count == 0) { 375 memset(&(par->state), 0, sizeof(struct vgastate)); 376 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; 377 par->state.num_crtc = 0x70; 378 par->state.num_seq = 0x20; 379 save_vga(&(par->state)); 380 } 381 382 par->ref_count++; 383 mutex_unlock(&(par->open_lock)); 384 385 return 0; 386} 387 388/* Close framebuffer */ 389 390static int s3fb_release(struct fb_info *info, int user) 391{ 392 struct s3fb_info *par = info->par; 393 394 mutex_lock(&(par->open_lock)); 395 if (par->ref_count == 0) { 396 mutex_unlock(&(par->open_lock)); 397 return -EINVAL; 398 } 399 400 if (par->ref_count == 1) 401 restore_vga(&(par->state)); 402 403 par->ref_count--; 404 mutex_unlock(&(par->open_lock)); 405 406 return 0; 407} 408 409/* Validate passed in var */ 410 411static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 412{ 413 struct s3fb_info *par = info->par; 414 int rv, mem, step; 415 u16 m, n, r; 416 417 /* Find appropriate format */ 418 rv = svga_match_format (s3fb_formats, var, NULL); 419 420 /* 32bpp mode is not supported on VIRGE VX, 421 24bpp is not supported on others */ 422 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) 423 rv = -EINVAL; 424 425 if (rv < 0) { 426 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); 427 return rv; 428 } 429 430 /* Do not allow to have real resoulution larger than virtual */ 431 if (var->xres > var->xres_virtual) 432 var->xres_virtual = var->xres; 433 434 if (var->yres > var->yres_virtual) 435 var->yres_virtual = var->yres; 436 437 /* Round up xres_virtual to have proper alignment of lines */ 438 step = s3fb_formats[rv].xresstep - 1; 439 var->xres_virtual = (var->xres_virtual+step) & ~step; 440 441 /* Check whether have enough memory */ 442 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; 443 if (mem > info->screen_size) { 444 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", 445 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); 446 return -EINVAL; 447 } 448 449 rv = svga_check_timings (&s3_timing_regs, var, info->node); 450 if (rv < 0) { 451 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); 452 return rv; 453 } 454 455 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, 456 info->node); 457 if (rv < 0) { 458 printk(KERN_ERR "fb%d: invalid pixclock value requested\n", 459 info->node); 460 return rv; 461 } 462 463 return 0; 464} 465 466/* Set video mode from par */ 467 468static int s3fb_set_par(struct fb_info *info) 469{ 470 struct s3fb_info *par = info->par; 471 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; 472 u32 bpp = info->var.bits_per_pixel; 473 474 if (bpp != 0) { 475 info->fix.ypanstep = 1; 476 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; 477 478 info->flags &= ~FBINFO_MISC_TILEBLITTING; 479 info->tileops = NULL; 480 481 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ 482 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); 483 info->pixmap.blit_y = ~(u32)0; 484 485 offset_value = (info->var.xres_virtual * bpp) / 64; 486 screen_size = info->var.yres_virtual * info->fix.line_length; 487 } else { 488 info->fix.ypanstep = 16; 489 info->fix.line_length = 0; 490 491 info->flags |= FBINFO_MISC_TILEBLITTING; 492 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; 493 494 /* supports 8x16 tiles only */ 495 info->pixmap.blit_x = 1 << (8 - 1); 496 info->pixmap.blit_y = 1 << (16 - 1); 497 498 offset_value = info->var.xres_virtual / 16; 499 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; 500 } 501 502 info->var.xoffset = 0; 503 info->var.yoffset = 0; 504 info->var.activate = FB_ACTIVATE_NOW; 505 506 /* Unlock registers */ 507 vga_wcrt(NULL, 0x38, 0x48); 508 vga_wcrt(NULL, 0x39, 0xA5); 509 vga_wseq(NULL, 0x08, 0x06); 510 svga_wcrt_mask(0x11, 0x00, 0x80); 511 512 /* Blank screen and turn off sync */ 513 svga_wseq_mask(0x01, 0x20, 0x20); 514 svga_wcrt_mask(0x17, 0x00, 0x80); 515 516 /* Set default values */ 517 svga_set_default_gfx_regs(); 518 svga_set_default_atc_regs(); 519 svga_set_default_seq_regs(); 520 svga_set_default_crt_regs(); 521 svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF); 522 svga_wcrt_multi(s3_start_address_regs, 0); 523 524 /* S3 specific initialization */ 525 svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */ 526 svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ 527 528/* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */ 529/* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */ 530 svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */ 531 svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */ 532 533 svga_wcrt_mask(0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ 534 535/* svga_wcrt_mask(0x58, 0x03, 0x03); */ 536 537/* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */ 538/* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */ 539 540 541 /* Set the offset register */ 542 pr_debug("fb%d: offset register : %d\n", info->node, offset_value); 543 svga_wcrt_multi(s3_offset_regs, offset_value); 544 545 if (par->chip != CHIP_360_TRIO3D_1X && 546 par->chip != CHIP_362_TRIO3D_2X && 547 par->chip != CHIP_368_TRIO3D_2X) { 548 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */ 549 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */ 550 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */ 551 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */ 552 } 553 554 vga_wcrt(NULL, 0x3A, 0x35); 555 svga_wattr(0x33, 0x00); 556 557 if (info->var.vmode & FB_VMODE_DOUBLE) 558 svga_wcrt_mask(0x09, 0x80, 0x80); 559 else 560 svga_wcrt_mask(0x09, 0x00, 0x80); 561 562 if (info->var.vmode & FB_VMODE_INTERLACED) 563 svga_wcrt_mask(0x42, 0x20, 0x20); 564 else 565 svga_wcrt_mask(0x42, 0x00, 0x20); 566 567 /* Disable hardware graphics cursor */ 568 svga_wcrt_mask(0x45, 0x00, 0x01); 569 /* Disable Streams engine */ 570 svga_wcrt_mask(0x67, 0x00, 0x0C); 571 572 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); 573 574 /* S3 virge DX hack */ 575 if (par->chip == CHIP_375_VIRGE_DX) { 576 vga_wcrt(NULL, 0x86, 0x80); 577 vga_wcrt(NULL, 0x90, 0x00); 578 } 579 580 /* S3 virge VX hack */ 581 if (par->chip == CHIP_988_VIRGE_VX) { 582 vga_wcrt(NULL, 0x50, 0x00); 583 vga_wcrt(NULL, 0x67, 0x50); 584 585 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09); 586 vga_wcrt(NULL, 0x66, 0x90); 587 } 588 589 if (par->chip == CHIP_360_TRIO3D_1X || 590 par->chip == CHIP_362_TRIO3D_2X || 591 par->chip == CHIP_368_TRIO3D_2X) { 592 dbytes = info->var.xres * ((bpp+7)/8); 593 vga_wcrt(NULL, 0x91, (dbytes + 7) / 8); 594 vga_wcrt(NULL, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); 595 596 vga_wcrt(NULL, 0x66, 0x81); 597 } 598 599 svga_wcrt_mask(0x31, 0x00, 0x40); 600 multiplex = 0; 601 hmul = 1; 602 603 /* Set mode-specific register values */ 604 switch (mode) { 605 case 0: 606 pr_debug("fb%d: text mode\n", info->node); 607 svga_set_textmode_vga_regs(); 608 609 /* Set additional registers like in 8-bit mode */ 610 svga_wcrt_mask(0x50, 0x00, 0x30); 611 svga_wcrt_mask(0x67, 0x00, 0xF0); 612 613 /* Disable enhanced mode */ 614 svga_wcrt_mask(0x3A, 0x00, 0x30); 615 616 if (fasttext) { 617 pr_debug("fb%d: high speed text mode set\n", info->node); 618 svga_wcrt_mask(0x31, 0x40, 0x40); 619 } 620 break; 621 case 1: 622 pr_debug("fb%d: 4 bit pseudocolor\n", info->node); 623 vga_wgfx(NULL, VGA_GFX_MODE, 0x40); 624 625 /* Set additional registers like in 8-bit mode */ 626 svga_wcrt_mask(0x50, 0x00, 0x30); 627 svga_wcrt_mask(0x67, 0x00, 0xF0); 628 629 /* disable enhanced mode */ 630 svga_wcrt_mask(0x3A, 0x00, 0x30); 631 break; 632 case 2: 633 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); 634 635 /* Set additional registers like in 8-bit mode */ 636 svga_wcrt_mask(0x50, 0x00, 0x30); 637 svga_wcrt_mask(0x67, 0x00, 0xF0); 638 639 /* disable enhanced mode */ 640 svga_wcrt_mask(0x3A, 0x00, 0x30); 641 break; 642 case 3: 643 pr_debug("fb%d: 8 bit pseudocolor\n", info->node); 644 svga_wcrt_mask(0x50, 0x00, 0x30); 645 if (info->var.pixclock > 20000 || 646 par->chip == CHIP_360_TRIO3D_1X || 647 par->chip == CHIP_362_TRIO3D_2X || 648 par->chip == CHIP_368_TRIO3D_2X) 649 svga_wcrt_mask(0x67, 0x00, 0xF0); 650 else { 651 svga_wcrt_mask(0x67, 0x10, 0xF0); 652 multiplex = 1; 653 } 654 break; 655 case 4: 656 pr_debug("fb%d: 5/5/5 truecolor\n", info->node); 657 if (par->chip == CHIP_988_VIRGE_VX) { 658 if (info->var.pixclock > 20000) 659 svga_wcrt_mask(0x67, 0x20, 0xF0); 660 else 661 svga_wcrt_mask(0x67, 0x30, 0xF0); 662 } else { 663 svga_wcrt_mask(0x50, 0x10, 0x30); 664 svga_wcrt_mask(0x67, 0x30, 0xF0); 665 if (par->chip != CHIP_360_TRIO3D_1X && 666 par->chip != CHIP_362_TRIO3D_2X && 667 par->chip != CHIP_368_TRIO3D_2X) 668 hmul = 2; 669 } 670 break; 671 case 5: 672 pr_debug("fb%d: 5/6/5 truecolor\n", info->node); 673 if (par->chip == CHIP_988_VIRGE_VX) { 674 if (info->var.pixclock > 20000) 675 svga_wcrt_mask(0x67, 0x40, 0xF0); 676 else 677 svga_wcrt_mask(0x67, 0x50, 0xF0); 678 } else { 679 svga_wcrt_mask(0x50, 0x10, 0x30); 680 svga_wcrt_mask(0x67, 0x50, 0xF0); 681 if (par->chip != CHIP_360_TRIO3D_1X && 682 par->chip != CHIP_362_TRIO3D_2X && 683 par->chip != CHIP_368_TRIO3D_2X) 684 hmul = 2; 685 } 686 break; 687 case 6: 688 /* VIRGE VX case */ 689 pr_debug("fb%d: 8/8/8 truecolor\n", info->node); 690 svga_wcrt_mask(0x67, 0xD0, 0xF0); 691 break; 692 case 7: 693 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); 694 svga_wcrt_mask(0x50, 0x30, 0x30); 695 svga_wcrt_mask(0x67, 0xD0, 0xF0); 696 break; 697 default: 698 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); 699 return -EINVAL; 700 } 701 702 if (par->chip != CHIP_988_VIRGE_VX) { 703 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10); 704 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80); 705 } 706 707 s3_set_pixclock(info, info->var.pixclock); 708 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1, 709 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 710 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, 711 hmul, info->node); 712 713 /* Set interlaced mode start/end register */ 714 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; 715 value = ((value * hmul) / 8) - 5; 716 vga_wcrt(NULL, 0x3C, (value + 1) / 2); 717 718 memset_io(info->screen_base, 0x00, screen_size); 719 /* Device and screen back on */ 720 svga_wcrt_mask(0x17, 0x80, 0x80); 721 svga_wseq_mask(0x01, 0x00, 0x20); 722 723 return 0; 724} 725 726/* Set a colour register */ 727 728static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 729 u_int transp, struct fb_info *fb) 730{ 731 switch (fb->var.bits_per_pixel) { 732 case 0: 733 case 4: 734 if (regno >= 16) 735 return -EINVAL; 736 737 if ((fb->var.bits_per_pixel == 4) && 738 (fb->var.nonstd == 0)) { 739 outb(0xF0, VGA_PEL_MSK); 740 outb(regno*16, VGA_PEL_IW); 741 } else { 742 outb(0x0F, VGA_PEL_MSK); 743 outb(regno, VGA_PEL_IW); 744 } 745 outb(red >> 10, VGA_PEL_D); 746 outb(green >> 10, VGA_PEL_D); 747 outb(blue >> 10, VGA_PEL_D); 748 break; 749 case 8: 750 if (regno >= 256) 751 return -EINVAL; 752 753 outb(0xFF, VGA_PEL_MSK); 754 outb(regno, VGA_PEL_IW); 755 outb(red >> 10, VGA_PEL_D); 756 outb(green >> 10, VGA_PEL_D); 757 outb(blue >> 10, VGA_PEL_D); 758 break; 759 case 16: 760 if (regno >= 16) 761 return 0; 762 763 if (fb->var.green.length == 5) 764 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | 765 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); 766 else if (fb->var.green.length == 6) 767 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | 768 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 769 else return -EINVAL; 770 break; 771 case 24: 772 case 32: 773 if (regno >= 16) 774 return 0; 775 776 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | 777 (green & 0xFF00) | ((blue & 0xFF00) >> 8); 778 break; 779 default: 780 return -EINVAL; 781 } 782 783 return 0; 784} 785 786 787/* Set the display blanking state */ 788 789static int s3fb_blank(int blank_mode, struct fb_info *info) 790{ 791 switch (blank_mode) { 792 case FB_BLANK_UNBLANK: 793 pr_debug("fb%d: unblank\n", info->node); 794 svga_wcrt_mask(0x56, 0x00, 0x06); 795 svga_wseq_mask(0x01, 0x00, 0x20); 796 break; 797 case FB_BLANK_NORMAL: 798 pr_debug("fb%d: blank\n", info->node); 799 svga_wcrt_mask(0x56, 0x00, 0x06); 800 svga_wseq_mask(0x01, 0x20, 0x20); 801 break; 802 case FB_BLANK_HSYNC_SUSPEND: 803 pr_debug("fb%d: hsync\n", info->node); 804 svga_wcrt_mask(0x56, 0x02, 0x06); 805 svga_wseq_mask(0x01, 0x20, 0x20); 806 break; 807 case FB_BLANK_VSYNC_SUSPEND: 808 pr_debug("fb%d: vsync\n", info->node); 809 svga_wcrt_mask(0x56, 0x04, 0x06); 810 svga_wseq_mask(0x01, 0x20, 0x20); 811 break; 812 case FB_BLANK_POWERDOWN: 813 pr_debug("fb%d: sync down\n", info->node); 814 svga_wcrt_mask(0x56, 0x06, 0x06); 815 svga_wseq_mask(0x01, 0x20, 0x20); 816 break; 817 } 818 819 return 0; 820} 821 822 823/* Pan the display */ 824 825static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { 826 827 unsigned int offset; 828 829 /* Calculate the offset */ 830 if (var->bits_per_pixel == 0) { 831 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); 832 offset = offset >> 2; 833 } else { 834 offset = (var->yoffset * info->fix.line_length) + 835 (var->xoffset * var->bits_per_pixel / 8); 836 offset = offset >> 2; 837 } 838 839 /* Set the offset */ 840 svga_wcrt_multi(s3_start_address_regs, offset); 841 842 return 0; 843} 844 845/* ------------------------------------------------------------------------- */ 846 847/* Frame buffer operations */ 848 849static struct fb_ops s3fb_ops = { 850 .owner = THIS_MODULE, 851 .fb_open = s3fb_open, 852 .fb_release = s3fb_release, 853 .fb_check_var = s3fb_check_var, 854 .fb_set_par = s3fb_set_par, 855 .fb_setcolreg = s3fb_setcolreg, 856 .fb_blank = s3fb_blank, 857 .fb_pan_display = s3fb_pan_display, 858 .fb_fillrect = s3fb_fillrect, 859 .fb_copyarea = cfb_copyarea, 860 .fb_imageblit = s3fb_imageblit, 861 .fb_get_caps = svga_get_caps, 862}; 863 864/* ------------------------------------------------------------------------- */ 865 866static int __devinit s3_identification(int chip) 867{ 868 if (chip == CHIP_XXX_TRIO) { 869 u8 cr30 = vga_rcrt(NULL, 0x30); 870 u8 cr2e = vga_rcrt(NULL, 0x2e); 871 u8 cr2f = vga_rcrt(NULL, 0x2f); 872 873 if ((cr30 == 0xE0) || (cr30 == 0xE1)) { 874 if (cr2e == 0x10) 875 return CHIP_732_TRIO32; 876 if (cr2e == 0x11) { 877 if (! (cr2f & 0x40)) 878 return CHIP_764_TRIO64; 879 else 880 return CHIP_765_TRIO64VP; 881 } 882 } 883 } 884 885 if (chip == CHIP_XXX_TRIO64V2_DXGX) { 886 u8 cr6f = vga_rcrt(NULL, 0x6f); 887 888 if (! (cr6f & 0x01)) 889 return CHIP_775_TRIO64V2_DX; 890 else 891 return CHIP_785_TRIO64V2_GX; 892 } 893 894 if (chip == CHIP_XXX_VIRGE_DXGX) { 895 u8 cr6f = vga_rcrt(NULL, 0x6f); 896 897 if (! (cr6f & 0x01)) 898 return CHIP_375_VIRGE_DX; 899 else 900 return CHIP_385_VIRGE_GX; 901 } 902 903 if (chip == CHIP_36X_TRIO3D_1X_2X) { 904 switch (vga_rcrt(NULL, 0x2f)) { 905 case 0x00: 906 return CHIP_360_TRIO3D_1X; 907 case 0x01: 908 return CHIP_362_TRIO3D_2X; 909 case 0x02: 910 return CHIP_368_TRIO3D_2X; 911 } 912 } 913 914 return CHIP_UNKNOWN; 915} 916 917 918/* PCI probe */ 919 920static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 921{ 922 struct fb_info *info; 923 struct s3fb_info *par; 924 int rc; 925 u8 regval, cr38, cr39; 926 927 /* Ignore secondary VGA device because there is no VGA arbitration */ 928 if (! svga_primary_device(dev)) { 929 dev_info(&(dev->dev), "ignoring secondary device\n"); 930 return -ENODEV; 931 } 932 933 /* Allocate and fill driver data structure */ 934 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); 935 if (!info) { 936 dev_err(&(dev->dev), "cannot allocate memory\n"); 937 return -ENOMEM; 938 } 939 940 par = info->par; 941 mutex_init(&par->open_lock); 942 943 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; 944 info->fbops = &s3fb_ops; 945 946 /* Prepare PCI device */ 947 rc = pci_enable_device(dev); 948 if (rc < 0) { 949 dev_err(info->device, "cannot enable PCI device\n"); 950 goto err_enable_device; 951 } 952 953 rc = pci_request_regions(dev, "s3fb"); 954 if (rc < 0) { 955 dev_err(info->device, "cannot reserve framebuffer region\n"); 956 goto err_request_regions; 957 } 958 959 960 info->fix.smem_start = pci_resource_start(dev, 0); 961 info->fix.smem_len = pci_resource_len(dev, 0); 962 963 /* Map physical IO memory address into kernel space */ 964 info->screen_base = pci_iomap(dev, 0, 0); 965 if (! info->screen_base) { 966 rc = -ENOMEM; 967 dev_err(info->device, "iomap for framebuffer failed\n"); 968 goto err_iomap; 969 } 970 971 /* Unlock regs */ 972 cr38 = vga_rcrt(NULL, 0x38); 973 cr39 = vga_rcrt(NULL, 0x39); 974 vga_wseq(NULL, 0x08, 0x06); 975 vga_wcrt(NULL, 0x38, 0x48); 976 vga_wcrt(NULL, 0x39, 0xA5); 977 978 /* Identify chip type */ 979 par->chip = id->driver_data & CHIP_MASK; 980 par->rev = vga_rcrt(NULL, 0x2f); 981 if (par->chip & CHIP_UNDECIDED_FLAG) 982 par->chip = s3_identification(par->chip); 983 984 /* Find how many physical memory there is on card */ 985 /* 0x36 register is accessible even if other registers are locked */ 986 regval = vga_rcrt(NULL, 0x36); 987 if (par->chip == CHIP_360_TRIO3D_1X || 988 par->chip == CHIP_362_TRIO3D_2X || 989 par->chip == CHIP_368_TRIO3D_2X) { 990 switch ((regval & 0xE0) >> 5) { 991 case 0: /* 8MB -- only 4MB usable for display */ 992 case 1: /* 4MB with 32-bit bus */ 993 case 2: /* 4MB */ 994 info->screen_size = 4 << 20; 995 break; 996 case 6: /* 2MB */ 997 info->screen_size = 2 << 20; 998 break; 999 } 1000 } else 1001 info->screen_size = s3_memsizes[regval >> 5] << 10; 1002 info->fix.smem_len = info->screen_size; 1003 1004 /* Find MCLK frequency */ 1005 regval = vga_rseq(NULL, 0x10); 1006 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); 1007 par->mclk_freq = par->mclk_freq >> (regval >> 5); 1008 1009 /* Restore locks */ 1010 vga_wcrt(NULL, 0x38, cr38); 1011 vga_wcrt(NULL, 0x39, cr39); 1012 1013 strcpy(info->fix.id, s3_names [par->chip]); 1014 info->fix.mmio_start = 0; 1015 info->fix.mmio_len = 0; 1016 info->fix.type = FB_TYPE_PACKED_PIXELS; 1017 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 1018 info->fix.ypanstep = 0; 1019 info->fix.accel = FB_ACCEL_NONE; 1020 info->pseudo_palette = (void*) (par->pseudo_palette); 1021 1022 /* Prepare startup mode */ 1023 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); 1024 if (! ((rc == 1) || (rc == 2))) { 1025 rc = -EINVAL; 1026 dev_err(info->device, "mode %s not found\n", mode_option); 1027 goto err_find_mode; 1028 } 1029 1030 rc = fb_alloc_cmap(&info->cmap, 256, 0); 1031 if (rc < 0) { 1032 dev_err(info->device, "cannot allocate colormap\n"); 1033 goto err_alloc_cmap; 1034 } 1035 1036 rc = register_framebuffer(info); 1037 if (rc < 0) { 1038 dev_err(info->device, "cannot register framebuffer\n"); 1039 goto err_reg_fb; 1040 } 1041 1042 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, 1043 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); 1044 1045 if (par->chip == CHIP_UNKNOWN) 1046 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", 1047 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e), 1048 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30)); 1049 1050 /* Record a reference to the driver data */ 1051 pci_set_drvdata(dev, info); 1052 1053#ifdef CONFIG_MTRR 1054 if (mtrr) { 1055 par->mtrr_reg = -1; 1056 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); 1057 } 1058#endif 1059 1060 return 0; 1061 1062 /* Error handling */ 1063err_reg_fb: 1064 fb_dealloc_cmap(&info->cmap); 1065err_alloc_cmap: 1066err_find_mode: 1067 pci_iounmap(dev, info->screen_base); 1068err_iomap: 1069 pci_release_regions(dev); 1070err_request_regions: 1071/* pci_disable_device(dev); */ 1072err_enable_device: 1073 framebuffer_release(info); 1074 return rc; 1075} 1076 1077 1078/* PCI remove */ 1079 1080static void __devexit s3_pci_remove(struct pci_dev *dev) 1081{ 1082 struct fb_info *info = pci_get_drvdata(dev); 1083 1084 if (info) { 1085 1086#ifdef CONFIG_MTRR 1087 struct s3fb_info *par = info->par; 1088 1089 if (par->mtrr_reg >= 0) { 1090 mtrr_del(par->mtrr_reg, 0, 0); 1091 par->mtrr_reg = -1; 1092 } 1093#endif 1094 1095 unregister_framebuffer(info); 1096 fb_dealloc_cmap(&info->cmap); 1097 1098 pci_iounmap(dev, info->screen_base); 1099 pci_release_regions(dev); 1100/* pci_disable_device(dev); */ 1101 1102 pci_set_drvdata(dev, NULL); 1103 framebuffer_release(info); 1104 } 1105} 1106 1107/* PCI suspend */ 1108 1109static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state) 1110{ 1111 struct fb_info *info = pci_get_drvdata(dev); 1112 struct s3fb_info *par = info->par; 1113 1114 dev_info(info->device, "suspend\n"); 1115 1116 acquire_console_sem(); 1117 mutex_lock(&(par->open_lock)); 1118 1119 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { 1120 mutex_unlock(&(par->open_lock)); 1121 release_console_sem(); 1122 return 0; 1123 } 1124 1125 fb_set_suspend(info, 1); 1126 1127 pci_save_state(dev); 1128 pci_disable_device(dev); 1129 pci_set_power_state(dev, pci_choose_state(dev, state)); 1130 1131 mutex_unlock(&(par->open_lock)); 1132 release_console_sem(); 1133 1134 return 0; 1135} 1136 1137 1138/* PCI resume */ 1139 1140static int s3_pci_resume(struct pci_dev* dev) 1141{ 1142 struct fb_info *info = pci_get_drvdata(dev); 1143 struct s3fb_info *par = info->par; 1144 int err; 1145 1146 dev_info(info->device, "resume\n"); 1147 1148 acquire_console_sem(); 1149 mutex_lock(&(par->open_lock)); 1150 1151 if (par->ref_count == 0) { 1152 mutex_unlock(&(par->open_lock)); 1153 release_console_sem(); 1154 return 0; 1155 } 1156 1157 pci_set_power_state(dev, PCI_D0); 1158 pci_restore_state(dev); 1159 err = pci_enable_device(dev); 1160 if (err) { 1161 mutex_unlock(&(par->open_lock)); 1162 release_console_sem(); 1163 dev_err(info->device, "error %d enabling device for resume\n", err); 1164 return err; 1165 } 1166 pci_set_master(dev); 1167 1168 s3fb_set_par(info); 1169 fb_set_suspend(info, 0); 1170 1171 mutex_unlock(&(par->open_lock)); 1172 release_console_sem(); 1173 1174 return 0; 1175} 1176 1177 1178/* List of boards that we are trying to support */ 1179 1180static struct pci_device_id s3_devices[] __devinitdata = { 1181 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, 1182 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, 1183 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, 1184 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, 1185 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, 1186 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, 1187 1188 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, 1189 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, 1190 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, 1191 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2}, 1192 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P}, 1193 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, 1194 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, 1195 1196 {0, 0, 0, 0, 0, 0, 0} 1197}; 1198 1199 1200MODULE_DEVICE_TABLE(pci, s3_devices); 1201 1202static struct pci_driver s3fb_pci_driver = { 1203 .name = "s3fb", 1204 .id_table = s3_devices, 1205 .probe = s3_pci_probe, 1206 .remove = __devexit_p(s3_pci_remove), 1207 .suspend = s3_pci_suspend, 1208 .resume = s3_pci_resume, 1209}; 1210 1211/* Parse user speficied options */ 1212 1213#ifndef MODULE 1214static int __init s3fb_setup(char *options) 1215{ 1216 char *opt; 1217 1218 if (!options || !*options) 1219 return 0; 1220 1221 while ((opt = strsep(&options, ",")) != NULL) { 1222 1223 if (!*opt) 1224 continue; 1225#ifdef CONFIG_MTRR 1226 else if (!strncmp(opt, "mtrr:", 5)) 1227 mtrr = simple_strtoul(opt + 5, NULL, 0); 1228#endif 1229 else if (!strncmp(opt, "fasttext:", 9)) 1230 fasttext = simple_strtoul(opt + 9, NULL, 0); 1231 else 1232 mode_option = opt; 1233 } 1234 1235 return 0; 1236} 1237#endif 1238 1239/* Cleanup */ 1240 1241static void __exit s3fb_cleanup(void) 1242{ 1243 pr_debug("s3fb: cleaning up\n"); 1244 pci_unregister_driver(&s3fb_pci_driver); 1245} 1246 1247/* Driver Initialisation */ 1248 1249static int __init s3fb_init(void) 1250{ 1251 1252#ifndef MODULE 1253 char *option = NULL; 1254 1255 if (fb_get_options("s3fb", &option)) 1256 return -ENODEV; 1257 s3fb_setup(option); 1258#endif 1259 1260 pr_debug("s3fb: initializing\n"); 1261 return pci_register_driver(&s3fb_pci_driver); 1262} 1263 1264/* ------------------------------------------------------------------------- */ 1265 1266/* Modularization */ 1267 1268module_init(s3fb_init); 1269module_exit(s3fb_cleanup); 1270