1/* 2 * linux/drivers/video/pxafb.c 3 * 4 * Copyright (C) 1999 Eric A. Thomas. 5 * Copyright (C) 2004 Jean-Frederic Clere. 6 * Copyright (C) 2004 Ian Campbell. 7 * Copyright (C) 2004 Jeff Lackey. 8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas 9 * which in turn is 10 * Based on acornfb.c Copyright (C) Russell King. 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file COPYING in the main directory of this archive for 14 * more details. 15 * 16 * Intel PXA250/210 LCD Controller Frame Buffer Driver 17 * 18 * Please direct your questions and comments on this driver to the following 19 * email address: 20 * 21 * linux-arm-kernel@lists.arm.linux.org.uk 22 * 23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c: 24 * 25 * Copyright (C) 2004, Intel Corporation 26 * 27 * 2003/08/27: <yu.tang@intel.com> 28 * 2004/03/10: <stanley.cai@intel.com> 29 * 2004/10/28: <yan.yin@intel.com> 30 * 31 * Copyright (C) 2006-2008 Marvell International Ltd. 32 * All Rights Reserved 33 */ 34 35#include <linux/module.h> 36#include <linux/moduleparam.h> 37#include <linux/kernel.h> 38#include <linux/sched.h> 39#include <linux/errno.h> 40#include <linux/string.h> 41#include <linux/interrupt.h> 42#include <linux/slab.h> 43#include <linux/mm.h> 44#include <linux/fb.h> 45#include <linux/delay.h> 46#include <linux/init.h> 47#include <linux/ioport.h> 48#include <linux/cpufreq.h> 49#include <linux/platform_device.h> 50#include <linux/dma-mapping.h> 51#include <linux/clk.h> 52#include <linux/err.h> 53#include <linux/completion.h> 54#include <linux/mutex.h> 55#include <linux/kthread.h> 56#include <linux/freezer.h> 57 58#include <mach/hardware.h> 59#include <asm/io.h> 60#include <asm/irq.h> 61#include <asm/div64.h> 62#include <mach/bitfield.h> 63#include <mach/pxafb.h> 64 65/* 66 * Complain if VAR is out of range. 67 */ 68#define DEBUG_VAR 1 69 70#include "pxafb.h" 71 72/* Bits which should not be set in machine configuration structures */ 73#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\ 74 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\ 75 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) 76 77#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ 78 LCCR3_PCD | LCCR3_BPP(0xf)) 79 80static int pxafb_activate_var(struct fb_var_screeninfo *var, 81 struct pxafb_info *); 82static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 83static void setup_base_frame(struct pxafb_info *fbi, 84 struct fb_var_screeninfo *var, int branch); 85static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 86 unsigned long offset, size_t size); 87 88static unsigned long video_mem_size = 0; 89 90static inline unsigned long 91lcd_readl(struct pxafb_info *fbi, unsigned int off) 92{ 93 return __raw_readl(fbi->mmio_base + off); 94} 95 96static inline void 97lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val) 98{ 99 __raw_writel(val, fbi->mmio_base + off); 100} 101 102static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) 103{ 104 unsigned long flags; 105 106 local_irq_save(flags); 107 /* 108 * We need to handle two requests being made at the same time. 109 * There are two important cases: 110 * 1. When we are changing VT (C_REENABLE) while unblanking 111 * (C_ENABLE) We must perform the unblanking, which will 112 * do our REENABLE for us. 113 * 2. When we are blanking, but immediately unblank before 114 * we have blanked. We do the "REENABLE" thing here as 115 * well, just to be sure. 116 */ 117 if (fbi->task_state == C_ENABLE && state == C_REENABLE) 118 state = (u_int) -1; 119 if (fbi->task_state == C_DISABLE && state == C_ENABLE) 120 state = C_REENABLE; 121 122 if (state != (u_int)-1) { 123 fbi->task_state = state; 124 schedule_work(&fbi->task); 125 } 126 local_irq_restore(flags); 127} 128 129static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) 130{ 131 chan &= 0xffff; 132 chan >>= 16 - bf->length; 133 return chan << bf->offset; 134} 135 136static int 137pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, 138 u_int trans, struct fb_info *info) 139{ 140 struct pxafb_info *fbi = (struct pxafb_info *)info; 141 u_int val; 142 143 if (regno >= fbi->palette_size) 144 return 1; 145 146 if (fbi->fb.var.grayscale) { 147 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff); 148 return 0; 149 } 150 151 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) { 152 case LCCR4_PAL_FOR_0: 153 val = ((red >> 0) & 0xf800); 154 val |= ((green >> 5) & 0x07e0); 155 val |= ((blue >> 11) & 0x001f); 156 fbi->palette_cpu[regno] = val; 157 break; 158 case LCCR4_PAL_FOR_1: 159 val = ((red << 8) & 0x00f80000); 160 val |= ((green >> 0) & 0x0000fc00); 161 val |= ((blue >> 8) & 0x000000f8); 162 ((u32 *)(fbi->palette_cpu))[regno] = val; 163 break; 164 case LCCR4_PAL_FOR_2: 165 val = ((red << 8) & 0x00fc0000); 166 val |= ((green >> 0) & 0x0000fc00); 167 val |= ((blue >> 8) & 0x000000fc); 168 ((u32 *)(fbi->palette_cpu))[regno] = val; 169 break; 170 case LCCR4_PAL_FOR_3: 171 val = ((red << 8) & 0x00ff0000); 172 val |= ((green >> 0) & 0x0000ff00); 173 val |= ((blue >> 8) & 0x000000ff); 174 ((u32 *)(fbi->palette_cpu))[regno] = val; 175 break; 176 } 177 178 return 0; 179} 180 181static int 182pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 183 u_int trans, struct fb_info *info) 184{ 185 struct pxafb_info *fbi = (struct pxafb_info *)info; 186 unsigned int val; 187 int ret = 1; 188 189 /* 190 * If inverse mode was selected, invert all the colours 191 * rather than the register number. The register number 192 * is what you poke into the framebuffer to produce the 193 * colour you requested. 194 */ 195 if (fbi->cmap_inverse) { 196 red = 0xffff - red; 197 green = 0xffff - green; 198 blue = 0xffff - blue; 199 } 200 201 /* 202 * If greyscale is true, then we convert the RGB value 203 * to greyscale no matter what visual we are using. 204 */ 205 if (fbi->fb.var.grayscale) 206 red = green = blue = (19595 * red + 38470 * green + 207 7471 * blue) >> 16; 208 209 switch (fbi->fb.fix.visual) { 210 case FB_VISUAL_TRUECOLOR: 211 /* 212 * 16-bit True Colour. We encode the RGB value 213 * according to the RGB bitfield information. 214 */ 215 if (regno < 16) { 216 u32 *pal = fbi->fb.pseudo_palette; 217 218 val = chan_to_field(red, &fbi->fb.var.red); 219 val |= chan_to_field(green, &fbi->fb.var.green); 220 val |= chan_to_field(blue, &fbi->fb.var.blue); 221 222 pal[regno] = val; 223 ret = 0; 224 } 225 break; 226 227 case FB_VISUAL_STATIC_PSEUDOCOLOR: 228 case FB_VISUAL_PSEUDOCOLOR: 229 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); 230 break; 231 } 232 233 return ret; 234} 235 236/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */ 237static inline int var_to_depth(struct fb_var_screeninfo *var) 238{ 239 return var->red.length + var->green.length + 240 var->blue.length + var->transp.length; 241} 242 243/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */ 244static int pxafb_var_to_bpp(struct fb_var_screeninfo *var) 245{ 246 int bpp = -EINVAL; 247 248 switch (var->bits_per_pixel) { 249 case 1: bpp = 0; break; 250 case 2: bpp = 1; break; 251 case 4: bpp = 2; break; 252 case 8: bpp = 3; break; 253 case 16: bpp = 4; break; 254 case 24: 255 switch (var_to_depth(var)) { 256 case 18: bpp = 6; break; /* 18-bits/pixel packed */ 257 case 19: bpp = 8; break; /* 19-bits/pixel packed */ 258 case 24: bpp = 9; break; 259 } 260 break; 261 case 32: 262 switch (var_to_depth(var)) { 263 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */ 264 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */ 265 case 25: bpp = 10; break; 266 } 267 break; 268 } 269 return bpp; 270} 271 272/* 273 * pxafb_var_to_lccr3(): 274 * Convert a bits per pixel value to the correct bit pattern for LCCR3 275 * 276 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an 277 * implication of the acutal use of transparency bit, which we handle it 278 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel 279 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP. 280 * 281 * Transparency for palette pixel formats is not supported at the moment. 282 */ 283static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var) 284{ 285 int bpp = pxafb_var_to_bpp(var); 286 uint32_t lccr3; 287 288 if (bpp < 0) 289 return 0; 290 291 lccr3 = LCCR3_BPP(bpp); 292 293 switch (var_to_depth(var)) { 294 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break; 295 case 18: lccr3 |= LCCR3_PDFOR_3; break; 296 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3; 297 break; 298 case 19: 299 case 25: lccr3 |= LCCR3_PDFOR_0; break; 300 } 301 return lccr3; 302} 303 304#define SET_PIXFMT(v, r, g, b, t) \ 305({ \ 306 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \ 307 (v)->transp.length = (t) ? (t) : 0; \ 308 (v)->blue.length = (b); (v)->blue.offset = 0; \ 309 (v)->green.length = (g); (v)->green.offset = (b); \ 310 (v)->red.length = (r); (v)->red.offset = (b) + (g); \ 311}) 312 313/* set the RGBT bitfields of fb_var_screeninf according to 314 * var->bits_per_pixel and given depth 315 */ 316static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth) 317{ 318 if (depth == 0) 319 depth = var->bits_per_pixel; 320 321 if (var->bits_per_pixel < 16) { 322 /* indexed pixel formats */ 323 var->red.offset = 0; var->red.length = 8; 324 var->green.offset = 0; var->green.length = 8; 325 var->blue.offset = 0; var->blue.length = 8; 326 var->transp.offset = 0; var->transp.length = 8; 327 } 328 329 switch (depth) { 330 case 16: var->transp.length ? 331 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */ 332 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */ 333 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */ 334 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */ 335 case 24: var->transp.length ? 336 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */ 337 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */ 338 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */ 339 } 340} 341 342#ifdef CONFIG_CPU_FREQ 343/* 344 * pxafb_display_dma_period() 345 * Calculate the minimum period (in picoseconds) between two DMA 346 * requests for the LCD controller. If we hit this, it means we're 347 * doing nothing but LCD DMA. 348 */ 349static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) 350{ 351 /* 352 * Period = pixclock * bits_per_byte * bytes_per_transfer 353 * / memory_bits_per_pixel; 354 */ 355 return var->pixclock * 8 * 16 / var->bits_per_pixel; 356} 357#endif 358 359/* 360 * Select the smallest mode that allows the desired resolution to be 361 * displayed. If desired parameters can be rounded up. 362 */ 363static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, 364 struct fb_var_screeninfo *var) 365{ 366 struct pxafb_mode_info *mode = NULL; 367 struct pxafb_mode_info *modelist = mach->modes; 368 unsigned int best_x = 0xffffffff, best_y = 0xffffffff; 369 unsigned int i; 370 371 for (i = 0; i < mach->num_modes; i++) { 372 if (modelist[i].xres >= var->xres && 373 modelist[i].yres >= var->yres && 374 modelist[i].xres < best_x && 375 modelist[i].yres < best_y && 376 modelist[i].bpp >= var->bits_per_pixel) { 377 best_x = modelist[i].xres; 378 best_y = modelist[i].yres; 379 mode = &modelist[i]; 380 } 381 } 382 383 return mode; 384} 385 386static void pxafb_setmode(struct fb_var_screeninfo *var, 387 struct pxafb_mode_info *mode) 388{ 389 var->xres = mode->xres; 390 var->yres = mode->yres; 391 var->bits_per_pixel = mode->bpp; 392 var->pixclock = mode->pixclock; 393 var->hsync_len = mode->hsync_len; 394 var->left_margin = mode->left_margin; 395 var->right_margin = mode->right_margin; 396 var->vsync_len = mode->vsync_len; 397 var->upper_margin = mode->upper_margin; 398 var->lower_margin = mode->lower_margin; 399 var->sync = mode->sync; 400 var->grayscale = mode->cmap_greyscale; 401 var->transp.length = mode->transparency; 402 403 /* set the initial RGBA bitfields */ 404 pxafb_set_pixfmt(var, mode->depth); 405} 406 407static int pxafb_adjust_timing(struct pxafb_info *fbi, 408 struct fb_var_screeninfo *var) 409{ 410 int line_length; 411 412 var->xres = max_t(int, var->xres, MIN_XRES); 413 var->yres = max_t(int, var->yres, MIN_YRES); 414 415 if (!(fbi->lccr0 & LCCR0_LCDT)) { 416 clamp_val(var->hsync_len, 1, 64); 417 clamp_val(var->vsync_len, 1, 64); 418 clamp_val(var->left_margin, 1, 255); 419 clamp_val(var->right_margin, 1, 255); 420 clamp_val(var->upper_margin, 1, 255); 421 clamp_val(var->lower_margin, 1, 255); 422 } 423 424 /* make sure each line is aligned on word boundary */ 425 line_length = var->xres * var->bits_per_pixel / 8; 426 line_length = ALIGN(line_length, 4); 427 var->xres = line_length * 8 / var->bits_per_pixel; 428 429 /* we don't support xpan, force xres_virtual to be equal to xres */ 430 var->xres_virtual = var->xres; 431 432 if (var->accel_flags & FB_ACCELF_TEXT) 433 var->yres_virtual = fbi->fb.fix.smem_len / line_length; 434 else 435 var->yres_virtual = max(var->yres_virtual, var->yres); 436 437 /* check for limits */ 438 if (var->xres > MAX_XRES || var->yres > MAX_YRES) 439 return -EINVAL; 440 441 if (var->yres > var->yres_virtual) 442 return -EINVAL; 443 444 return 0; 445} 446 447/* 448 * pxafb_check_var(): 449 * Get the video params out of 'var'. If a value doesn't fit, round it up, 450 * if it's too big, return -EINVAL. 451 * 452 * Round up in the following order: bits_per_pixel, xres, 453 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, 454 * bitfields, horizontal timing, vertical timing. 455 */ 456static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 457{ 458 struct pxafb_info *fbi = (struct pxafb_info *)info; 459 struct pxafb_mach_info *inf = fbi->dev->platform_data; 460 int err; 461 462 if (inf->fixed_modes) { 463 struct pxafb_mode_info *mode; 464 465 mode = pxafb_getmode(inf, var); 466 if (!mode) 467 return -EINVAL; 468 pxafb_setmode(var, mode); 469 } 470 471 /* do a test conversion to BPP fields to check the color formats */ 472 err = pxafb_var_to_bpp(var); 473 if (err < 0) 474 return err; 475 476 pxafb_set_pixfmt(var, var_to_depth(var)); 477 478 err = pxafb_adjust_timing(fbi, var); 479 if (err) 480 return err; 481 482#ifdef CONFIG_CPU_FREQ 483 pr_debug("pxafb: dma period = %d ps\n", 484 pxafb_display_dma_period(var)); 485#endif 486 487 return 0; 488} 489 490/* 491 * pxafb_set_par(): 492 * Set the user defined part of the display for the specified console 493 */ 494static int pxafb_set_par(struct fb_info *info) 495{ 496 struct pxafb_info *fbi = (struct pxafb_info *)info; 497 struct fb_var_screeninfo *var = &info->var; 498 499 if (var->bits_per_pixel >= 16) 500 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; 501 else if (!fbi->cmap_static) 502 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 503 else { 504 /* 505 * Some people have weird ideas about wanting static 506 * pseudocolor maps. I suspect their user space 507 * applications are broken. 508 */ 509 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; 510 } 511 512 fbi->fb.fix.line_length = var->xres_virtual * 513 var->bits_per_pixel / 8; 514 if (var->bits_per_pixel >= 16) 515 fbi->palette_size = 0; 516 else 517 fbi->palette_size = var->bits_per_pixel == 1 ? 518 4 : 1 << var->bits_per_pixel; 519 520 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; 521 522 if (fbi->fb.var.bits_per_pixel >= 16) 523 fb_dealloc_cmap(&fbi->fb.cmap); 524 else 525 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); 526 527 pxafb_activate_var(var, fbi); 528 529 return 0; 530} 531 532static int pxafb_pan_display(struct fb_var_screeninfo *var, 533 struct fb_info *info) 534{ 535 struct pxafb_info *fbi = (struct pxafb_info *)info; 536 struct fb_var_screeninfo newvar; 537 int dma = DMA_MAX + DMA_BASE; 538 539 if (fbi->state != C_ENABLE) 540 return 0; 541 542 /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what 543 * was passed in and copy the rest from the old screeninfo. 544 */ 545 memcpy(&newvar, &fbi->fb.var, sizeof(newvar)); 546 newvar.xoffset = var->xoffset; 547 newvar.yoffset = var->yoffset; 548 newvar.vmode &= ~FB_VMODE_YWRAP; 549 newvar.vmode |= var->vmode & FB_VMODE_YWRAP; 550 551 setup_base_frame(fbi, &newvar, 1); 552 553 if (fbi->lccr0 & LCCR0_SDS) 554 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1); 555 556 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1); 557 return 0; 558} 559 560/* 561 * pxafb_blank(): 562 * Blank the display by setting all palette values to zero. Note, the 563 * 16 bpp mode does not really use the palette, so this will not 564 * blank the display in all modes. 565 */ 566static int pxafb_blank(int blank, struct fb_info *info) 567{ 568 struct pxafb_info *fbi = (struct pxafb_info *)info; 569 int i; 570 571 switch (blank) { 572 case FB_BLANK_POWERDOWN: 573 case FB_BLANK_VSYNC_SUSPEND: 574 case FB_BLANK_HSYNC_SUSPEND: 575 case FB_BLANK_NORMAL: 576 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 577 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 578 for (i = 0; i < fbi->palette_size; i++) 579 pxafb_setpalettereg(i, 0, 0, 0, 0, info); 580 581 pxafb_schedule_work(fbi, C_DISABLE); 582 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ 583 break; 584 585 case FB_BLANK_UNBLANK: 586 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ 587 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || 588 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) 589 fb_set_cmap(&fbi->fb.cmap, info); 590 pxafb_schedule_work(fbi, C_ENABLE); 591 } 592 return 0; 593} 594 595static struct fb_ops pxafb_ops = { 596 .owner = THIS_MODULE, 597 .fb_check_var = pxafb_check_var, 598 .fb_set_par = pxafb_set_par, 599 .fb_pan_display = pxafb_pan_display, 600 .fb_setcolreg = pxafb_setcolreg, 601 .fb_fillrect = cfb_fillrect, 602 .fb_copyarea = cfb_copyarea, 603 .fb_imageblit = cfb_imageblit, 604 .fb_blank = pxafb_blank, 605}; 606 607#ifdef CONFIG_FB_PXA_OVERLAY 608static void overlay1fb_setup(struct pxafb_layer *ofb) 609{ 610 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; 611 unsigned long start = ofb->video_mem_phys; 612 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size); 613} 614 615/* Depending on the enable status of overlay1/2, the DMA should be 616 * updated from FDADRx (when disabled) or FBRx (when enabled). 617 */ 618static void overlay1fb_enable(struct pxafb_layer *ofb) 619{ 620 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN; 621 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0); 622 623 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1); 624 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]); 625 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN); 626} 627 628static void overlay1fb_disable(struct pxafb_layer *ofb) 629{ 630 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5); 631 632 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN); 633 634 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1)); 635 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1)); 636 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3); 637 638 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) 639 pr_warning("%s: timeout disabling overlay1\n", __func__); 640 641 lcd_writel(ofb->fbi, LCCR5, lccr5); 642} 643 644static void overlay2fb_setup(struct pxafb_layer *ofb) 645{ 646 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); 647 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 }; 648 649 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) { 650 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; 651 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); 652 } else { 653 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual; 654 switch (pfor) { 655 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break; 656 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break; 657 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break; 658 } 659 start[1] = start[0] + size; 660 start[2] = start[1] + size / div; 661 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); 662 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div); 663 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div); 664 } 665} 666 667static void overlay2fb_enable(struct pxafb_layer *ofb) 668{ 669 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); 670 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN; 671 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0); 672 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0); 673 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0); 674 675 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) 676 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); 677 else { 678 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); 679 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3); 680 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4); 681 } 682 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]); 683 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN); 684} 685 686static void overlay2fb_disable(struct pxafb_layer *ofb) 687{ 688 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5); 689 690 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN); 691 692 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2)); 693 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2)); 694 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3); 695 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3); 696 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3); 697 698 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) 699 pr_warning("%s: timeout disabling overlay2\n", __func__); 700} 701 702static struct pxafb_layer_ops ofb_ops[] = { 703 [0] = { 704 .enable = overlay1fb_enable, 705 .disable = overlay1fb_disable, 706 .setup = overlay1fb_setup, 707 }, 708 [1] = { 709 .enable = overlay2fb_enable, 710 .disable = overlay2fb_disable, 711 .setup = overlay2fb_setup, 712 }, 713}; 714 715static int overlayfb_open(struct fb_info *info, int user) 716{ 717 struct pxafb_layer *ofb = (struct pxafb_layer *)info; 718 719 /* no support for framebuffer console on overlay */ 720 if (user == 0) 721 return -ENODEV; 722 723 /* allow only one user at a time */ 724 if (atomic_inc_and_test(&ofb->usage)) 725 return -EBUSY; 726 727 /* unblank the base framebuffer */ 728 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK); 729 return 0; 730} 731 732static int overlayfb_release(struct fb_info *info, int user) 733{ 734 struct pxafb_layer *ofb = (struct pxafb_layer*) info; 735 736 atomic_dec(&ofb->usage); 737 ofb->ops->disable(ofb); 738 739 free_pages_exact(ofb->video_mem, ofb->video_mem_size); 740 ofb->video_mem = NULL; 741 ofb->video_mem_size = 0; 742 return 0; 743} 744 745static int overlayfb_check_var(struct fb_var_screeninfo *var, 746 struct fb_info *info) 747{ 748 struct pxafb_layer *ofb = (struct pxafb_layer *)info; 749 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var; 750 int xpos, ypos, pfor, bpp; 751 752 xpos = NONSTD_TO_XPOS(var->nonstd); 753 ypos = NONSTD_TO_XPOS(var->nonstd); 754 pfor = NONSTD_TO_PFOR(var->nonstd); 755 756 bpp = pxafb_var_to_bpp(var); 757 if (bpp < 0) 758 return -EINVAL; 759 760 /* no support for YUV format on overlay1 */ 761 if (ofb->id == OVERLAY1 && pfor != 0) 762 return -EINVAL; 763 764 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */ 765 switch (pfor) { 766 case OVERLAY_FORMAT_RGB: 767 bpp = pxafb_var_to_bpp(var); 768 if (bpp < 0) 769 return -EINVAL; 770 771 pxafb_set_pixfmt(var, var_to_depth(var)); 772 break; 773 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; 774 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break; 775 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break; 776 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break; 777 default: 778 return -EINVAL; 779 } 780 781 /* each line must start at a 32-bit word boundary */ 782 if ((xpos * bpp) % 32) 783 return -EINVAL; 784 785 /* xres must align on 32-bit word boundary */ 786 var->xres = roundup(var->xres * bpp, 32) / bpp; 787 788 if ((xpos + var->xres > base_var->xres) || 789 (ypos + var->yres > base_var->yres)) 790 return -EINVAL; 791 792 var->xres_virtual = var->xres; 793 var->yres_virtual = max(var->yres, var->yres_virtual); 794 return 0; 795} 796 797static int overlayfb_map_video_memory(struct pxafb_layer *ofb) 798{ 799 struct fb_var_screeninfo *var = &ofb->fb.var; 800 int pfor = NONSTD_TO_PFOR(var->nonstd); 801 int size, bpp = 0; 802 803 switch (pfor) { 804 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break; 805 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; 806 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break; 807 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break; 808 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break; 809 } 810 811 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8; 812 813 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual); 814 815 /* don't re-allocate if the original video memory is enough */ 816 if (ofb->video_mem) { 817 if (ofb->video_mem_size >= size) 818 return 0; 819 820 free_pages_exact(ofb->video_mem, ofb->video_mem_size); 821 } 822 823 ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO); 824 if (ofb->video_mem == NULL) 825 return -ENOMEM; 826 827 ofb->video_mem_phys = virt_to_phys(ofb->video_mem); 828 ofb->video_mem_size = size; 829 830 mutex_lock(&ofb->fb.mm_lock); 831 ofb->fb.fix.smem_start = ofb->video_mem_phys; 832 ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual; 833 mutex_unlock(&ofb->fb.mm_lock); 834 ofb->fb.screen_base = ofb->video_mem; 835 return 0; 836} 837 838static int overlayfb_set_par(struct fb_info *info) 839{ 840 struct pxafb_layer *ofb = (struct pxafb_layer *)info; 841 struct fb_var_screeninfo *var = &info->var; 842 int xpos, ypos, pfor, bpp, ret; 843 844 ret = overlayfb_map_video_memory(ofb); 845 if (ret) 846 return ret; 847 848 bpp = pxafb_var_to_bpp(var); 849 xpos = NONSTD_TO_XPOS(var->nonstd); 850 ypos = NONSTD_TO_XPOS(var->nonstd); 851 pfor = NONSTD_TO_PFOR(var->nonstd); 852 853 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) | 854 OVLxC1_BPP(bpp); 855 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos); 856 857 if (ofb->id == OVERLAY2) 858 ofb->control[1] |= OVL2C2_PFOR(pfor); 859 860 ofb->ops->setup(ofb); 861 ofb->ops->enable(ofb); 862 return 0; 863} 864 865static struct fb_ops overlay_fb_ops = { 866 .owner = THIS_MODULE, 867 .fb_open = overlayfb_open, 868 .fb_release = overlayfb_release, 869 .fb_check_var = overlayfb_check_var, 870 .fb_set_par = overlayfb_set_par, 871}; 872 873static void __devinit init_pxafb_overlay(struct pxafb_info *fbi, 874 struct pxafb_layer *ofb, int id) 875{ 876 sprintf(ofb->fb.fix.id, "overlay%d", id + 1); 877 878 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 879 ofb->fb.fix.xpanstep = 0; 880 ofb->fb.fix.ypanstep = 1; 881 882 ofb->fb.var.activate = FB_ACTIVATE_NOW; 883 ofb->fb.var.height = -1; 884 ofb->fb.var.width = -1; 885 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED; 886 887 ofb->fb.fbops = &overlay_fb_ops; 888 ofb->fb.flags = FBINFO_FLAG_DEFAULT; 889 ofb->fb.node = -1; 890 ofb->fb.pseudo_palette = NULL; 891 892 ofb->id = id; 893 ofb->ops = &ofb_ops[id]; 894 atomic_set(&ofb->usage, 0); 895 ofb->fbi = fbi; 896 init_completion(&ofb->branch_done); 897} 898 899static inline int pxafb_overlay_supported(void) 900{ 901 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) 902 return 1; 903 904 return 0; 905} 906 907static int __devinit pxafb_overlay_init(struct pxafb_info *fbi) 908{ 909 int i, ret; 910 911 if (!pxafb_overlay_supported()) 912 return 0; 913 914 for (i = 0; i < 2; i++) { 915 init_pxafb_overlay(fbi, &fbi->overlay[i], i); 916 ret = register_framebuffer(&fbi->overlay[i].fb); 917 if (ret) { 918 dev_err(fbi->dev, "failed to register overlay %d\n", i); 919 return ret; 920 } 921 } 922 923 /* mask all IU/BS/EOF/SOF interrupts */ 924 lcd_writel(fbi, LCCR5, ~0); 925 926 /* place overlay(s) on top of base */ 927 fbi->lccr0 |= LCCR0_OUC; 928 pr_info("PXA Overlay driver loaded successfully!\n"); 929 return 0; 930} 931 932static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi) 933{ 934 int i; 935 936 if (!pxafb_overlay_supported()) 937 return; 938 939 for (i = 0; i < 2; i++) 940 unregister_framebuffer(&fbi->overlay[i].fb); 941} 942#else 943static inline void pxafb_overlay_init(struct pxafb_info *fbi) {} 944static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {} 945#endif /* CONFIG_FB_PXA_OVERLAY */ 946 947/* 948 * Calculate the PCD value from the clock rate (in picoseconds). 949 * We take account of the PPCR clock setting. 950 * From PXA Developer's Manual: 951 * 952 * PixelClock = LCLK 953 * ------------- 954 * 2 ( PCD + 1 ) 955 * 956 * PCD = LCLK 957 * ------------- - 1 958 * 2(PixelClock) 959 * 960 * Where: 961 * LCLK = LCD/Memory Clock 962 * PCD = LCCR3[7:0] 963 * 964 * PixelClock here is in Hz while the pixclock argument given is the 965 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) 966 * 967 * The function get_lclk_frequency_10khz returns LCLK in units of 968 * 10khz. Calling the result of this function lclk gives us the 969 * following 970 * 971 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) 972 * -------------------------------------- - 1 973 * 2 974 * 975 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. 976 */ 977static inline unsigned int get_pcd(struct pxafb_info *fbi, 978 unsigned int pixclock) 979{ 980 unsigned long long pcd; 981 982 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); 983 pcd *= pixclock; 984 do_div(pcd, 100000000 * 2); 985 /* no need for this, since we should subtract 1 anyway. they cancel */ 986 /* pcd += 1; */ /* make up for integer math truncations */ 987 return (unsigned int)pcd; 988} 989 990/* 991 * Some touchscreens need hsync information from the video driver to 992 * function correctly. We export it here. Note that 'hsync_time' and 993 * the value returned from pxafb_get_hsync_time() is the *reciprocal* 994 * of the hsync period in seconds. 995 */ 996static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) 997{ 998 unsigned long htime; 999 1000 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { 1001 fbi->hsync_time = 0; 1002 return; 1003 } 1004 1005 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); 1006 1007 fbi->hsync_time = htime; 1008} 1009 1010unsigned long pxafb_get_hsync_time(struct device *dev) 1011{ 1012 struct pxafb_info *fbi = dev_get_drvdata(dev); 1013 1014 /* If display is blanked/suspended, hsync isn't active */ 1015 if (!fbi || (fbi->state != C_ENABLE)) 1016 return 0; 1017 1018 return fbi->hsync_time; 1019} 1020EXPORT_SYMBOL(pxafb_get_hsync_time); 1021 1022static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 1023 unsigned long start, size_t size) 1024{ 1025 struct pxafb_dma_descriptor *dma_desc, *pal_desc; 1026 unsigned int dma_desc_off, pal_desc_off; 1027 1028 if (dma < 0 || dma >= DMA_MAX * 2) 1029 return -EINVAL; 1030 1031 dma_desc = &fbi->dma_buff->dma_desc[dma]; 1032 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); 1033 1034 dma_desc->fsadr = start; 1035 dma_desc->fidr = 0; 1036 dma_desc->ldcmd = size; 1037 1038 if (pal < 0 || pal >= PAL_MAX * 2) { 1039 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1040 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1041 } else { 1042 pal_desc = &fbi->dma_buff->pal_desc[pal]; 1043 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]); 1044 1045 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE; 1046 pal_desc->fidr = 0; 1047 1048 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) 1049 pal_desc->ldcmd = fbi->palette_size * sizeof(u16); 1050 else 1051 pal_desc->ldcmd = fbi->palette_size * sizeof(u32); 1052 1053 pal_desc->ldcmd |= LDCMD_PAL; 1054 1055 /* flip back and forth between palette and frame buffer */ 1056 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1057 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off; 1058 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1059 } 1060 1061 return 0; 1062} 1063 1064static void setup_base_frame(struct pxafb_info *fbi, 1065 struct fb_var_screeninfo *var, 1066 int branch) 1067{ 1068 struct fb_fix_screeninfo *fix = &fbi->fb.fix; 1069 int nbytes, dma, pal, bpp = var->bits_per_pixel; 1070 unsigned long offset; 1071 1072 dma = DMA_BASE + (branch ? DMA_MAX : 0); 1073 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0); 1074 1075 nbytes = fix->line_length * var->yres; 1076 offset = fix->line_length * var->yoffset + fbi->video_mem_phys; 1077 1078 if (fbi->lccr0 & LCCR0_SDS) { 1079 nbytes = nbytes / 2; 1080 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes); 1081 } 1082 1083 setup_frame_dma(fbi, dma, pal, offset, nbytes); 1084} 1085 1086#ifdef CONFIG_FB_PXA_SMARTPANEL 1087static int setup_smart_dma(struct pxafb_info *fbi) 1088{ 1089 struct pxafb_dma_descriptor *dma_desc; 1090 unsigned long dma_desc_off, cmd_buff_off; 1091 1092 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD]; 1093 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]); 1094 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff); 1095 1096 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1097 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off; 1098 dma_desc->fidr = 0; 1099 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t); 1100 1101 fbi->fdadr[DMA_CMD] = dma_desc->fdadr; 1102 return 0; 1103} 1104 1105int pxafb_smart_flush(struct fb_info *info) 1106{ 1107 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 1108 uint32_t prsr; 1109 int ret = 0; 1110 1111 /* disable controller until all registers are set up */ 1112 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1113 1114 /* 1. make it an even number of commands to align on 32-bit boundary 1115 * 2. add the interrupt command to the end of the chain so we can 1116 * keep track of the end of the transfer 1117 */ 1118 1119 while (fbi->n_smart_cmds & 1) 1120 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP; 1121 1122 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT; 1123 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC; 1124 setup_smart_dma(fbi); 1125 1126 /* continue to execute next command */ 1127 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT; 1128 lcd_writel(fbi, PRSR, prsr); 1129 1130 /* stop the processor in case it executed "wait for sync" cmd */ 1131 lcd_writel(fbi, CMDCR, 0x0001); 1132 1133 /* don't send interrupts for fifo underruns on channel 6 */ 1134 lcd_writel(fbi, LCCR5, LCCR5_IUM(6)); 1135 1136 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1137 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1138 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1139 lcd_writel(fbi, LCCR4, fbi->reg_lccr4); 1140 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1141 lcd_writel(fbi, FDADR6, fbi->fdadr[6]); 1142 1143 /* begin sending */ 1144 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); 1145 1146 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) { 1147 pr_warning("%s: timeout waiting for command done\n", 1148 __func__); 1149 ret = -ETIMEDOUT; 1150 } 1151 1152 /* quick disable */ 1153 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT); 1154 lcd_writel(fbi, PRSR, prsr); 1155 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1156 lcd_writel(fbi, FDADR6, 0); 1157 fbi->n_smart_cmds = 0; 1158 return ret; 1159} 1160 1161int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) 1162{ 1163 int i; 1164 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); 1165 1166 for (i = 0; i < n_cmds; i++, cmds++) { 1167 /* if it is a software delay, flush and delay */ 1168 if ((*cmds & 0xff00) == SMART_CMD_DELAY) { 1169 pxafb_smart_flush(info); 1170 mdelay(*cmds & 0xff); 1171 continue; 1172 } 1173 1174 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ 1175 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) 1176 pxafb_smart_flush(info); 1177 1178 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds; 1179 } 1180 1181 return 0; 1182} 1183 1184static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk) 1185{ 1186 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000); 1187 return (t == 0) ? 1 : t; 1188} 1189 1190static void setup_smart_timing(struct pxafb_info *fbi, 1191 struct fb_var_screeninfo *var) 1192{ 1193 struct pxafb_mach_info *inf = fbi->dev->platform_data; 1194 struct pxafb_mode_info *mode = &inf->modes[0]; 1195 unsigned long lclk = clk_get_rate(fbi->clk); 1196 unsigned t1, t2, t3, t4; 1197 1198 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld); 1199 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width); 1200 t3 = mode->op_hold_time; 1201 t4 = mode->cmd_inh_time; 1202 1203 fbi->reg_lccr1 = 1204 LCCR1_DisWdth(var->xres) | 1205 LCCR1_BegLnDel(__smart_timing(t1, lclk)) | 1206 LCCR1_EndLnDel(__smart_timing(t2, lclk)) | 1207 LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); 1208 1209 fbi->reg_lccr2 = LCCR2_DisHght(var->yres); 1210 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); 1211 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; 1212 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; 1213 1214 fbi->reg_cmdcr = 1; 1215} 1216 1217static int pxafb_smart_thread(void *arg) 1218{ 1219 struct pxafb_info *fbi = arg; 1220 struct pxafb_mach_info *inf = fbi->dev->platform_data; 1221 1222 if (!inf->smart_update) { 1223 pr_err("%s: not properly initialized, thread terminated\n", 1224 __func__); 1225 return -EINVAL; 1226 } 1227 inf = fbi->dev->platform_data; 1228 1229 pr_debug("%s(): task starting\n", __func__); 1230 1231 set_freezable(); 1232 while (!kthread_should_stop()) { 1233 1234 if (try_to_freeze()) 1235 continue; 1236 1237 mutex_lock(&fbi->ctrlr_lock); 1238 1239 if (fbi->state == C_ENABLE) { 1240 inf->smart_update(&fbi->fb); 1241 complete(&fbi->refresh_done); 1242 } 1243 1244 mutex_unlock(&fbi->ctrlr_lock); 1245 1246 set_current_state(TASK_INTERRUPTIBLE); 1247 schedule_timeout(30 * HZ / 1000); 1248 } 1249 1250 pr_debug("%s(): task ending\n", __func__); 1251 return 0; 1252} 1253 1254static int pxafb_smart_init(struct pxafb_info *fbi) 1255{ 1256 if (!(fbi->lccr0 & LCCR0_LCDT)) 1257 return 0; 1258 1259 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; 1260 fbi->n_smart_cmds = 0; 1261 1262 init_completion(&fbi->command_done); 1263 init_completion(&fbi->refresh_done); 1264 1265 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, 1266 "lcd_refresh"); 1267 if (IS_ERR(fbi->smart_thread)) { 1268 pr_err("%s: unable to create kernel thread\n", __func__); 1269 return PTR_ERR(fbi->smart_thread); 1270 } 1271 1272 return 0; 1273} 1274#else 1275int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) 1276{ 1277 return 0; 1278} 1279 1280int pxafb_smart_flush(struct fb_info *info) 1281{ 1282 return 0; 1283} 1284 1285static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; } 1286#endif /* CONFIG_FB_PXA_SMARTPANEL */ 1287 1288static void setup_parallel_timing(struct pxafb_info *fbi, 1289 struct fb_var_screeninfo *var) 1290{ 1291 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); 1292 1293 fbi->reg_lccr1 = 1294 LCCR1_DisWdth(var->xres) + 1295 LCCR1_HorSnchWdth(var->hsync_len) + 1296 LCCR1_BegLnDel(var->left_margin) + 1297 LCCR1_EndLnDel(var->right_margin); 1298 1299 /* 1300 * If we have a dual scan LCD, we need to halve 1301 * the YRES parameter. 1302 */ 1303 lines_per_panel = var->yres; 1304 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) 1305 lines_per_panel /= 2; 1306 1307 fbi->reg_lccr2 = 1308 LCCR2_DisHght(lines_per_panel) + 1309 LCCR2_VrtSnchWdth(var->vsync_len) + 1310 LCCR2_BegFrmDel(var->upper_margin) + 1311 LCCR2_EndFrmDel(var->lower_margin); 1312 1313 fbi->reg_lccr3 = fbi->lccr3 | 1314 (var->sync & FB_SYNC_HOR_HIGH_ACT ? 1315 LCCR3_HorSnchH : LCCR3_HorSnchL) | 1316 (var->sync & FB_SYNC_VERT_HIGH_ACT ? 1317 LCCR3_VrtSnchH : LCCR3_VrtSnchL); 1318 1319 if (pcd) { 1320 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd); 1321 set_hsync_time(fbi, pcd); 1322 } 1323} 1324 1325/* 1326 * pxafb_activate_var(): 1327 * Configures LCD Controller based on entries in var parameter. 1328 * Settings are only written to the controller if changes were made. 1329 */ 1330static int pxafb_activate_var(struct fb_var_screeninfo *var, 1331 struct pxafb_info *fbi) 1332{ 1333 u_long flags; 1334 1335 /* Update shadow copy atomically */ 1336 local_irq_save(flags); 1337 1338#ifdef CONFIG_FB_PXA_SMARTPANEL 1339 if (fbi->lccr0 & LCCR0_LCDT) 1340 setup_smart_timing(fbi, var); 1341 else 1342#endif 1343 setup_parallel_timing(fbi, var); 1344 1345 setup_base_frame(fbi, var, 0); 1346 1347 fbi->reg_lccr0 = fbi->lccr0 | 1348 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | 1349 LCCR0_QDM | LCCR0_BM | LCCR0_OUM); 1350 1351 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var); 1352 1353 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; 1354 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); 1355 local_irq_restore(flags); 1356 1357 /* 1358 * Only update the registers if the controller is enabled 1359 * and something has changed. 1360 */ 1361 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) || 1362 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || 1363 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || 1364 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || 1365 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) || 1366 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || 1367 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])) 1368 pxafb_schedule_work(fbi, C_REENABLE); 1369 1370 return 0; 1371} 1372 1373/* 1374 * NOTE! The following functions are purely helpers for set_ctrlr_state. 1375 * Do not call them directly; set_ctrlr_state does the correct serialisation 1376 * to ensure that things happen in the right way 100% of time time. 1377 * -- rmk 1378 */ 1379static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) 1380{ 1381 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); 1382 1383 if (fbi->backlight_power) 1384 fbi->backlight_power(on); 1385} 1386 1387static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) 1388{ 1389 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); 1390 1391 if (fbi->lcd_power) 1392 fbi->lcd_power(on, &fbi->fb.var); 1393} 1394 1395static void pxafb_enable_controller(struct pxafb_info *fbi) 1396{ 1397 pr_debug("pxafb: Enabling LCD controller\n"); 1398 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]); 1399 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]); 1400 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); 1401 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); 1402 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); 1403 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); 1404 1405 /* enable LCD controller clock */ 1406 clk_enable(fbi->clk); 1407 1408 if (fbi->lccr0 & LCCR0_LCDT) 1409 return; 1410 1411 /* Sequence from 11.7.10 */ 1412 lcd_writel(fbi, LCCR4, fbi->reg_lccr4); 1413 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1414 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1415 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1416 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); 1417 1418 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1419 lcd_writel(fbi, FDADR1, fbi->fdadr[1]); 1420 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); 1421} 1422 1423static void pxafb_disable_controller(struct pxafb_info *fbi) 1424{ 1425 uint32_t lccr0; 1426 1427#ifdef CONFIG_FB_PXA_SMARTPANEL 1428 if (fbi->lccr0 & LCCR0_LCDT) { 1429 wait_for_completion_timeout(&fbi->refresh_done, 1430 200 * HZ / 1000); 1431 return; 1432 } 1433#endif 1434 1435 /* Clear LCD Status Register */ 1436 lcd_writel(fbi, LCSR, 0xffffffff); 1437 1438 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM; 1439 lcd_writel(fbi, LCCR0, lccr0); 1440 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS); 1441 1442 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000); 1443 1444 /* disable LCD controller clock */ 1445 clk_disable(fbi->clk); 1446} 1447 1448/* 1449 * pxafb_handle_irq: Handle 'LCD DONE' interrupts. 1450 */ 1451static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) 1452{ 1453 struct pxafb_info *fbi = dev_id; 1454 unsigned int lccr0, lcsr; 1455 1456 lcsr = lcd_readl(fbi, LCSR); 1457 if (lcsr & LCSR_LDD) { 1458 lccr0 = lcd_readl(fbi, LCCR0); 1459 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); 1460 complete(&fbi->disable_done); 1461 } 1462 1463#ifdef CONFIG_FB_PXA_SMARTPANEL 1464 if (lcsr & LCSR_CMD_INT) 1465 complete(&fbi->command_done); 1466#endif 1467 lcd_writel(fbi, LCSR, lcsr); 1468 1469#ifdef CONFIG_FB_PXA_OVERLAY 1470 { 1471 unsigned int lcsr1 = lcd_readl(fbi, LCSR1); 1472 if (lcsr1 & LCSR1_BS(1)) 1473 complete(&fbi->overlay[0].branch_done); 1474 1475 if (lcsr1 & LCSR1_BS(2)) 1476 complete(&fbi->overlay[1].branch_done); 1477 1478 lcd_writel(fbi, LCSR1, lcsr1); 1479 } 1480#endif 1481 return IRQ_HANDLED; 1482} 1483 1484/* 1485 * This function must be called from task context only, since it will 1486 * sleep when disabling the LCD controller, or if we get two contending 1487 * processes trying to alter state. 1488 */ 1489static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) 1490{ 1491 u_int old_state; 1492 1493 mutex_lock(&fbi->ctrlr_lock); 1494 1495 old_state = fbi->state; 1496 1497 /* 1498 * Hack around fbcon initialisation. 1499 */ 1500 if (old_state == C_STARTUP && state == C_REENABLE) 1501 state = C_ENABLE; 1502 1503 switch (state) { 1504 case C_DISABLE_CLKCHANGE: 1505 /* 1506 * Disable controller for clock change. If the 1507 * controller is already disabled, then do nothing. 1508 */ 1509 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { 1510 fbi->state = state; 1511 /* TODO __pxafb_lcd_power(fbi, 0); */ 1512 pxafb_disable_controller(fbi); 1513 } 1514 break; 1515 1516 case C_DISABLE_PM: 1517 case C_DISABLE: 1518 /* 1519 * Disable controller 1520 */ 1521 if (old_state != C_DISABLE) { 1522 fbi->state = state; 1523 __pxafb_backlight_power(fbi, 0); 1524 __pxafb_lcd_power(fbi, 0); 1525 if (old_state != C_DISABLE_CLKCHANGE) 1526 pxafb_disable_controller(fbi); 1527 } 1528 break; 1529 1530 case C_ENABLE_CLKCHANGE: 1531 /* 1532 * Enable the controller after clock change. Only 1533 * do this if we were disabled for the clock change. 1534 */ 1535 if (old_state == C_DISABLE_CLKCHANGE) { 1536 fbi->state = C_ENABLE; 1537 pxafb_enable_controller(fbi); 1538 /* TODO __pxafb_lcd_power(fbi, 1); */ 1539 } 1540 break; 1541 1542 case C_REENABLE: 1543 /* 1544 * Re-enable the controller only if it was already 1545 * enabled. This is so we reprogram the control 1546 * registers. 1547 */ 1548 if (old_state == C_ENABLE) { 1549 __pxafb_lcd_power(fbi, 0); 1550 pxafb_disable_controller(fbi); 1551 pxafb_enable_controller(fbi); 1552 __pxafb_lcd_power(fbi, 1); 1553 } 1554 break; 1555 1556 case C_ENABLE_PM: 1557 /* 1558 * Re-enable the controller after PM. This is not 1559 * perfect - think about the case where we were doing 1560 * a clock change, and we suspended half-way through. 1561 */ 1562 if (old_state != C_DISABLE_PM) 1563 break; 1564 /* fall through */ 1565 1566 case C_ENABLE: 1567 /* 1568 * Power up the LCD screen, enable controller, and 1569 * turn on the backlight. 1570 */ 1571 if (old_state != C_ENABLE) { 1572 fbi->state = C_ENABLE; 1573 pxafb_enable_controller(fbi); 1574 __pxafb_lcd_power(fbi, 1); 1575 __pxafb_backlight_power(fbi, 1); 1576 } 1577 break; 1578 } 1579 mutex_unlock(&fbi->ctrlr_lock); 1580} 1581 1582/* 1583 * Our LCD controller task (which is called when we blank or unblank) 1584 * via keventd. 1585 */ 1586static void pxafb_task(struct work_struct *work) 1587{ 1588 struct pxafb_info *fbi = 1589 container_of(work, struct pxafb_info, task); 1590 u_int state = xchg(&fbi->task_state, -1); 1591 1592 set_ctrlr_state(fbi, state); 1593} 1594 1595#ifdef CONFIG_CPU_FREQ 1596/* 1597 * CPU clock speed change handler. We need to adjust the LCD timing 1598 * parameters when the CPU clock is adjusted by the power management 1599 * subsystem. 1600 * 1601 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() 1602 */ 1603static int 1604pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) 1605{ 1606 struct pxafb_info *fbi = TO_INF(nb, freq_transition); 1607 /* TODO struct cpufreq_freqs *f = data; */ 1608 u_int pcd; 1609 1610 switch (val) { 1611 case CPUFREQ_PRECHANGE: 1612 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); 1613 break; 1614 1615 case CPUFREQ_POSTCHANGE: 1616 pcd = get_pcd(fbi, fbi->fb.var.pixclock); 1617 set_hsync_time(fbi, pcd); 1618 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | 1619 LCCR3_PixClkDiv(pcd); 1620 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); 1621 break; 1622 } 1623 return 0; 1624} 1625 1626static int 1627pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) 1628{ 1629 struct pxafb_info *fbi = TO_INF(nb, freq_policy); 1630 struct fb_var_screeninfo *var = &fbi->fb.var; 1631 struct cpufreq_policy *policy = data; 1632 1633 switch (val) { 1634 case CPUFREQ_ADJUST: 1635 case CPUFREQ_INCOMPATIBLE: 1636 pr_debug("min dma period: %d ps, " 1637 "new clock %d kHz\n", pxafb_display_dma_period(var), 1638 policy->max); 1639 /* TODO: fill in min/max values */ 1640 break; 1641 } 1642 return 0; 1643} 1644#endif 1645 1646#ifdef CONFIG_PM 1647/* 1648 * Power management hooks. Note that we won't be called from IRQ context, 1649 * unlike the blank functions above, so we may sleep. 1650 */ 1651static int pxafb_suspend(struct device *dev) 1652{ 1653 struct pxafb_info *fbi = dev_get_drvdata(dev); 1654 1655 set_ctrlr_state(fbi, C_DISABLE_PM); 1656 return 0; 1657} 1658 1659static int pxafb_resume(struct device *dev) 1660{ 1661 struct pxafb_info *fbi = dev_get_drvdata(dev); 1662 1663 set_ctrlr_state(fbi, C_ENABLE_PM); 1664 return 0; 1665} 1666 1667static const struct dev_pm_ops pxafb_pm_ops = { 1668 .suspend = pxafb_suspend, 1669 .resume = pxafb_resume, 1670}; 1671#endif 1672 1673static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi) 1674{ 1675 int size = PAGE_ALIGN(fbi->video_mem_size); 1676 1677 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO); 1678 if (fbi->video_mem == NULL) 1679 return -ENOMEM; 1680 1681 fbi->video_mem_phys = virt_to_phys(fbi->video_mem); 1682 fbi->video_mem_size = size; 1683 1684 fbi->fb.fix.smem_start = fbi->video_mem_phys; 1685 fbi->fb.fix.smem_len = fbi->video_mem_size; 1686 fbi->fb.screen_base = fbi->video_mem; 1687 1688 return fbi->video_mem ? 0 : -ENOMEM; 1689} 1690 1691static void pxafb_decode_mach_info(struct pxafb_info *fbi, 1692 struct pxafb_mach_info *inf) 1693{ 1694 unsigned int lcd_conn = inf->lcd_conn; 1695 struct pxafb_mode_info *m; 1696 int i; 1697 1698 fbi->cmap_inverse = inf->cmap_inverse; 1699 fbi->cmap_static = inf->cmap_static; 1700 fbi->lccr4 = inf->lccr4; 1701 1702 switch (lcd_conn & LCD_TYPE_MASK) { 1703 case LCD_TYPE_MONO_STN: 1704 fbi->lccr0 = LCCR0_CMS; 1705 break; 1706 case LCD_TYPE_MONO_DSTN: 1707 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS; 1708 break; 1709 case LCD_TYPE_COLOR_STN: 1710 fbi->lccr0 = 0; 1711 break; 1712 case LCD_TYPE_COLOR_DSTN: 1713 fbi->lccr0 = LCCR0_SDS; 1714 break; 1715 case LCD_TYPE_COLOR_TFT: 1716 fbi->lccr0 = LCCR0_PAS; 1717 break; 1718 case LCD_TYPE_SMART_PANEL: 1719 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS; 1720 break; 1721 default: 1722 /* fall back to backward compatibility way */ 1723 fbi->lccr0 = inf->lccr0; 1724 fbi->lccr3 = inf->lccr3; 1725 goto decode_mode; 1726 } 1727 1728 if (lcd_conn == LCD_MONO_STN_8BPP) 1729 fbi->lccr0 |= LCCR0_DPD; 1730 1731 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0; 1732 1733 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff); 1734 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0; 1735 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; 1736 1737decode_mode: 1738 pxafb_setmode(&fbi->fb.var, &inf->modes[0]); 1739 1740 /* decide video memory size as follows: 1741 * 1. default to mode of maximum resolution 1742 * 2. allow platform to override 1743 * 3. allow module parameter to override 1744 */ 1745 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++) 1746 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size, 1747 m->xres * m->yres * m->bpp / 8); 1748 1749 if (inf->video_mem_size > fbi->video_mem_size) 1750 fbi->video_mem_size = inf->video_mem_size; 1751 1752 if (video_mem_size > fbi->video_mem_size) 1753 fbi->video_mem_size = video_mem_size; 1754} 1755 1756static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) 1757{ 1758 struct pxafb_info *fbi; 1759 void *addr; 1760 struct pxafb_mach_info *inf = dev->platform_data; 1761 1762 /* Alloc the pxafb_info and pseudo_palette in one step */ 1763 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); 1764 if (!fbi) 1765 return NULL; 1766 1767 memset(fbi, 0, sizeof(struct pxafb_info)); 1768 fbi->dev = dev; 1769 1770 fbi->clk = clk_get(dev, NULL); 1771 if (IS_ERR(fbi->clk)) { 1772 kfree(fbi); 1773 return NULL; 1774 } 1775 1776 strcpy(fbi->fb.fix.id, PXA_NAME); 1777 1778 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1779 fbi->fb.fix.type_aux = 0; 1780 fbi->fb.fix.xpanstep = 0; 1781 fbi->fb.fix.ypanstep = 1; 1782 fbi->fb.fix.ywrapstep = 0; 1783 fbi->fb.fix.accel = FB_ACCEL_NONE; 1784 1785 fbi->fb.var.nonstd = 0; 1786 fbi->fb.var.activate = FB_ACTIVATE_NOW; 1787 fbi->fb.var.height = -1; 1788 fbi->fb.var.width = -1; 1789 fbi->fb.var.accel_flags = FB_ACCELF_TEXT; 1790 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; 1791 1792 fbi->fb.fbops = &pxafb_ops; 1793 fbi->fb.flags = FBINFO_DEFAULT; 1794 fbi->fb.node = -1; 1795 1796 addr = fbi; 1797 addr = addr + sizeof(struct pxafb_info); 1798 fbi->fb.pseudo_palette = addr; 1799 1800 fbi->state = C_STARTUP; 1801 fbi->task_state = (u_char)-1; 1802 1803 pxafb_decode_mach_info(fbi, inf); 1804 1805 init_waitqueue_head(&fbi->ctrlr_wait); 1806 INIT_WORK(&fbi->task, pxafb_task); 1807 mutex_init(&fbi->ctrlr_lock); 1808 init_completion(&fbi->disable_done); 1809 1810 return fbi; 1811} 1812 1813#ifdef CONFIG_FB_PXA_PARAMETERS 1814static int __devinit parse_opt_mode(struct device *dev, const char *this_opt) 1815{ 1816 struct pxafb_mach_info *inf = dev->platform_data; 1817 1818 const char *name = this_opt+5; 1819 unsigned int namelen = strlen(name); 1820 int res_specified = 0, bpp_specified = 0; 1821 unsigned int xres = 0, yres = 0, bpp = 0; 1822 int yres_specified = 0; 1823 int i; 1824 for (i = namelen-1; i >= 0; i--) { 1825 switch (name[i]) { 1826 case '-': 1827 namelen = i; 1828 if (!bpp_specified && !yres_specified) { 1829 bpp = simple_strtoul(&name[i+1], NULL, 0); 1830 bpp_specified = 1; 1831 } else 1832 goto done; 1833 break; 1834 case 'x': 1835 if (!yres_specified) { 1836 yres = simple_strtoul(&name[i+1], NULL, 0); 1837 yres_specified = 1; 1838 } else 1839 goto done; 1840 break; 1841 case '0' ... '9': 1842 break; 1843 default: 1844 goto done; 1845 } 1846 } 1847 if (i < 0 && yres_specified) { 1848 xres = simple_strtoul(name, NULL, 0); 1849 res_specified = 1; 1850 } 1851done: 1852 if (res_specified) { 1853 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); 1854 inf->modes[0].xres = xres; inf->modes[0].yres = yres; 1855 } 1856 if (bpp_specified) 1857 switch (bpp) { 1858 case 1: 1859 case 2: 1860 case 4: 1861 case 8: 1862 case 16: 1863 inf->modes[0].bpp = bpp; 1864 dev_info(dev, "overriding bit depth: %d\n", bpp); 1865 break; 1866 default: 1867 dev_err(dev, "Depth %d is not valid\n", bpp); 1868 return -EINVAL; 1869 } 1870 return 0; 1871} 1872 1873static int __devinit parse_opt(struct device *dev, char *this_opt) 1874{ 1875 struct pxafb_mach_info *inf = dev->platform_data; 1876 struct pxafb_mode_info *mode = &inf->modes[0]; 1877 char s[64]; 1878 1879 s[0] = '\0'; 1880 1881 if (!strncmp(this_opt, "vmem:", 5)) { 1882 video_mem_size = memparse(this_opt + 5, NULL); 1883 } else if (!strncmp(this_opt, "mode:", 5)) { 1884 return parse_opt_mode(dev, this_opt); 1885 } else if (!strncmp(this_opt, "pixclock:", 9)) { 1886 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); 1887 sprintf(s, "pixclock: %ld\n", mode->pixclock); 1888 } else if (!strncmp(this_opt, "left:", 5)) { 1889 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0); 1890 sprintf(s, "left: %u\n", mode->left_margin); 1891 } else if (!strncmp(this_opt, "right:", 6)) { 1892 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0); 1893 sprintf(s, "right: %u\n", mode->right_margin); 1894 } else if (!strncmp(this_opt, "upper:", 6)) { 1895 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0); 1896 sprintf(s, "upper: %u\n", mode->upper_margin); 1897 } else if (!strncmp(this_opt, "lower:", 6)) { 1898 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0); 1899 sprintf(s, "lower: %u\n", mode->lower_margin); 1900 } else if (!strncmp(this_opt, "hsynclen:", 9)) { 1901 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0); 1902 sprintf(s, "hsynclen: %u\n", mode->hsync_len); 1903 } else if (!strncmp(this_opt, "vsynclen:", 9)) { 1904 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0); 1905 sprintf(s, "vsynclen: %u\n", mode->vsync_len); 1906 } else if (!strncmp(this_opt, "hsync:", 6)) { 1907 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1908 sprintf(s, "hsync: Active Low\n"); 1909 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT; 1910 } else { 1911 sprintf(s, "hsync: Active High\n"); 1912 mode->sync |= FB_SYNC_HOR_HIGH_ACT; 1913 } 1914 } else if (!strncmp(this_opt, "vsync:", 6)) { 1915 if (simple_strtoul(this_opt+6, NULL, 0) == 0) { 1916 sprintf(s, "vsync: Active Low\n"); 1917 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT; 1918 } else { 1919 sprintf(s, "vsync: Active High\n"); 1920 mode->sync |= FB_SYNC_VERT_HIGH_ACT; 1921 } 1922 } else if (!strncmp(this_opt, "dpc:", 4)) { 1923 if (simple_strtoul(this_opt+4, NULL, 0) == 0) { 1924 sprintf(s, "double pixel clock: false\n"); 1925 inf->lccr3 &= ~LCCR3_DPC; 1926 } else { 1927 sprintf(s, "double pixel clock: true\n"); 1928 inf->lccr3 |= LCCR3_DPC; 1929 } 1930 } else if (!strncmp(this_opt, "outputen:", 9)) { 1931 if (simple_strtoul(this_opt+9, NULL, 0) == 0) { 1932 sprintf(s, "output enable: active low\n"); 1933 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; 1934 } else { 1935 sprintf(s, "output enable: active high\n"); 1936 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; 1937 } 1938 } else if (!strncmp(this_opt, "pixclockpol:", 12)) { 1939 if (simple_strtoul(this_opt+12, NULL, 0) == 0) { 1940 sprintf(s, "pixel clock polarity: falling edge\n"); 1941 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; 1942 } else { 1943 sprintf(s, "pixel clock polarity: rising edge\n"); 1944 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; 1945 } 1946 } else if (!strncmp(this_opt, "color", 5)) { 1947 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; 1948 } else if (!strncmp(this_opt, "mono", 4)) { 1949 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; 1950 } else if (!strncmp(this_opt, "active", 6)) { 1951 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; 1952 } else if (!strncmp(this_opt, "passive", 7)) { 1953 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; 1954 } else if (!strncmp(this_opt, "single", 6)) { 1955 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; 1956 } else if (!strncmp(this_opt, "dual", 4)) { 1957 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; 1958 } else if (!strncmp(this_opt, "4pix", 4)) { 1959 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; 1960 } else if (!strncmp(this_opt, "8pix", 4)) { 1961 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; 1962 } else { 1963 dev_err(dev, "unknown option: %s\n", this_opt); 1964 return -EINVAL; 1965 } 1966 1967 if (s[0] != '\0') 1968 dev_info(dev, "override %s", s); 1969 1970 return 0; 1971} 1972 1973static int __devinit pxafb_parse_options(struct device *dev, char *options) 1974{ 1975 char *this_opt; 1976 int ret; 1977 1978 if (!options || !*options) 1979 return 0; 1980 1981 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); 1982 1983 /* could be made table driven or similar?... */ 1984 while ((this_opt = strsep(&options, ",")) != NULL) { 1985 ret = parse_opt(dev, this_opt); 1986 if (ret) 1987 return ret; 1988 } 1989 return 0; 1990} 1991 1992static char g_options[256] __devinitdata = ""; 1993 1994#ifndef MODULE 1995static int __init pxafb_setup_options(void) 1996{ 1997 char *options = NULL; 1998 1999 if (fb_get_options("pxafb", &options)) 2000 return -ENODEV; 2001 2002 if (options) 2003 strlcpy(g_options, options, sizeof(g_options)); 2004 2005 return 0; 2006} 2007#else 2008#define pxafb_setup_options() (0) 2009 2010module_param_string(options, g_options, sizeof(g_options), 0); 2011MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); 2012#endif 2013 2014#else 2015#define pxafb_parse_options(...) (0) 2016#define pxafb_setup_options() (0) 2017#endif 2018 2019#ifdef DEBUG_VAR 2020/* Check for various illegal bit-combinations. Currently only 2021 * a warning is given. */ 2022static void __devinit pxafb_check_options(struct device *dev, 2023 struct pxafb_mach_info *inf) 2024{ 2025 if (inf->lcd_conn) 2026 return; 2027 2028 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) 2029 dev_warn(dev, "machine LCCR0 setting contains " 2030 "illegal bits: %08x\n", 2031 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); 2032 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) 2033 dev_warn(dev, "machine LCCR3 setting contains " 2034 "illegal bits: %08x\n", 2035 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); 2036 if (inf->lccr0 & LCCR0_DPD && 2037 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || 2038 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || 2039 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) 2040 dev_warn(dev, "Double Pixel Data (DPD) mode is " 2041 "only valid in passive mono" 2042 " single panel mode\n"); 2043 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && 2044 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) 2045 dev_warn(dev, "Dual panel only valid in passive mode\n"); 2046 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && 2047 (inf->modes->upper_margin || inf->modes->lower_margin)) 2048 dev_warn(dev, "Upper and lower margins must be 0 in " 2049 "passive mode\n"); 2050} 2051#else 2052#define pxafb_check_options(...) do {} while (0) 2053#endif 2054 2055static int __devinit pxafb_probe(struct platform_device *dev) 2056{ 2057 struct pxafb_info *fbi; 2058 struct pxafb_mach_info *inf; 2059 struct resource *r; 2060 int irq, ret; 2061 2062 dev_dbg(&dev->dev, "pxafb_probe\n"); 2063 2064 inf = dev->dev.platform_data; 2065 ret = -ENOMEM; 2066 fbi = NULL; 2067 if (!inf) 2068 goto failed; 2069 2070 ret = pxafb_parse_options(&dev->dev, g_options); 2071 if (ret < 0) 2072 goto failed; 2073 2074 pxafb_check_options(&dev->dev, inf); 2075 2076 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n", 2077 inf->modes->xres, 2078 inf->modes->yres, 2079 inf->modes->bpp); 2080 if (inf->modes->xres == 0 || 2081 inf->modes->yres == 0 || 2082 inf->modes->bpp == 0) { 2083 dev_err(&dev->dev, "Invalid resolution or bit depth\n"); 2084 ret = -EINVAL; 2085 goto failed; 2086 } 2087 2088 fbi = pxafb_init_fbinfo(&dev->dev); 2089 if (!fbi) { 2090 /* only reason for pxafb_init_fbinfo to fail is kmalloc */ 2091 dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); 2092 ret = -ENOMEM; 2093 goto failed; 2094 } 2095 2096 if (cpu_is_pxa3xx() && inf->acceleration_enabled) 2097 fbi->fb.fix.accel = FB_ACCEL_PXA3XX; 2098 2099 fbi->backlight_power = inf->pxafb_backlight_power; 2100 fbi->lcd_power = inf->pxafb_lcd_power; 2101 2102 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 2103 if (r == NULL) { 2104 dev_err(&dev->dev, "no I/O memory resource defined\n"); 2105 ret = -ENODEV; 2106 goto failed_fbi; 2107 } 2108 2109 r = request_mem_region(r->start, resource_size(r), dev->name); 2110 if (r == NULL) { 2111 dev_err(&dev->dev, "failed to request I/O memory\n"); 2112 ret = -EBUSY; 2113 goto failed_fbi; 2114 } 2115 2116 fbi->mmio_base = ioremap(r->start, resource_size(r)); 2117 if (fbi->mmio_base == NULL) { 2118 dev_err(&dev->dev, "failed to map I/O memory\n"); 2119 ret = -EBUSY; 2120 goto failed_free_res; 2121 } 2122 2123 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); 2124 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size, 2125 &fbi->dma_buff_phys, GFP_KERNEL); 2126 if (fbi->dma_buff == NULL) { 2127 dev_err(&dev->dev, "failed to allocate memory for DMA\n"); 2128 ret = -ENOMEM; 2129 goto failed_free_io; 2130 } 2131 2132 ret = pxafb_init_video_memory(fbi); 2133 if (ret) { 2134 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); 2135 ret = -ENOMEM; 2136 goto failed_free_dma; 2137 } 2138 2139 irq = platform_get_irq(dev, 0); 2140 if (irq < 0) { 2141 dev_err(&dev->dev, "no IRQ defined\n"); 2142 ret = -ENODEV; 2143 goto failed_free_mem; 2144 } 2145 2146 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi); 2147 if (ret) { 2148 dev_err(&dev->dev, "request_irq failed: %d\n", ret); 2149 ret = -EBUSY; 2150 goto failed_free_mem; 2151 } 2152 2153 ret = pxafb_smart_init(fbi); 2154 if (ret) { 2155 dev_err(&dev->dev, "failed to initialize smartpanel\n"); 2156 goto failed_free_irq; 2157 } 2158 2159 /* 2160 * This makes sure that our colour bitfield 2161 * descriptors are correctly initialised. 2162 */ 2163 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb); 2164 if (ret) { 2165 dev_err(&dev->dev, "failed to get suitable mode\n"); 2166 goto failed_free_irq; 2167 } 2168 2169 ret = pxafb_set_par(&fbi->fb); 2170 if (ret) { 2171 dev_err(&dev->dev, "Failed to set parameters\n"); 2172 goto failed_free_irq; 2173 } 2174 2175 platform_set_drvdata(dev, fbi); 2176 2177 ret = register_framebuffer(&fbi->fb); 2178 if (ret < 0) { 2179 dev_err(&dev->dev, 2180 "Failed to register framebuffer device: %d\n", ret); 2181 goto failed_free_cmap; 2182 } 2183 2184 pxafb_overlay_init(fbi); 2185 2186#ifdef CONFIG_CPU_FREQ 2187 fbi->freq_transition.notifier_call = pxafb_freq_transition; 2188 fbi->freq_policy.notifier_call = pxafb_freq_policy; 2189 cpufreq_register_notifier(&fbi->freq_transition, 2190 CPUFREQ_TRANSITION_NOTIFIER); 2191 cpufreq_register_notifier(&fbi->freq_policy, 2192 CPUFREQ_POLICY_NOTIFIER); 2193#endif 2194 2195 /* 2196 * Ok, now enable the LCD controller 2197 */ 2198 set_ctrlr_state(fbi, C_ENABLE); 2199 2200 return 0; 2201 2202failed_free_cmap: 2203 if (fbi->fb.cmap.len) 2204 fb_dealloc_cmap(&fbi->fb.cmap); 2205failed_free_irq: 2206 free_irq(irq, fbi); 2207failed_free_mem: 2208 free_pages_exact(fbi->video_mem, fbi->video_mem_size); 2209failed_free_dma: 2210 dma_free_coherent(&dev->dev, fbi->dma_buff_size, 2211 fbi->dma_buff, fbi->dma_buff_phys); 2212failed_free_io: 2213 iounmap(fbi->mmio_base); 2214failed_free_res: 2215 release_mem_region(r->start, resource_size(r)); 2216failed_fbi: 2217 clk_put(fbi->clk); 2218 platform_set_drvdata(dev, NULL); 2219 kfree(fbi); 2220failed: 2221 return ret; 2222} 2223 2224static int __devexit pxafb_remove(struct platform_device *dev) 2225{ 2226 struct pxafb_info *fbi = platform_get_drvdata(dev); 2227 struct resource *r; 2228 int irq; 2229 struct fb_info *info; 2230 2231 if (!fbi) 2232 return 0; 2233 2234 info = &fbi->fb; 2235 2236 pxafb_overlay_exit(fbi); 2237 unregister_framebuffer(info); 2238 2239 pxafb_disable_controller(fbi); 2240 2241 if (fbi->fb.cmap.len) 2242 fb_dealloc_cmap(&fbi->fb.cmap); 2243 2244 irq = platform_get_irq(dev, 0); 2245 free_irq(irq, fbi); 2246 2247 free_pages_exact(fbi->video_mem, fbi->video_mem_size); 2248 2249 dma_free_writecombine(&dev->dev, fbi->dma_buff_size, 2250 fbi->dma_buff, fbi->dma_buff_phys); 2251 2252 iounmap(fbi->mmio_base); 2253 2254 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 2255 release_mem_region(r->start, resource_size(r)); 2256 2257 clk_put(fbi->clk); 2258 kfree(fbi); 2259 2260 return 0; 2261} 2262 2263static struct platform_driver pxafb_driver = { 2264 .probe = pxafb_probe, 2265 .remove = __devexit_p(pxafb_remove), 2266 .driver = { 2267 .owner = THIS_MODULE, 2268 .name = "pxa2xx-fb", 2269#ifdef CONFIG_PM 2270 .pm = &pxafb_pm_ops, 2271#endif 2272 }, 2273}; 2274 2275static int __init pxafb_init(void) 2276{ 2277 if (pxafb_setup_options()) 2278 return -EINVAL; 2279 2280 return platform_driver_register(&pxafb_driver); 2281} 2282 2283static void __exit pxafb_exit(void) 2284{ 2285 platform_driver_unregister(&pxafb_driver); 2286} 2287 2288module_init(pxafb_init); 2289module_exit(pxafb_exit); 2290 2291MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); 2292MODULE_LICENSE("GPL"); 2293