1/* drivers/video/msm_fb/mdp_hw.h 2 * 3 * Copyright (C) 2007 QUALCOMM Incorporated 4 * Copyright (C) 2007 Google Incorporated 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15#ifndef _MDP_HW_H_ 16#define _MDP_HW_H_ 17 18#include <mach/msm_iomap.h> 19#include <mach/msm_fb.h> 20 21struct mdp_info { 22 struct mdp_device mdp_dev; 23 char * __iomem base; 24 int irq; 25}; 26struct mdp_blit_req; 27struct mdp_device; 28int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req, 29 struct file *src_file, unsigned long src_start, 30 unsigned long src_len, struct file *dst_file, 31 unsigned long dst_start, unsigned long dst_len); 32#define mdp_writel(mdp, value, offset) writel(value, mdp->base + offset) 33#define mdp_readl(mdp, offset) readl(mdp->base + offset) 34 35#define MDP_SYNC_CONFIG_0 (0x00000) 36#define MDP_SYNC_CONFIG_1 (0x00004) 37#define MDP_SYNC_CONFIG_2 (0x00008) 38#define MDP_SYNC_STATUS_0 (0x0000c) 39#define MDP_SYNC_STATUS_1 (0x00010) 40#define MDP_SYNC_STATUS_2 (0x00014) 41#define MDP_SYNC_THRESH_0 (0x00018) 42#define MDP_SYNC_THRESH_1 (0x0001c) 43#define MDP_INTR_ENABLE (0x00020) 44#define MDP_INTR_STATUS (0x00024) 45#define MDP_INTR_CLEAR (0x00028) 46#define MDP_DISPLAY0_START (0x00030) 47#define MDP_DISPLAY1_START (0x00034) 48#define MDP_DISPLAY_STATUS (0x00038) 49#define MDP_EBI2_LCD0 (0x0003c) 50#define MDP_EBI2_LCD1 (0x00040) 51#define MDP_DISPLAY0_ADDR (0x00054) 52#define MDP_DISPLAY1_ADDR (0x00058) 53#define MDP_EBI2_PORTMAP_MODE (0x0005c) 54#define MDP_MODE (0x00060) 55#define MDP_TV_OUT_STATUS (0x00064) 56#define MDP_HW_VERSION (0x00070) 57#define MDP_SW_RESET (0x00074) 58#define MDP_AXI_ERROR_MASTER_STOP (0x00078) 59#define MDP_SEL_CLK_OR_HCLK_TEST_BUS (0x0007c) 60#define MDP_PRIMARY_VSYNC_OUT_CTRL (0x00080) 61#define MDP_SECONDARY_VSYNC_OUT_CTRL (0x00084) 62#define MDP_EXTERNAL_VSYNC_OUT_CTRL (0x00088) 63#define MDP_VSYNC_CTRL (0x0008c) 64#define MDP_CGC_EN (0x00100) 65#define MDP_CMD_STATUS (0x10008) 66#define MDP_PROFILE_EN (0x10010) 67#define MDP_PROFILE_COUNT (0x10014) 68#define MDP_DMA_START (0x10044) 69#define MDP_FULL_BYPASS_WORD0 (0x10100) 70#define MDP_FULL_BYPASS_WORD1 (0x10104) 71#define MDP_COMMAND_CONFIG (0x10104) 72#define MDP_FULL_BYPASS_WORD2 (0x10108) 73#define MDP_FULL_BYPASS_WORD3 (0x1010c) 74#define MDP_FULL_BYPASS_WORD4 (0x10110) 75#define MDP_FULL_BYPASS_WORD6 (0x10118) 76#define MDP_FULL_BYPASS_WORD7 (0x1011c) 77#define MDP_FULL_BYPASS_WORD8 (0x10120) 78#define MDP_FULL_BYPASS_WORD9 (0x10124) 79#define MDP_PPP_SOURCE_CONFIG (0x10124) 80#define MDP_FULL_BYPASS_WORD10 (0x10128) 81#define MDP_FULL_BYPASS_WORD11 (0x1012c) 82#define MDP_FULL_BYPASS_WORD12 (0x10130) 83#define MDP_FULL_BYPASS_WORD13 (0x10134) 84#define MDP_FULL_BYPASS_WORD14 (0x10138) 85#define MDP_PPP_OPERATION_CONFIG (0x10138) 86#define MDP_FULL_BYPASS_WORD15 (0x1013c) 87#define MDP_FULL_BYPASS_WORD16 (0x10140) 88#define MDP_FULL_BYPASS_WORD17 (0x10144) 89#define MDP_FULL_BYPASS_WORD18 (0x10148) 90#define MDP_FULL_BYPASS_WORD19 (0x1014c) 91#define MDP_FULL_BYPASS_WORD20 (0x10150) 92#define MDP_PPP_DESTINATION_CONFIG (0x10150) 93#define MDP_FULL_BYPASS_WORD21 (0x10154) 94#define MDP_FULL_BYPASS_WORD22 (0x10158) 95#define MDP_FULL_BYPASS_WORD23 (0x1015c) 96#define MDP_FULL_BYPASS_WORD24 (0x10160) 97#define MDP_FULL_BYPASS_WORD25 (0x10164) 98#define MDP_FULL_BYPASS_WORD26 (0x10168) 99#define MDP_FULL_BYPASS_WORD27 (0x1016c) 100#define MDP_FULL_BYPASS_WORD29 (0x10174) 101#define MDP_FULL_BYPASS_WORD30 (0x10178) 102#define MDP_FULL_BYPASS_WORD31 (0x1017c) 103#define MDP_FULL_BYPASS_WORD32 (0x10180) 104#define MDP_DMA_CONFIG (0x10180) 105#define MDP_FULL_BYPASS_WORD33 (0x10184) 106#define MDP_FULL_BYPASS_WORD34 (0x10188) 107#define MDP_FULL_BYPASS_WORD35 (0x1018c) 108#define MDP_FULL_BYPASS_WORD37 (0x10194) 109#define MDP_FULL_BYPASS_WORD39 (0x1019c) 110#define MDP_FULL_BYPASS_WORD40 (0x101a0) 111#define MDP_FULL_BYPASS_WORD41 (0x101a4) 112#define MDP_FULL_BYPASS_WORD43 (0x101ac) 113#define MDP_FULL_BYPASS_WORD46 (0x101b8) 114#define MDP_FULL_BYPASS_WORD47 (0x101bc) 115#define MDP_FULL_BYPASS_WORD48 (0x101c0) 116#define MDP_FULL_BYPASS_WORD49 (0x101c4) 117#define MDP_FULL_BYPASS_WORD50 (0x101c8) 118#define MDP_FULL_BYPASS_WORD51 (0x101cc) 119#define MDP_FULL_BYPASS_WORD52 (0x101d0) 120#define MDP_FULL_BYPASS_WORD53 (0x101d4) 121#define MDP_FULL_BYPASS_WORD54 (0x101d8) 122#define MDP_FULL_BYPASS_WORD55 (0x101dc) 123#define MDP_FULL_BYPASS_WORD56 (0x101e0) 124#define MDP_FULL_BYPASS_WORD57 (0x101e4) 125#define MDP_FULL_BYPASS_WORD58 (0x101e8) 126#define MDP_FULL_BYPASS_WORD59 (0x101ec) 127#define MDP_FULL_BYPASS_WORD60 (0x101f0) 128#define MDP_VSYNC_THRESHOLD (0x101f0) 129#define MDP_FULL_BYPASS_WORD61 (0x101f4) 130#define MDP_FULL_BYPASS_WORD62 (0x101f8) 131#define MDP_FULL_BYPASS_WORD63 (0x101fc) 132#define MDP_TFETCH_TEST_MODE (0x20004) 133#define MDP_TFETCH_STATUS (0x20008) 134#define MDP_TFETCH_TILE_COUNT (0x20010) 135#define MDP_TFETCH_FETCH_COUNT (0x20014) 136#define MDP_TFETCH_CONSTANT_COLOR (0x20040) 137#define MDP_CSC_BYPASS (0x40004) 138#define MDP_SCALE_COEFF_LSB (0x5fffc) 139#define MDP_TV_OUT_CTL (0xc0000) 140#define MDP_TV_OUT_FIR_COEFF (0xc0004) 141#define MDP_TV_OUT_BUF_ADDR (0xc0008) 142#define MDP_TV_OUT_CC_DATA (0xc000c) 143#define MDP_TV_OUT_SOBEL (0xc0010) 144#define MDP_TV_OUT_Y_CLAMP (0xc0018) 145#define MDP_TV_OUT_CB_CLAMP (0xc001c) 146#define MDP_TV_OUT_CR_CLAMP (0xc0020) 147#define MDP_TEST_MODE_CLK (0xd0000) 148#define MDP_TEST_MISR_RESET_CLK (0xd0004) 149#define MDP_TEST_EXPORT_MISR_CLK (0xd0008) 150#define MDP_TEST_MISR_CURR_VAL_CLK (0xd000c) 151#define MDP_TEST_MODE_HCLK (0xd0100) 152#define MDP_TEST_MISR_RESET_HCLK (0xd0104) 153#define MDP_TEST_EXPORT_MISR_HCLK (0xd0108) 154#define MDP_TEST_MISR_CURR_VAL_HCLK (0xd010c) 155#define MDP_TEST_MODE_DCLK (0xd0200) 156#define MDP_TEST_MISR_RESET_DCLK (0xd0204) 157#define MDP_TEST_EXPORT_MISR_DCLK (0xd0208) 158#define MDP_TEST_MISR_CURR_VAL_DCLK (0xd020c) 159#define MDP_TEST_CAPTURED_DCLK (0xd0210) 160#define MDP_TEST_MISR_CAPT_VAL_DCLK (0xd0214) 161#define MDP_LCDC_CTL (0xe0000) 162#define MDP_LCDC_HSYNC_CTL (0xe0004) 163#define MDP_LCDC_VSYNC_CTL (0xe0008) 164#define MDP_LCDC_ACTIVE_HCTL (0xe000c) 165#define MDP_LCDC_ACTIVE_VCTL (0xe0010) 166#define MDP_LCDC_BORDER_CLR (0xe0014) 167#define MDP_LCDC_H_BLANK (0xe0018) 168#define MDP_LCDC_V_BLANK (0xe001c) 169#define MDP_LCDC_UNDERFLOW_CLR (0xe0020) 170#define MDP_LCDC_HSYNC_SKEW (0xe0024) 171#define MDP_LCDC_TEST_CTL (0xe0028) 172#define MDP_LCDC_LINE_IRQ (0xe002c) 173#define MDP_LCDC_CTL_POLARITY (0xe0030) 174#define MDP_LCDC_DMA_CONFIG (0xe1000) 175#define MDP_LCDC_DMA_SIZE (0xe1004) 176#define MDP_LCDC_DMA_IBUF_ADDR (0xe1008) 177#define MDP_LCDC_DMA_IBUF_Y_STRIDE (0xe100c) 178 179 180#define MDP_DMA2_TERM 0x1 181#define MDP_DMA3_TERM 0x2 182#define MDP_PPP_TERM 0x3 183 184/* MDP_INTR_ENABLE */ 185#define DL0_ROI_DONE (1<<0) 186#define DL1_ROI_DONE (1<<1) 187#define DL0_DMA2_TERM_DONE (1<<2) 188#define DL1_DMA2_TERM_DONE (1<<3) 189#define DL0_PPP_TERM_DONE (1<<4) 190#define DL1_PPP_TERM_DONE (1<<5) 191#define TV_OUT_DMA3_DONE (1<<6) 192#define TV_ENC_UNDERRUN (1<<7) 193#define DL0_FETCH_DONE (1<<11) 194#define DL1_FETCH_DONE (1<<12) 195 196#define MDP_PPP_BUSY_STATUS (DL0_ROI_DONE| \ 197 DL1_ROI_DONE| \ 198 DL0_PPP_TERM_DONE| \ 199 DL1_PPP_TERM_DONE) 200 201#define MDP_ANY_INTR_MASK (DL0_ROI_DONE| \ 202 DL1_ROI_DONE| \ 203 DL0_DMA2_TERM_DONE| \ 204 DL1_DMA2_TERM_DONE| \ 205 DL0_PPP_TERM_DONE| \ 206 DL1_PPP_TERM_DONE| \ 207 DL0_FETCH_DONE| \ 208 DL1_FETCH_DONE| \ 209 TV_ENC_UNDERRUN) 210 211#define MDP_TOP_LUMA 16 212#define MDP_TOP_CHROMA 0 213#define MDP_BOTTOM_LUMA 19 214#define MDP_BOTTOM_CHROMA 3 215#define MDP_LEFT_LUMA 22 216#define MDP_LEFT_CHROMA 6 217#define MDP_RIGHT_LUMA 25 218#define MDP_RIGHT_CHROMA 9 219 220#define CLR_G 0x0 221#define CLR_B 0x1 222#define CLR_R 0x2 223#define CLR_ALPHA 0x3 224 225#define CLR_Y CLR_G 226#define CLR_CB CLR_B 227#define CLR_CR CLR_R 228 229/* from lsb to msb */ 230#define MDP_GET_PACK_PATTERN(a, x, y, z, bit) \ 231 (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z)) 232 233/* MDP_SYNC_CONFIG_0/1/2 */ 234#define MDP_SYNCFG_HGT_LOC 22 235#define MDP_SYNCFG_VSYNC_EXT_EN (1<<21) 236#define MDP_SYNCFG_VSYNC_INT_EN (1<<20) 237 238/* MDP_SYNC_THRESH_0 */ 239#define MDP_PRIM_BELOW_LOC 0 240#define MDP_PRIM_ABOVE_LOC 8 241 242/* MDP_{PRIMARY,SECONDARY,EXTERNAL}_VSYNC_OUT_CRL */ 243#define VSYNC_PULSE_EN (1<<31) 244#define VSYNC_PULSE_INV (1<<30) 245 246/* MDP_VSYNC_CTRL */ 247#define DISP0_VSYNC_MAP_VSYNC0 0 248#define DISP0_VSYNC_MAP_VSYNC1 (1<<0) 249#define DISP0_VSYNC_MAP_VSYNC2 ((1<<0)|(1<<1)) 250 251#define DISP1_VSYNC_MAP_VSYNC0 0 252#define DISP1_VSYNC_MAP_VSYNC1 (1<<2) 253#define DISP1_VSYNC_MAP_VSYNC2 ((1<<2)|(1<<3)) 254 255#define PRIMARY_LCD_SYNC_EN (1<<4) 256#define PRIMARY_LCD_SYNC_DISABLE 0 257 258#define SECONDARY_LCD_SYNC_EN (1<<5) 259#define SECONDARY_LCD_SYNC_DISABLE 0 260 261#define EXTERNAL_LCD_SYNC_EN (1<<6) 262#define EXTERNAL_LCD_SYNC_DISABLE 0 263 264/* MDP_VSYNC_THRESHOLD / MDP_FULL_BYPASS_WORD60 */ 265#define VSYNC_THRESHOLD_ABOVE_LOC 0 266#define VSYNC_THRESHOLD_BELOW_LOC 16 267#define VSYNC_ANTI_TEAR_EN (1<<31) 268 269/* MDP_COMMAND_CONFIG / MDP_FULL_BYPASS_WORD1 */ 270#define MDP_CMD_DBGBUS_EN (1<<0) 271 272/* MDP_PPP_SOURCE_CONFIG / MDP_FULL_BYPASS_WORD9&53 */ 273#define PPP_SRC_C0G_8BIT ((1<<1)|(1<<0)) 274#define PPP_SRC_C1B_8BIT ((1<<3)|(1<<2)) 275#define PPP_SRC_C2R_8BIT ((1<<5)|(1<<4)) 276#define PPP_SRC_C3A_8BIT ((1<<7)|(1<<6)) 277 278#define PPP_SRC_C0G_6BIT (1<<1) 279#define PPP_SRC_C1B_6BIT (1<<3) 280#define PPP_SRC_C2R_6BIT (1<<5) 281 282#define PPP_SRC_C0G_5BIT (1<<0) 283#define PPP_SRC_C1B_5BIT (1<<2) 284#define PPP_SRC_C2R_5BIT (1<<4) 285 286#define PPP_SRC_C3ALPHA_EN (1<<8) 287 288#define PPP_SRC_BPP_1BYTES 0 289#define PPP_SRC_BPP_2BYTES (1<<9) 290#define PPP_SRC_BPP_3BYTES (1<<10) 291#define PPP_SRC_BPP_4BYTES ((1<<10)|(1<<9)) 292 293#define PPP_SRC_BPP_ROI_ODD_X (1<<11) 294#define PPP_SRC_BPP_ROI_ODD_Y (1<<12) 295#define PPP_SRC_INTERLVD_2COMPONENTS (1<<13) 296#define PPP_SRC_INTERLVD_3COMPONENTS (1<<14) 297#define PPP_SRC_INTERLVD_4COMPONENTS ((1<<14)|(1<<13)) 298 299 300/* RGB666 unpack format 301** TIGHT means R6+G6+B6 together 302** LOOSE means R6+2 +G6+2+ B6+2 (with MSB) 303** or 2+R6 +2+G6 +2+B6 (with LSB) 304*/ 305#define PPP_SRC_PACK_TIGHT (1<<17) 306#define PPP_SRC_PACK_LOOSE 0 307#define PPP_SRC_PACK_ALIGN_LSB 0 308#define PPP_SRC_PACK_ALIGN_MSB (1<<18) 309 310#define PPP_SRC_PLANE_INTERLVD 0 311#define PPP_SRC_PLANE_PSEUDOPLNR (1<<20) 312 313#define PPP_SRC_WMV9_MODE (1<<21) 314 315/* MDP_PPP_OPERATION_CONFIG / MDP_FULL_BYPASS_WORD14 */ 316#define PPP_OP_SCALE_X_ON (1<<0) 317#define PPP_OP_SCALE_Y_ON (1<<1) 318 319#define PPP_OP_CONVERT_RGB2YCBCR 0 320#define PPP_OP_CONVERT_YCBCR2RGB (1<<2) 321#define PPP_OP_CONVERT_ON (1<<3) 322 323#define PPP_OP_CONVERT_MATRIX_PRIMARY 0 324#define PPP_OP_CONVERT_MATRIX_SECONDARY (1<<4) 325 326#define PPP_OP_LUT_C0_ON (1<<5) 327#define PPP_OP_LUT_C1_ON (1<<6) 328#define PPP_OP_LUT_C2_ON (1<<7) 329 330/* rotate or blend enable */ 331#define PPP_OP_ROT_ON (1<<8) 332 333#define PPP_OP_ROT_90 (1<<9) 334#define PPP_OP_FLIP_LR (1<<10) 335#define PPP_OP_FLIP_UD (1<<11) 336 337#define PPP_OP_BLEND_ON (1<<12) 338 339#define PPP_OP_BLEND_SRCPIXEL_ALPHA 0 340#define PPP_OP_BLEND_DSTPIXEL_ALPHA (1<<13) 341#define PPP_OP_BLEND_CONSTANT_ALPHA (1<<14) 342#define PPP_OP_BLEND_SRCPIXEL_TRANSP ((1<<13)|(1<<14)) 343 344#define PPP_OP_BLEND_ALPHA_BLEND_NORMAL 0 345#define PPP_OP_BLEND_ALPHA_BLEND_REVERSE (1<<15) 346 347#define PPP_OP_DITHER_EN (1<<16) 348 349#define PPP_OP_COLOR_SPACE_RGB 0 350#define PPP_OP_COLOR_SPACE_YCBCR (1<<17) 351 352#define PPP_OP_SRC_CHROMA_RGB 0 353#define PPP_OP_SRC_CHROMA_H2V1 (1<<18) 354#define PPP_OP_SRC_CHROMA_H1V2 (1<<19) 355#define PPP_OP_SRC_CHROMA_420 ((1<<18)|(1<<19)) 356#define PPP_OP_SRC_CHROMA_COSITE 0 357#define PPP_OP_SRC_CHROMA_OFFSITE (1<<20) 358 359#define PPP_OP_DST_CHROMA_RGB 0 360#define PPP_OP_DST_CHROMA_H2V1 (1<<21) 361#define PPP_OP_DST_CHROMA_H1V2 (1<<22) 362#define PPP_OP_DST_CHROMA_420 ((1<<21)|(1<<22)) 363#define PPP_OP_DST_CHROMA_COSITE 0 364#define PPP_OP_DST_CHROMA_OFFSITE (1<<23) 365 366#define PPP_BLEND_ALPHA_TRANSP (1<<24) 367 368#define PPP_OP_BG_CHROMA_RGB 0 369#define PPP_OP_BG_CHROMA_H2V1 (1<<25) 370#define PPP_OP_BG_CHROMA_H1V2 (1<<26) 371#define PPP_OP_BG_CHROMA_420 ((1<<25)|(1<<26)) 372#define PPP_OP_BG_CHROMA_SITE_COSITE 0 373#define PPP_OP_BG_CHROMA_SITE_OFFSITE (1<<27) 374 375/* MDP_PPP_DESTINATION_CONFIG / MDP_FULL_BYPASS_WORD20 */ 376#define PPP_DST_C0G_8BIT ((1<<0)|(1<<1)) 377#define PPP_DST_C1B_8BIT ((1<<3)|(1<<2)) 378#define PPP_DST_C2R_8BIT ((1<<5)|(1<<4)) 379#define PPP_DST_C3A_8BIT ((1<<7)|(1<<6)) 380 381#define PPP_DST_C0G_6BIT (1<<1) 382#define PPP_DST_C1B_6BIT (1<<3) 383#define PPP_DST_C2R_6BIT (1<<5) 384 385#define PPP_DST_C0G_5BIT (1<<0) 386#define PPP_DST_C1B_5BIT (1<<2) 387#define PPP_DST_C2R_5BIT (1<<4) 388 389#define PPP_DST_C3A_8BIT ((1<<7)|(1<<6)) 390#define PPP_DST_C3ALPHA_EN (1<<8) 391 392#define PPP_DST_INTERLVD_2COMPONENTS (1<<9) 393#define PPP_DST_INTERLVD_3COMPONENTS (1<<10) 394#define PPP_DST_INTERLVD_4COMPONENTS ((1<<10)|(1<<9)) 395#define PPP_DST_INTERLVD_6COMPONENTS ((1<<11)|(1<<9)) 396 397#define PPP_DST_PACK_LOOSE 0 398#define PPP_DST_PACK_TIGHT (1<<13) 399#define PPP_DST_PACK_ALIGN_LSB 0 400#define PPP_DST_PACK_ALIGN_MSB (1<<14) 401 402#define PPP_DST_OUT_SEL_AXI 0 403#define PPP_DST_OUT_SEL_MDDI (1<<15) 404 405#define PPP_DST_BPP_2BYTES (1<<16) 406#define PPP_DST_BPP_3BYTES (1<<17) 407#define PPP_DST_BPP_4BYTES ((1<<17)|(1<<16)) 408 409#define PPP_DST_PLANE_INTERLVD 0 410#define PPP_DST_PLANE_PLANAR (1<<18) 411#define PPP_DST_PLANE_PSEUDOPLNR (1<<19) 412 413#define PPP_DST_TO_TV (1<<20) 414 415#define PPP_DST_MDDI_PRIMARY 0 416#define PPP_DST_MDDI_SECONDARY (1<<21) 417#define PPP_DST_MDDI_EXTERNAL (1<<22) 418 419/* image configurations by image type */ 420#define PPP_CFG_MDP_RGB_565(dir) (PPP_##dir##_C2R_5BIT | \ 421 PPP_##dir##_C0G_6BIT | \ 422 PPP_##dir##_C1B_5BIT | \ 423 PPP_##dir##_BPP_2BYTES | \ 424 PPP_##dir##_INTERLVD_3COMPONENTS | \ 425 PPP_##dir##_PACK_TIGHT | \ 426 PPP_##dir##_PACK_ALIGN_LSB | \ 427 PPP_##dir##_PLANE_INTERLVD) 428 429#define PPP_CFG_MDP_RGB_888(dir) (PPP_##dir##_C2R_8BIT | \ 430 PPP_##dir##_C0G_8BIT | \ 431 PPP_##dir##_C1B_8BIT | \ 432 PPP_##dir##_BPP_3BYTES | \ 433 PPP_##dir##_INTERLVD_3COMPONENTS | \ 434 PPP_##dir##_PACK_TIGHT | \ 435 PPP_##dir##_PACK_ALIGN_LSB | \ 436 PPP_##dir##_PLANE_INTERLVD) 437 438#define PPP_CFG_MDP_ARGB_8888(dir) (PPP_##dir##_C2R_8BIT | \ 439 PPP_##dir##_C0G_8BIT | \ 440 PPP_##dir##_C1B_8BIT | \ 441 PPP_##dir##_C3A_8BIT | \ 442 PPP_##dir##_C3ALPHA_EN | \ 443 PPP_##dir##_BPP_4BYTES | \ 444 PPP_##dir##_INTERLVD_4COMPONENTS | \ 445 PPP_##dir##_PACK_TIGHT | \ 446 PPP_##dir##_PACK_ALIGN_LSB | \ 447 PPP_##dir##_PLANE_INTERLVD) 448 449#define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) 450#define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) 451#define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir) 452 453#define PPP_CFG_MDP_Y_CBCR_H2V2(dir) (PPP_##dir##_C2R_8BIT | \ 454 PPP_##dir##_C0G_8BIT | \ 455 PPP_##dir##_C1B_8BIT | \ 456 PPP_##dir##_C3A_8BIT | \ 457 PPP_##dir##_BPP_2BYTES | \ 458 PPP_##dir##_INTERLVD_2COMPONENTS | \ 459 PPP_##dir##_PACK_TIGHT | \ 460 PPP_##dir##_PACK_ALIGN_LSB | \ 461 PPP_##dir##_PLANE_PSEUDOPLNR) 462 463#define PPP_CFG_MDP_Y_CRCB_H2V2(dir) PPP_CFG_MDP_Y_CBCR_H2V2(dir) 464 465#define PPP_CFG_MDP_YCRYCB_H2V1(dir) (PPP_##dir##_C2R_8BIT | \ 466 PPP_##dir##_C0G_8BIT | \ 467 PPP_##dir##_C1B_8BIT | \ 468 PPP_##dir##_C3A_8BIT | \ 469 PPP_##dir##_BPP_2BYTES | \ 470 PPP_##dir##_INTERLVD_4COMPONENTS | \ 471 PPP_##dir##_PACK_TIGHT | \ 472 PPP_##dir##_PACK_ALIGN_LSB |\ 473 PPP_##dir##_PLANE_INTERLVD) 474 475#define PPP_CFG_MDP_Y_CBCR_H2V1(dir) (PPP_##dir##_C2R_8BIT | \ 476 PPP_##dir##_C0G_8BIT | \ 477 PPP_##dir##_C1B_8BIT | \ 478 PPP_##dir##_C3A_8BIT | \ 479 PPP_##dir##_BPP_2BYTES | \ 480 PPP_##dir##_INTERLVD_2COMPONENTS | \ 481 PPP_##dir##_PACK_TIGHT | \ 482 PPP_##dir##_PACK_ALIGN_LSB | \ 483 PPP_##dir##_PLANE_PSEUDOPLNR) 484 485#define PPP_CFG_MDP_Y_CRCB_H2V1(dir) PPP_CFG_MDP_Y_CBCR_H2V1(dir) 486 487#define PPP_PACK_PATTERN_MDP_RGB_565 \ 488 MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8) 489#define PPP_PACK_PATTERN_MDP_RGB_888 PPP_PACK_PATTERN_MDP_RGB_565 490#define PPP_PACK_PATTERN_MDP_XRGB_8888 \ 491 MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8) 492#define PPP_PACK_PATTERN_MDP_ARGB_8888 PPP_PACK_PATTERN_MDP_XRGB_8888 493#define PPP_PACK_PATTERN_MDP_RGBA_8888 \ 494 MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8) 495#define PPP_PACK_PATTERN_MDP_BGRA_8888 \ 496 MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8) 497#define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 \ 498 MDP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8) 499#define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V2 PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 500#define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 \ 501 MDP_GET_PACK_PATTERN(0, 0, CLR_CR, CLR_CB, 8) 502#define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V2 PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 503#define PPP_PACK_PATTERN_MDP_YCRYCB_H2V1 \ 504 MDP_GET_PACK_PATTERN(CLR_Y, CLR_R, CLR_Y, CLR_B, 8) 505 506#define PPP_CHROMA_SAMP_MDP_RGB_565(dir) PPP_OP_##dir##_CHROMA_RGB 507#define PPP_CHROMA_SAMP_MDP_RGB_888(dir) PPP_OP_##dir##_CHROMA_RGB 508#define PPP_CHROMA_SAMP_MDP_XRGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB 509#define PPP_CHROMA_SAMP_MDP_ARGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB 510#define PPP_CHROMA_SAMP_MDP_RGBA_8888(dir) PPP_OP_##dir##_CHROMA_RGB 511#define PPP_CHROMA_SAMP_MDP_BGRA_8888(dir) PPP_OP_##dir##_CHROMA_RGB 512#define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 513#define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V2(dir) PPP_OP_##dir##_CHROMA_420 514#define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 515#define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V2(dir) PPP_OP_##dir##_CHROMA_420 516#define PPP_CHROMA_SAMP_MDP_YCRYCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1 517 518/* Helpful array generation macros */ 519#define PPP_ARRAY0(name) \ 520 [MDP_RGB_565] = PPP_##name##_MDP_RGB_565,\ 521 [MDP_RGB_888] = PPP_##name##_MDP_RGB_888,\ 522 [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888,\ 523 [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888,\ 524 [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888,\ 525 [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888,\ 526 [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1,\ 527 [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2,\ 528 [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1,\ 529 [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2,\ 530 [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1 531 532#define PPP_ARRAY1(name, dir) \ 533 [MDP_RGB_565] = PPP_##name##_MDP_RGB_565(dir),\ 534 [MDP_RGB_888] = PPP_##name##_MDP_RGB_888(dir),\ 535 [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888(dir),\ 536 [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888(dir),\ 537 [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888(dir),\ 538 [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888(dir),\ 539 [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1(dir),\ 540 [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2(dir),\ 541 [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1(dir),\ 542 [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2(dir),\ 543 [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1(dir) 544 545#define IS_YCRCB(img) ((img == MDP_Y_CRCB_H2V2) | (img == MDP_Y_CBCR_H2V2) | \ 546 (img == MDP_Y_CRCB_H2V1) | (img == MDP_Y_CBCR_H2V1) | \ 547 (img == MDP_YCRYCB_H2V1)) 548#define IS_RGB(img) ((img == MDP_RGB_565) | (img == MDP_RGB_888) | \ 549 (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ 550 (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888)) 551#define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \ 552 (img == MDP_BGRA_8888)) 553 554#define IS_PSEUDOPLNR(img) ((img == MDP_Y_CRCB_H2V2) | \ 555 (img == MDP_Y_CBCR_H2V2) | \ 556 (img == MDP_Y_CRCB_H2V1) | \ 557 (img == MDP_Y_CBCR_H2V1)) 558 559/* Mappings from addr to purpose */ 560#define PPP_ADDR_SRC_ROI MDP_FULL_BYPASS_WORD2 561#define PPP_ADDR_SRC0 MDP_FULL_BYPASS_WORD3 562#define PPP_ADDR_SRC1 MDP_FULL_BYPASS_WORD4 563#define PPP_ADDR_SRC_YSTRIDE MDP_FULL_BYPASS_WORD7 564#define PPP_ADDR_SRC_CFG MDP_FULL_BYPASS_WORD9 565#define PPP_ADDR_SRC_PACK_PATTERN MDP_FULL_BYPASS_WORD10 566#define PPP_ADDR_OPERATION MDP_FULL_BYPASS_WORD14 567#define PPP_ADDR_PHASEX_INIT MDP_FULL_BYPASS_WORD15 568#define PPP_ADDR_PHASEY_INIT MDP_FULL_BYPASS_WORD16 569#define PPP_ADDR_PHASEX_STEP MDP_FULL_BYPASS_WORD17 570#define PPP_ADDR_PHASEY_STEP MDP_FULL_BYPASS_WORD18 571#define PPP_ADDR_ALPHA_TRANSP MDP_FULL_BYPASS_WORD19 572#define PPP_ADDR_DST_CFG MDP_FULL_BYPASS_WORD20 573#define PPP_ADDR_DST_PACK_PATTERN MDP_FULL_BYPASS_WORD21 574#define PPP_ADDR_DST_ROI MDP_FULL_BYPASS_WORD25 575#define PPP_ADDR_DST0 MDP_FULL_BYPASS_WORD26 576#define PPP_ADDR_DST1 MDP_FULL_BYPASS_WORD27 577#define PPP_ADDR_DST_YSTRIDE MDP_FULL_BYPASS_WORD30 578#define PPP_ADDR_EDGE MDP_FULL_BYPASS_WORD46 579#define PPP_ADDR_BG0 MDP_FULL_BYPASS_WORD48 580#define PPP_ADDR_BG1 MDP_FULL_BYPASS_WORD49 581#define PPP_ADDR_BG_YSTRIDE MDP_FULL_BYPASS_WORD51 582#define PPP_ADDR_BG_CFG MDP_FULL_BYPASS_WORD53 583#define PPP_ADDR_BG_PACK_PATTERN MDP_FULL_BYPASS_WORD54 584 585/* MDP_DMA_CONFIG / MDP_FULL_BYPASS_WORD32 */ 586#define DMA_DSTC0G_6BITS (1<<1) 587#define DMA_DSTC1B_6BITS (1<<3) 588#define DMA_DSTC2R_6BITS (1<<5) 589#define DMA_DSTC0G_5BITS (1<<0) 590#define DMA_DSTC1B_5BITS (1<<2) 591#define DMA_DSTC2R_5BITS (1<<4) 592 593#define DMA_PACK_TIGHT (1<<6) 594#define DMA_PACK_LOOSE 0 595#define DMA_PACK_ALIGN_LSB 0 596#define DMA_PACK_ALIGN_MSB (1<<7) 597#define DMA_PACK_PATTERN_RGB \ 598 (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8) 599 600#define DMA_OUT_SEL_AHB 0 601#define DMA_OUT_SEL_MDDI (1<<14) 602#define DMA_AHBM_LCD_SEL_PRIMARY 0 603#define DMA_AHBM_LCD_SEL_SECONDARY (1<<15) 604#define DMA_IBUF_C3ALPHA_EN (1<<16) 605#define DMA_DITHER_EN (1<<17) 606 607#define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0 608#define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY (1<<18) 609#define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL (1<<19) 610 611#define DMA_IBUF_FORMAT_RGB565 (1<<20) 612#define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 0 613 614#define DMA_IBUF_NONCONTIGUOUS (1<<21) 615 616/* MDDI REGISTER ? */ 617#define MDDI_VDO_PACKET_DESC 0x5666 618#define MDDI_VDO_PACKET_PRIM 0xC3 619#define MDDI_VDO_PACKET_SECD 0xC0 620 621#endif 622