1#include <linux/kernel.h> 2#include <linux/errno.h> 3#include <linux/string.h> 4#include <linux/mm.h> 5#include <linux/delay.h> 6#include <linux/interrupt.h> 7#include <linux/platform_device.h> 8 9#include <asm/setup.h> 10#include <asm/system.h> 11#include <asm/irq.h> 12#include <asm/amigahw.h> 13#include <asm/amigaints.h> 14#include <asm/apollohw.h> 15#include <linux/fb.h> 16#include <linux/module.h> 17 18/* apollo video HW definitions */ 19 20/* 21 * Control Registers. IOBASE + $x 22 * 23 * Note: these are the Memory/IO BASE definitions for a mono card set to the 24 * alternate address 25 * 26 * Control 3A and 3B serve identical functions except that 3A 27 * deals with control 1 and 3b deals with Color LUT reg. 28 */ 29 30#define AP_IOBASE 0x3b0 /* Base address of 1 plane board. */ 31#define AP_STATUS isaIO2mem(AP_IOBASE+0) /* Status register. Read */ 32#define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0) /* Write Enable Register Write */ 33#define AP_DEVICE_ID isaIO2mem(AP_IOBASE+1) /* Device ID Register. Read */ 34#define AP_ROP_1 isaIO2mem(AP_IOBASE+2) /* Raster Operation reg. Write Word */ 35#define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4) /* Diagnostic Memory Request. Write Word */ 36#define AP_CONTROL_0 isaIO2mem(AP_IOBASE+8) /* Control Register 0. Read/Write */ 37#define AP_CONTROL_1 isaIO2mem(AP_IOBASE+0xa) /* Control Register 1. Read/Write */ 38#define AP_CONTROL_3A isaIO2mem(AP_IOBASE+0xe) /* Control Register 3a. Read/Write */ 39#define AP_CONTROL_2 isaIO2mem(AP_IOBASE+0xc) /* Control Register 2. Read/Write */ 40 41 42#define FRAME_BUFFER_START 0x0FA0000 43#define FRAME_BUFFER_LEN 0x40000 44 45/* CREG 0 */ 46#define VECTOR_MODE 0x40 47#define DBLT_MODE 0x80 48#define NORMAL_MODE 0xE0 49#define SHIFT_BITS 0x1F /* xxx1.1111 */ 50 /* other bits are Shift value */ 51 52/* CREG 1 */ 53#define AD_BLT 0x80 54#define NORMAL 0x80 /* What is happening here ?? */ 55#define INVERSE 0x00 /* Clearing this reverses the screen */ 56#define PIX_BLT 0x00 57 58#define AD_HIBIT 0x40 59 60#define ROP_EN 0x10 61#define DST_EQ_SRC 0x00 62#define nRESET_SYNC 0x08 63#define SYNC_ENAB 0x02 64 65#define BLANK_DISP 0x00 66#define ENAB_DISP 0x01 67 68#define NORM_CREG1 (nRESET_SYNC | SYNC_ENAB | ENAB_DISP) /* no reset sync */ 69 70/* CREG 2 */ 71 72/* 73 * Following 3 defines are common to 1, 4 and 8 plane. 74 */ 75 76#define S_DATA_1s 0x00 /* set source to all 1's -- vector drawing */ 77#define S_DATA_PIX 0x40 /* takes source from ls-bits and replicates over 16 bits */ 78#define S_DATA_PLN 0xC0 /* normal, each data access =16-bits in 79 one plane of image mem */ 80 81/* CREG 3A/CREG 3B */ 82# define RESET_CREG 0x80 /* 1000.0000 */ 83 84/* ROP REG - all one nibble */ 85/* ********* NOTE : this is used r0,r1,r2,r3 *********** */ 86#define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) ) 87#define DEST_ZERO 0x0 88#define SRC_AND_DEST 0x1 89#define SRC_AND_nDEST 0x2 90#define SRC 0x3 91#define nSRC_AND_DEST 0x4 92#define DEST 0x5 93#define SRC_XOR_DEST 0x6 94#define SRC_OR_DEST 0x7 95#define SRC_NOR_DEST 0x8 96#define SRC_XNOR_DEST 0x9 97#define nDEST 0xA 98#define SRC_OR_nDEST 0xB 99#define nSRC 0xC 100#define nSRC_OR_DEST 0xD 101#define SRC_NAND_DEST 0xE 102#define DEST_ONE 0xF 103 104#define SWAP(A) ((A>>8) | ((A&0xff) <<8)) 105 106/* frame buffer operations */ 107 108static int dnfb_blank(int blank, struct fb_info *info); 109static void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area); 110 111static struct fb_ops dn_fb_ops = { 112 .owner = THIS_MODULE, 113 .fb_blank = dnfb_blank, 114 .fb_fillrect = cfb_fillrect, 115 .fb_copyarea = dnfb_copyarea, 116 .fb_imageblit = cfb_imageblit, 117}; 118 119struct fb_var_screeninfo dnfb_var __devinitdata = { 120 .xres = 1280, 121 .yres = 1024, 122 .xres_virtual = 2048, 123 .yres_virtual = 1024, 124 .bits_per_pixel = 1, 125 .height = -1, 126 .width = -1, 127 .vmode = FB_VMODE_NONINTERLACED, 128}; 129 130static struct fb_fix_screeninfo dnfb_fix __devinitdata = { 131 .id = "Apollo Mono", 132 .smem_start = (FRAME_BUFFER_START + IO_BASE), 133 .smem_len = FRAME_BUFFER_LEN, 134 .type = FB_TYPE_PACKED_PIXELS, 135 .visual = FB_VISUAL_MONO10, 136 .line_length = 256, 137}; 138 139static int dnfb_blank(int blank, struct fb_info *info) 140{ 141 if (blank) 142 out_8(AP_CONTROL_3A, 0x0); 143 else 144 out_8(AP_CONTROL_3A, 0x1); 145 return 0; 146} 147 148static 149void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 150{ 151 152 int incr, y_delta, pre_read = 0, x_end, x_word_count; 153 uint start_mask, end_mask, dest; 154 ushort *src, dummy; 155 short i, j; 156 157 incr = (area->dy <= area->sy) ? 1 : -1; 158 159 src = (ushort *)(info->screen_base + area->sy * info->fix.line_length + 160 (area->sx >> 4)); 161 dest = area->dy * (info->fix.line_length >> 1) + (area->dx >> 4); 162 163 if (incr > 0) { 164 y_delta = (info->fix.line_length * 8) - area->sx - area->width; 165 x_end = area->dx + area->width - 1; 166 x_word_count = (x_end >> 4) - (area->dx >> 4) + 1; 167 start_mask = 0xffff0000 >> (area->dx & 0xf); 168 end_mask = 0x7ffff >> (x_end & 0xf); 169 out_8(AP_CONTROL_0, 170 (((area->dx & 0xf) - (area->sx & 0xf)) % 16) | (0x4 << 5)); 171 if ((area->dx & 0xf) < (area->sx & 0xf)) 172 pre_read = 1; 173 } else { 174 y_delta = -((info->fix.line_length * 8) - area->sx - area->width); 175 x_end = area->dx - area->width + 1; 176 x_word_count = (area->dx >> 4) - (x_end >> 4) + 1; 177 start_mask = 0x7ffff >> (area->dx & 0xf); 178 end_mask = 0xffff0000 >> (x_end & 0xf); 179 out_8(AP_CONTROL_0, 180 ((-((area->sx & 0xf) - (area->dx & 0xf))) % 16) | 181 (0x4 << 5)); 182 if ((area->dx & 0xf) > (area->sx & 0xf)) 183 pre_read = 1; 184 } 185 186 for (i = 0; i < area->height; i++) { 187 188 out_8(AP_CONTROL_3A, 0xc | (dest >> 16)); 189 190 if (pre_read) { 191 dummy = *src; 192 src += incr; 193 } 194 195 if (x_word_count) { 196 out_8(AP_WRITE_ENABLE, start_mask); 197 *src = dest; 198 src += incr; 199 dest += incr; 200 out_8(AP_WRITE_ENABLE, 0); 201 202 for (j = 1; j < (x_word_count - 1); j++) { 203 *src = dest; 204 src += incr; 205 dest += incr; 206 } 207 208 out_8(AP_WRITE_ENABLE, start_mask); 209 *src = dest; 210 dest += incr; 211 src += incr; 212 } else { 213 out_8(AP_WRITE_ENABLE, start_mask | end_mask); 214 *src = dest; 215 dest += incr; 216 src += incr; 217 } 218 src += (y_delta / 16); 219 dest += (y_delta / 16); 220 } 221 out_8(AP_CONTROL_0, NORMAL_MODE); 222} 223 224/* 225 * Initialization 226 */ 227 228static int __devinit dnfb_probe(struct platform_device *dev) 229{ 230 struct fb_info *info; 231 int err = 0; 232 233 info = framebuffer_alloc(0, &dev->dev); 234 if (!info) 235 return -ENOMEM; 236 237 info->fbops = &dn_fb_ops; 238 info->fix = dnfb_fix; 239 info->var = dnfb_var; 240 info->var.red.length = 1; 241 info->var.red.offset = 0; 242 info->var.green = info->var.blue = info->var.red; 243 info->screen_base = (u_char *) info->fix.smem_start; 244 245 err = fb_alloc_cmap(&info->cmap, 2, 0); 246 if (err < 0) { 247 framebuffer_release(info); 248 return err; 249 } 250 251 err = register_framebuffer(info); 252 if (err < 0) { 253 fb_dealloc_cmap(&info->cmap); 254 framebuffer_release(info); 255 return err; 256 } 257 platform_set_drvdata(dev, info); 258 259 /* now we have registered we can safely setup the hardware */ 260 out_8(AP_CONTROL_3A, RESET_CREG); 261 out_be16(AP_WRITE_ENABLE, 0x0); 262 out_8(AP_CONTROL_0, NORMAL_MODE); 263 out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1)); 264 out_8(AP_CONTROL_2, S_DATA_PLN); 265 out_be16(AP_ROP_1, SWAP(0x3)); 266 267 printk("apollo frame buffer alive and kicking !\n"); 268 return err; 269} 270 271static struct platform_driver dnfb_driver = { 272 .probe = dnfb_probe, 273 .driver = { 274 .name = "dnfb", 275 }, 276}; 277 278static struct platform_device dnfb_device = { 279 .name = "dnfb", 280}; 281 282int __init dnfb_init(void) 283{ 284 int ret; 285 286 if (!MACH_IS_APOLLO) 287 return -ENODEV; 288 289 if (fb_get_options("dnfb", NULL)) 290 return -ENODEV; 291 292 ret = platform_driver_register(&dnfb_driver); 293 294 if (!ret) { 295 ret = platform_device_register(&dnfb_device); 296 if (ret) 297 platform_driver_unregister(&dnfb_driver); 298 } 299 return ret; 300} 301 302module_init(dnfb_init); 303 304MODULE_LICENSE("GPL"); 305