1/* Copyright (C) 2005-2006 by Texas Instruments */ 2 3#ifndef _CPPI_DMA_H_ 4#define _CPPI_DMA_H_ 5 6#include <linux/slab.h> 7#include <linux/list.h> 8#include <linux/errno.h> 9#include <linux/dmapool.h> 10 11#include "musb_dma.h" 12#include "musb_core.h" 13 14 15 16#include "davinci.h" 17 18 19/* CPPI RX/TX state RAM */ 20 21struct cppi_tx_stateram { 22 u32 tx_head; /* "DMA packet" head descriptor */ 23 u32 tx_buf; 24 u32 tx_current; /* current descriptor */ 25 u32 tx_buf_current; 26 u32 tx_info; /* flags, remaining buflen */ 27 u32 tx_rem_len; 28 u32 tx_dummy; /* unused */ 29 u32 tx_complete; 30}; 31 32struct cppi_rx_stateram { 33 u32 rx_skipbytes; 34 u32 rx_head; 35 u32 rx_sop; /* "DMA packet" head descriptor */ 36 u32 rx_current; /* current descriptor */ 37 u32 rx_buf_current; 38 u32 rx_len_len; 39 u32 rx_cnt_cnt; 40 u32 rx_complete; 41}; 42 43/* hw_options bits in CPPI buffer descriptors */ 44#define CPPI_SOP_SET ((u32)(1 << 31)) 45#define CPPI_EOP_SET ((u32)(1 << 30)) 46#define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */ 47#define CPPI_EOQ_MASK ((u32)(1 << 28)) 48#define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */ 49#define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */ 50 51#define CPPI_RECV_PKTLEN_MASK 0xFFFF 52#define CPPI_BUFFER_LEN_MASK 0xFFFF 53 54#define CPPI_TEAR_READY ((u32)(1 << 31)) 55 56/* CPPI data structure definitions */ 57 58#define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */ 59 60struct cppi_descriptor { 61 /* hardware overlay */ 62 u32 hw_next; /* next buffer descriptor Pointer */ 63 u32 hw_bufp; /* i/o buffer pointer */ 64 u32 hw_off_len; /* buffer_offset16, buffer_length16 */ 65 u32 hw_options; /* flags: SOP, EOP etc*/ 66 67 struct cppi_descriptor *next; 68 dma_addr_t dma; /* address of this descriptor */ 69 u32 buflen; /* for RX: original buffer length */ 70} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN))); 71 72 73struct cppi; 74 75/* CPPI Channel Control structure */ 76struct cppi_channel { 77 struct dma_channel channel; 78 79 /* back pointer to the DMA controller structure */ 80 struct cppi *controller; 81 82 /* which direction of which endpoint? */ 83 struct musb_hw_ep *hw_ep; 84 bool transmit; 85 u8 index; 86 87 /* DMA modes: RNDIS or "transparent" */ 88 u8 is_rndis; 89 90 /* book keeping for current transfer request */ 91 dma_addr_t buf_dma; 92 u32 buf_len; 93 u32 maxpacket; 94 u32 offset; /* dma requested */ 95 96 void __iomem *state_ram; /* CPPI state */ 97 98 struct cppi_descriptor *freelist; 99 100 /* BD management fields */ 101 struct cppi_descriptor *head; 102 struct cppi_descriptor *tail; 103 struct cppi_descriptor *last_processed; 104 105 /* use tx_complete in host role to track endpoints waiting for 106 * FIFONOTEMPTY to clear. 107 */ 108 struct list_head tx_complete; 109}; 110 111/* CPPI DMA controller object */ 112struct cppi { 113 struct dma_controller controller; 114 struct musb *musb; 115 void __iomem *mregs; /* Mentor regs */ 116 void __iomem *tibase; /* TI/CPPI regs */ 117 118 int irq; 119 120 struct cppi_channel tx[4]; 121 struct cppi_channel rx[4]; 122 123 struct dma_pool *pool; 124 125 struct list_head tx_complete; 126}; 127 128/* CPPI IRQ handler */ 129extern irqreturn_t cppi_interrupt(int, void *); 130 131#endif /* end of ifndef _CPPI_DMA_H_ */ 132