1/* 2 * This file contains code to reset and initialize USB host controllers. 3 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 4 * It may need to run early during booting -- before USB would normally 5 * initialize -- to ensure that Linux doesn't use any legacy modes. 6 * 7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 8 * (and others) 9 */ 10 11#include <linux/types.h> 12#include <linux/kernel.h> 13#include <linux/pci.h> 14#include <linux/init.h> 15#include <linux/delay.h> 16#include <linux/acpi.h> 17#include "pci-quirks.h" 18#include "xhci-ext-caps.h" 19 20 21#define UHCI_USBLEGSUP 0xc0 /* legacy support */ 22#define UHCI_USBCMD 0 /* command register */ 23#define UHCI_USBINTR 4 /* interrupt register */ 24#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 25#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 26#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 27#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 28#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 29#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 30#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 31 32#define OHCI_CONTROL 0x04 33#define OHCI_CMDSTATUS 0x08 34#define OHCI_INTRSTATUS 0x0c 35#define OHCI_INTRENABLE 0x10 36#define OHCI_INTRDISABLE 0x14 37#define OHCI_OCR (1 << 3) /* ownership change request */ 38#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 39#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 40#define OHCI_INTR_OC (1 << 30) /* ownership change */ 41 42#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 43#define EHCI_USBCMD 0 /* command register */ 44#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 45#define EHCI_USBSTS 4 /* status register */ 46#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 47#define EHCI_USBINTR 8 /* interrupt register */ 48#define EHCI_CONFIGFLAG 0x40 /* configured flag register */ 49#define EHCI_USBLEGSUP 0 /* legacy support register */ 50#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 51#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 52#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 53#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 54 55 56/* 57 * Make sure the controller is completely inactive, unable to 58 * generate interrupts or do DMA. 59 */ 60void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 61{ 62 /* Turn off PIRQ enable and SMI enable. (This also turns off the 63 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 64 */ 65 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 66 67 /* Reset the HC - this will force us to get a 68 * new notification of any already connected 69 * ports due to the virtual disconnect that it 70 * implies. 71 */ 72 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 73 mb(); 74 udelay(5); 75 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 76 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 77 78 /* Just to be safe, disable interrupt requests and 79 * make sure the controller is stopped. 80 */ 81 outw(0, base + UHCI_USBINTR); 82 outw(0, base + UHCI_USBCMD); 83} 84EXPORT_SYMBOL_GPL(uhci_reset_hc); 85 86/* 87 * Initialize a controller that was newly discovered or has just been 88 * resumed. In either case we can't be sure of its previous state. 89 * 90 * Returns: 1 if the controller was reset, 0 otherwise. 91 */ 92int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 93{ 94 u16 legsup; 95 unsigned int cmd, intr; 96 97 /* 98 * When restarting a suspended controller, we expect all the 99 * settings to be the same as we left them: 100 * 101 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 102 * Controller is stopped and configured with EGSM set; 103 * No interrupts enabled except possibly Resume Detect. 104 * 105 * If any of these conditions are violated we do a complete reset. 106 */ 107 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 108 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 109 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 110 __func__, legsup); 111 goto reset_needed; 112 } 113 114 cmd = inw(base + UHCI_USBCMD); 115 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 116 !(cmd & UHCI_USBCMD_EGSM)) { 117 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 118 __func__, cmd); 119 goto reset_needed; 120 } 121 122 intr = inw(base + UHCI_USBINTR); 123 if (intr & (~UHCI_USBINTR_RESUME)) { 124 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 125 __func__, intr); 126 goto reset_needed; 127 } 128 return 0; 129 130reset_needed: 131 dev_dbg(&pdev->dev, "Performing full reset\n"); 132 uhci_reset_hc(pdev, base); 133 return 1; 134} 135EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 136 137static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 138{ 139 u16 cmd; 140 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 141} 142 143#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 144#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 145 146static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) 147{ 148 unsigned long base = 0; 149 int i; 150 151 if (!pio_enabled(pdev)) 152 return; 153 154 for (i = 0; i < PCI_ROM_RESOURCE; i++) 155 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 156 base = pci_resource_start(pdev, i); 157 break; 158 } 159 160 if (base) 161 uhci_check_and_reset_hc(pdev, base); 162} 163 164static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx) 165{ 166 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 167} 168 169static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) 170{ 171 void __iomem *base; 172 173 if (!mmio_resource_enabled(pdev, 0)) 174 return; 175 176 base = pci_ioremap_bar(pdev, 0); 177 if (base == NULL) 178 return; 179 180/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 181#ifndef __hppa__ 182{ 183 u32 control = readl(base + OHCI_CONTROL); 184 if (control & OHCI_CTRL_IR) { 185 int wait_time = 500; /* arbitrary; 5 seconds */ 186 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 187 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 188 while (wait_time > 0 && 189 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 190 wait_time -= 10; 191 msleep(10); 192 } 193 if (wait_time <= 0) 194 dev_warn(&pdev->dev, "OHCI: BIOS handoff failed" 195 " (BIOS bug?) %08x\n", 196 readl(base + OHCI_CONTROL)); 197 198 /* reset controller, preserving RWC */ 199 writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL); 200 } 201} 202#endif 203 204 /* 205 * disable interrupts 206 */ 207 writel(~(u32)0, base + OHCI_INTRDISABLE); 208 writel(~(u32)0, base + OHCI_INTRSTATUS); 209 210 iounmap(base); 211} 212 213static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) 214{ 215 int wait_time, delta; 216 void __iomem *base, *op_reg_base; 217 u32 hcc_params, val; 218 u8 offset, cap_length; 219 int count = 256/4; 220 int tried_handoff = 0; 221 222 if (!mmio_resource_enabled(pdev, 0)) 223 return; 224 225 base = pci_ioremap_bar(pdev, 0); 226 if (base == NULL) 227 return; 228 229 cap_length = readb(base); 230 op_reg_base = base + cap_length; 231 232 /* EHCI 0.96 and later may have "extended capabilities" 233 * spec section 5.1 explains the bios handoff, e.g. for 234 * booting from USB disk or using a usb keyboard 235 */ 236 hcc_params = readl(base + EHCI_HCC_PARAMS); 237 offset = (hcc_params >> 8) & 0xff; 238 while (offset && --count) { 239 u32 cap; 240 int msec; 241 242 pci_read_config_dword(pdev, offset, &cap); 243 switch (cap & 0xff) { 244 case 1: /* BIOS/SMM/... handoff support */ 245 if ((cap & EHCI_USBLEGSUP_BIOS)) { 246 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); 247 248 249 /* some systems get upset if this semaphore is 250 * set for any other reason than forcing a BIOS 251 * handoff.. 252 */ 253 pci_write_config_byte(pdev, offset + 3, 1); 254 } 255 256 /* if boot firmware now owns EHCI, spin till 257 * it hands it over. 258 */ 259 msec = 1000; 260 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { 261 tried_handoff = 1; 262 msleep(10); 263 msec -= 10; 264 pci_read_config_dword(pdev, offset, &cap); 265 } 266 267 if (cap & EHCI_USBLEGSUP_BIOS) { 268 /* well, possibly buggy BIOS... try to shut 269 * it down, and hope nothing goes too wrong 270 */ 271 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed" 272 " (BIOS bug?) %08x\n", cap); 273 pci_write_config_byte(pdev, offset + 2, 0); 274 } 275 276 /* just in case, always disable EHCI SMIs */ 277 pci_write_config_dword(pdev, 278 offset + EHCI_USBLEGCTLSTS, 279 0); 280 281 /* If the BIOS ever owned the controller then we 282 * can't expect any power sessions to remain intact. 283 */ 284 if (tried_handoff) 285 writel(0, op_reg_base + EHCI_CONFIGFLAG); 286 break; 287 case 0: /* illegal reserved capability */ 288 cap = 0; 289 /* FALLTHROUGH */ 290 default: 291 dev_warn(&pdev->dev, "EHCI: unrecognized capability " 292 "%02x\n", cap & 0xff); 293 break; 294 } 295 offset = (cap >> 8) & 0xff; 296 } 297 if (!count) 298 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); 299 300 /* 301 * halt EHCI & disable its interrupts in any case 302 */ 303 val = readl(op_reg_base + EHCI_USBSTS); 304 if ((val & EHCI_USBSTS_HALTED) == 0) { 305 val = readl(op_reg_base + EHCI_USBCMD); 306 val &= ~EHCI_USBCMD_RUN; 307 writel(val, op_reg_base + EHCI_USBCMD); 308 309 wait_time = 2000; 310 delta = 100; 311 do { 312 writel(0x3f, op_reg_base + EHCI_USBSTS); 313 udelay(delta); 314 wait_time -= delta; 315 val = readl(op_reg_base + EHCI_USBSTS); 316 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 317 break; 318 } 319 } while (wait_time > 0); 320 } 321 writel(0, op_reg_base + EHCI_USBINTR); 322 writel(0x3f, op_reg_base + EHCI_USBSTS); 323 324 iounmap(base); 325 326 return; 327} 328 329/* 330 * handshake - spin reading a register until handshake completes 331 * @ptr: address of hc register to be read 332 * @mask: bits to look at in result of read 333 * @done: value of those bits when handshake succeeds 334 * @wait_usec: timeout in microseconds 335 * @delay_usec: delay in microseconds to wait between polling 336 * 337 * Polls a register every delay_usec microseconds. 338 * Returns 0 when the mask bits have the value done. 339 * Returns -ETIMEDOUT if this condition is not true after 340 * wait_usec microseconds have passed. 341 */ 342static int handshake(void __iomem *ptr, u32 mask, u32 done, 343 int wait_usec, int delay_usec) 344{ 345 u32 result; 346 347 do { 348 result = readl(ptr); 349 result &= mask; 350 if (result == done) 351 return 0; 352 udelay(delay_usec); 353 wait_usec -= delay_usec; 354 } while (wait_usec > 0); 355 return -ETIMEDOUT; 356} 357 358/** 359 * PCI Quirks for xHCI. 360 * 361 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. 362 * It signals to the BIOS that the OS wants control of the host controller, 363 * and then waits 5 seconds for the BIOS to hand over control. 364 * If we timeout, assume the BIOS is broken and take control anyway. 365 */ 366static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev) 367{ 368 void __iomem *base; 369 int ext_cap_offset; 370 void __iomem *op_reg_base; 371 u32 val; 372 int timeout; 373 374 if (!mmio_resource_enabled(pdev, 0)) 375 return; 376 377 base = ioremap_nocache(pci_resource_start(pdev, 0), 378 pci_resource_len(pdev, 0)); 379 if (base == NULL) 380 return; 381 382 /* 383 * Find the Legacy Support Capability register - 384 * this is optional for xHCI host controllers. 385 */ 386 ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET); 387 do { 388 if (!ext_cap_offset) 389 /* We've reached the end of the extended capabilities */ 390 goto hc_init; 391 val = readl(base + ext_cap_offset); 392 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY) 393 break; 394 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset); 395 } while (1); 396 397 /* If the BIOS owns the HC, signal that the OS wants it, and wait */ 398 if (val & XHCI_HC_BIOS_OWNED) { 399 writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset); 400 401 /* Wait for 5 seconds with 10 microsecond polling interval */ 402 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, 403 0, 5000, 10); 404 405 /* Assume a buggy BIOS and take HC ownership anyway */ 406 if (timeout) { 407 dev_warn(&pdev->dev, "xHCI BIOS handoff failed" 408 " (BIOS bug ?) %08x\n", val); 409 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); 410 } 411 } 412 413 /* Disable any BIOS SMIs */ 414 writel(XHCI_LEGACY_DISABLE_SMI, 415 base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 416 417hc_init: 418 op_reg_base = base + XHCI_HC_LENGTH(readl(base)); 419 420 /* Wait for the host controller to be ready before writing any 421 * operational or runtime registers. Wait 5 seconds and no more. 422 */ 423 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, 424 5000, 10); 425 /* Assume a buggy HC and start HC initialization anyway */ 426 if (timeout) { 427 val = readl(op_reg_base + XHCI_STS_OFFSET); 428 dev_warn(&pdev->dev, 429 "xHCI HW not ready after 5 sec (HC bug?) " 430 "status = 0x%x\n", val); 431 } 432 433 /* Send the halt and disable interrupts command */ 434 val = readl(op_reg_base + XHCI_CMD_OFFSET); 435 val &= ~(XHCI_CMD_RUN | XHCI_IRQS); 436 writel(val, op_reg_base + XHCI_CMD_OFFSET); 437 438 /* Wait for the HC to halt - poll every 125 usec (one microframe). */ 439 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, 440 XHCI_MAX_HALT_USEC, 125); 441 if (timeout) { 442 val = readl(op_reg_base + XHCI_STS_OFFSET); 443 dev_warn(&pdev->dev, 444 "xHCI HW did not halt within %d usec " 445 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val); 446 } 447 448 iounmap(base); 449} 450 451static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) 452{ 453 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 454 quirk_usb_handoff_uhci(pdev); 455 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 456 quirk_usb_handoff_ohci(pdev); 457 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 458 quirk_usb_disable_ehci(pdev); 459 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) 460 quirk_usb_handoff_xhci(pdev); 461} 462DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); 463