1/* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * PCI Bus Glue 13 * 14 * This file is licenced under the GPL. 15 */ 16 17#ifndef CONFIG_PCI 18#error "This file is PCI bus glue. CONFIG_PCI must be defined." 19#endif 20 21#include <linux/pci.h> 22#include <linux/io.h> 23 24 25#define AB_REG_BAR 0xf0 26#define AB_INDX(addr) ((addr) + 0x00) 27#define AB_DATA(addr) ((addr) + 0x04) 28#define AX_INDXC 0X30 29#define AX_DATAC 0x34 30 31#define NB_PCIE_INDX_ADDR 0xe0 32#define NB_PCIE_INDX_DATA 0xe4 33#define PCIE_P_CNTL 0x10040 34#define BIF_NB 0x10002 35 36static struct pci_dev *amd_smbus_dev; 37static struct pci_dev *amd_hb_dev; 38static int amd_ohci_iso_count; 39 40/*-------------------------------------------------------------------------*/ 41 42static int broken_suspend(struct usb_hcd *hcd) 43{ 44 device_init_wakeup(&hcd->self.root_hub->dev, 0); 45 return 0; 46} 47 48static int ohci_quirk_amd756(struct usb_hcd *hcd) 49{ 50 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 51 52 ohci->flags = OHCI_QUIRK_AMD756; 53 ohci_dbg (ohci, "AMD756 erratum 4 workaround\n"); 54 55 /* also erratum 10 (suspend/resume issues) */ 56 return broken_suspend(hcd); 57} 58 59/* Apple's OHCI driver has a lot of bizarre workarounds 60 * for this chip. Evidently control and bulk lists 61 * can get confused. (B&W G3 models, and ...) 62 */ 63static int ohci_quirk_opti(struct usb_hcd *hcd) 64{ 65 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 66 67 ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n"); 68 69 return 0; 70} 71 72/* Check for NSC87560. We have to look at the bridge (fn1) to 73 * identify the USB (fn2). This quirk might apply to more or 74 * even all NSC stuff. 75 */ 76static int ohci_quirk_ns(struct usb_hcd *hcd) 77{ 78 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 79 struct pci_dev *b; 80 81 b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1)); 82 if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO 83 && b->vendor == PCI_VENDOR_ID_NS) { 84 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 85 86 ohci->flags |= OHCI_QUIRK_SUPERIO; 87 ohci_dbg (ohci, "Using NSC SuperIO setup\n"); 88 } 89 pci_dev_put(b); 90 91 return 0; 92} 93 94/* Check for Compaq's ZFMicro chipset, which needs short 95 * delays before control or bulk queues get re-activated 96 * in finish_unlinks() 97 */ 98static int ohci_quirk_zfmicro(struct usb_hcd *hcd) 99{ 100 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 101 102 ohci->flags |= OHCI_QUIRK_ZFMICRO; 103 ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n"); 104 105 return 0; 106} 107 108/* Check for Toshiba SCC OHCI which has big endian registers 109 * and little endian in memory data structures 110 */ 111static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd) 112{ 113 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 114 115 /* That chip is only present in the southbridge of some 116 * cell based platforms which are supposed to select 117 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if 118 * that was the case though. 119 */ 120#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 121 ohci->flags |= OHCI_QUIRK_BE_MMIO; 122 ohci_dbg (ohci, "enabled big endian Toshiba quirk\n"); 123 return 0; 124#else 125 ohci_err (ohci, "unsupported big endian Toshiba quirk\n"); 126 return -ENXIO; 127#endif 128} 129 130/* Check for NEC chip and apply quirk for allegedly lost interrupts. 131 */ 132 133static void ohci_quirk_nec_worker(struct work_struct *work) 134{ 135 struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work); 136 int status; 137 138 status = ohci_init(ohci); 139 if (status != 0) { 140 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n", 141 "ohci_init", status); 142 return; 143 } 144 145 status = ohci_restart(ohci); 146 if (status != 0) 147 ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n", 148 "ohci_restart", status); 149} 150 151static int ohci_quirk_nec(struct usb_hcd *hcd) 152{ 153 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 154 155 ohci->flags |= OHCI_QUIRK_NEC; 156 INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker); 157 ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n"); 158 159 return 0; 160} 161 162static int ohci_quirk_amd700(struct usb_hcd *hcd) 163{ 164 struct ohci_hcd *ohci = hcd_to_ohci(hcd); 165 u8 rev = 0; 166 167 if (!amd_smbus_dev) 168 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 169 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 170 if (!amd_smbus_dev) 171 return 0; 172 173 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev); 174 175 /* SB800 needs pre-fetch fix */ 176 if ((rev >= 0x40) && (rev <= 0x4f)) { 177 ohci->flags |= OHCI_QUIRK_AMD_PREFETCH; 178 ohci_dbg(ohci, "enabled AMD prefetch quirk\n"); 179 } 180 181 if ((rev > 0x3b) || (rev < 0x30)) { 182 pci_dev_put(amd_smbus_dev); 183 amd_smbus_dev = NULL; 184 return 0; 185 } 186 187 amd_ohci_iso_count++; 188 189 if (!amd_hb_dev) 190 amd_hb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9600, NULL); 191 192 ohci->flags |= OHCI_QUIRK_AMD_ISO; 193 ohci_dbg(ohci, "enabled AMD ISO transfers quirk\n"); 194 195 return 0; 196} 197 198/* 199 * The hardware normally enables the A-link power management feature, which 200 * lets the system lower the power consumption in idle states. 201 * 202 * Assume the system is configured to have USB 1.1 ISO transfers going 203 * to or from a USB device. Without this quirk, that stream may stutter 204 * or have breaks occasionally. For transfers going to speakers, this 205 * makes a very audible mess... 206 * 207 * That audio playback corruption is due to the audio stream getting 208 * interrupted occasionally when the link goes in lower power state 209 * This USB quirk prevents the link going into that lower power state 210 * during audio playback or other ISO operations. 211 */ 212static void quirk_amd_pll(int on) 213{ 214 u32 addr; 215 u32 val; 216 u32 bit = (on > 0) ? 1 : 0; 217 218 pci_read_config_dword(amd_smbus_dev, AB_REG_BAR, &addr); 219 220 /* BIT names/meanings are NDA-protected, sorry ... */ 221 222 outl(AX_INDXC, AB_INDX(addr)); 223 outl(0x40, AB_DATA(addr)); 224 outl(AX_DATAC, AB_INDX(addr)); 225 val = inl(AB_DATA(addr)); 226 val &= ~((1 << 3) | (1 << 4) | (1 << 9)); 227 val |= (bit << 3) | ((!bit) << 4) | ((!bit) << 9); 228 outl(val, AB_DATA(addr)); 229 230 if (amd_hb_dev) { 231 addr = PCIE_P_CNTL; 232 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr); 233 234 pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val); 235 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); 236 val |= bit | (bit << 3) | (bit << 12); 237 val |= ((!bit) << 4) | ((!bit) << 9); 238 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val); 239 240 addr = BIF_NB; 241 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr); 242 243 pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val); 244 val &= ~(1 << 8); 245 val |= bit << 8; 246 pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val); 247 } 248} 249 250static void amd_iso_dev_put(void) 251{ 252 amd_ohci_iso_count--; 253 if (amd_ohci_iso_count == 0) { 254 if (amd_smbus_dev) { 255 pci_dev_put(amd_smbus_dev); 256 amd_smbus_dev = NULL; 257 } 258 if (amd_hb_dev) { 259 pci_dev_put(amd_hb_dev); 260 amd_hb_dev = NULL; 261 } 262 } 263 264} 265 266static void sb800_prefetch(struct ohci_hcd *ohci, int on) 267{ 268 struct pci_dev *pdev; 269 u16 misc; 270 271 pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller); 272 pci_read_config_word(pdev, 0x50, &misc); 273 if (on == 0) 274 pci_write_config_word(pdev, 0x50, misc & 0xfcff); 275 else 276 pci_write_config_word(pdev, 0x50, misc | 0x0300); 277} 278 279/* List of quirks for OHCI */ 280static const struct pci_device_id ohci_pci_quirks[] = { 281 { 282 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c), 283 .driver_data = (unsigned long)ohci_quirk_amd756, 284 }, 285 { 286 PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861), 287 .driver_data = (unsigned long)ohci_quirk_opti, 288 }, 289 { 290 PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID), 291 .driver_data = (unsigned long)ohci_quirk_ns, 292 }, 293 { 294 PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8), 295 .driver_data = (unsigned long)ohci_quirk_zfmicro, 296 }, 297 { 298 PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6), 299 .driver_data = (unsigned long)ohci_quirk_toshiba_scc, 300 }, 301 { 302 PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB), 303 .driver_data = (unsigned long)ohci_quirk_nec, 304 }, 305 { 306 /* Toshiba portege 4000 */ 307 .vendor = PCI_VENDOR_ID_AL, 308 .device = 0x5237, 309 .subvendor = PCI_VENDOR_ID_TOSHIBA, 310 .subdevice = 0x0004, 311 .driver_data = (unsigned long) broken_suspend, 312 }, 313 { 314 PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152), 315 .driver_data = (unsigned long) broken_suspend, 316 }, 317 { 318 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397), 319 .driver_data = (unsigned long)ohci_quirk_amd700, 320 }, 321 { 322 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398), 323 .driver_data = (unsigned long)ohci_quirk_amd700, 324 }, 325 { 326 PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399), 327 .driver_data = (unsigned long)ohci_quirk_amd700, 328 }, 329 330 331 {}, 332}; 333 334static int ohci_pci_reset (struct usb_hcd *hcd) 335{ 336 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 337 int ret = 0; 338 339 if (hcd->self.controller) { 340 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 341 const struct pci_device_id *quirk_id; 342 343 quirk_id = pci_match_id(ohci_pci_quirks, pdev); 344 if (quirk_id != NULL) { 345 int (*quirk)(struct usb_hcd *ohci); 346 quirk = (void *)quirk_id->driver_data; 347 ret = quirk(hcd); 348 } 349 } 350 if (ret == 0) { 351 ohci_hcd_init (ohci); 352 return ohci_init (ohci); 353 } 354 return ret; 355} 356 357 358static int __devinit ohci_pci_start (struct usb_hcd *hcd) 359{ 360 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 361 int ret; 362 363#ifdef CONFIG_PM /* avoid warnings about unused pdev */ 364 if (hcd->self.controller) { 365 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 366 367 /* RWC may not be set for add-in PCI cards, since boot 368 * firmware probably ignored them. This transfers PCI 369 * PM wakeup capabilities. 370 */ 371 if (device_can_wakeup(&pdev->dev)) 372 ohci->hc_control |= OHCI_CTRL_RWC; 373 } 374#endif /* CONFIG_PM */ 375 376 ret = ohci_run (ohci); 377 if (ret < 0) { 378 ohci_err (ohci, "can't start\n"); 379 ohci_stop (hcd); 380 } 381 return ret; 382} 383 384#ifdef CONFIG_PM 385 386static int ohci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 387{ 388 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 389 unsigned long flags; 390 int rc = 0; 391 392 /* Root hub was already suspended. Disable irq emission and 393 * mark HW unaccessible, bail out if RH has been resumed. Use 394 * the spinlock to properly synchronize with possible pending 395 * RH suspend or resume activity. 396 * 397 * This is still racy as hcd->state is manipulated outside of 398 * any locks =P But that will be a different fix. 399 */ 400 spin_lock_irqsave (&ohci->lock, flags); 401 if (hcd->state != HC_STATE_SUSPENDED) { 402 rc = -EINVAL; 403 goto bail; 404 } 405 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 406 (void)ohci_readl(ohci, &ohci->regs->intrdisable); 407 408 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 409 bail: 410 spin_unlock_irqrestore (&ohci->lock, flags); 411 412 return rc; 413} 414 415 416static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated) 417{ 418 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 419 420 /* Make sure resume from hibernation re-enumerates everything */ 421 if (hibernated) 422 ohci_usb_reset(hcd_to_ohci(hcd)); 423 424 ohci_finish_controller_resume(hcd); 425 return 0; 426} 427 428#endif /* CONFIG_PM */ 429 430 431/*-------------------------------------------------------------------------*/ 432 433static const struct hc_driver ohci_pci_hc_driver = { 434 .description = hcd_name, 435 .product_desc = "OHCI Host Controller", 436 .hcd_priv_size = sizeof(struct ohci_hcd), 437 438 /* 439 * generic hardware linkage 440 */ 441 .irq = ohci_irq, 442 .flags = HCD_MEMORY | HCD_USB11, 443 444 /* 445 * basic lifecycle operations 446 */ 447 .reset = ohci_pci_reset, 448 .start = ohci_pci_start, 449 .stop = ohci_stop, 450 .shutdown = ohci_shutdown, 451 452#ifdef CONFIG_PM 453 .pci_suspend = ohci_pci_suspend, 454 .pci_resume = ohci_pci_resume, 455#endif 456 457 /* 458 * managing i/o requests and associated device resources 459 */ 460 .urb_enqueue = ohci_urb_enqueue, 461 .urb_dequeue = ohci_urb_dequeue, 462 .endpoint_disable = ohci_endpoint_disable, 463 464 /* 465 * scheduling support 466 */ 467 .get_frame_number = ohci_get_frame, 468 469 /* 470 * root hub support 471 */ 472 .hub_status_data = ohci_hub_status_data, 473 .hub_control = ohci_hub_control, 474#ifdef CONFIG_PM 475 .bus_suspend = ohci_bus_suspend, 476 .bus_resume = ohci_bus_resume, 477#endif 478 .start_port_reset = ohci_start_port_reset, 479}; 480 481/*-------------------------------------------------------------------------*/ 482 483 484static const struct pci_device_id pci_ids [] = { { 485 /* handle any USB OHCI controller */ 486 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0), 487 .driver_data = (unsigned long) &ohci_pci_hc_driver, 488 }, { /* end: all zeroes */ } 489}; 490MODULE_DEVICE_TABLE (pci, pci_ids); 491 492/* pci driver glue; this is a "new style" PCI driver module */ 493static struct pci_driver ohci_pci_driver = { 494 .name = (char *) hcd_name, 495 .id_table = pci_ids, 496 497 .probe = usb_hcd_pci_probe, 498 .remove = usb_hcd_pci_remove, 499 .shutdown = usb_hcd_pci_shutdown, 500 501#ifdef CONFIG_PM_SLEEP 502 .driver = { 503 .pm = &usb_hcd_pci_pm_ops 504 }, 505#endif 506}; 507