1/* 2 * Driver for the NXP ISP1760 chip 3 * 4 * However, the code might contain some bugs. What doesn't work for sure is: 5 * - ISO 6 * - OTG 7 e The interrupt line is configured as active low, level. 8 * 9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> 10 * 11 */ 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/slab.h> 15#include <linux/list.h> 16#include <linux/usb.h> 17#include <linux/usb/hcd.h> 18#include <linux/debugfs.h> 19#include <linux/uaccess.h> 20#include <linux/io.h> 21#include <linux/mm.h> 22#include <asm/unaligned.h> 23#include <asm/cacheflush.h> 24 25#include "isp1760-hcd.h" 26 27static struct kmem_cache *qtd_cachep; 28static struct kmem_cache *qh_cachep; 29 30struct isp1760_hcd { 31 u32 hcs_params; 32 spinlock_t lock; 33 struct inter_packet_info atl_ints[32]; 34 struct inter_packet_info int_ints[32]; 35 struct memory_chunk memory_pool[BLOCKS]; 36 37 /* periodic schedule support */ 38#define DEFAULT_I_TDPS 1024 39 unsigned periodic_size; 40 unsigned i_thresh; 41 unsigned long reset_done; 42 unsigned long next_statechange; 43 unsigned int devflags; 44}; 45 46static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) 47{ 48 return (struct isp1760_hcd *) (hcd->hcd_priv); 49} 50static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv) 51{ 52 return container_of((void *) priv, struct usb_hcd, hcd_priv); 53} 54 55/* Section 2.2 Host Controller Capability Registers */ 56#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 57#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 58#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 59#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 60#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 61#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 62#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 63 64/* Section 2.3 Host Controller Operational Registers */ 65#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 66#define CMD_RESET (1<<1) /* reset HC not bus */ 67#define CMD_RUN (1<<0) /* start/stop HC */ 68#define STS_PCD (1<<2) /* port change detect */ 69#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 70 71#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 72#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 73#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ 74#define PORT_RESET (1<<8) /* reset port */ 75#define PORT_SUSPEND (1<<7) /* suspend port */ 76#define PORT_RESUME (1<<6) /* resume it */ 77#define PORT_PE (1<<2) /* port enable */ 78#define PORT_CSC (1<<1) /* connect status change */ 79#define PORT_CONNECT (1<<0) /* device connected */ 80#define PORT_RWC_BITS (PORT_CSC) 81 82struct isp1760_qtd { 83 struct isp1760_qtd *hw_next; 84 u8 packet_type; 85 u8 toggle; 86 87 void *data_buffer; 88 /* the rest is HCD-private */ 89 struct list_head qtd_list; 90 struct urb *urb; 91 size_t length; 92 93 /* isp special*/ 94 u32 status; 95#define URB_COMPLETE_NOTIFY (1 << 0) 96#define URB_ENQUEUED (1 << 1) 97#define URB_TYPE_ATL (1 << 2) 98#define URB_TYPE_INT (1 << 3) 99}; 100 101struct isp1760_qh { 102 /* first part defined by EHCI spec */ 103 struct list_head qtd_list; 104 struct isp1760_hcd *priv; 105 106 /* periodic schedule info */ 107 unsigned short period; /* polling interval */ 108 struct usb_device *dev; 109 110 u32 toggle; 111 u32 ping; 112}; 113 114#define ehci_port_speed(priv, portsc) USB_PORT_STAT_HIGH_SPEED 115 116static unsigned int isp1760_readl(__u32 __iomem *regs) 117{ 118 return readl(regs); 119} 120 121static void isp1760_writel(const unsigned int val, __u32 __iomem *regs) 122{ 123 writel(val, regs); 124} 125 126/* 127 * The next two copy via MMIO data to/from the device. memcpy_{to|from}io() 128 * doesn't quite work because some people have to enforce 32-bit access 129 */ 130static void priv_read_copy(struct isp1760_hcd *priv, u32 *src, 131 __u32 __iomem *dst, u32 len) 132{ 133 u32 val; 134 u8 *buff8; 135 136 if (!src) { 137 printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len); 138 return; 139 } 140 141 while (len >= 4) { 142 *src = __raw_readl(dst); 143 len -= 4; 144 src++; 145 dst++; 146 } 147 148 if (!len) 149 return; 150 151 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully 152 * allocated. 153 */ 154 val = isp1760_readl(dst); 155 156 buff8 = (u8 *)src; 157 while (len) { 158 159 *buff8 = val; 160 val >>= 8; 161 len--; 162 buff8++; 163 } 164} 165 166static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src, 167 __u32 __iomem *dst, u32 len) 168{ 169 while (len >= 4) { 170 __raw_writel(*src, dst); 171 len -= 4; 172 src++; 173 dst++; 174 } 175 176 if (!len) 177 return; 178 /* in case we have 3, 2 or 1 by left. The buffer is allocated and the 179 * extra bytes should not be read by the HW 180 */ 181 182 __raw_writel(*src, dst); 183} 184 185/* memory management of the 60kb on the chip from 0x1000 to 0xffff */ 186static void init_memory(struct isp1760_hcd *priv) 187{ 188 int i; 189 u32 payload; 190 191 payload = 0x1000; 192 for (i = 0; i < BLOCK_1_NUM; i++) { 193 priv->memory_pool[i].start = payload; 194 priv->memory_pool[i].size = BLOCK_1_SIZE; 195 priv->memory_pool[i].free = 1; 196 payload += priv->memory_pool[i].size; 197 } 198 199 200 for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) { 201 priv->memory_pool[i].start = payload; 202 priv->memory_pool[i].size = BLOCK_2_SIZE; 203 priv->memory_pool[i].free = 1; 204 payload += priv->memory_pool[i].size; 205 } 206 207 208 for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) { 209 priv->memory_pool[i].start = payload; 210 priv->memory_pool[i].size = BLOCK_3_SIZE; 211 priv->memory_pool[i].free = 1; 212 payload += priv->memory_pool[i].size; 213 } 214 215 BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE); 216} 217 218static u32 alloc_mem(struct isp1760_hcd *priv, u32 size) 219{ 220 int i; 221 222 if (!size) 223 return ISP1760_NULL_POINTER; 224 225 for (i = 0; i < BLOCKS; i++) { 226 if (priv->memory_pool[i].size >= size && 227 priv->memory_pool[i].free) { 228 229 priv->memory_pool[i].free = 0; 230 return priv->memory_pool[i].start; 231 } 232 } 233 234 printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n", 235 size); 236 printk(KERN_ERR "Current memory map:\n"); 237 for (i = 0; i < BLOCKS; i++) { 238 printk(KERN_ERR "Pool %2d size %4d status: %d\n", 239 i, priv->memory_pool[i].size, 240 priv->memory_pool[i].free); 241 } 242 BUG(); 243 return 0; 244} 245 246static void free_mem(struct isp1760_hcd *priv, u32 mem) 247{ 248 int i; 249 250 if (mem == ISP1760_NULL_POINTER) 251 return; 252 253 for (i = 0; i < BLOCKS; i++) { 254 if (priv->memory_pool[i].start == mem) { 255 256 BUG_ON(priv->memory_pool[i].free); 257 258 priv->memory_pool[i].free = 1; 259 return ; 260 } 261 } 262 263 printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n", 264 mem); 265 BUG(); 266} 267 268static void isp1760_init_regs(struct usb_hcd *hcd) 269{ 270 isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG); 271 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + 272 HC_ATL_PTD_SKIPMAP_REG); 273 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + 274 HC_INT_PTD_SKIPMAP_REG); 275 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + 276 HC_ISO_PTD_SKIPMAP_REG); 277 278 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + 279 HC_ATL_PTD_DONEMAP_REG); 280 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + 281 HC_INT_PTD_DONEMAP_REG); 282 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + 283 HC_ISO_PTD_DONEMAP_REG); 284} 285 286static int handshake(struct isp1760_hcd *priv, void __iomem *ptr, 287 u32 mask, u32 done, int usec) 288{ 289 u32 result; 290 291 do { 292 result = isp1760_readl(ptr); 293 if (result == ~0) 294 return -ENODEV; 295 result &= mask; 296 if (result == done) 297 return 0; 298 udelay(1); 299 usec--; 300 } while (usec > 0); 301 return -ETIMEDOUT; 302} 303 304/* reset a non-running (STS_HALT == 1) controller */ 305static int ehci_reset(struct isp1760_hcd *priv) 306{ 307 int retval; 308 struct usb_hcd *hcd = priv_to_hcd(priv); 309 u32 command = isp1760_readl(hcd->regs + HC_USBCMD); 310 311 command |= CMD_RESET; 312 isp1760_writel(command, hcd->regs + HC_USBCMD); 313 hcd->state = HC_STATE_HALT; 314 priv->next_statechange = jiffies; 315 retval = handshake(priv, hcd->regs + HC_USBCMD, 316 CMD_RESET, 0, 250 * 1000); 317 return retval; 318} 319 320static void qh_destroy(struct isp1760_qh *qh) 321{ 322 BUG_ON(!list_empty(&qh->qtd_list)); 323 kmem_cache_free(qh_cachep, qh); 324} 325 326static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv, 327 gfp_t flags) 328{ 329 struct isp1760_qh *qh; 330 331 qh = kmem_cache_zalloc(qh_cachep, flags); 332 if (!qh) 333 return qh; 334 335 INIT_LIST_HEAD(&qh->qtd_list); 336 qh->priv = priv; 337 return qh; 338} 339 340/* magic numbers that can affect system performance */ 341#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 342#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 343#define EHCI_TUNE_RL_TT 0 344#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 345#define EHCI_TUNE_MULT_TT 1 346#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 347 348/* one-time init, only for memory state */ 349static int priv_init(struct usb_hcd *hcd) 350{ 351 struct isp1760_hcd *priv = hcd_to_priv(hcd); 352 u32 hcc_params; 353 354 spin_lock_init(&priv->lock); 355 356 /* 357 * hw default: 1K periodic list heads, one per frame. 358 * periodic_size can shrink by USBCMD update if hcc_params allows. 359 */ 360 priv->periodic_size = DEFAULT_I_TDPS; 361 362 /* controllers may cache some of the periodic schedule ... */ 363 hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS); 364 /* full frame cache */ 365 if (HCC_ISOC_CACHE(hcc_params)) 366 priv->i_thresh = 8; 367 else /* N microframes cached */ 368 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 369 370 return 0; 371} 372 373static int isp1760_hc_setup(struct usb_hcd *hcd) 374{ 375 struct isp1760_hcd *priv = hcd_to_priv(hcd); 376 int result; 377 u32 scratch, hwmode; 378 379 /* Setup HW Mode Control: This assumes a level active-low interrupt */ 380 hwmode = HW_DATA_BUS_32BIT; 381 382 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) 383 hwmode &= ~HW_DATA_BUS_32BIT; 384 if (priv->devflags & ISP1760_FLAG_ANALOG_OC) 385 hwmode |= HW_ANA_DIGI_OC; 386 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH) 387 hwmode |= HW_DACK_POL_HIGH; 388 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH) 389 hwmode |= HW_DREQ_POL_HIGH; 390 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH) 391 hwmode |= HW_INTR_HIGH_ACT; 392 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) 393 hwmode |= HW_INTR_EDGE_TRIG; 394 395 /* 396 * We have to set this first in case we're in 16-bit mode. 397 * Write it twice to ensure correct upper bits if switching 398 * to 16-bit mode. 399 */ 400 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); 401 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); 402 403 isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG); 404 /* Change bus pattern */ 405 scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); 406 scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG); 407 if (scratch != 0xdeadbabe) { 408 printk(KERN_ERR "ISP1760: Scratch test failed.\n"); 409 return -ENODEV; 410 } 411 412 /* pre reset */ 413 isp1760_init_regs(hcd); 414 415 /* reset */ 416 isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG); 417 mdelay(100); 418 419 isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG); 420 mdelay(100); 421 422 result = ehci_reset(priv); 423 if (result) 424 return result; 425 426 /* Step 11 passed */ 427 428 isp1760_info(priv, "bus width: %d, oc: %s\n", 429 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? 430 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? 431 "analog" : "digital"); 432 433 /* ATL reset */ 434 isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL); 435 mdelay(10); 436 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); 437 438 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG); 439 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE); 440 441 /* 442 * PORT 1 Control register of the ISP1760 is the OTG control 443 * register on ISP1761. Since there is no OTG or device controller 444 * support in this driver, we use port 1 as a "normal" USB host port on 445 * both chips. 446 */ 447 isp1760_writel(PORT1_POWER | PORT1_INIT2, 448 hcd->regs + HC_PORT1_CTRL); 449 mdelay(10); 450 451 priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS); 452 453 return priv_init(hcd); 454} 455 456static void isp1760_init_maps(struct usb_hcd *hcd) 457{ 458 /*set last maps, for iso its only 1, else 32 tds bitmap*/ 459 isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG); 460 isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG); 461 isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG); 462} 463 464static void isp1760_enable_interrupts(struct usb_hcd *hcd) 465{ 466 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG); 467 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 468 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG); 469 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG); 470 isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG); 471 isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG); 472 /* step 23 passed */ 473} 474 475static int isp1760_run(struct usb_hcd *hcd) 476{ 477 struct isp1760_hcd *priv = hcd_to_priv(hcd); 478 int retval; 479 u32 temp; 480 u32 command; 481 u32 chipid; 482 483 hcd->uses_new_polling = 1; 484 485 hcd->state = HC_STATE_RUNNING; 486 isp1760_enable_interrupts(hcd); 487 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); 488 isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); 489 490 command = isp1760_readl(hcd->regs + HC_USBCMD); 491 command &= ~(CMD_LRESET|CMD_RESET); 492 command |= CMD_RUN; 493 isp1760_writel(command, hcd->regs + HC_USBCMD); 494 495 retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN, 496 250 * 1000); 497 if (retval) 498 return retval; 499 500 down_write(&ehci_cf_port_reset_rwsem); 501 isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG); 502 503 retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 504 250 * 1000); 505 up_write(&ehci_cf_port_reset_rwsem); 506 if (retval) 507 return retval; 508 509 chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); 510 isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff, 511 chipid >> 16); 512 513 /* PTD Register Init Part 2, Step 28 */ 514 /* enable INTs */ 515 isp1760_init_maps(hcd); 516 517 /* GRR this is run-once init(), being done every time the HC starts. 518 * So long as they're part of class devices, we can't do it init() 519 * since the class device isn't created that early. 520 */ 521 return 0; 522} 523 524static u32 base_to_chip(u32 base) 525{ 526 return ((base - 0x400) >> 3); 527} 528 529static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh, 530 struct isp1760_qtd *qtd, struct urb *urb, 531 u32 payload, struct ptd *ptd) 532{ 533 u32 dw0; 534 u32 dw1; 535 u32 dw2; 536 u32 dw3; 537 u32 maxpacket; 538 u32 multi; 539 u32 pid_code; 540 u32 rl = RL_COUNTER; 541 u32 nak = NAK_COUNTER; 542 543 /* according to 3.6.2, max packet len can not be > 0x400 */ 544 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); 545 multi = 1 + ((maxpacket >> 11) & 0x3); 546 maxpacket &= 0x7ff; 547 548 /* DW0 */ 549 dw0 = PTD_VALID; 550 dw0 |= PTD_LENGTH(qtd->length); 551 dw0 |= PTD_MAXPACKET(maxpacket); 552 dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe)); 553 dw1 = usb_pipeendpoint(urb->pipe) >> 1; 554 555 /* DW1 */ 556 dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe)); 557 558 pid_code = qtd->packet_type; 559 dw1 |= PTD_PID_TOKEN(pid_code); 560 561 if (usb_pipebulk(urb->pipe)) 562 dw1 |= PTD_TRANS_BULK; 563 else if (usb_pipeint(urb->pipe)) 564 dw1 |= PTD_TRANS_INT; 565 566 if (urb->dev->speed != USB_SPEED_HIGH) { 567 /* split transaction */ 568 569 dw1 |= PTD_TRANS_SPLIT; 570 if (urb->dev->speed == USB_SPEED_LOW) 571 dw1 |= PTD_SE_USB_LOSPEED; 572 573 dw1 |= PTD_PORT_NUM(urb->dev->ttport); 574 dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum); 575 576 /* SE bit for Split INT transfers */ 577 if (usb_pipeint(urb->pipe) && 578 (urb->dev->speed == USB_SPEED_LOW)) 579 dw1 |= 2 << 16; 580 581 dw3 = 0; 582 rl = 0; 583 nak = 0; 584 } else { 585 dw0 |= PTD_MULTI(multi); 586 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) 587 dw3 = qh->ping; 588 else 589 dw3 = 0; 590 } 591 /* DW2 */ 592 dw2 = 0; 593 dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload)); 594 dw2 |= PTD_RL_CNT(rl); 595 dw3 |= PTD_NAC_CNT(nak); 596 597 /* DW3 */ 598 if (usb_pipecontrol(urb->pipe)) 599 dw3 |= PTD_DATA_TOGGLE(qtd->toggle); 600 else 601 dw3 |= qh->toggle; 602 603 604 dw3 |= PTD_ACTIVE; 605 /* Cerr */ 606 dw3 |= PTD_CERR(ERR_COUNTER); 607 608 memset(ptd, 0, sizeof(*ptd)); 609 610 ptd->dw0 = cpu_to_le32(dw0); 611 ptd->dw1 = cpu_to_le32(dw1); 612 ptd->dw2 = cpu_to_le32(dw2); 613 ptd->dw3 = cpu_to_le32(dw3); 614} 615 616static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, 617 struct isp1760_qtd *qtd, struct urb *urb, 618 u32 payload, struct ptd *ptd) 619{ 620 u32 maxpacket; 621 u32 multi; 622 u32 numberofusofs; 623 u32 i; 624 u32 usofmask, usof; 625 u32 period; 626 627 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); 628 multi = 1 + ((maxpacket >> 11) & 0x3); 629 maxpacket &= 0x7ff; 630 /* length of the data per uframe */ 631 maxpacket = multi * maxpacket; 632 633 numberofusofs = urb->transfer_buffer_length / maxpacket; 634 if (urb->transfer_buffer_length % maxpacket) 635 numberofusofs += 1; 636 637 usofmask = 1; 638 usof = 0; 639 for (i = 0; i < numberofusofs; i++) { 640 usof |= usofmask; 641 usofmask <<= 1; 642 } 643 644 if (urb->dev->speed != USB_SPEED_HIGH) { 645 /* split */ 646 ptd->dw5 = cpu_to_le32(0x1c); 647 648 if (qh->period >= 32) 649 period = qh->period / 2; 650 else 651 period = qh->period; 652 653 } else { 654 655 if (qh->period >= 8) 656 period = qh->period/8; 657 else 658 period = qh->period; 659 660 if (period >= 32) 661 period = 16; 662 663 if (qh->period >= 8) { 664 /* millisecond period */ 665 period = (period << 3); 666 } else { 667 /* usof based tranmsfers */ 668 /* minimum 4 usofs */ 669 usof = 0x11; 670 } 671 } 672 673 ptd->dw2 |= cpu_to_le32(period); 674 ptd->dw4 = cpu_to_le32(usof); 675} 676 677static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, 678 struct isp1760_qtd *qtd, struct urb *urb, 679 u32 payload, struct ptd *ptd) 680{ 681 transform_into_atl(priv, qh, qtd, urb, payload, ptd); 682 transform_add_int(priv, qh, qtd, urb, payload, ptd); 683} 684 685static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len, 686 u32 token) 687{ 688 int count; 689 690 qtd->data_buffer = databuffer; 691 qtd->packet_type = GET_QTD_TOKEN_TYPE(token); 692 qtd->toggle = GET_DATA_TOGGLE(token); 693 694 if (len > HC_ATL_PL_SIZE) 695 count = HC_ATL_PL_SIZE; 696 else 697 count = len; 698 699 qtd->length = count; 700 return count; 701} 702 703static int check_error(struct ptd *ptd) 704{ 705 int error = 0; 706 u32 dw3; 707 708 dw3 = le32_to_cpu(ptd->dw3); 709 if (dw3 & DW3_HALT_BIT) { 710 error = -EPIPE; 711 712 if (dw3 & DW3_ERROR_BIT) 713 pr_err("error bit is set in DW3\n"); 714 } 715 716 if (dw3 & DW3_QTD_ACTIVE) { 717 printk(KERN_ERR "transfer active bit is set DW3\n"); 718 printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf, 719 (le32_to_cpu(ptd->dw2) >> 25) & 0xf); 720 } 721 722 return error; 723} 724 725static void check_int_err_status(u32 dw4) 726{ 727 u32 i; 728 729 dw4 >>= 8; 730 731 for (i = 0; i < 8; i++) { 732 switch (dw4 & 0x7) { 733 case INT_UNDERRUN: 734 printk(KERN_ERR "ERROR: under run , %d\n", i); 735 break; 736 737 case INT_EXACT: 738 printk(KERN_ERR "ERROR: transaction error, %d\n", i); 739 break; 740 741 case INT_BABBLE: 742 printk(KERN_ERR "ERROR: babble error, %d\n", i); 743 break; 744 } 745 dw4 >>= 3; 746 } 747} 748 749static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv, 750 u32 payload) 751{ 752 u32 token; 753 struct usb_hcd *hcd = priv_to_hcd(priv); 754 755 token = qtd->packet_type; 756 757 if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) { 758 switch (token) { 759 case IN_PID: 760 break; 761 case OUT_PID: 762 case SETUP_PID: 763 priv_write_copy(priv, qtd->data_buffer, 764 hcd->regs + payload, 765 qtd->length); 766 } 767 } 768} 769 770static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload, 771 struct isp1760_hcd *priv, struct isp1760_qh *qh, 772 struct urb *urb, u32 slot, struct isp1760_qtd *qtd) 773{ 774 struct ptd ptd; 775 struct usb_hcd *hcd = priv_to_hcd(priv); 776 777 transform_into_atl(priv, qh, qtd, urb, payload, &ptd); 778 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd)); 779 enqueue_one_qtd(qtd, priv, payload); 780 781 priv->atl_ints[slot].urb = urb; 782 priv->atl_ints[slot].qh = qh; 783 priv->atl_ints[slot].qtd = qtd; 784 priv->atl_ints[slot].data_buffer = qtd->data_buffer; 785 priv->atl_ints[slot].payload = payload; 786 qtd->status |= URB_ENQUEUED | URB_TYPE_ATL; 787 qtd->status |= slot << 16; 788} 789 790static void enqueue_one_int_qtd(u32 int_regs, u32 payload, 791 struct isp1760_hcd *priv, struct isp1760_qh *qh, 792 struct urb *urb, u32 slot, struct isp1760_qtd *qtd) 793{ 794 struct ptd ptd; 795 struct usb_hcd *hcd = priv_to_hcd(priv); 796 797 transform_into_int(priv, qh, qtd, urb, payload, &ptd); 798 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd)); 799 enqueue_one_qtd(qtd, priv, payload); 800 801 priv->int_ints[slot].urb = urb; 802 priv->int_ints[slot].qh = qh; 803 priv->int_ints[slot].qtd = qtd; 804 priv->int_ints[slot].data_buffer = qtd->data_buffer; 805 priv->int_ints[slot].payload = payload; 806 qtd->status |= URB_ENQUEUED | URB_TYPE_INT; 807 qtd->status |= slot << 16; 808} 809 810static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, 811 struct isp1760_qtd *qtd) 812{ 813 struct isp1760_hcd *priv = hcd_to_priv(hcd); 814 u32 skip_map, or_map; 815 u32 queue_entry; 816 u32 slot; 817 u32 atl_regs, payload; 818 u32 buffstatus; 819 820 /* 821 * When this function is called from the interrupt handler to enqueue 822 * a follow-up packet, the SKIP register gets written and read back 823 * almost immediately. With ISP1761, this register requires a delay of 824 * 195ns between a write and subsequent read (see section 15.1.1.3). 825 */ 826 mmiowb(); 827 ndelay(195); 828 skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG); 829 830 BUG_ON(!skip_map); 831 slot = __ffs(skip_map); 832 queue_entry = 1 << slot; 833 834 atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd); 835 836 payload = alloc_mem(priv, qtd->length); 837 838 enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd); 839 840 or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 841 or_map |= queue_entry; 842 isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 843 844 skip_map &= ~queue_entry; 845 isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG); 846 847 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); 848 buffstatus |= ATL_BUFFER; 849 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); 850} 851 852static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, 853 struct isp1760_qtd *qtd) 854{ 855 struct isp1760_hcd *priv = hcd_to_priv(hcd); 856 u32 skip_map, or_map; 857 u32 queue_entry; 858 u32 slot; 859 u32 int_regs, payload; 860 u32 buffstatus; 861 862 /* 863 * When this function is called from the interrupt handler to enqueue 864 * a follow-up packet, the SKIP register gets written and read back 865 * almost immediately. With ISP1761, this register requires a delay of 866 * 195ns between a write and subsequent read (see section 15.1.1.3). 867 */ 868 mmiowb(); 869 ndelay(195); 870 skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG); 871 872 BUG_ON(!skip_map); 873 slot = __ffs(skip_map); 874 queue_entry = 1 << slot; 875 876 int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd); 877 878 payload = alloc_mem(priv, qtd->length); 879 880 enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd); 881 882 or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG); 883 or_map |= queue_entry; 884 isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG); 885 886 skip_map &= ~queue_entry; 887 isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG); 888 889 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); 890 buffstatus |= INT_BUFFER; 891 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); 892} 893 894static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status) 895__releases(priv->lock) 896__acquires(priv->lock) 897{ 898 if (!urb->unlinked) { 899 if (status == -EINPROGRESS) 900 status = 0; 901 } 902 903 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { 904 void *ptr; 905 for (ptr = urb->transfer_buffer; 906 ptr < urb->transfer_buffer + urb->transfer_buffer_length; 907 ptr += PAGE_SIZE) 908 flush_dcache_page(virt_to_page(ptr)); 909 } 910 911 /* complete() can reenter this HCD */ 912 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); 913 spin_unlock(&priv->lock); 914 usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status); 915 spin_lock(&priv->lock); 916} 917 918static void isp1760_qtd_free(struct isp1760_qtd *qtd) 919{ 920 kmem_cache_free(qtd_cachep, qtd); 921} 922 923static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd) 924{ 925 struct isp1760_qtd *tmp_qtd; 926 927 tmp_qtd = qtd->hw_next; 928 list_del(&qtd->qtd_list); 929 isp1760_qtd_free(qtd); 930 return tmp_qtd; 931} 932 933/* 934 * Remove this QTD from the QH list and free its memory. If this QTD 935 * isn't the last one than remove also his successor(s). 936 * Returns the QTD which is part of an new URB and should be enqueued. 937 */ 938static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd) 939{ 940 struct isp1760_qtd *tmp_qtd; 941 int last_one; 942 943 do { 944 tmp_qtd = qtd->hw_next; 945 last_one = qtd->status & URB_COMPLETE_NOTIFY; 946 list_del(&qtd->qtd_list); 947 isp1760_qtd_free(qtd); 948 qtd = tmp_qtd; 949 } while (!last_one && qtd); 950 951 return qtd; 952} 953 954static void do_atl_int(struct usb_hcd *usb_hcd) 955{ 956 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 957 u32 done_map, skip_map; 958 struct ptd ptd; 959 struct urb *urb = NULL; 960 u32 atl_regs_base; 961 u32 atl_regs; 962 u32 queue_entry; 963 u32 payload; 964 u32 length; 965 u32 or_map; 966 u32 status = -EINVAL; 967 int error; 968 struct isp1760_qtd *qtd; 969 struct isp1760_qh *qh; 970 u32 rl; 971 u32 nakcount; 972 973 done_map = isp1760_readl(usb_hcd->regs + 974 HC_ATL_PTD_DONEMAP_REG); 975 skip_map = isp1760_readl(usb_hcd->regs + 976 HC_ATL_PTD_SKIPMAP_REG); 977 978 or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 979 or_map &= ~done_map; 980 isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); 981 982 atl_regs_base = ATL_REGS_OFFSET; 983 while (done_map) { 984 u32 dw1; 985 u32 dw2; 986 u32 dw3; 987 988 status = 0; 989 990 queue_entry = __ffs(done_map); 991 done_map &= ~(1 << queue_entry); 992 skip_map |= 1 << queue_entry; 993 994 atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd); 995 996 urb = priv->atl_ints[queue_entry].urb; 997 qtd = priv->atl_ints[queue_entry].qtd; 998 qh = priv->atl_ints[queue_entry].qh; 999 payload = priv->atl_ints[queue_entry].payload; 1000 1001 if (!qh) { 1002 printk(KERN_ERR "qh is 0\n"); 1003 continue; 1004 } 1005 isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs + 1006 HC_MEMORY_REG); 1007 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + 1008 HC_MEMORY_REG); 1009 /* 1010 * write bank1 address twice to ensure the 90ns delay (time 1011 * between BANK0 write and the priv_read_copy() call is at 1012 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns) 1013 */ 1014 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + 1015 HC_MEMORY_REG); 1016 1017 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs + 1018 ISP_BANK(0), sizeof(ptd)); 1019 1020 dw1 = le32_to_cpu(ptd.dw1); 1021 dw2 = le32_to_cpu(ptd.dw2); 1022 dw3 = le32_to_cpu(ptd.dw3); 1023 rl = (dw2 >> 25) & 0x0f; 1024 nakcount = (dw3 >> 19) & 0xf; 1025 1026 /* Transfer Error, *but* active and no HALT -> reload */ 1027 if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) && 1028 !(dw3 & DW3_HALT_BIT)) { 1029 1030 1031 length = PTD_XFERRED_LENGTH(dw3); 1032 printk(KERN_ERR "Should reload now.... transfered %d " 1033 "of %zu\n", length, qtd->length); 1034 BUG(); 1035 } 1036 1037 if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) { 1038 u32 buffstatus; 1039 1040 /* 1041 * NAKs are handled in HW by the chip. Usually if the 1042 * device is not able to send data fast enough. 1043 * This happens mostly on slower hardware. 1044 */ 1045 printk(KERN_NOTICE "Reloading ptd %p/%p... qh %p read: " 1046 "%d of %zu done: %08x cur: %08x\n", qtd, 1047 urb, qh, PTD_XFERRED_LENGTH(dw3), 1048 qtd->length, done_map, 1049 (1 << queue_entry)); 1050 1051 /* RL counter = ERR counter */ 1052 dw3 &= ~(0xf << 19); 1053 dw3 |= rl << 19; 1054 dw3 &= ~(3 << (55 - 32)); 1055 dw3 |= ERR_COUNTER << (55 - 32); 1056 1057 /* 1058 * It is not needed to write skip map back because it 1059 * is unchanged. Just make sure that this entry is 1060 * unskipped once it gets written to the HW. 1061 */ 1062 skip_map &= ~(1 << queue_entry); 1063 or_map = isp1760_readl(usb_hcd->regs + 1064 HC_ATL_IRQ_MASK_OR_REG); 1065 or_map |= 1 << queue_entry; 1066 isp1760_writel(or_map, usb_hcd->regs + 1067 HC_ATL_IRQ_MASK_OR_REG); 1068 1069 ptd.dw3 = cpu_to_le32(dw3); 1070 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + 1071 atl_regs, sizeof(ptd)); 1072 1073 ptd.dw0 |= cpu_to_le32(PTD_VALID); 1074 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + 1075 atl_regs, sizeof(ptd)); 1076 1077 buffstatus = isp1760_readl(usb_hcd->regs + 1078 HC_BUFFER_STATUS_REG); 1079 buffstatus |= ATL_BUFFER; 1080 isp1760_writel(buffstatus, usb_hcd->regs + 1081 HC_BUFFER_STATUS_REG); 1082 continue; 1083 } 1084 1085 error = check_error(&ptd); 1086 if (error) { 1087 status = error; 1088 priv->atl_ints[queue_entry].qh->toggle = 0; 1089 priv->atl_ints[queue_entry].qh->ping = 0; 1090 urb->status = -EPIPE; 1091 1092 } else { 1093 if (usb_pipetype(urb->pipe) == PIPE_BULK) { 1094 priv->atl_ints[queue_entry].qh->toggle = dw3 & 1095 (1 << 25); 1096 priv->atl_ints[queue_entry].qh->ping = dw3 & 1097 (1 << 26); 1098 } 1099 } 1100 1101 length = PTD_XFERRED_LENGTH(dw3); 1102 if (length) { 1103 switch (DW1_GET_PID(dw1)) { 1104 case IN_PID: 1105 priv_read_copy(priv, 1106 priv->atl_ints[queue_entry].data_buffer, 1107 usb_hcd->regs + payload + ISP_BANK(1), 1108 length); 1109 1110 case OUT_PID: 1111 1112 urb->actual_length += length; 1113 1114 case SETUP_PID: 1115 break; 1116 } 1117 } 1118 1119 priv->atl_ints[queue_entry].data_buffer = NULL; 1120 priv->atl_ints[queue_entry].urb = NULL; 1121 priv->atl_ints[queue_entry].qtd = NULL; 1122 priv->atl_ints[queue_entry].qh = NULL; 1123 1124 free_mem(priv, payload); 1125 1126 isp1760_writel(skip_map, usb_hcd->regs + 1127 HC_ATL_PTD_SKIPMAP_REG); 1128 1129 if (urb->status == -EPIPE) { 1130 /* HALT was received */ 1131 1132 qtd = clean_up_qtdlist(qtd); 1133 isp1760_urb_done(priv, urb, urb->status); 1134 1135 } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) { 1136 /* short BULK received */ 1137 1138 if (urb->transfer_flags & URB_SHORT_NOT_OK) { 1139 urb->status = -EREMOTEIO; 1140 isp1760_dbg(priv, "short bulk, %d instead %zu " 1141 "with URB_SHORT_NOT_OK flag.\n", 1142 length, qtd->length); 1143 } 1144 1145 if (urb->status == -EINPROGRESS) 1146 urb->status = 0; 1147 1148 qtd = clean_up_qtdlist(qtd); 1149 1150 isp1760_urb_done(priv, urb, urb->status); 1151 1152 } else if (qtd->status & URB_COMPLETE_NOTIFY) { 1153 /* that was the last qtd of that URB */ 1154 1155 if (urb->status == -EINPROGRESS) 1156 urb->status = 0; 1157 1158 qtd = clean_this_qtd(qtd); 1159 isp1760_urb_done(priv, urb, urb->status); 1160 1161 } else { 1162 /* next QTD of this URB */ 1163 1164 qtd = clean_this_qtd(qtd); 1165 BUG_ON(!qtd); 1166 } 1167 1168 if (qtd) 1169 enqueue_an_ATL_packet(usb_hcd, qh, qtd); 1170 1171 skip_map = isp1760_readl(usb_hcd->regs + 1172 HC_ATL_PTD_SKIPMAP_REG); 1173 } 1174} 1175 1176static void do_intl_int(struct usb_hcd *usb_hcd) 1177{ 1178 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 1179 u32 done_map, skip_map; 1180 struct ptd ptd; 1181 struct urb *urb = NULL; 1182 u32 int_regs; 1183 u32 int_regs_base; 1184 u32 payload; 1185 u32 length; 1186 u32 or_map; 1187 int error; 1188 u32 queue_entry; 1189 struct isp1760_qtd *qtd; 1190 struct isp1760_qh *qh; 1191 1192 done_map = isp1760_readl(usb_hcd->regs + 1193 HC_INT_PTD_DONEMAP_REG); 1194 skip_map = isp1760_readl(usb_hcd->regs + 1195 HC_INT_PTD_SKIPMAP_REG); 1196 1197 or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); 1198 or_map &= ~done_map; 1199 isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); 1200 1201 int_regs_base = INT_REGS_OFFSET; 1202 1203 while (done_map) { 1204 u32 dw1; 1205 u32 dw3; 1206 1207 queue_entry = __ffs(done_map); 1208 done_map &= ~(1 << queue_entry); 1209 skip_map |= 1 << queue_entry; 1210 1211 int_regs = int_regs_base + queue_entry * sizeof(struct ptd); 1212 urb = priv->int_ints[queue_entry].urb; 1213 qtd = priv->int_ints[queue_entry].qtd; 1214 qh = priv->int_ints[queue_entry].qh; 1215 payload = priv->int_ints[queue_entry].payload; 1216 1217 if (!qh) { 1218 printk(KERN_ERR "(INT) qh is 0\n"); 1219 continue; 1220 } 1221 1222 isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs + 1223 HC_MEMORY_REG); 1224 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + 1225 HC_MEMORY_REG); 1226 /* 1227 * write bank1 address twice to ensure the 90ns delay (time 1228 * between BANK0 write and the priv_read_copy() call is at 1229 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns) 1230 */ 1231 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + 1232 HC_MEMORY_REG); 1233 1234 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs + 1235 ISP_BANK(0), sizeof(ptd)); 1236 dw1 = le32_to_cpu(ptd.dw1); 1237 dw3 = le32_to_cpu(ptd.dw3); 1238 check_int_err_status(le32_to_cpu(ptd.dw4)); 1239 1240 error = check_error(&ptd); 1241 if (error) { 1242 urb->status = -EPIPE; 1243 priv->int_ints[queue_entry].qh->toggle = 0; 1244 priv->int_ints[queue_entry].qh->ping = 0; 1245 1246 } else { 1247 priv->int_ints[queue_entry].qh->toggle = 1248 dw3 & (1 << 25); 1249 priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26); 1250 } 1251 1252 if (urb->dev->speed != USB_SPEED_HIGH) 1253 length = PTD_XFERRED_LENGTH_LO(dw3); 1254 else 1255 length = PTD_XFERRED_LENGTH(dw3); 1256 1257 if (length) { 1258 switch (DW1_GET_PID(dw1)) { 1259 case IN_PID: 1260 priv_read_copy(priv, 1261 priv->int_ints[queue_entry].data_buffer, 1262 usb_hcd->regs + payload + ISP_BANK(1), 1263 length); 1264 case OUT_PID: 1265 1266 urb->actual_length += length; 1267 1268 case SETUP_PID: 1269 break; 1270 } 1271 } 1272 1273 priv->int_ints[queue_entry].data_buffer = NULL; 1274 priv->int_ints[queue_entry].urb = NULL; 1275 priv->int_ints[queue_entry].qtd = NULL; 1276 priv->int_ints[queue_entry].qh = NULL; 1277 1278 isp1760_writel(skip_map, usb_hcd->regs + 1279 HC_INT_PTD_SKIPMAP_REG); 1280 free_mem(priv, payload); 1281 1282 if (urb->status == -EPIPE) { 1283 /* HALT received */ 1284 1285 qtd = clean_up_qtdlist(qtd); 1286 isp1760_urb_done(priv, urb, urb->status); 1287 1288 } else if (qtd->status & URB_COMPLETE_NOTIFY) { 1289 1290 if (urb->status == -EINPROGRESS) 1291 urb->status = 0; 1292 1293 qtd = clean_this_qtd(qtd); 1294 isp1760_urb_done(priv, urb, urb->status); 1295 1296 } else { 1297 /* next QTD of this URB */ 1298 1299 qtd = clean_this_qtd(qtd); 1300 BUG_ON(!qtd); 1301 } 1302 1303 if (qtd) 1304 enqueue_an_INT_packet(usb_hcd, qh, qtd); 1305 1306 skip_map = isp1760_readl(usb_hcd->regs + 1307 HC_INT_PTD_SKIPMAP_REG); 1308 } 1309} 1310 1311#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1312static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb, 1313 gfp_t flags) 1314{ 1315 struct isp1760_qh *qh; 1316 int is_input, type; 1317 1318 qh = isp1760_qh_alloc(priv, flags); 1319 if (!qh) 1320 return qh; 1321 1322 /* 1323 * init endpoint/device data for this QH 1324 */ 1325 is_input = usb_pipein(urb->pipe); 1326 type = usb_pipetype(urb->pipe); 1327 1328 if (type == PIPE_INTERRUPT) { 1329 1330 if (urb->dev->speed == USB_SPEED_HIGH) { 1331 1332 qh->period = urb->interval >> 3; 1333 if (qh->period == 0 && urb->interval != 1) { 1334 /* NOTE interval 2 or 4 uframes could work. 1335 * But interval 1 scheduling is simpler, and 1336 * includes high bandwidth. 1337 */ 1338 printk(KERN_ERR "intr period %d uframes, NYET!", 1339 urb->interval); 1340 qh_destroy(qh); 1341 return NULL; 1342 } 1343 } else { 1344 qh->period = urb->interval; 1345 } 1346 } 1347 1348 /* support for tt scheduling, and access to toggles */ 1349 qh->dev = urb->dev; 1350 1351 if (!usb_pipecontrol(urb->pipe)) 1352 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1353 1); 1354 return qh; 1355} 1356 1357/* 1358 * For control/bulk/interrupt, return QH with these TDs appended. 1359 * Allocates and initializes the QH if necessary. 1360 * Returns null if it can't allocate a QH it needs to. 1361 * If the QH has TDs (urbs) already, that's great. 1362 */ 1363static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv, 1364 struct urb *urb, struct list_head *qtd_list, int epnum, 1365 void **ptr) 1366{ 1367 struct isp1760_qh *qh; 1368 struct isp1760_qtd *qtd; 1369 struct isp1760_qtd *prev_qtd; 1370 1371 qh = (struct isp1760_qh *)*ptr; 1372 if (!qh) { 1373 /* can't sleep here, we have priv->lock... */ 1374 qh = qh_make(priv, urb, GFP_ATOMIC); 1375 if (!qh) 1376 return qh; 1377 *ptr = qh; 1378 } 1379 1380 qtd = list_entry(qtd_list->next, struct isp1760_qtd, 1381 qtd_list); 1382 if (!list_empty(&qh->qtd_list)) 1383 prev_qtd = list_entry(qh->qtd_list.prev, 1384 struct isp1760_qtd, qtd_list); 1385 else 1386 prev_qtd = NULL; 1387 1388 list_splice(qtd_list, qh->qtd_list.prev); 1389 if (prev_qtd) { 1390 BUG_ON(prev_qtd->hw_next); 1391 prev_qtd->hw_next = qtd; 1392 } 1393 1394 urb->hcpriv = qh; 1395 return qh; 1396} 1397 1398static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb, 1399 struct list_head *qtd_list) 1400{ 1401 struct list_head *entry, *temp; 1402 1403 list_for_each_safe(entry, temp, qtd_list) { 1404 struct isp1760_qtd *qtd; 1405 1406 qtd = list_entry(entry, struct isp1760_qtd, qtd_list); 1407 list_del(&qtd->qtd_list); 1408 isp1760_qtd_free(qtd); 1409 } 1410} 1411 1412static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb, 1413 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p) 1414{ 1415 struct isp1760_qtd *qtd; 1416 int epnum; 1417 unsigned long flags; 1418 struct isp1760_qh *qh = NULL; 1419 int rc; 1420 int qh_busy; 1421 1422 qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list); 1423 epnum = urb->ep->desc.bEndpointAddress; 1424 1425 spin_lock_irqsave(&priv->lock, flags); 1426 if (!HCD_HW_ACCESSIBLE(priv_to_hcd(priv))) { 1427 rc = -ESHUTDOWN; 1428 goto done; 1429 } 1430 rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb); 1431 if (rc) 1432 goto done; 1433 1434 qh = urb->ep->hcpriv; 1435 if (qh) 1436 qh_busy = !list_empty(&qh->qtd_list); 1437 else 1438 qh_busy = 0; 1439 1440 qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv); 1441 if (!qh) { 1442 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); 1443 rc = -ENOMEM; 1444 goto done; 1445 } 1446 1447 if (!qh_busy) 1448 p(priv_to_hcd(priv), qh, qtd); 1449 1450done: 1451 spin_unlock_irqrestore(&priv->lock, flags); 1452 if (!qh) 1453 qtd_list_free(priv, urb, qtd_list); 1454 return rc; 1455} 1456 1457static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv, 1458 gfp_t flags) 1459{ 1460 struct isp1760_qtd *qtd; 1461 1462 qtd = kmem_cache_zalloc(qtd_cachep, flags); 1463 if (qtd) 1464 INIT_LIST_HEAD(&qtd->qtd_list); 1465 1466 return qtd; 1467} 1468 1469/* 1470 * create a list of filled qtds for this URB; won't link into qh. 1471 */ 1472static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv, 1473 struct urb *urb, struct list_head *head, gfp_t flags) 1474{ 1475 struct isp1760_qtd *qtd, *qtd_prev; 1476 void *buf; 1477 int len, maxpacket; 1478 int is_input; 1479 u32 token; 1480 1481 /* 1482 * URBs map to sequences of QTDs: one logical transaction 1483 */ 1484 qtd = isp1760_qtd_alloc(priv, flags); 1485 if (!qtd) 1486 return NULL; 1487 1488 list_add_tail(&qtd->qtd_list, head); 1489 qtd->urb = urb; 1490 urb->status = -EINPROGRESS; 1491 1492 token = 0; 1493 /* for split transactions, SplitXState initialized to zero */ 1494 1495 len = urb->transfer_buffer_length; 1496 is_input = usb_pipein(urb->pipe); 1497 if (usb_pipecontrol(urb->pipe)) { 1498 /* SETUP pid */ 1499 qtd_fill(qtd, urb->setup_packet, 1500 sizeof(struct usb_ctrlrequest), 1501 token | SETUP_PID); 1502 1503 /* ... and always at least one more pid */ 1504 token ^= DATA_TOGGLE; 1505 qtd_prev = qtd; 1506 qtd = isp1760_qtd_alloc(priv, flags); 1507 if (!qtd) 1508 goto cleanup; 1509 qtd->urb = urb; 1510 qtd_prev->hw_next = qtd; 1511 list_add_tail(&qtd->qtd_list, head); 1512 1513 /* for zero length DATA stages, STATUS is always IN */ 1514 if (len == 0) 1515 token |= IN_PID; 1516 } 1517 1518 /* 1519 * data transfer stage: buffer setup 1520 */ 1521 buf = urb->transfer_buffer; 1522 1523 if (is_input) 1524 token |= IN_PID; 1525 else 1526 token |= OUT_PID; 1527 1528 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); 1529 1530 /* 1531 * buffer gets wrapped in one or more qtds; 1532 * last one may be "short" (including zero len) 1533 * and may serve as a control status ack 1534 */ 1535 for (;;) { 1536 int this_qtd_len; 1537 1538 if (!buf && len) { 1539 printk(KERN_ERR "buf is null, dma is %08lx len is %d\n", 1540 (long unsigned)urb->transfer_dma, len); 1541 WARN_ON(1); 1542 } 1543 1544 this_qtd_len = qtd_fill(qtd, buf, len, token); 1545 len -= this_qtd_len; 1546 buf += this_qtd_len; 1547 1548 /* qh makes control packets use qtd toggle; maybe switch it */ 1549 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) 1550 token ^= DATA_TOGGLE; 1551 1552 if (len <= 0) 1553 break; 1554 1555 qtd_prev = qtd; 1556 qtd = isp1760_qtd_alloc(priv, flags); 1557 if (!qtd) 1558 goto cleanup; 1559 qtd->urb = urb; 1560 qtd_prev->hw_next = qtd; 1561 list_add_tail(&qtd->qtd_list, head); 1562 } 1563 1564 /* 1565 * control requests may need a terminating data "status" ack; 1566 * bulk ones may need a terminating short packet (zero length). 1567 */ 1568 if (urb->transfer_buffer_length != 0) { 1569 int one_more = 0; 1570 1571 if (usb_pipecontrol(urb->pipe)) { 1572 one_more = 1; 1573 /* "in" <--> "out" */ 1574 token ^= IN_PID; 1575 /* force DATA1 */ 1576 token |= DATA_TOGGLE; 1577 } else if (usb_pipebulk(urb->pipe) 1578 && (urb->transfer_flags & URB_ZERO_PACKET) 1579 && !(urb->transfer_buffer_length % maxpacket)) { 1580 one_more = 1; 1581 } 1582 if (one_more) { 1583 qtd_prev = qtd; 1584 qtd = isp1760_qtd_alloc(priv, flags); 1585 if (!qtd) 1586 goto cleanup; 1587 qtd->urb = urb; 1588 qtd_prev->hw_next = qtd; 1589 list_add_tail(&qtd->qtd_list, head); 1590 1591 /* never any data in such packets */ 1592 qtd_fill(qtd, NULL, 0, token); 1593 } 1594 } 1595 1596 qtd->status = URB_COMPLETE_NOTIFY; 1597 return head; 1598 1599cleanup: 1600 qtd_list_free(priv, urb, head); 1601 return NULL; 1602} 1603 1604static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 1605 gfp_t mem_flags) 1606{ 1607 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1608 struct list_head qtd_list; 1609 packet_enqueue *pe; 1610 1611 INIT_LIST_HEAD(&qtd_list); 1612 1613 switch (usb_pipetype(urb->pipe)) { 1614 case PIPE_CONTROL: 1615 case PIPE_BULK: 1616 1617 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) 1618 return -ENOMEM; 1619 pe = enqueue_an_ATL_packet; 1620 break; 1621 1622 case PIPE_INTERRUPT: 1623 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) 1624 return -ENOMEM; 1625 pe = enqueue_an_INT_packet; 1626 break; 1627 1628 case PIPE_ISOCHRONOUS: 1629 printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n"); 1630 default: 1631 return -EPIPE; 1632 } 1633 1634 return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe); 1635} 1636 1637static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 1638 int status) 1639{ 1640 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1641 struct inter_packet_info *ints; 1642 u32 i; 1643 u32 reg_base, or_reg, skip_reg; 1644 unsigned long flags; 1645 struct ptd ptd; 1646 packet_enqueue *pe; 1647 1648 switch (usb_pipetype(urb->pipe)) { 1649 case PIPE_ISOCHRONOUS: 1650 return -EPIPE; 1651 break; 1652 1653 case PIPE_INTERRUPT: 1654 ints = priv->int_ints; 1655 reg_base = INT_REGS_OFFSET; 1656 or_reg = HC_INT_IRQ_MASK_OR_REG; 1657 skip_reg = HC_INT_PTD_SKIPMAP_REG; 1658 pe = enqueue_an_INT_packet; 1659 break; 1660 1661 default: 1662 ints = priv->atl_ints; 1663 reg_base = ATL_REGS_OFFSET; 1664 or_reg = HC_ATL_IRQ_MASK_OR_REG; 1665 skip_reg = HC_ATL_PTD_SKIPMAP_REG; 1666 pe = enqueue_an_ATL_packet; 1667 break; 1668 } 1669 1670 memset(&ptd, 0, sizeof(ptd)); 1671 spin_lock_irqsave(&priv->lock, flags); 1672 1673 for (i = 0; i < 32; i++) { 1674 if (ints->urb == urb) { 1675 u32 skip_map; 1676 u32 or_map; 1677 struct isp1760_qtd *qtd; 1678 struct isp1760_qh *qh = ints->qh; 1679 1680 skip_map = isp1760_readl(hcd->regs + skip_reg); 1681 skip_map |= 1 << i; 1682 isp1760_writel(skip_map, hcd->regs + skip_reg); 1683 1684 or_map = isp1760_readl(hcd->regs + or_reg); 1685 or_map &= ~(1 << i); 1686 isp1760_writel(or_map, hcd->regs + or_reg); 1687 1688 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base 1689 + i * sizeof(ptd), sizeof(ptd)); 1690 qtd = ints->qtd; 1691 qtd = clean_up_qtdlist(qtd); 1692 1693 free_mem(priv, ints->payload); 1694 1695 ints->urb = NULL; 1696 ints->qh = NULL; 1697 ints->qtd = NULL; 1698 ints->data_buffer = NULL; 1699 ints->payload = 0; 1700 1701 isp1760_urb_done(priv, urb, status); 1702 if (qtd) 1703 pe(hcd, qh, qtd); 1704 break; 1705 1706 } else if (ints->qtd) { 1707 struct isp1760_qtd *qtd, *prev_qtd = ints->qtd; 1708 1709 for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) { 1710 if (qtd->urb == urb) { 1711 prev_qtd->hw_next = clean_up_qtdlist(qtd); 1712 isp1760_urb_done(priv, urb, status); 1713 break; 1714 } 1715 prev_qtd = qtd; 1716 } 1717 /* we found the urb before the end of the list */ 1718 if (qtd) 1719 break; 1720 } 1721 ints++; 1722 } 1723 1724 spin_unlock_irqrestore(&priv->lock, flags); 1725 return 0; 1726} 1727 1728static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd) 1729{ 1730 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 1731 u32 imask; 1732 irqreturn_t irqret = IRQ_NONE; 1733 1734 spin_lock(&priv->lock); 1735 1736 if (!(usb_hcd->state & HC_STATE_RUNNING)) 1737 goto leave; 1738 1739 imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG); 1740 if (unlikely(!imask)) 1741 goto leave; 1742 1743 isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG); 1744 if (imask & HC_ATL_INT) 1745 do_atl_int(usb_hcd); 1746 1747 if (imask & HC_INTL_INT) 1748 do_intl_int(usb_hcd); 1749 1750 irqret = IRQ_HANDLED; 1751leave: 1752 spin_unlock(&priv->lock); 1753 return irqret; 1754} 1755 1756static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) 1757{ 1758 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1759 u32 temp, status = 0; 1760 u32 mask; 1761 int retval = 1; 1762 unsigned long flags; 1763 1764 /* if !USB_SUSPEND, root hub timers won't get shut down ... */ 1765 if (!HC_IS_RUNNING(hcd->state)) 1766 return 0; 1767 1768 /* init status to no-changes */ 1769 buf[0] = 0; 1770 mask = PORT_CSC; 1771 1772 spin_lock_irqsave(&priv->lock, flags); 1773 temp = isp1760_readl(hcd->regs + HC_PORTSC1); 1774 1775 if (temp & PORT_OWNER) { 1776 if (temp & PORT_CSC) { 1777 temp &= ~PORT_CSC; 1778 isp1760_writel(temp, hcd->regs + HC_PORTSC1); 1779 goto done; 1780 } 1781 } 1782 1783 /* 1784 * Return status information even for ports with OWNER set. 1785 * Otherwise khubd wouldn't see the disconnect event when a 1786 * high-speed device is switched over to the companion 1787 * controller by the user. 1788 */ 1789 1790 if ((temp & mask) != 0 1791 || ((temp & PORT_RESUME) != 0 1792 && time_after_eq(jiffies, 1793 priv->reset_done))) { 1794 buf [0] |= 1 << (0 + 1); 1795 status = STS_PCD; 1796 } 1797done: 1798 spin_unlock_irqrestore(&priv->lock, flags); 1799 return status ? retval : 0; 1800} 1801 1802static void isp1760_hub_descriptor(struct isp1760_hcd *priv, 1803 struct usb_hub_descriptor *desc) 1804{ 1805 int ports = HCS_N_PORTS(priv->hcs_params); 1806 u16 temp; 1807 1808 desc->bDescriptorType = 0x29; 1809 /* priv 1.0, 2.3.9 says 20ms max */ 1810 desc->bPwrOn2PwrGood = 10; 1811 desc->bHubContrCurrent = 0; 1812 1813 desc->bNbrPorts = ports; 1814 temp = 1 + (ports / 8); 1815 desc->bDescLength = 7 + 2 * temp; 1816 1817 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 1818 memset(&desc->bitmap[0], 0, temp); 1819 memset(&desc->bitmap[temp], 0xff, temp); 1820 1821 /* per-port overcurrent reporting */ 1822 temp = 0x0008; 1823 if (HCS_PPC(priv->hcs_params)) 1824 /* per-port power control */ 1825 temp |= 0x0001; 1826 else 1827 /* no power switching */ 1828 temp |= 0x0002; 1829 desc->wHubCharacteristics = cpu_to_le16(temp); 1830} 1831 1832#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) 1833 1834static int check_reset_complete(struct isp1760_hcd *priv, int index, 1835 u32 __iomem *status_reg, int port_status) 1836{ 1837 if (!(port_status & PORT_CONNECT)) 1838 return port_status; 1839 1840 /* if reset finished and it's still not enabled -- handoff */ 1841 if (!(port_status & PORT_PE)) { 1842 1843 printk(KERN_ERR "port %d full speed --> companion\n", 1844 index + 1); 1845 1846 port_status |= PORT_OWNER; 1847 port_status &= ~PORT_RWC_BITS; 1848 isp1760_writel(port_status, status_reg); 1849 1850 } else 1851 printk(KERN_ERR "port %d high speed\n", index + 1); 1852 1853 return port_status; 1854} 1855 1856static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, 1857 u16 wValue, u16 wIndex, char *buf, u16 wLength) 1858{ 1859 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1860 int ports = HCS_N_PORTS(priv->hcs_params); 1861 u32 __iomem *status_reg = hcd->regs + HC_PORTSC1; 1862 u32 temp, status; 1863 unsigned long flags; 1864 int retval = 0; 1865 unsigned selector; 1866 1867 1868 spin_lock_irqsave(&priv->lock, flags); 1869 switch (typeReq) { 1870 case ClearHubFeature: 1871 switch (wValue) { 1872 case C_HUB_LOCAL_POWER: 1873 case C_HUB_OVER_CURRENT: 1874 /* no hub-wide feature/status flags */ 1875 break; 1876 default: 1877 goto error; 1878 } 1879 break; 1880 case ClearPortFeature: 1881 if (!wIndex || wIndex > ports) 1882 goto error; 1883 wIndex--; 1884 temp = isp1760_readl(status_reg); 1885 1886 /* 1887 * Even if OWNER is set, so the port is owned by the 1888 * companion controller, khubd needs to be able to clear 1889 * the port-change status bits (especially 1890 * USB_PORT_STAT_C_CONNECTION). 1891 */ 1892 1893 switch (wValue) { 1894 case USB_PORT_FEAT_ENABLE: 1895 isp1760_writel(temp & ~PORT_PE, status_reg); 1896 break; 1897 case USB_PORT_FEAT_C_ENABLE: 1898 break; 1899 case USB_PORT_FEAT_SUSPEND: 1900 if (temp & PORT_RESET) 1901 goto error; 1902 1903 if (temp & PORT_SUSPEND) { 1904 if ((temp & PORT_PE) == 0) 1905 goto error; 1906 /* resume signaling for 20 msec */ 1907 temp &= ~(PORT_RWC_BITS); 1908 isp1760_writel(temp | PORT_RESUME, 1909 status_reg); 1910 priv->reset_done = jiffies + 1911 msecs_to_jiffies(20); 1912 } 1913 break; 1914 case USB_PORT_FEAT_C_SUSPEND: 1915 /* we auto-clear this feature */ 1916 break; 1917 case USB_PORT_FEAT_POWER: 1918 if (HCS_PPC(priv->hcs_params)) 1919 isp1760_writel(temp & ~PORT_POWER, status_reg); 1920 break; 1921 case USB_PORT_FEAT_C_CONNECTION: 1922 isp1760_writel(temp | PORT_CSC, 1923 status_reg); 1924 break; 1925 case USB_PORT_FEAT_C_OVER_CURRENT: 1926 break; 1927 case USB_PORT_FEAT_C_RESET: 1928 /* GetPortStatus clears reset */ 1929 break; 1930 default: 1931 goto error; 1932 } 1933 isp1760_readl(hcd->regs + HC_USBCMD); 1934 break; 1935 case GetHubDescriptor: 1936 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) 1937 buf); 1938 break; 1939 case GetHubStatus: 1940 /* no hub-wide feature/status flags */ 1941 memset(buf, 0, 4); 1942 break; 1943 case GetPortStatus: 1944 if (!wIndex || wIndex > ports) 1945 goto error; 1946 wIndex--; 1947 status = 0; 1948 temp = isp1760_readl(status_reg); 1949 1950 /* wPortChange bits */ 1951 if (temp & PORT_CSC) 1952 status |= USB_PORT_STAT_C_CONNECTION << 16; 1953 1954 1955 /* whoever resumes must GetPortStatus to complete it!! */ 1956 if (temp & PORT_RESUME) { 1957 printk(KERN_ERR "Port resume should be skipped.\n"); 1958 1959 /* Remote Wakeup received? */ 1960 if (!priv->reset_done) { 1961 /* resume signaling for 20 msec */ 1962 priv->reset_done = jiffies 1963 + msecs_to_jiffies(20); 1964 /* check the port again */ 1965 mod_timer(&priv_to_hcd(priv)->rh_timer, 1966 priv->reset_done); 1967 } 1968 1969 /* resume completed? */ 1970 else if (time_after_eq(jiffies, 1971 priv->reset_done)) { 1972 status |= USB_PORT_STAT_C_SUSPEND << 16; 1973 priv->reset_done = 0; 1974 1975 /* stop resume signaling */ 1976 temp = isp1760_readl(status_reg); 1977 isp1760_writel( 1978 temp & ~(PORT_RWC_BITS | PORT_RESUME), 1979 status_reg); 1980 retval = handshake(priv, status_reg, 1981 PORT_RESUME, 0, 2000 /* 2msec */); 1982 if (retval != 0) { 1983 isp1760_err(priv, 1984 "port %d resume error %d\n", 1985 wIndex + 1, retval); 1986 goto error; 1987 } 1988 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); 1989 } 1990 } 1991 1992 /* whoever resets must GetPortStatus to complete it!! */ 1993 if ((temp & PORT_RESET) 1994 && time_after_eq(jiffies, 1995 priv->reset_done)) { 1996 status |= USB_PORT_STAT_C_RESET << 16; 1997 priv->reset_done = 0; 1998 1999 /* force reset to complete */ 2000 isp1760_writel(temp & ~PORT_RESET, 2001 status_reg); 2002 /* REVISIT: some hardware needs 550+ usec to clear 2003 * this bit; seems too long to spin routinely... 2004 */ 2005 retval = handshake(priv, status_reg, 2006 PORT_RESET, 0, 750); 2007 if (retval != 0) { 2008 isp1760_err(priv, "port %d reset error %d\n", 2009 wIndex + 1, retval); 2010 goto error; 2011 } 2012 2013 /* see what we found out */ 2014 temp = check_reset_complete(priv, wIndex, status_reg, 2015 isp1760_readl(status_reg)); 2016 } 2017 /* 2018 * Even if OWNER is set, there's no harm letting khubd 2019 * see the wPortStatus values (they should all be 0 except 2020 * for PORT_POWER anyway). 2021 */ 2022 2023 if (temp & PORT_OWNER) 2024 printk(KERN_ERR "Warning: PORT_OWNER is set\n"); 2025 2026 if (temp & PORT_CONNECT) { 2027 status |= USB_PORT_STAT_CONNECTION; 2028 /* status may be from integrated TT */ 2029 status |= ehci_port_speed(priv, temp); 2030 } 2031 if (temp & PORT_PE) 2032 status |= USB_PORT_STAT_ENABLE; 2033 if (temp & (PORT_SUSPEND|PORT_RESUME)) 2034 status |= USB_PORT_STAT_SUSPEND; 2035 if (temp & PORT_RESET) 2036 status |= USB_PORT_STAT_RESET; 2037 if (temp & PORT_POWER) 2038 status |= USB_PORT_STAT_POWER; 2039 2040 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 2041 break; 2042 case SetHubFeature: 2043 switch (wValue) { 2044 case C_HUB_LOCAL_POWER: 2045 case C_HUB_OVER_CURRENT: 2046 /* no hub-wide feature/status flags */ 2047 break; 2048 default: 2049 goto error; 2050 } 2051 break; 2052 case SetPortFeature: 2053 selector = wIndex >> 8; 2054 wIndex &= 0xff; 2055 if (!wIndex || wIndex > ports) 2056 goto error; 2057 wIndex--; 2058 temp = isp1760_readl(status_reg); 2059 if (temp & PORT_OWNER) 2060 break; 2061 2062/* temp &= ~PORT_RWC_BITS; */ 2063 switch (wValue) { 2064 case USB_PORT_FEAT_ENABLE: 2065 isp1760_writel(temp | PORT_PE, status_reg); 2066 break; 2067 2068 case USB_PORT_FEAT_SUSPEND: 2069 if ((temp & PORT_PE) == 0 2070 || (temp & PORT_RESET) != 0) 2071 goto error; 2072 2073 isp1760_writel(temp | PORT_SUSPEND, status_reg); 2074 break; 2075 case USB_PORT_FEAT_POWER: 2076 if (HCS_PPC(priv->hcs_params)) 2077 isp1760_writel(temp | PORT_POWER, 2078 status_reg); 2079 break; 2080 case USB_PORT_FEAT_RESET: 2081 if (temp & PORT_RESUME) 2082 goto error; 2083 /* line status bits may report this as low speed, 2084 * which can be fine if this root hub has a 2085 * transaction translator built in. 2086 */ 2087 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT 2088 && PORT_USB11(temp)) { 2089 temp |= PORT_OWNER; 2090 } else { 2091 temp |= PORT_RESET; 2092 temp &= ~PORT_PE; 2093 2094 /* 2095 * caller must wait, then call GetPortStatus 2096 * usb 2.0 spec says 50 ms resets on root 2097 */ 2098 priv->reset_done = jiffies + 2099 msecs_to_jiffies(50); 2100 } 2101 isp1760_writel(temp, status_reg); 2102 break; 2103 default: 2104 goto error; 2105 } 2106 isp1760_readl(hcd->regs + HC_USBCMD); 2107 break; 2108 2109 default: 2110error: 2111 /* "stall" on error */ 2112 retval = -EPIPE; 2113 } 2114 spin_unlock_irqrestore(&priv->lock, flags); 2115 return retval; 2116} 2117 2118static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd, 2119 struct usb_host_endpoint *ep) 2120{ 2121 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); 2122 struct isp1760_qh *qh; 2123 struct isp1760_qtd *qtd; 2124 unsigned long flags; 2125 2126 spin_lock_irqsave(&priv->lock, flags); 2127 qh = ep->hcpriv; 2128 if (!qh) 2129 goto out; 2130 2131 ep->hcpriv = NULL; 2132 do { 2133 /* more than entry might get removed */ 2134 if (list_empty(&qh->qtd_list)) 2135 break; 2136 2137 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd, 2138 qtd_list); 2139 2140 if (qtd->status & URB_ENQUEUED) { 2141 2142 spin_unlock_irqrestore(&priv->lock, flags); 2143 isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET); 2144 spin_lock_irqsave(&priv->lock, flags); 2145 } else { 2146 struct urb *urb; 2147 2148 urb = qtd->urb; 2149 clean_up_qtdlist(qtd); 2150 isp1760_urb_done(priv, urb, -ECONNRESET); 2151 } 2152 } while (1); 2153 2154 qh_destroy(qh); 2155 /* remove requests and leak them. 2156 * ATL are pretty fast done, INT could take a while... 2157 * The latter shoule be removed 2158 */ 2159out: 2160 spin_unlock_irqrestore(&priv->lock, flags); 2161} 2162 2163static int isp1760_get_frame(struct usb_hcd *hcd) 2164{ 2165 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2166 u32 fr; 2167 2168 fr = isp1760_readl(hcd->regs + HC_FRINDEX); 2169 return (fr >> 3) % priv->periodic_size; 2170} 2171 2172static void isp1760_stop(struct usb_hcd *hcd) 2173{ 2174 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2175 u32 temp; 2176 2177 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, 2178 NULL, 0); 2179 mdelay(20); 2180 2181 spin_lock_irq(&priv->lock); 2182 ehci_reset(priv); 2183 /* Disable IRQ */ 2184 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); 2185 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); 2186 spin_unlock_irq(&priv->lock); 2187 2188 isp1760_writel(0, hcd->regs + HC_CONFIGFLAG); 2189} 2190 2191static void isp1760_shutdown(struct usb_hcd *hcd) 2192{ 2193 u32 command, temp; 2194 2195 isp1760_stop(hcd); 2196 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); 2197 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); 2198 2199 command = isp1760_readl(hcd->regs + HC_USBCMD); 2200 command &= ~CMD_RUN; 2201 isp1760_writel(command, hcd->regs + HC_USBCMD); 2202} 2203 2204static const struct hc_driver isp1760_hc_driver = { 2205 .description = "isp1760-hcd", 2206 .product_desc = "NXP ISP1760 USB Host Controller", 2207 .hcd_priv_size = sizeof(struct isp1760_hcd), 2208 .irq = isp1760_irq, 2209 .flags = HCD_MEMORY | HCD_USB2, 2210 .reset = isp1760_hc_setup, 2211 .start = isp1760_run, 2212 .stop = isp1760_stop, 2213 .shutdown = isp1760_shutdown, 2214 .urb_enqueue = isp1760_urb_enqueue, 2215 .urb_dequeue = isp1760_urb_dequeue, 2216 .endpoint_disable = isp1760_endpoint_disable, 2217 .get_frame_number = isp1760_get_frame, 2218 .hub_status_data = isp1760_hub_status_data, 2219 .hub_control = isp1760_hub_control, 2220}; 2221 2222int __init init_kmem_once(void) 2223{ 2224 qtd_cachep = kmem_cache_create("isp1760_qtd", 2225 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | 2226 SLAB_MEM_SPREAD, NULL); 2227 2228 if (!qtd_cachep) 2229 return -ENOMEM; 2230 2231 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), 2232 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); 2233 2234 if (!qh_cachep) { 2235 kmem_cache_destroy(qtd_cachep); 2236 return -ENOMEM; 2237 } 2238 2239 return 0; 2240} 2241 2242void deinit_kmem_cache(void) 2243{ 2244 kmem_cache_destroy(qtd_cachep); 2245 kmem_cache_destroy(qh_cachep); 2246} 2247 2248struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, 2249 int irq, unsigned long irqflags, 2250 struct device *dev, const char *busname, 2251 unsigned int devflags) 2252{ 2253 struct usb_hcd *hcd; 2254 struct isp1760_hcd *priv; 2255 int ret; 2256 2257 if (usb_disabled()) 2258 return ERR_PTR(-ENODEV); 2259 2260 /* prevent usb-core allocating DMA pages */ 2261 dev->dma_mask = NULL; 2262 2263 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); 2264 if (!hcd) 2265 return ERR_PTR(-ENOMEM); 2266 2267 priv = hcd_to_priv(hcd); 2268 priv->devflags = devflags; 2269 init_memory(priv); 2270 hcd->regs = ioremap(res_start, res_len); 2271 if (!hcd->regs) { 2272 ret = -EIO; 2273 goto err_put; 2274 } 2275 2276 hcd->irq = irq; 2277 hcd->rsrc_start = res_start; 2278 hcd->rsrc_len = res_len; 2279 2280 ret = usb_add_hcd(hcd, irq, irqflags); 2281 if (ret) 2282 goto err_unmap; 2283 2284 return hcd; 2285 2286err_unmap: 2287 iounmap(hcd->regs); 2288 2289err_put: 2290 usb_put_hcd(hcd); 2291 2292 return ERR_PTR(ret); 2293} 2294 2295MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP"); 2296MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>"); 2297MODULE_LICENSE("GPL v2"); 2298