1/* 2 * Support for the Tundra TSI148 VME-PCI Bridge Chip 3 * 4 * Author: Martyn Welch <martyn.welch@ge.com> 5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. 6 * 7 * Based on work by Tom Armistead and Ajit Prem 8 * Copyright 2004 Motorola Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16#include <linux/module.h> 17#include <linux/moduleparam.h> 18#include <linux/mm.h> 19#include <linux/types.h> 20#include <linux/errno.h> 21#include <linux/proc_fs.h> 22#include <linux/pci.h> 23#include <linux/poll.h> 24#include <linux/dma-mapping.h> 25#include <linux/interrupt.h> 26#include <linux/spinlock.h> 27#include <linux/sched.h> 28#include <linux/slab.h> 29#include <linux/time.h> 30#include <linux/io.h> 31#include <linux/uaccess.h> 32 33#include "../vme.h" 34#include "../vme_bridge.h" 35#include "vme_tsi148.h" 36 37static int __init tsi148_init(void); 38static int tsi148_probe(struct pci_dev *, const struct pci_device_id *); 39static void tsi148_remove(struct pci_dev *); 40static void __exit tsi148_exit(void); 41 42 43/* Module parameter */ 44static int err_chk; 45static int geoid; 46 47static char driver_name[] = "vme_tsi148"; 48 49static const struct pci_device_id tsi148_ids[] = { 50 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) }, 51 { }, 52}; 53 54static struct pci_driver tsi148_driver = { 55 .name = driver_name, 56 .id_table = tsi148_ids, 57 .probe = tsi148_probe, 58 .remove = tsi148_remove, 59}; 60 61static void reg_join(unsigned int high, unsigned int low, 62 unsigned long long *variable) 63{ 64 *variable = (unsigned long long)high << 32; 65 *variable |= (unsigned long long)low; 66} 67 68static void reg_split(unsigned long long variable, unsigned int *high, 69 unsigned int *low) 70{ 71 *low = (unsigned int)variable & 0xFFFFFFFF; 72 *high = (unsigned int)(variable >> 32); 73} 74 75/* 76 * Wakes up DMA queue. 77 */ 78static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, 79 int channel_mask) 80{ 81 u32 serviced = 0; 82 83 if (channel_mask & TSI148_LCSR_INTS_DMA0S) { 84 wake_up(&(bridge->dma_queue[0])); 85 serviced |= TSI148_LCSR_INTC_DMA0C; 86 } 87 if (channel_mask & TSI148_LCSR_INTS_DMA1S) { 88 wake_up(&(bridge->dma_queue[1])); 89 serviced |= TSI148_LCSR_INTC_DMA1C; 90 } 91 92 return serviced; 93} 94 95/* 96 * Wake up location monitor queue 97 */ 98static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) 99{ 100 int i; 101 u32 serviced = 0; 102 103 for (i = 0; i < 4; i++) { 104 if (stat & TSI148_LCSR_INTS_LMS[i]) { 105 /* We only enable interrupts if the callback is set */ 106 bridge->lm_callback[i](i); 107 serviced |= TSI148_LCSR_INTC_LMC[i]; 108 } 109 } 110 111 return serviced; 112} 113 114static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat) 115{ 116 int i; 117 u32 val; 118 u32 serviced = 0; 119 struct tsi148_driver *bridge; 120 121 bridge = tsi148_bridge->driver_priv; 122 123 for (i = 0; i < 4; i++) { 124 if (stat & TSI148_LCSR_INTS_MBS[i]) { 125 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); 126 dev_err(tsi148_bridge->parent, "VME Mailbox %d received" 127 ": 0x%x\n", i, val); 128 serviced |= TSI148_LCSR_INTC_MBC[i]; 129 } 130 } 131 132 return serviced; 133} 134 135/* 136 * Display error & status message when PERR (PCI) exception interrupt occurs. 137 */ 138static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge) 139{ 140 struct tsi148_driver *bridge; 141 142 bridge = tsi148_bridge->driver_priv; 143 144 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, " 145 "attributes: %08x\n", 146 ioread32be(bridge->base + TSI148_LCSR_EDPAU), 147 ioread32be(bridge->base + TSI148_LCSR_EDPAL), 148 ioread32be(bridge->base + TSI148_LCSR_EDPAT)); 149 150 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split " 151 "completion reg: %08x\n", 152 ioread32be(bridge->base + TSI148_LCSR_EDPXA), 153 ioread32be(bridge->base + TSI148_LCSR_EDPXS)); 154 155 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); 156 157 return TSI148_LCSR_INTC_PERRC; 158} 159 160/* 161 * Save address and status when VME error interrupt occurs. 162 */ 163static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) 164{ 165 unsigned int error_addr_high, error_addr_low; 166 unsigned long long error_addr; 167 u32 error_attrib; 168 struct vme_bus_error *error; 169 struct tsi148_driver *bridge; 170 171 bridge = tsi148_bridge->driver_priv; 172 173 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); 174 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); 175 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); 176 177 reg_join(error_addr_high, error_addr_low, &error_addr); 178 179 /* Check for exception register overflow (we have lost error data) */ 180 if (error_attrib & TSI148_LCSR_VEAT_VEOF) { 181 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow " 182 "Occurred\n"); 183 } 184 185 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC); 186 if (error) { 187 error->address = error_addr; 188 error->attributes = error_attrib; 189 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors)); 190 } else { 191 dev_err(tsi148_bridge->parent, "Unable to alloc memory for " 192 "VMEbus Error reporting\n"); 193 dev_err(tsi148_bridge->parent, "VME Bus Error at address: " 194 "0x%llx, attributes: %08x\n", error_addr, error_attrib); 195 } 196 197 /* Clear Status */ 198 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); 199 200 return TSI148_LCSR_INTC_VERRC; 201} 202 203/* 204 * Wake up IACK queue. 205 */ 206static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) 207{ 208 wake_up(&(bridge->iack_queue)); 209 210 return TSI148_LCSR_INTC_IACKC; 211} 212 213/* 214 * Calling VME bus interrupt callback if provided. 215 */ 216static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, 217 u32 stat) 218{ 219 int vec, i, serviced = 0; 220 struct tsi148_driver *bridge; 221 222 bridge = tsi148_bridge->driver_priv; 223 224 for (i = 7; i > 0; i--) { 225 if (stat & (1 << i)) { 226 /* 227 * Note: Even though the registers are defined as 228 * 32-bits in the spec, we only want to issue 8-bit 229 * IACK cycles on the bus, read from offset 3. 230 */ 231 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); 232 233 vme_irq_handler(tsi148_bridge, i, vec); 234 235 serviced |= (1 << i); 236 } 237 } 238 239 return serviced; 240} 241 242/* 243 * Top level interrupt handler. Clears appropriate interrupt status bits and 244 * then calls appropriate sub handler(s). 245 */ 246static irqreturn_t tsi148_irqhandler(int irq, void *ptr) 247{ 248 u32 stat, enable, serviced = 0; 249 struct vme_bridge *tsi148_bridge; 250 struct tsi148_driver *bridge; 251 252 tsi148_bridge = ptr; 253 254 bridge = tsi148_bridge->driver_priv; 255 256 /* Determine which interrupts are unmasked and set */ 257 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); 258 stat = ioread32be(bridge->base + TSI148_LCSR_INTS); 259 260 /* Only look at unmasked interrupts */ 261 stat &= enable; 262 263 if (unlikely(!stat)) 264 return IRQ_NONE; 265 266 /* Call subhandlers as appropriate */ 267 /* DMA irqs */ 268 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S)) 269 serviced |= tsi148_DMA_irqhandler(bridge, stat); 270 271 /* Location monitor irqs */ 272 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S | 273 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S)) 274 serviced |= tsi148_LM_irqhandler(bridge, stat); 275 276 /* Mail box irqs */ 277 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | 278 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) 279 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat); 280 281 /* PCI bus error */ 282 if (stat & TSI148_LCSR_INTS_PERRS) 283 serviced |= tsi148_PERR_irqhandler(tsi148_bridge); 284 285 /* VME bus error */ 286 if (stat & TSI148_LCSR_INTS_VERRS) 287 serviced |= tsi148_VERR_irqhandler(tsi148_bridge); 288 289 /* IACK irq */ 290 if (stat & TSI148_LCSR_INTS_IACKS) 291 serviced |= tsi148_IACK_irqhandler(bridge); 292 293 /* VME bus irqs */ 294 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S | 295 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S | 296 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S | 297 TSI148_LCSR_INTS_IRQ1S)) 298 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat); 299 300 /* Clear serviced interrupts */ 301 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); 302 303 return IRQ_HANDLED; 304} 305 306static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) 307{ 308 int result; 309 unsigned int tmp; 310 struct pci_dev *pdev; 311 struct tsi148_driver *bridge; 312 313 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); 314 315 bridge = tsi148_bridge->driver_priv; 316 317 /* Initialise list for VME bus errors */ 318 INIT_LIST_HEAD(&(tsi148_bridge->vme_errors)); 319 320 mutex_init(&(tsi148_bridge->irq_mtx)); 321 322 result = request_irq(pdev->irq, 323 tsi148_irqhandler, 324 IRQF_SHARED, 325 driver_name, tsi148_bridge); 326 if (result) { 327 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq " 328 "vector %02X\n", pdev->irq); 329 return result; 330 } 331 332 /* Enable and unmask interrupts */ 333 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO | 334 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO | 335 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO | 336 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO | 337 TSI148_LCSR_INTEO_IACKEO; 338 339 /* This leaves the following interrupts masked. 340 * TSI148_LCSR_INTEO_VIEEO 341 * TSI148_LCSR_INTEO_SYSFLEO 342 * TSI148_LCSR_INTEO_ACFLEO 343 */ 344 345 /* Don't enable Location Monitor interrupts here - they will be 346 * enabled when the location monitors are properly configured and 347 * a callback has been attached. 348 * TSI148_LCSR_INTEO_LM0EO 349 * TSI148_LCSR_INTEO_LM1EO 350 * TSI148_LCSR_INTEO_LM2EO 351 * TSI148_LCSR_INTEO_LM3EO 352 */ 353 354 /* Don't enable VME interrupts until we add a handler, else the board 355 * will respond to it and we don't want that unless it knows how to 356 * properly deal with it. 357 * TSI148_LCSR_INTEO_IRQ7EO 358 * TSI148_LCSR_INTEO_IRQ6EO 359 * TSI148_LCSR_INTEO_IRQ5EO 360 * TSI148_LCSR_INTEO_IRQ4EO 361 * TSI148_LCSR_INTEO_IRQ3EO 362 * TSI148_LCSR_INTEO_IRQ2EO 363 * TSI148_LCSR_INTEO_IRQ1EO 364 */ 365 366 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); 367 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); 368 369 return 0; 370} 371 372static void tsi148_irq_exit(struct tsi148_driver *bridge, struct pci_dev *pdev) 373{ 374 /* Turn off interrupts */ 375 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); 376 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); 377 378 /* Clear all interrupts */ 379 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); 380 381 /* Detach interrupt handler */ 382 free_irq(pdev->irq, pdev); 383} 384 385/* 386 * Check to see if an IACk has been received, return true (1) or false (0). 387 */ 388int tsi148_iack_received(struct tsi148_driver *bridge) 389{ 390 u32 tmp; 391 392 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); 393 394 if (tmp & TSI148_LCSR_VICR_IRQS) 395 return 0; 396 else 397 return 1; 398} 399 400/* 401 * Configure VME interrupt 402 */ 403void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level, 404 int state, int sync) 405{ 406 struct pci_dev *pdev; 407 u32 tmp; 408 struct tsi148_driver *bridge; 409 410 bridge = tsi148_bridge->driver_priv; 411 412 /* We need to do the ordering differently for enabling and disabling */ 413 if (state == 0) { 414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); 415 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; 416 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); 417 418 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); 419 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; 420 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); 421 422 if (sync != 0) { 423 pdev = container_of(tsi148_bridge->parent, 424 struct pci_dev, dev); 425 426 synchronize_irq(pdev->irq); 427 } 428 } else { 429 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); 430 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; 431 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); 432 433 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); 434 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; 435 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); 436 } 437} 438 439/* 440 * Generate a VME bus interrupt at the requested level & vector. Wait for 441 * interrupt to be acked. 442 */ 443int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid) 444{ 445 u32 tmp; 446 struct tsi148_driver *bridge; 447 448 bridge = tsi148_bridge->driver_priv; 449 450 mutex_lock(&(bridge->vme_int)); 451 452 /* Read VICR register */ 453 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); 454 455 /* Set Status/ID */ 456 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) | 457 (statid & TSI148_LCSR_VICR_STID_M); 458 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); 459 460 /* Assert VMEbus IRQ */ 461 tmp = tmp | TSI148_LCSR_VICR_IRQL[level]; 462 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); 463 464 wait_event_interruptible(bridge->iack_queue, 465 tsi148_iack_received(bridge)); 466 467 mutex_unlock(&(bridge->vme_int)); 468 469 return 0; 470} 471 472/* 473 * Find the first error in this address range 474 */ 475static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge, 476 vme_address_t aspace, unsigned long long address, size_t count) 477{ 478 struct list_head *err_pos; 479 struct vme_bus_error *vme_err, *valid = NULL; 480 unsigned long long bound; 481 482 bound = address + count; 483 484 err_pos = NULL; 485 /* Iterate through errors */ 486 list_for_each(err_pos, &(tsi148_bridge->vme_errors)) { 487 vme_err = list_entry(err_pos, struct vme_bus_error, list); 488 if ((vme_err->address >= address) && 489 (vme_err->address < bound)) { 490 491 valid = vme_err; 492 break; 493 } 494 } 495 496 return valid; 497} 498 499/* 500 * Clear errors in the provided address range. 501 */ 502static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge, 503 vme_address_t aspace, unsigned long long address, size_t count) 504{ 505 struct list_head *err_pos, *temp; 506 struct vme_bus_error *vme_err; 507 unsigned long long bound; 508 509 bound = address + count; 510 511 err_pos = NULL; 512 /* Iterate through errors */ 513 list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) { 514 vme_err = list_entry(err_pos, struct vme_bus_error, list); 515 516 if ((vme_err->address >= address) && 517 (vme_err->address < bound)) { 518 519 list_del(err_pos); 520 kfree(vme_err); 521 } 522 } 523} 524 525/* 526 * Initialize a slave window with the requested attributes. 527 */ 528int tsi148_slave_set(struct vme_slave_resource *image, int enabled, 529 unsigned long long vme_base, unsigned long long size, 530 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle) 531{ 532 unsigned int i, addr = 0, granularity = 0; 533 unsigned int temp_ctl = 0; 534 unsigned int vme_base_low, vme_base_high; 535 unsigned int vme_bound_low, vme_bound_high; 536 unsigned int pci_offset_low, pci_offset_high; 537 unsigned long long vme_bound, pci_offset; 538 struct vme_bridge *tsi148_bridge; 539 struct tsi148_driver *bridge; 540 541 tsi148_bridge = image->parent; 542 bridge = tsi148_bridge->driver_priv; 543 544 i = image->number; 545 546 switch (aspace) { 547 case VME_A16: 548 granularity = 0x10; 549 addr |= TSI148_LCSR_ITAT_AS_A16; 550 break; 551 case VME_A24: 552 granularity = 0x1000; 553 addr |= TSI148_LCSR_ITAT_AS_A24; 554 break; 555 case VME_A32: 556 granularity = 0x10000; 557 addr |= TSI148_LCSR_ITAT_AS_A32; 558 break; 559 case VME_A64: 560 granularity = 0x10000; 561 addr |= TSI148_LCSR_ITAT_AS_A64; 562 break; 563 case VME_CRCSR: 564 case VME_USER1: 565 case VME_USER2: 566 case VME_USER3: 567 case VME_USER4: 568 default: 569 dev_err(tsi148_bridge->parent, "Invalid address space\n"); 570 return -EINVAL; 571 break; 572 } 573 574 /* Convert 64-bit variables to 2x 32-bit variables */ 575 reg_split(vme_base, &vme_base_high, &vme_base_low); 576 577 /* 578 * Bound address is a valid address for the window, adjust 579 * accordingly 580 */ 581 vme_bound = vme_base + size - granularity; 582 reg_split(vme_bound, &vme_bound_high, &vme_bound_low); 583 pci_offset = (unsigned long long)pci_base - vme_base; 584 reg_split(pci_offset, &pci_offset_high, &pci_offset_low); 585 586 if (vme_base_low & (granularity - 1)) { 587 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n"); 588 return -EINVAL; 589 } 590 if (vme_bound_low & (granularity - 1)) { 591 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n"); 592 return -EINVAL; 593 } 594 if (pci_offset_low & (granularity - 1)) { 595 dev_err(tsi148_bridge->parent, "Invalid PCI Offset " 596 "alignment\n"); 597 return -EINVAL; 598 } 599 600 /* Disable while we are mucking around */ 601 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 602 TSI148_LCSR_OFFSET_ITAT); 603 temp_ctl &= ~TSI148_LCSR_ITAT_EN; 604 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + 605 TSI148_LCSR_OFFSET_ITAT); 606 607 /* Setup mapping */ 608 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + 609 TSI148_LCSR_OFFSET_ITSAU); 610 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + 611 TSI148_LCSR_OFFSET_ITSAL); 612 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + 613 TSI148_LCSR_OFFSET_ITEAU); 614 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + 615 TSI148_LCSR_OFFSET_ITEAL); 616 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + 617 TSI148_LCSR_OFFSET_ITOFU); 618 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + 619 TSI148_LCSR_OFFSET_ITOFL); 620 621 /* Setup 2eSST speeds */ 622 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; 623 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { 624 case VME_2eSST160: 625 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160; 626 break; 627 case VME_2eSST267: 628 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267; 629 break; 630 case VME_2eSST320: 631 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320; 632 break; 633 } 634 635 /* Setup cycle types */ 636 temp_ctl &= ~(0x1F << 7); 637 if (cycle & VME_BLT) 638 temp_ctl |= TSI148_LCSR_ITAT_BLT; 639 if (cycle & VME_MBLT) 640 temp_ctl |= TSI148_LCSR_ITAT_MBLT; 641 if (cycle & VME_2eVME) 642 temp_ctl |= TSI148_LCSR_ITAT_2eVME; 643 if (cycle & VME_2eSST) 644 temp_ctl |= TSI148_LCSR_ITAT_2eSST; 645 if (cycle & VME_2eSSTB) 646 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB; 647 648 /* Setup address space */ 649 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M; 650 temp_ctl |= addr; 651 652 temp_ctl &= ~0xF; 653 if (cycle & VME_SUPER) 654 temp_ctl |= TSI148_LCSR_ITAT_SUPR ; 655 if (cycle & VME_USER) 656 temp_ctl |= TSI148_LCSR_ITAT_NPRIV; 657 if (cycle & VME_PROG) 658 temp_ctl |= TSI148_LCSR_ITAT_PGM; 659 if (cycle & VME_DATA) 660 temp_ctl |= TSI148_LCSR_ITAT_DATA; 661 662 /* Write ctl reg without enable */ 663 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + 664 TSI148_LCSR_OFFSET_ITAT); 665 666 if (enabled) 667 temp_ctl |= TSI148_LCSR_ITAT_EN; 668 669 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + 670 TSI148_LCSR_OFFSET_ITAT); 671 672 return 0; 673} 674 675/* 676 * Get slave window configuration. 677 */ 678int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, 679 unsigned long long *vme_base, unsigned long long *size, 680 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle) 681{ 682 unsigned int i, granularity = 0, ctl = 0; 683 unsigned int vme_base_low, vme_base_high; 684 unsigned int vme_bound_low, vme_bound_high; 685 unsigned int pci_offset_low, pci_offset_high; 686 unsigned long long vme_bound, pci_offset; 687 struct tsi148_driver *bridge; 688 689 bridge = image->parent->driver_priv; 690 691 i = image->number; 692 693 /* Read registers */ 694 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 695 TSI148_LCSR_OFFSET_ITAT); 696 697 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 698 TSI148_LCSR_OFFSET_ITSAU); 699 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 700 TSI148_LCSR_OFFSET_ITSAL); 701 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 702 TSI148_LCSR_OFFSET_ITEAU); 703 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 704 TSI148_LCSR_OFFSET_ITEAL); 705 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 706 TSI148_LCSR_OFFSET_ITOFU); 707 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + 708 TSI148_LCSR_OFFSET_ITOFL); 709 710 /* Convert 64-bit variables to 2x 32-bit variables */ 711 reg_join(vme_base_high, vme_base_low, vme_base); 712 reg_join(vme_bound_high, vme_bound_low, &vme_bound); 713 reg_join(pci_offset_high, pci_offset_low, &pci_offset); 714 715 *pci_base = (dma_addr_t)vme_base + pci_offset; 716 717 *enabled = 0; 718 *aspace = 0; 719 *cycle = 0; 720 721 if (ctl & TSI148_LCSR_ITAT_EN) 722 *enabled = 1; 723 724 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) { 725 granularity = 0x10; 726 *aspace |= VME_A16; 727 } 728 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) { 729 granularity = 0x1000; 730 *aspace |= VME_A24; 731 } 732 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) { 733 granularity = 0x10000; 734 *aspace |= VME_A32; 735 } 736 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) { 737 granularity = 0x10000; 738 *aspace |= VME_A64; 739 } 740 741 /* Need granularity before we set the size */ 742 *size = (unsigned long long)((vme_bound - *vme_base) + granularity); 743 744 745 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160) 746 *cycle |= VME_2eSST160; 747 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267) 748 *cycle |= VME_2eSST267; 749 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320) 750 *cycle |= VME_2eSST320; 751 752 if (ctl & TSI148_LCSR_ITAT_BLT) 753 *cycle |= VME_BLT; 754 if (ctl & TSI148_LCSR_ITAT_MBLT) 755 *cycle |= VME_MBLT; 756 if (ctl & TSI148_LCSR_ITAT_2eVME) 757 *cycle |= VME_2eVME; 758 if (ctl & TSI148_LCSR_ITAT_2eSST) 759 *cycle |= VME_2eSST; 760 if (ctl & TSI148_LCSR_ITAT_2eSSTB) 761 *cycle |= VME_2eSSTB; 762 763 if (ctl & TSI148_LCSR_ITAT_SUPR) 764 *cycle |= VME_SUPER; 765 if (ctl & TSI148_LCSR_ITAT_NPRIV) 766 *cycle |= VME_USER; 767 if (ctl & TSI148_LCSR_ITAT_PGM) 768 *cycle |= VME_PROG; 769 if (ctl & TSI148_LCSR_ITAT_DATA) 770 *cycle |= VME_DATA; 771 772 return 0; 773} 774 775/* 776 * Allocate and map PCI Resource 777 */ 778static int tsi148_alloc_resource(struct vme_master_resource *image, 779 unsigned long long size) 780{ 781 unsigned long long existing_size; 782 int retval = 0; 783 struct pci_dev *pdev; 784 struct vme_bridge *tsi148_bridge; 785 786 tsi148_bridge = image->parent; 787 788 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); 789 790 existing_size = (unsigned long long)(image->bus_resource.end - 791 image->bus_resource.start); 792 793 /* If the existing size is OK, return */ 794 if ((size != 0) && (existing_size == (size - 1))) 795 return 0; 796 797 if (existing_size != 0) { 798 iounmap(image->kern_base); 799 image->kern_base = NULL; 800 if (image->bus_resource.name != NULL) 801 kfree(image->bus_resource.name); 802 release_resource(&(image->bus_resource)); 803 memset(&(image->bus_resource), 0, sizeof(struct resource)); 804 } 805 806 /* Exit here if size is zero */ 807 if (size == 0) 808 return 0; 809 810 if (image->bus_resource.name == NULL) { 811 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); 812 if (image->bus_resource.name == NULL) { 813 dev_err(tsi148_bridge->parent, "Unable to allocate " 814 "memory for resource name\n"); 815 retval = -ENOMEM; 816 goto err_name; 817 } 818 } 819 820 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name, 821 image->number); 822 823 image->bus_resource.start = 0; 824 image->bus_resource.end = (unsigned long)size; 825 image->bus_resource.flags = IORESOURCE_MEM; 826 827 retval = pci_bus_alloc_resource(pdev->bus, 828 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, 829 0, NULL, NULL); 830 if (retval) { 831 dev_err(tsi148_bridge->parent, "Failed to allocate mem " 832 "resource for window %d size 0x%lx start 0x%lx\n", 833 image->number, (unsigned long)size, 834 (unsigned long)image->bus_resource.start); 835 goto err_resource; 836 } 837 838 image->kern_base = ioremap_nocache( 839 image->bus_resource.start, size); 840 if (image->kern_base == NULL) { 841 dev_err(tsi148_bridge->parent, "Failed to remap resource\n"); 842 retval = -ENOMEM; 843 goto err_remap; 844 } 845 846 return 0; 847 848 iounmap(image->kern_base); 849 image->kern_base = NULL; 850err_remap: 851 release_resource(&(image->bus_resource)); 852err_resource: 853 kfree(image->bus_resource.name); 854 memset(&(image->bus_resource), 0, sizeof(struct resource)); 855err_name: 856 return retval; 857} 858 859/* 860 * Free and unmap PCI Resource 861 */ 862static void tsi148_free_resource(struct vme_master_resource *image) 863{ 864 iounmap(image->kern_base); 865 image->kern_base = NULL; 866 release_resource(&(image->bus_resource)); 867 kfree(image->bus_resource.name); 868 memset(&(image->bus_resource), 0, sizeof(struct resource)); 869} 870 871/* 872 * Set the attributes of an outbound window. 873 */ 874int tsi148_master_set(struct vme_master_resource *image, int enabled, 875 unsigned long long vme_base, unsigned long long size, 876 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) 877{ 878 int retval = 0; 879 unsigned int i; 880 unsigned int temp_ctl = 0; 881 unsigned int pci_base_low, pci_base_high; 882 unsigned int pci_bound_low, pci_bound_high; 883 unsigned int vme_offset_low, vme_offset_high; 884 unsigned long long pci_bound, vme_offset, pci_base; 885 struct vme_bridge *tsi148_bridge; 886 struct tsi148_driver *bridge; 887 888 tsi148_bridge = image->parent; 889 890 bridge = tsi148_bridge->driver_priv; 891 892 /* Verify input data */ 893 if (vme_base & 0xFFFF) { 894 dev_err(tsi148_bridge->parent, "Invalid VME Window " 895 "alignment\n"); 896 retval = -EINVAL; 897 goto err_window; 898 } 899 900 if ((size == 0) && (enabled != 0)) { 901 dev_err(tsi148_bridge->parent, "Size must be non-zero for " 902 "enabled windows\n"); 903 retval = -EINVAL; 904 goto err_window; 905 } 906 907 spin_lock(&(image->lock)); 908 909 /* Let's allocate the resource here rather than further up the stack as 910 * it avoids pushing loads of bus dependant stuff up the stack. If size 911 * is zero, any existing resource will be freed. 912 */ 913 retval = tsi148_alloc_resource(image, size); 914 if (retval) { 915 spin_unlock(&(image->lock)); 916 dev_err(tsi148_bridge->parent, "Unable to allocate memory for " 917 "resource\n"); 918 goto err_res; 919 } 920 921 if (size == 0) { 922 pci_base = 0; 923 pci_bound = 0; 924 vme_offset = 0; 925 } else { 926 pci_base = (unsigned long long)image->bus_resource.start; 927 928 /* 929 * Bound address is a valid address for the window, adjust 930 * according to window granularity. 931 */ 932 pci_bound = pci_base + (size - 0x10000); 933 vme_offset = vme_base - pci_base; 934 } 935 936 /* Convert 64-bit variables to 2x 32-bit variables */ 937 reg_split(pci_base, &pci_base_high, &pci_base_low); 938 reg_split(pci_bound, &pci_bound_high, &pci_bound_low); 939 reg_split(vme_offset, &vme_offset_high, &vme_offset_low); 940 941 if (pci_base_low & 0xFFFF) { 942 spin_unlock(&(image->lock)); 943 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n"); 944 retval = -EINVAL; 945 goto err_gran; 946 } 947 if (pci_bound_low & 0xFFFF) { 948 spin_unlock(&(image->lock)); 949 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n"); 950 retval = -EINVAL; 951 goto err_gran; 952 } 953 if (vme_offset_low & 0xFFFF) { 954 spin_unlock(&(image->lock)); 955 dev_err(tsi148_bridge->parent, "Invalid VME Offset " 956 "alignment\n"); 957 retval = -EINVAL; 958 goto err_gran; 959 } 960 961 i = image->number; 962 963 /* Disable while we are mucking around */ 964 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 965 TSI148_LCSR_OFFSET_OTAT); 966 temp_ctl &= ~TSI148_LCSR_OTAT_EN; 967 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + 968 TSI148_LCSR_OFFSET_OTAT); 969 970 /* Setup 2eSST speeds */ 971 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M; 972 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { 973 case VME_2eSST160: 974 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160; 975 break; 976 case VME_2eSST267: 977 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267; 978 break; 979 case VME_2eSST320: 980 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320; 981 break; 982 } 983 984 /* Setup cycle types */ 985 if (cycle & VME_BLT) { 986 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; 987 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT; 988 } 989 if (cycle & VME_MBLT) { 990 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; 991 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT; 992 } 993 if (cycle & VME_2eVME) { 994 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; 995 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME; 996 } 997 if (cycle & VME_2eSST) { 998 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; 999 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST; 1000 } 1001 if (cycle & VME_2eSSTB) { 1002 dev_warn(tsi148_bridge->parent, "Currently not setting " 1003 "Broadcast Select Registers\n"); 1004 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; 1005 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB; 1006 } 1007 1008 /* Setup data width */ 1009 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M; 1010 switch (dwidth) { 1011 case VME_D16: 1012 temp_ctl |= TSI148_LCSR_OTAT_DBW_16; 1013 break; 1014 case VME_D32: 1015 temp_ctl |= TSI148_LCSR_OTAT_DBW_32; 1016 break; 1017 default: 1018 spin_unlock(&(image->lock)); 1019 dev_err(tsi148_bridge->parent, "Invalid data width\n"); 1020 retval = -EINVAL; 1021 goto err_dwidth; 1022 } 1023 1024 /* Setup address space */ 1025 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M; 1026 switch (aspace) { 1027 case VME_A16: 1028 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16; 1029 break; 1030 case VME_A24: 1031 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24; 1032 break; 1033 case VME_A32: 1034 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32; 1035 break; 1036 case VME_A64: 1037 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64; 1038 break; 1039 case VME_CRCSR: 1040 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR; 1041 break; 1042 case VME_USER1: 1043 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1; 1044 break; 1045 case VME_USER2: 1046 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2; 1047 break; 1048 case VME_USER3: 1049 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3; 1050 break; 1051 case VME_USER4: 1052 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4; 1053 break; 1054 default: 1055 spin_unlock(&(image->lock)); 1056 dev_err(tsi148_bridge->parent, "Invalid address space\n"); 1057 retval = -EINVAL; 1058 goto err_aspace; 1059 break; 1060 } 1061 1062 temp_ctl &= ~(3<<4); 1063 if (cycle & VME_SUPER) 1064 temp_ctl |= TSI148_LCSR_OTAT_SUP; 1065 if (cycle & VME_PROG) 1066 temp_ctl |= TSI148_LCSR_OTAT_PGM; 1067 1068 /* Setup mapping */ 1069 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + 1070 TSI148_LCSR_OFFSET_OTSAU); 1071 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + 1072 TSI148_LCSR_OFFSET_OTSAL); 1073 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + 1074 TSI148_LCSR_OFFSET_OTEAU); 1075 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + 1076 TSI148_LCSR_OFFSET_OTEAL); 1077 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + 1078 TSI148_LCSR_OFFSET_OTOFU); 1079 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + 1080 TSI148_LCSR_OFFSET_OTOFL); 1081 1082 /* Write ctl reg without enable */ 1083 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + 1084 TSI148_LCSR_OFFSET_OTAT); 1085 1086 if (enabled) 1087 temp_ctl |= TSI148_LCSR_OTAT_EN; 1088 1089 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + 1090 TSI148_LCSR_OFFSET_OTAT); 1091 1092 spin_unlock(&(image->lock)); 1093 return 0; 1094 1095err_aspace: 1096err_dwidth: 1097err_gran: 1098 tsi148_free_resource(image); 1099err_res: 1100err_window: 1101 return retval; 1102 1103} 1104 1105int __tsi148_master_get(struct vme_master_resource *image, int *enabled, 1106 unsigned long long *vme_base, unsigned long long *size, 1107 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) 1108{ 1109 unsigned int i, ctl; 1110 unsigned int pci_base_low, pci_base_high; 1111 unsigned int pci_bound_low, pci_bound_high; 1112 unsigned int vme_offset_low, vme_offset_high; 1113 1114 unsigned long long pci_base, pci_bound, vme_offset; 1115 struct tsi148_driver *bridge; 1116 1117 bridge = image->parent->driver_priv; 1118 1119 i = image->number; 1120 1121 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1122 TSI148_LCSR_OFFSET_OTAT); 1123 1124 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1125 TSI148_LCSR_OFFSET_OTSAU); 1126 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1127 TSI148_LCSR_OFFSET_OTSAL); 1128 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1129 TSI148_LCSR_OFFSET_OTEAU); 1130 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1131 TSI148_LCSR_OFFSET_OTEAL); 1132 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1133 TSI148_LCSR_OFFSET_OTOFU); 1134 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1135 TSI148_LCSR_OFFSET_OTOFL); 1136 1137 /* Convert 64-bit variables to 2x 32-bit variables */ 1138 reg_join(pci_base_high, pci_base_low, &pci_base); 1139 reg_join(pci_bound_high, pci_bound_low, &pci_bound); 1140 reg_join(vme_offset_high, vme_offset_low, &vme_offset); 1141 1142 *vme_base = pci_base + vme_offset; 1143 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000; 1144 1145 *enabled = 0; 1146 *aspace = 0; 1147 *cycle = 0; 1148 *dwidth = 0; 1149 1150 if (ctl & TSI148_LCSR_OTAT_EN) 1151 *enabled = 1; 1152 1153 /* Setup address space */ 1154 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16) 1155 *aspace |= VME_A16; 1156 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24) 1157 *aspace |= VME_A24; 1158 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32) 1159 *aspace |= VME_A32; 1160 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64) 1161 *aspace |= VME_A64; 1162 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR) 1163 *aspace |= VME_CRCSR; 1164 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1) 1165 *aspace |= VME_USER1; 1166 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2) 1167 *aspace |= VME_USER2; 1168 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3) 1169 *aspace |= VME_USER3; 1170 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4) 1171 *aspace |= VME_USER4; 1172 1173 /* Setup 2eSST speeds */ 1174 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160) 1175 *cycle |= VME_2eSST160; 1176 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267) 1177 *cycle |= VME_2eSST267; 1178 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320) 1179 *cycle |= VME_2eSST320; 1180 1181 /* Setup cycle types */ 1182 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT) 1183 *cycle |= VME_SCT; 1184 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT) 1185 *cycle |= VME_BLT; 1186 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT) 1187 *cycle |= VME_MBLT; 1188 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME) 1189 *cycle |= VME_2eVME; 1190 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST) 1191 *cycle |= VME_2eSST; 1192 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB) 1193 *cycle |= VME_2eSSTB; 1194 1195 if (ctl & TSI148_LCSR_OTAT_SUP) 1196 *cycle |= VME_SUPER; 1197 else 1198 *cycle |= VME_USER; 1199 1200 if (ctl & TSI148_LCSR_OTAT_PGM) 1201 *cycle |= VME_PROG; 1202 else 1203 *cycle |= VME_DATA; 1204 1205 /* Setup data width */ 1206 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16) 1207 *dwidth = VME_D16; 1208 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32) 1209 *dwidth = VME_D32; 1210 1211 return 0; 1212} 1213 1214 1215int tsi148_master_get(struct vme_master_resource *image, int *enabled, 1216 unsigned long long *vme_base, unsigned long long *size, 1217 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) 1218{ 1219 int retval; 1220 1221 spin_lock(&(image->lock)); 1222 1223 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace, 1224 cycle, dwidth); 1225 1226 spin_unlock(&(image->lock)); 1227 1228 return retval; 1229} 1230 1231ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, 1232 size_t count, loff_t offset) 1233{ 1234 int retval, enabled; 1235 unsigned long long vme_base, size; 1236 vme_address_t aspace; 1237 vme_cycle_t cycle; 1238 vme_width_t dwidth; 1239 struct vme_bus_error *vme_err = NULL; 1240 struct vme_bridge *tsi148_bridge; 1241 1242 tsi148_bridge = image->parent; 1243 1244 spin_lock(&(image->lock)); 1245 1246 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count); 1247 retval = count; 1248 1249 if (!err_chk) 1250 goto skip_chk; 1251 1252 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, 1253 &dwidth); 1254 1255 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, 1256 count); 1257 if (vme_err != NULL) { 1258 dev_err(image->parent->parent, "First VME read error detected " 1259 "an at address 0x%llx\n", vme_err->address); 1260 retval = vme_err->address - (vme_base + offset); 1261 /* Clear down save errors in this address range */ 1262 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, 1263 count); 1264 } 1265 1266skip_chk: 1267 spin_unlock(&(image->lock)); 1268 1269 return retval; 1270} 1271 1272 1273ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, 1274 size_t count, loff_t offset) 1275{ 1276 int retval = 0, enabled; 1277 unsigned long long vme_base, size; 1278 vme_address_t aspace; 1279 vme_cycle_t cycle; 1280 vme_width_t dwidth; 1281 1282 struct vme_bus_error *vme_err = NULL; 1283 struct vme_bridge *tsi148_bridge; 1284 struct tsi148_driver *bridge; 1285 1286 tsi148_bridge = image->parent; 1287 1288 bridge = tsi148_bridge->driver_priv; 1289 1290 spin_lock(&(image->lock)); 1291 1292 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count); 1293 retval = count; 1294 1295 /* 1296 * Writes are posted. We need to do a read on the VME bus to flush out 1297 * all of the writes before we check for errors. We can't guarentee 1298 * that reading the data we have just written is safe. It is believed 1299 * that there isn't any read, write re-ordering, so we can read any 1300 * location in VME space, so lets read the Device ID from the tsi148's 1301 * own registers as mapped into CR/CSR space. 1302 * 1303 * We check for saved errors in the written address range/space. 1304 */ 1305 1306 if (!err_chk) 1307 goto skip_chk; 1308 1309 /* 1310 * Get window info first, to maximise the time that the buffers may 1311 * fluch on their own 1312 */ 1313 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, 1314 &dwidth); 1315 1316 ioread16(bridge->flush_image->kern_base + 0x7F000); 1317 1318 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, 1319 count); 1320 if (vme_err != NULL) { 1321 dev_warn(tsi148_bridge->parent, "First VME write error detected" 1322 " an at address 0x%llx\n", vme_err->address); 1323 retval = vme_err->address - (vme_base + offset); 1324 /* Clear down save errors in this address range */ 1325 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, 1326 count); 1327 } 1328 1329skip_chk: 1330 spin_unlock(&(image->lock)); 1331 1332 return retval; 1333} 1334 1335/* 1336 * Perform an RMW cycle on the VME bus. 1337 * 1338 * Requires a previously configured master window, returns final value. 1339 */ 1340unsigned int tsi148_master_rmw(struct vme_master_resource *image, 1341 unsigned int mask, unsigned int compare, unsigned int swap, 1342 loff_t offset) 1343{ 1344 unsigned long long pci_addr; 1345 unsigned int pci_addr_high, pci_addr_low; 1346 u32 tmp, result; 1347 int i; 1348 struct tsi148_driver *bridge; 1349 1350 bridge = image->parent->driver_priv; 1351 1352 /* Find the PCI address that maps to the desired VME address */ 1353 i = image->number; 1354 1355 /* Locking as we can only do one of these at a time */ 1356 mutex_lock(&(bridge->vme_rmw)); 1357 1358 /* Lock image */ 1359 spin_lock(&(image->lock)); 1360 1361 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1362 TSI148_LCSR_OFFSET_OTSAU); 1363 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + 1364 TSI148_LCSR_OFFSET_OTSAL); 1365 1366 reg_join(pci_addr_high, pci_addr_low, &pci_addr); 1367 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low); 1368 1369 /* Configure registers */ 1370 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); 1371 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); 1372 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); 1373 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); 1374 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); 1375 1376 /* Enable RMW */ 1377 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); 1378 tmp |= TSI148_LCSR_VMCTRL_RMWEN; 1379 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); 1380 1381 /* Kick process off with a read to the required address. */ 1382 result = ioread32be(image->kern_base + offset); 1383 1384 /* Disable RMW */ 1385 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); 1386 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN; 1387 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); 1388 1389 spin_unlock(&(image->lock)); 1390 1391 mutex_unlock(&(bridge->vme_rmw)); 1392 1393 return result; 1394} 1395 1396static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr, 1397 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) 1398{ 1399 /* Setup 2eSST speeds */ 1400 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { 1401 case VME_2eSST160: 1402 *attr |= TSI148_LCSR_DSAT_2eSSTM_160; 1403 break; 1404 case VME_2eSST267: 1405 *attr |= TSI148_LCSR_DSAT_2eSSTM_267; 1406 break; 1407 case VME_2eSST320: 1408 *attr |= TSI148_LCSR_DSAT_2eSSTM_320; 1409 break; 1410 } 1411 1412 /* Setup cycle types */ 1413 if (cycle & VME_SCT) 1414 *attr |= TSI148_LCSR_DSAT_TM_SCT; 1415 1416 if (cycle & VME_BLT) 1417 *attr |= TSI148_LCSR_DSAT_TM_BLT; 1418 1419 if (cycle & VME_MBLT) 1420 *attr |= TSI148_LCSR_DSAT_TM_MBLT; 1421 1422 if (cycle & VME_2eVME) 1423 *attr |= TSI148_LCSR_DSAT_TM_2eVME; 1424 1425 if (cycle & VME_2eSST) 1426 *attr |= TSI148_LCSR_DSAT_TM_2eSST; 1427 1428 if (cycle & VME_2eSSTB) { 1429 dev_err(dev, "Currently not setting Broadcast Select " 1430 "Registers\n"); 1431 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB; 1432 } 1433 1434 /* Setup data width */ 1435 switch (dwidth) { 1436 case VME_D16: 1437 *attr |= TSI148_LCSR_DSAT_DBW_16; 1438 break; 1439 case VME_D32: 1440 *attr |= TSI148_LCSR_DSAT_DBW_32; 1441 break; 1442 default: 1443 dev_err(dev, "Invalid data width\n"); 1444 return -EINVAL; 1445 } 1446 1447 /* Setup address space */ 1448 switch (aspace) { 1449 case VME_A16: 1450 *attr |= TSI148_LCSR_DSAT_AMODE_A16; 1451 break; 1452 case VME_A24: 1453 *attr |= TSI148_LCSR_DSAT_AMODE_A24; 1454 break; 1455 case VME_A32: 1456 *attr |= TSI148_LCSR_DSAT_AMODE_A32; 1457 break; 1458 case VME_A64: 1459 *attr |= TSI148_LCSR_DSAT_AMODE_A64; 1460 break; 1461 case VME_CRCSR: 1462 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR; 1463 break; 1464 case VME_USER1: 1465 *attr |= TSI148_LCSR_DSAT_AMODE_USER1; 1466 break; 1467 case VME_USER2: 1468 *attr |= TSI148_LCSR_DSAT_AMODE_USER2; 1469 break; 1470 case VME_USER3: 1471 *attr |= TSI148_LCSR_DSAT_AMODE_USER3; 1472 break; 1473 case VME_USER4: 1474 *attr |= TSI148_LCSR_DSAT_AMODE_USER4; 1475 break; 1476 default: 1477 dev_err(dev, "Invalid address space\n"); 1478 return -EINVAL; 1479 break; 1480 } 1481 1482 if (cycle & VME_SUPER) 1483 *attr |= TSI148_LCSR_DSAT_SUP; 1484 if (cycle & VME_PROG) 1485 *attr |= TSI148_LCSR_DSAT_PGM; 1486 1487 return 0; 1488} 1489 1490static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr, 1491 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) 1492{ 1493 /* Setup 2eSST speeds */ 1494 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { 1495 case VME_2eSST160: 1496 *attr |= TSI148_LCSR_DDAT_2eSSTM_160; 1497 break; 1498 case VME_2eSST267: 1499 *attr |= TSI148_LCSR_DDAT_2eSSTM_267; 1500 break; 1501 case VME_2eSST320: 1502 *attr |= TSI148_LCSR_DDAT_2eSSTM_320; 1503 break; 1504 } 1505 1506 /* Setup cycle types */ 1507 if (cycle & VME_SCT) 1508 *attr |= TSI148_LCSR_DDAT_TM_SCT; 1509 1510 if (cycle & VME_BLT) 1511 *attr |= TSI148_LCSR_DDAT_TM_BLT; 1512 1513 if (cycle & VME_MBLT) 1514 *attr |= TSI148_LCSR_DDAT_TM_MBLT; 1515 1516 if (cycle & VME_2eVME) 1517 *attr |= TSI148_LCSR_DDAT_TM_2eVME; 1518 1519 if (cycle & VME_2eSST) 1520 *attr |= TSI148_LCSR_DDAT_TM_2eSST; 1521 1522 if (cycle & VME_2eSSTB) { 1523 dev_err(dev, "Currently not setting Broadcast Select " 1524 "Registers\n"); 1525 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB; 1526 } 1527 1528 /* Setup data width */ 1529 switch (dwidth) { 1530 case VME_D16: 1531 *attr |= TSI148_LCSR_DDAT_DBW_16; 1532 break; 1533 case VME_D32: 1534 *attr |= TSI148_LCSR_DDAT_DBW_32; 1535 break; 1536 default: 1537 dev_err(dev, "Invalid data width\n"); 1538 return -EINVAL; 1539 } 1540 1541 /* Setup address space */ 1542 switch (aspace) { 1543 case VME_A16: 1544 *attr |= TSI148_LCSR_DDAT_AMODE_A16; 1545 break; 1546 case VME_A24: 1547 *attr |= TSI148_LCSR_DDAT_AMODE_A24; 1548 break; 1549 case VME_A32: 1550 *attr |= TSI148_LCSR_DDAT_AMODE_A32; 1551 break; 1552 case VME_A64: 1553 *attr |= TSI148_LCSR_DDAT_AMODE_A64; 1554 break; 1555 case VME_CRCSR: 1556 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR; 1557 break; 1558 case VME_USER1: 1559 *attr |= TSI148_LCSR_DDAT_AMODE_USER1; 1560 break; 1561 case VME_USER2: 1562 *attr |= TSI148_LCSR_DDAT_AMODE_USER2; 1563 break; 1564 case VME_USER3: 1565 *attr |= TSI148_LCSR_DDAT_AMODE_USER3; 1566 break; 1567 case VME_USER4: 1568 *attr |= TSI148_LCSR_DDAT_AMODE_USER4; 1569 break; 1570 default: 1571 dev_err(dev, "Invalid address space\n"); 1572 return -EINVAL; 1573 break; 1574 } 1575 1576 if (cycle & VME_SUPER) 1577 *attr |= TSI148_LCSR_DDAT_SUP; 1578 if (cycle & VME_PROG) 1579 *attr |= TSI148_LCSR_DDAT_PGM; 1580 1581 return 0; 1582} 1583 1584/* 1585 * Add a link list descriptor to the list 1586 */ 1587int tsi148_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, 1588 struct vme_dma_attr *dest, size_t count) 1589{ 1590 struct tsi148_dma_entry *entry, *prev; 1591 u32 address_high, address_low; 1592 struct vme_dma_pattern *pattern_attr; 1593 struct vme_dma_pci *pci_attr; 1594 struct vme_dma_vme *vme_attr; 1595 dma_addr_t desc_ptr; 1596 int retval = 0; 1597 struct vme_bridge *tsi148_bridge; 1598 1599 tsi148_bridge = list->parent->parent; 1600 1601 /* Descriptor must be aligned on 64-bit boundaries */ 1602 entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL); 1603 if (entry == NULL) { 1604 dev_err(tsi148_bridge->parent, "Failed to allocate memory for " 1605 "dma resource structure\n"); 1606 retval = -ENOMEM; 1607 goto err_mem; 1608 } 1609 1610 /* Test descriptor alignment */ 1611 if ((unsigned long)&(entry->descriptor) & 0x7) { 1612 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 " 1613 "byte boundary as required: %p\n", 1614 &(entry->descriptor)); 1615 retval = -EINVAL; 1616 goto err_align; 1617 } 1618 1619 /* Given we are going to fill out the structure, we probably don't 1620 * need to zero it, but better safe than sorry for now. 1621 */ 1622 memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor)); 1623 1624 /* Fill out source part */ 1625 switch (src->type) { 1626 case VME_DMA_PATTERN: 1627 pattern_attr = src->private; 1628 1629 entry->descriptor.dsal = pattern_attr->pattern; 1630 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT; 1631 /* Default behaviour is 32 bit pattern */ 1632 if (pattern_attr->type & VME_DMA_PATTERN_BYTE) 1633 entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ; 1634 1635 /* It seems that the default behaviour is to increment */ 1636 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) 1637 entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN; 1638 1639 break; 1640 case VME_DMA_PCI: 1641 pci_attr = src->private; 1642 1643 reg_split((unsigned long long)pci_attr->address, &address_high, 1644 &address_low); 1645 entry->descriptor.dsau = address_high; 1646 entry->descriptor.dsal = address_low; 1647 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI; 1648 break; 1649 case VME_DMA_VME: 1650 vme_attr = src->private; 1651 1652 reg_split((unsigned long long)vme_attr->address, &address_high, 1653 &address_low); 1654 entry->descriptor.dsau = address_high; 1655 entry->descriptor.dsal = address_low; 1656 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME; 1657 1658 retval = tsi148_dma_set_vme_src_attributes( 1659 tsi148_bridge->parent, &(entry->descriptor.dsat), 1660 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); 1661 if (retval < 0) 1662 goto err_source; 1663 break; 1664 default: 1665 dev_err(tsi148_bridge->parent, "Invalid source type\n"); 1666 retval = -EINVAL; 1667 goto err_source; 1668 break; 1669 } 1670 1671 /* Assume last link - this will be over-written by adding another */ 1672 entry->descriptor.dnlau = 0; 1673 entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA; 1674 1675 1676 /* Fill out destination part */ 1677 switch (dest->type) { 1678 case VME_DMA_PCI: 1679 pci_attr = dest->private; 1680 1681 reg_split((unsigned long long)pci_attr->address, &address_high, 1682 &address_low); 1683 entry->descriptor.ddau = address_high; 1684 entry->descriptor.ddal = address_low; 1685 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI; 1686 break; 1687 case VME_DMA_VME: 1688 vme_attr = dest->private; 1689 1690 reg_split((unsigned long long)vme_attr->address, &address_high, 1691 &address_low); 1692 entry->descriptor.ddau = address_high; 1693 entry->descriptor.ddal = address_low; 1694 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME; 1695 1696 retval = tsi148_dma_set_vme_dest_attributes( 1697 tsi148_bridge->parent, &(entry->descriptor.ddat), 1698 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); 1699 if (retval < 0) 1700 goto err_dest; 1701 break; 1702 default: 1703 dev_err(tsi148_bridge->parent, "Invalid destination type\n"); 1704 retval = -EINVAL; 1705 goto err_dest; 1706 break; 1707 } 1708 1709 /* Fill out count */ 1710 entry->descriptor.dcnt = (u32)count; 1711 1712 /* Add to list */ 1713 list_add_tail(&(entry->list), &(list->entries)); 1714 1715 /* Fill out previous descriptors "Next Address" */ 1716 if (entry->list.prev != &(list->entries)) { 1717 prev = list_entry(entry->list.prev, struct tsi148_dma_entry, 1718 list); 1719 /* We need the bus address for the pointer */ 1720 desc_ptr = virt_to_bus(&(entry->descriptor)); 1721 reg_split(desc_ptr, &(prev->descriptor.dnlau), 1722 &(prev->descriptor.dnlal)); 1723 } 1724 1725 return 0; 1726 1727err_dest: 1728err_source: 1729err_align: 1730 kfree(entry); 1731err_mem: 1732 return retval; 1733} 1734 1735/* 1736 * Check to see if the provided DMA channel is busy. 1737 */ 1738static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel) 1739{ 1740 u32 tmp; 1741 struct tsi148_driver *bridge; 1742 1743 bridge = tsi148_bridge->driver_priv; 1744 1745 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + 1746 TSI148_LCSR_OFFSET_DSTA); 1747 1748 if (tmp & TSI148_LCSR_DSTA_BSY) 1749 return 0; 1750 else 1751 return 1; 1752 1753} 1754 1755int tsi148_dma_list_exec(struct vme_dma_list *list) 1756{ 1757 struct vme_dma_resource *ctrlr; 1758 int channel, retval = 0; 1759 struct tsi148_dma_entry *entry; 1760 dma_addr_t bus_addr; 1761 u32 bus_addr_high, bus_addr_low; 1762 u32 val, dctlreg = 0; 1763 struct vme_bridge *tsi148_bridge; 1764 struct tsi148_driver *bridge; 1765 1766 ctrlr = list->parent; 1767 1768 tsi148_bridge = ctrlr->parent; 1769 1770 bridge = tsi148_bridge->driver_priv; 1771 1772 mutex_lock(&(ctrlr->mtx)); 1773 1774 channel = ctrlr->number; 1775 1776 if (!list_empty(&(ctrlr->running))) { 1777 /* Need to add to pending here */ 1778 mutex_unlock(&(ctrlr->mtx)); 1779 return -EBUSY; 1780 } else { 1781 list_add(&(list->list), &(ctrlr->running)); 1782 } 1783 1784 /* Get first bus address and write into registers */ 1785 entry = list_first_entry(&(list->entries), struct tsi148_dma_entry, 1786 list); 1787 1788 bus_addr = virt_to_bus(&(entry->descriptor)); 1789 1790 mutex_unlock(&(ctrlr->mtx)); 1791 1792 reg_split(bus_addr, &bus_addr_high, &bus_addr_low); 1793 1794 iowrite32be(bus_addr_high, bridge->base + 1795 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU); 1796 iowrite32be(bus_addr_low, bridge->base + 1797 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL); 1798 1799 /* Start the operation */ 1800 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + 1801 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); 1802 1803 wait_event_interruptible(bridge->dma_queue[channel], 1804 tsi148_dma_busy(ctrlr->parent, channel)); 1805 /* 1806 * Read status register, this register is valid until we kick off a 1807 * new transfer. 1808 */ 1809 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + 1810 TSI148_LCSR_OFFSET_DSTA); 1811 1812 if (val & TSI148_LCSR_DSTA_VBE) { 1813 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val); 1814 retval = -EIO; 1815 } 1816 1817 /* Remove list from running list */ 1818 mutex_lock(&(ctrlr->mtx)); 1819 list_del(&(list->list)); 1820 mutex_unlock(&(ctrlr->mtx)); 1821 1822 return retval; 1823} 1824 1825/* 1826 * Clean up a previously generated link list 1827 * 1828 * We have a separate function, don't assume that the chain can't be reused. 1829 */ 1830int tsi148_dma_list_empty(struct vme_dma_list *list) 1831{ 1832 struct list_head *pos, *temp; 1833 struct tsi148_dma_entry *entry; 1834 1835 /* detach and free each entry */ 1836 list_for_each_safe(pos, temp, &(list->entries)) { 1837 list_del(pos); 1838 entry = list_entry(pos, struct tsi148_dma_entry, list); 1839 kfree(entry); 1840 } 1841 1842 return 0; 1843} 1844 1845/* 1846 * All 4 location monitors reside at the same base - this is therefore a 1847 * system wide configuration. 1848 * 1849 * This does not enable the LM monitor - that should be done when the first 1850 * callback is attached and disabled when the last callback is removed. 1851 */ 1852int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, 1853 vme_address_t aspace, vme_cycle_t cycle) 1854{ 1855 u32 lm_base_high, lm_base_low, lm_ctl = 0; 1856 int i; 1857 struct vme_bridge *tsi148_bridge; 1858 struct tsi148_driver *bridge; 1859 1860 tsi148_bridge = lm->parent; 1861 1862 bridge = tsi148_bridge->driver_priv; 1863 1864 mutex_lock(&(lm->mtx)); 1865 1866 /* If we already have a callback attached, we can't move it! */ 1867 for (i = 0; i < lm->monitors; i++) { 1868 if (bridge->lm_callback[i] != NULL) { 1869 mutex_unlock(&(lm->mtx)); 1870 dev_err(tsi148_bridge->parent, "Location monitor " 1871 "callback attached, can't reset\n"); 1872 return -EBUSY; 1873 } 1874 } 1875 1876 switch (aspace) { 1877 case VME_A16: 1878 lm_ctl |= TSI148_LCSR_LMAT_AS_A16; 1879 break; 1880 case VME_A24: 1881 lm_ctl |= TSI148_LCSR_LMAT_AS_A24; 1882 break; 1883 case VME_A32: 1884 lm_ctl |= TSI148_LCSR_LMAT_AS_A32; 1885 break; 1886 case VME_A64: 1887 lm_ctl |= TSI148_LCSR_LMAT_AS_A64; 1888 break; 1889 default: 1890 mutex_unlock(&(lm->mtx)); 1891 dev_err(tsi148_bridge->parent, "Invalid address space\n"); 1892 return -EINVAL; 1893 break; 1894 } 1895 1896 if (cycle & VME_SUPER) 1897 lm_ctl |= TSI148_LCSR_LMAT_SUPR ; 1898 if (cycle & VME_USER) 1899 lm_ctl |= TSI148_LCSR_LMAT_NPRIV; 1900 if (cycle & VME_PROG) 1901 lm_ctl |= TSI148_LCSR_LMAT_PGM; 1902 if (cycle & VME_DATA) 1903 lm_ctl |= TSI148_LCSR_LMAT_DATA; 1904 1905 reg_split(lm_base, &lm_base_high, &lm_base_low); 1906 1907 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); 1908 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); 1909 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); 1910 1911 mutex_unlock(&(lm->mtx)); 1912 1913 return 0; 1914} 1915 1916/* Get configuration of the callback monitor and return whether it is enabled 1917 * or disabled. 1918 */ 1919int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, 1920 vme_address_t *aspace, vme_cycle_t *cycle) 1921{ 1922 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0; 1923 struct tsi148_driver *bridge; 1924 1925 bridge = lm->parent->driver_priv; 1926 1927 mutex_lock(&(lm->mtx)); 1928 1929 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); 1930 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); 1931 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); 1932 1933 reg_join(lm_base_high, lm_base_low, lm_base); 1934 1935 if (lm_ctl & TSI148_LCSR_LMAT_EN) 1936 enabled = 1; 1937 1938 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) 1939 *aspace |= VME_A16; 1940 1941 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) 1942 *aspace |= VME_A24; 1943 1944 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) 1945 *aspace |= VME_A32; 1946 1947 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) 1948 *aspace |= VME_A64; 1949 1950 1951 if (lm_ctl & TSI148_LCSR_LMAT_SUPR) 1952 *cycle |= VME_SUPER; 1953 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV) 1954 *cycle |= VME_USER; 1955 if (lm_ctl & TSI148_LCSR_LMAT_PGM) 1956 *cycle |= VME_PROG; 1957 if (lm_ctl & TSI148_LCSR_LMAT_DATA) 1958 *cycle |= VME_DATA; 1959 1960 mutex_unlock(&(lm->mtx)); 1961 1962 return enabled; 1963} 1964 1965/* 1966 * Attach a callback to a specific location monitor. 1967 * 1968 * Callback will be passed the monitor triggered. 1969 */ 1970int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, 1971 void (*callback)(int)) 1972{ 1973 u32 lm_ctl, tmp; 1974 struct vme_bridge *tsi148_bridge; 1975 struct tsi148_driver *bridge; 1976 1977 tsi148_bridge = lm->parent; 1978 1979 bridge = tsi148_bridge->driver_priv; 1980 1981 mutex_lock(&(lm->mtx)); 1982 1983 /* Ensure that the location monitor is configured - need PGM or DATA */ 1984 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); 1985 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { 1986 mutex_unlock(&(lm->mtx)); 1987 dev_err(tsi148_bridge->parent, "Location monitor not properly " 1988 "configured\n"); 1989 return -EINVAL; 1990 } 1991 1992 /* Check that a callback isn't already attached */ 1993 if (bridge->lm_callback[monitor] != NULL) { 1994 mutex_unlock(&(lm->mtx)); 1995 dev_err(tsi148_bridge->parent, "Existing callback attached\n"); 1996 return -EBUSY; 1997 } 1998 1999 /* Attach callback */ 2000 bridge->lm_callback[monitor] = callback; 2001 2002 /* Enable Location Monitor interrupt */ 2003 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); 2004 tmp |= TSI148_LCSR_INTEN_LMEN[monitor]; 2005 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); 2006 2007 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); 2008 tmp |= TSI148_LCSR_INTEO_LMEO[monitor]; 2009 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); 2010 2011 /* Ensure that global Location Monitor Enable set */ 2012 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) { 2013 lm_ctl |= TSI148_LCSR_LMAT_EN; 2014 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); 2015 } 2016 2017 mutex_unlock(&(lm->mtx)); 2018 2019 return 0; 2020} 2021 2022/* 2023 * Detach a callback function forn a specific location monitor. 2024 */ 2025int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) 2026{ 2027 u32 lm_en, tmp; 2028 struct tsi148_driver *bridge; 2029 2030 bridge = lm->parent->driver_priv; 2031 2032 mutex_lock(&(lm->mtx)); 2033 2034 /* Disable Location Monitor and ensure previous interrupts are clear */ 2035 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); 2036 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor]; 2037 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); 2038 2039 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); 2040 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor]; 2041 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); 2042 2043 iowrite32be(TSI148_LCSR_INTC_LMC[monitor], 2044 bridge->base + TSI148_LCSR_INTC); 2045 2046 /* Detach callback */ 2047 bridge->lm_callback[monitor] = NULL; 2048 2049 /* If all location monitors disabled, disable global Location Monitor */ 2050 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S | 2051 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) { 2052 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); 2053 tmp &= ~TSI148_LCSR_LMAT_EN; 2054 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); 2055 } 2056 2057 mutex_unlock(&(lm->mtx)); 2058 2059 return 0; 2060} 2061 2062/* 2063 * Determine Geographical Addressing 2064 */ 2065int tsi148_slot_get(struct vme_bridge *tsi148_bridge) 2066{ 2067 u32 slot = 0; 2068 struct tsi148_driver *bridge; 2069 2070 bridge = tsi148_bridge->driver_priv; 2071 2072 if (!geoid) { 2073 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); 2074 slot = slot & TSI148_LCSR_VSTAT_GA_M; 2075 } else 2076 slot = geoid; 2077 2078 return (int)slot; 2079} 2080 2081static int __init tsi148_init(void) 2082{ 2083 return pci_register_driver(&tsi148_driver); 2084} 2085 2086/* 2087 * Configure CR/CSR space 2088 * 2089 * Access to the CR/CSR can be configured at power-up. The location of the 2090 * CR/CSR registers in the CR/CSR address space is determined by the boards 2091 * Auto-ID or Geographic address. This function ensures that the window is 2092 * enabled at an offset consistent with the boards geopgraphic address. 2093 * 2094 * Each board has a 512kB window, with the highest 4kB being used for the 2095 * boards registers, this means there is a fix length 508kB window which must 2096 * be mapped onto PCI memory. 2097 */ 2098static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, 2099 struct pci_dev *pdev) 2100{ 2101 u32 cbar, crat, vstat; 2102 u32 crcsr_bus_high, crcsr_bus_low; 2103 int retval; 2104 struct tsi148_driver *bridge; 2105 2106 bridge = tsi148_bridge->driver_priv; 2107 2108 /* Allocate mem for CR/CSR image */ 2109 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, 2110 &(bridge->crcsr_bus)); 2111 if (bridge->crcsr_kernel == NULL) { 2112 dev_err(tsi148_bridge->parent, "Failed to allocate memory for " 2113 "CR/CSR image\n"); 2114 return -ENOMEM; 2115 } 2116 2117 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); 2118 2119 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); 2120 2121 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); 2122 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); 2123 2124 /* Ensure that the CR/CSR is configured at the correct offset */ 2125 cbar = ioread32be(bridge->base + TSI148_CBAR); 2126 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3; 2127 2128 vstat = tsi148_slot_get(tsi148_bridge); 2129 2130 if (cbar != vstat) { 2131 cbar = vstat; 2132 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n"); 2133 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); 2134 } 2135 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); 2136 2137 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); 2138 if (crat & TSI148_LCSR_CRAT_EN) { 2139 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); 2140 iowrite32be(crat | TSI148_LCSR_CRAT_EN, 2141 bridge->base + TSI148_LCSR_CRAT); 2142 } else 2143 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); 2144 2145 /* If we want flushed, error-checked writes, set up a window 2146 * over the CR/CSR registers. We read from here to safely flush 2147 * through VME writes. 2148 */ 2149 if (err_chk) { 2150 retval = tsi148_master_set(bridge->flush_image, 1, 2151 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, 2152 VME_D16); 2153 if (retval) 2154 dev_err(tsi148_bridge->parent, "Configuring flush image" 2155 " failed\n"); 2156 } 2157 2158 return 0; 2159 2160} 2161 2162static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge, 2163 struct pci_dev *pdev) 2164{ 2165 u32 crat; 2166 struct tsi148_driver *bridge; 2167 2168 bridge = tsi148_bridge->driver_priv; 2169 2170 /* Turn off CR/CSR space */ 2171 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); 2172 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN, 2173 bridge->base + TSI148_LCSR_CRAT); 2174 2175 /* Free image */ 2176 iowrite32be(0, bridge->base + TSI148_LCSR_CROU); 2177 iowrite32be(0, bridge->base + TSI148_LCSR_CROL); 2178 2179 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, 2180 bridge->crcsr_bus); 2181} 2182 2183static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2184{ 2185 int retval, i, master_num; 2186 u32 data; 2187 struct list_head *pos = NULL; 2188 struct vme_bridge *tsi148_bridge; 2189 struct tsi148_driver *tsi148_device; 2190 struct vme_master_resource *master_image; 2191 struct vme_slave_resource *slave_image; 2192 struct vme_dma_resource *dma_ctrlr; 2193 struct vme_lm_resource *lm; 2194 2195 /* If we want to support more than one of each bridge, we need to 2196 * dynamically generate this so we get one per device 2197 */ 2198 tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL); 2199 if (tsi148_bridge == NULL) { 2200 dev_err(&pdev->dev, "Failed to allocate memory for device " 2201 "structure\n"); 2202 retval = -ENOMEM; 2203 goto err_struct; 2204 } 2205 2206 tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL); 2207 if (tsi148_device == NULL) { 2208 dev_err(&pdev->dev, "Failed to allocate memory for device " 2209 "structure\n"); 2210 retval = -ENOMEM; 2211 goto err_driver; 2212 } 2213 2214 tsi148_bridge->driver_priv = tsi148_device; 2215 2216 /* Enable the device */ 2217 retval = pci_enable_device(pdev); 2218 if (retval) { 2219 dev_err(&pdev->dev, "Unable to enable device\n"); 2220 goto err_enable; 2221 } 2222 2223 /* Map Registers */ 2224 retval = pci_request_regions(pdev, driver_name); 2225 if (retval) { 2226 dev_err(&pdev->dev, "Unable to reserve resources\n"); 2227 goto err_resource; 2228 } 2229 2230 /* map registers in BAR 0 */ 2231 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0), 2232 4096); 2233 if (!tsi148_device->base) { 2234 dev_err(&pdev->dev, "Unable to remap CRG region\n"); 2235 retval = -EIO; 2236 goto err_remap; 2237 } 2238 2239 /* Check to see if the mapping worked out */ 2240 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; 2241 if (data != PCI_VENDOR_ID_TUNDRA) { 2242 dev_err(&pdev->dev, "CRG region check failed\n"); 2243 retval = -EIO; 2244 goto err_test; 2245 } 2246 2247 /* Initialize wait queues & mutual exclusion flags */ 2248 init_waitqueue_head(&(tsi148_device->dma_queue[0])); 2249 init_waitqueue_head(&(tsi148_device->dma_queue[1])); 2250 init_waitqueue_head(&(tsi148_device->iack_queue)); 2251 mutex_init(&(tsi148_device->vme_int)); 2252 mutex_init(&(tsi148_device->vme_rmw)); 2253 2254 tsi148_bridge->parent = &(pdev->dev); 2255 strcpy(tsi148_bridge->name, driver_name); 2256 2257 /* Setup IRQ */ 2258 retval = tsi148_irq_init(tsi148_bridge); 2259 if (retval != 0) { 2260 dev_err(&pdev->dev, "Chip Initialization failed.\n"); 2261 goto err_irq; 2262 } 2263 2264 /* If we are going to flush writes, we need to read from the VME bus. 2265 * We need to do this safely, thus we read the devices own CR/CSR 2266 * register. To do this we must set up a window in CR/CSR space and 2267 * hence have one less master window resource available. 2268 */ 2269 master_num = TSI148_MAX_MASTER; 2270 if (err_chk) { 2271 master_num--; 2272 2273 tsi148_device->flush_image = 2274 kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL); 2275 if (tsi148_device->flush_image == NULL) { 2276 dev_err(&pdev->dev, "Failed to allocate memory for " 2277 "flush resource structure\n"); 2278 retval = -ENOMEM; 2279 goto err_master; 2280 } 2281 tsi148_device->flush_image->parent = tsi148_bridge; 2282 spin_lock_init(&(tsi148_device->flush_image->lock)); 2283 tsi148_device->flush_image->locked = 1; 2284 tsi148_device->flush_image->number = master_num; 2285 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 | 2286 VME_A32 | VME_A64; 2287 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT | 2288 VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB | 2289 VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | 2290 VME_USER | VME_PROG | VME_DATA; 2291 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32; 2292 memset(&(tsi148_device->flush_image->bus_resource), 0, 2293 sizeof(struct resource)); 2294 tsi148_device->flush_image->kern_base = NULL; 2295 } 2296 2297 /* Add master windows to list */ 2298 INIT_LIST_HEAD(&(tsi148_bridge->master_resources)); 2299 for (i = 0; i < master_num; i++) { 2300 master_image = kmalloc(sizeof(struct vme_master_resource), 2301 GFP_KERNEL); 2302 if (master_image == NULL) { 2303 dev_err(&pdev->dev, "Failed to allocate memory for " 2304 "master resource structure\n"); 2305 retval = -ENOMEM; 2306 goto err_master; 2307 } 2308 master_image->parent = tsi148_bridge; 2309 spin_lock_init(&(master_image->lock)); 2310 master_image->locked = 0; 2311 master_image->number = i; 2312 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | 2313 VME_A64; 2314 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | 2315 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | 2316 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | 2317 VME_PROG | VME_DATA; 2318 master_image->width_attr = VME_D16 | VME_D32; 2319 memset(&(master_image->bus_resource), 0, 2320 sizeof(struct resource)); 2321 master_image->kern_base = NULL; 2322 list_add_tail(&(master_image->list), 2323 &(tsi148_bridge->master_resources)); 2324 } 2325 2326 /* Add slave windows to list */ 2327 INIT_LIST_HEAD(&(tsi148_bridge->slave_resources)); 2328 for (i = 0; i < TSI148_MAX_SLAVE; i++) { 2329 slave_image = kmalloc(sizeof(struct vme_slave_resource), 2330 GFP_KERNEL); 2331 if (slave_image == NULL) { 2332 dev_err(&pdev->dev, "Failed to allocate memory for " 2333 "slave resource structure\n"); 2334 retval = -ENOMEM; 2335 goto err_slave; 2336 } 2337 slave_image->parent = tsi148_bridge; 2338 mutex_init(&(slave_image->mtx)); 2339 slave_image->locked = 0; 2340 slave_image->number = i; 2341 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 | 2342 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 | 2343 VME_USER3 | VME_USER4; 2344 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | 2345 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | 2346 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | 2347 VME_PROG | VME_DATA; 2348 list_add_tail(&(slave_image->list), 2349 &(tsi148_bridge->slave_resources)); 2350 } 2351 2352 /* Add dma engines to list */ 2353 INIT_LIST_HEAD(&(tsi148_bridge->dma_resources)); 2354 for (i = 0; i < TSI148_MAX_DMA; i++) { 2355 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), 2356 GFP_KERNEL); 2357 if (dma_ctrlr == NULL) { 2358 dev_err(&pdev->dev, "Failed to allocate memory for " 2359 "dma resource structure\n"); 2360 retval = -ENOMEM; 2361 goto err_dma; 2362 } 2363 dma_ctrlr->parent = tsi148_bridge; 2364 mutex_init(&(dma_ctrlr->mtx)); 2365 dma_ctrlr->locked = 0; 2366 dma_ctrlr->number = i; 2367 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | 2368 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME | 2369 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME | 2370 VME_DMA_PATTERN_TO_MEM; 2371 INIT_LIST_HEAD(&(dma_ctrlr->pending)); 2372 INIT_LIST_HEAD(&(dma_ctrlr->running)); 2373 list_add_tail(&(dma_ctrlr->list), 2374 &(tsi148_bridge->dma_resources)); 2375 } 2376 2377 /* Add location monitor to list */ 2378 INIT_LIST_HEAD(&(tsi148_bridge->lm_resources)); 2379 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); 2380 if (lm == NULL) { 2381 dev_err(&pdev->dev, "Failed to allocate memory for " 2382 "location monitor resource structure\n"); 2383 retval = -ENOMEM; 2384 goto err_lm; 2385 } 2386 lm->parent = tsi148_bridge; 2387 mutex_init(&(lm->mtx)); 2388 lm->locked = 0; 2389 lm->number = 1; 2390 lm->monitors = 4; 2391 list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources)); 2392 2393 tsi148_bridge->slave_get = tsi148_slave_get; 2394 tsi148_bridge->slave_set = tsi148_slave_set; 2395 tsi148_bridge->master_get = tsi148_master_get; 2396 tsi148_bridge->master_set = tsi148_master_set; 2397 tsi148_bridge->master_read = tsi148_master_read; 2398 tsi148_bridge->master_write = tsi148_master_write; 2399 tsi148_bridge->master_rmw = tsi148_master_rmw; 2400 tsi148_bridge->dma_list_add = tsi148_dma_list_add; 2401 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec; 2402 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty; 2403 tsi148_bridge->irq_set = tsi148_irq_set; 2404 tsi148_bridge->irq_generate = tsi148_irq_generate; 2405 tsi148_bridge->lm_set = tsi148_lm_set; 2406 tsi148_bridge->lm_get = tsi148_lm_get; 2407 tsi148_bridge->lm_attach = tsi148_lm_attach; 2408 tsi148_bridge->lm_detach = tsi148_lm_detach; 2409 tsi148_bridge->slot_get = tsi148_slot_get; 2410 2411 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); 2412 dev_info(&pdev->dev, "Board is%s the VME system controller\n", 2413 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not"); 2414 if (!geoid) 2415 dev_info(&pdev->dev, "VME geographical address is %d\n", 2416 data & TSI148_LCSR_VSTAT_GA_M); 2417 else 2418 dev_info(&pdev->dev, "VME geographical address is set to %d\n", 2419 geoid); 2420 2421 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", 2422 err_chk ? "enabled" : "disabled"); 2423 2424 if (tsi148_crcsr_init(tsi148_bridge, pdev)) { 2425 dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); 2426 goto err_crcsr; 2427 } 2428 2429 retval = vme_register_bridge(tsi148_bridge); 2430 if (retval != 0) { 2431 dev_err(&pdev->dev, "Chip Registration failed.\n"); 2432 goto err_reg; 2433 } 2434 2435 pci_set_drvdata(pdev, tsi148_bridge); 2436 2437 /* Clear VME bus "board fail", and "power-up reset" lines */ 2438 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); 2439 data &= ~TSI148_LCSR_VSTAT_BRDFL; 2440 data |= TSI148_LCSR_VSTAT_CPURST; 2441 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); 2442 2443 return 0; 2444 2445 vme_unregister_bridge(tsi148_bridge); 2446err_reg: 2447 tsi148_crcsr_exit(tsi148_bridge, pdev); 2448err_crcsr: 2449err_lm: 2450 /* resources are stored in link list */ 2451 list_for_each(pos, &(tsi148_bridge->lm_resources)) { 2452 lm = list_entry(pos, struct vme_lm_resource, list); 2453 list_del(pos); 2454 kfree(lm); 2455 } 2456err_dma: 2457 /* resources are stored in link list */ 2458 list_for_each(pos, &(tsi148_bridge->dma_resources)) { 2459 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); 2460 list_del(pos); 2461 kfree(dma_ctrlr); 2462 } 2463err_slave: 2464 /* resources are stored in link list */ 2465 list_for_each(pos, &(tsi148_bridge->slave_resources)) { 2466 slave_image = list_entry(pos, struct vme_slave_resource, list); 2467 list_del(pos); 2468 kfree(slave_image); 2469 } 2470err_master: 2471 /* resources are stored in link list */ 2472 list_for_each(pos, &(tsi148_bridge->master_resources)) { 2473 master_image = list_entry(pos, struct vme_master_resource, 2474 list); 2475 list_del(pos); 2476 kfree(master_image); 2477 } 2478 2479 tsi148_irq_exit(tsi148_device, pdev); 2480err_irq: 2481err_test: 2482 iounmap(tsi148_device->base); 2483err_remap: 2484 pci_release_regions(pdev); 2485err_resource: 2486 pci_disable_device(pdev); 2487err_enable: 2488 kfree(tsi148_device); 2489err_driver: 2490 kfree(tsi148_bridge); 2491err_struct: 2492 return retval; 2493 2494} 2495 2496static void tsi148_remove(struct pci_dev *pdev) 2497{ 2498 struct list_head *pos = NULL; 2499 struct vme_master_resource *master_image; 2500 struct vme_slave_resource *slave_image; 2501 struct vme_dma_resource *dma_ctrlr; 2502 int i; 2503 struct tsi148_driver *bridge; 2504 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev); 2505 2506 bridge = tsi148_bridge->driver_priv; 2507 2508 2509 dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); 2510 2511 /* 2512 * Shutdown all inbound and outbound windows. 2513 */ 2514 for (i = 0; i < 8; i++) { 2515 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + 2516 TSI148_LCSR_OFFSET_ITAT); 2517 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + 2518 TSI148_LCSR_OFFSET_OTAT); 2519 } 2520 2521 /* 2522 * Shutdown Location monitor. 2523 */ 2524 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); 2525 2526 /* 2527 * Shutdown CRG map. 2528 */ 2529 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); 2530 2531 /* 2532 * Clear error status. 2533 */ 2534 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); 2535 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); 2536 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); 2537 2538 /* 2539 * Remove VIRQ interrupt (if any) 2540 */ 2541 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) 2542 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); 2543 2544 /* 2545 * Map all Interrupts to PCI INTA 2546 */ 2547 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); 2548 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); 2549 2550 tsi148_irq_exit(bridge, pdev); 2551 2552 vme_unregister_bridge(tsi148_bridge); 2553 2554 tsi148_crcsr_exit(tsi148_bridge, pdev); 2555 2556 /* resources are stored in link list */ 2557 list_for_each(pos, &(tsi148_bridge->dma_resources)) { 2558 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); 2559 list_del(pos); 2560 kfree(dma_ctrlr); 2561 } 2562 2563 /* resources are stored in link list */ 2564 list_for_each(pos, &(tsi148_bridge->slave_resources)) { 2565 slave_image = list_entry(pos, struct vme_slave_resource, list); 2566 list_del(pos); 2567 kfree(slave_image); 2568 } 2569 2570 /* resources are stored in link list */ 2571 list_for_each(pos, &(tsi148_bridge->master_resources)) { 2572 master_image = list_entry(pos, struct vme_master_resource, 2573 list); 2574 list_del(pos); 2575 kfree(master_image); 2576 } 2577 2578 tsi148_irq_exit(bridge, pdev); 2579 2580 iounmap(bridge->base); 2581 2582 pci_release_regions(pdev); 2583 2584 pci_disable_device(pdev); 2585 2586 kfree(tsi148_bridge->driver_priv); 2587 2588 kfree(tsi148_bridge); 2589} 2590 2591static void __exit tsi148_exit(void) 2592{ 2593 pci_unregister_driver(&tsi148_driver); 2594} 2595 2596MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); 2597module_param(err_chk, bool, 0); 2598 2599MODULE_PARM_DESC(geoid, "Override geographical addressing"); 2600module_param(geoid, int, 0); 2601 2602MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge"); 2603MODULE_LICENSE("GPL"); 2604 2605module_init(tsi148_init); 2606module_exit(tsi148_exit); 2607