1/***************************************************************************** 2 * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved. 3 * 4 * Module: Hal819xUsbDM.h (RTL8192 Header H File) 5 * 6 * 7 * Note: For dynamic control definition constant structure. 8 * 9 * 10 * Export: 11 * 12 * Abbrev: 13 * 14 * History: 15 * Data Who Remark 16 * 10/04/2007 MHC Create initial version. 17 * 18 *****************************************************************************/ 19 /* Check to see if the file has been included already. */ 20#ifndef __R8192UDM_H__ 21#define __R8192UDM_H__ 22 23 24/*--------------------------Define Parameters-------------------------------*/ 25#define OFDM_Table_Length 19 26#define CCK_Table_length 12 27 28#define DM_DIG_THRESH_HIGH 40 29#define DM_DIG_THRESH_LOW 35 30 31#define DM_DIG_HIGH_PWR_THRESH_HIGH 75 32#define DM_DIG_HIGH_PWR_THRESH_LOW 70 33 34#define BW_AUTO_SWITCH_HIGH_LOW 25 35#define BW_AUTO_SWITCH_LOW_HIGH 30 36 37#define DM_check_fsync_time_interval 500 38 39 40#define DM_DIG_BACKOFF 12 41#define DM_DIG_MAX 0x36 42#define DM_DIG_MIN 0x1c 43#define DM_DIG_MIN_Netcore 0x12 44 45#define RxPathSelection_SS_TH_low 30 46#define RxPathSelection_diff_TH 18 47 48#define RateAdaptiveTH_High 50 49#define RateAdaptiveTH_Low_20M 30 50#define RateAdaptiveTH_Low_40M 10 51#define VeryLowRSSI 15 52#define CTSToSelfTHVal 35 53 54//defined by vivi, for tx power track 55#define E_FOR_TX_POWER_TRACK 300 56//Dynamic Tx Power Control Threshold 57#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 58#define TX_POWER_NEAR_FIELD_THRESH_LOW 62 59//added by amy for atheros AP 60#define TX_POWER_ATHEROAP_THRESH_HIGH 78 61#define TX_POWER_ATHEROAP_THRESH_LOW 72 62 63//defined by vivi, for showing on UI. Newer firmware has changed to 0x1e0 64#define Current_Tx_Rate_Reg 0x1e0//0x1b8 65#define Initial_Tx_Rate_Reg 0x1e1 //0x1b9 66#define Tx_Retry_Count_Reg 0x1ac 67#define RegC38_TH 20 68/*--------------------------Define Parameters-------------------------------*/ 69 70 71/*------------------------------Define structure----------------------------*/ 72/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */ 73typedef struct _dynamic_initial_gain_threshold_ 74{ 75 u8 dig_enable_flag; 76 u8 dig_algorithm; 77 u8 dbg_mode; 78 u8 dig_algorithm_switch; 79 80 long rssi_low_thresh; 81 long rssi_high_thresh; 82 83 long rssi_high_power_lowthresh; 84 long rssi_high_power_highthresh; 85 86 u8 dig_state; 87 u8 dig_highpwr_state; 88 u8 cur_connect_state; 89 u8 pre_connect_state; 90 91 u8 curpd_thstate; 92 u8 prepd_thstate; 93 u8 curcs_ratio_state; 94 u8 precs_ratio_state; 95 96 u32 pre_ig_value; 97 u32 cur_ig_value; 98 99 u8 backoff_val; 100 u8 rx_gain_range_max; 101 u8 rx_gain_range_min; 102 bool initialgain_lowerbound_state; 103 104 long rssi_val; 105}dig_t; 106 107typedef enum tag_dynamic_init_gain_state_definition 108{ 109 DM_STA_DIG_OFF = 0, 110 DM_STA_DIG_ON, 111 DM_STA_DIG_MAX 112}dm_dig_sta_e; 113 114 115/* 2007/10/08 MH Define RATR state. */ 116typedef enum tag_dynamic_ratr_state_definition 117{ 118 DM_RATR_STA_HIGH = 0, 119 DM_RATR_STA_MIDDLE = 1, 120 DM_RATR_STA_LOW = 2, 121 DM_RATR_STA_MAX 122}dm_ratr_sta_e; 123 124/* 2007/10/11 MH Define DIG operation type. */ 125typedef enum tag_dynamic_init_gain_operation_type_definition 126{ 127 DIG_TYPE_THRESH_HIGH = 0, 128 DIG_TYPE_THRESH_LOW = 1, 129 DIG_TYPE_THRESH_HIGHPWR_HIGH = 2, 130 DIG_TYPE_THRESH_HIGHPWR_LOW = 3, 131 DIG_TYPE_DBG_MODE = 4, 132 DIG_TYPE_RSSI = 5, 133 DIG_TYPE_ALGORITHM = 6, 134 DIG_TYPE_BACKOFF = 7, 135 DIG_TYPE_PWDB_FACTOR = 8, 136 DIG_TYPE_RX_GAIN_MIN = 9, 137 DIG_TYPE_RX_GAIN_MAX = 10, 138 DIG_TYPE_ENABLE = 20, 139 DIG_TYPE_DISABLE = 30, 140 DIG_OP_TYPE_MAX 141}dm_dig_op_e; 142 143typedef enum tag_dig_algorithm_definition 144{ 145 DIG_ALGO_BY_FALSE_ALARM = 0, 146 DIG_ALGO_BY_RSSI = 1, 147 DIG_ALGO_MAX 148}dm_dig_alg_e; 149 150typedef enum tag_dig_dbgmode_definition 151{ 152 DIG_DBG_OFF = 0, 153 DIG_DBG_ON = 1, 154 DIG_DBG_MAX 155}dm_dig_dbg_e; 156 157typedef enum tag_dig_connect_definition 158{ 159 DIG_DISCONNECT = 0, 160 DIG_CONNECT = 1, 161 DIG_CONNECT_MAX 162}dm_dig_connect_e; 163 164typedef enum tag_dig_packetdetection_threshold_definition 165{ 166 DIG_PD_AT_LOW_POWER = 0, 167 DIG_PD_AT_NORMAL_POWER = 1, 168 DIG_PD_AT_HIGH_POWER = 2, 169 DIG_PD_MAX 170}dm_dig_pd_th_e; 171 172typedef enum tag_dig_cck_cs_ratio_state_definition 173{ 174 DIG_CS_RATIO_LOWER = 0, 175 DIG_CS_RATIO_HIGHER = 1, 176 DIG_CS_MAX 177}dm_dig_cs_ratio_e; 178typedef struct _Dynamic_Rx_Path_Selection_ 179{ 180 u8 Enable; 181 u8 DbgMode; 182 u8 cck_method; 183 u8 cck_Rx_path; 184 185 u8 SS_TH_low; 186 u8 diff_TH; 187 u8 disabledRF; 188 u8 reserved; 189 190 u8 rf_rssi[4]; 191 u8 rf_enable_rssi_th[4]; 192 long cck_pwdb_sta[4]; 193}DRxPathSel; 194 195typedef enum tag_CCK_Rx_Path_Method_Definition 196{ 197 CCK_Rx_Version_1 = 0, 198 CCK_Rx_Version_2= 1, 199 CCK_Rx_Version_MAX 200}DM_CCK_Rx_Path_Method; 201 202typedef enum tag_DM_DbgMode_Definition 203{ 204 DM_DBG_OFF = 0, 205 DM_DBG_ON = 1, 206 DM_DBG_MAX 207}DM_DBG_E; 208 209typedef struct tag_Tx_Config_Cmd_Format 210{ 211 u32 Op; /* Command packet type. */ 212 u32 Length; /* Command packet length. */ 213 u32 Value; 214}DCMD_TXCMD_T, *PDCMD_TXCMD_T; 215/*------------------------------Define structure----------------------------*/ 216 217 218/*------------------------Export global variable----------------------------*/ 219extern dig_t dm_digtable; 220extern u8 dm_shadow[16][256]; 221extern DRxPathSel DM_RxPathSelTable; 222/*------------------------Export global variable----------------------------*/ 223 224 225/*------------------------Export Marco Definition---------------------------*/ 226 227/*------------------------Export Marco Definition---------------------------*/ 228 229 230/*--------------------------Exported Function prototype---------------------*/ 231/*--------------------------Exported Function prototype---------------------*/ 232extern void init_hal_dm(struct net_device *dev); 233extern void deinit_hal_dm(struct net_device *dev); 234 235extern void hal_dm_watchdog(struct net_device *dev); 236 237 238extern void init_rate_adaptive(struct net_device *dev); 239extern void dm_txpower_trackingcallback(struct work_struct *work); 240 241extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14); 242extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); 243extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); 244extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, 245 u32 dm_type, 246 u32 dm_value); 247extern void DM_ChangeFsyncSetting(struct net_device *dev, 248 s32 DM_Type, 249 s32 DM_Value); 250extern void dm_force_tx_fw_info(struct net_device *dev, 251 u32 force_type, 252 u32 force_value); 253extern void dm_init_edca_turbo(struct net_device *dev); 254extern void dm_rf_operation_test_callback(unsigned long data); 255extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work); 256extern void dm_fsync_timer_callback(unsigned long data); 257extern void dm_check_fsync(struct net_device *dev); 258extern void dm_shadow_init(struct net_device *dev); 259extern void dm_initialize_txpower_tracking(struct net_device *dev); 260 261 262#endif /*__R8192UDM_H__ */ 263 264 265/* End of r8192U_dm.h */ 266