1/* 2 * Copyright (c) 2000-2005 ZyDAS Technology Corporation 3 * Copyright (c) 2007-2008 Atheros Communications Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17/* */ 18/* Module Name : hpreg.c */ 19/* */ 20/* Abstract */ 21/* This module contains Regulatory Table and related function. */ 22/* */ 23/* NOTES */ 24/* None */ 25/* */ 26/************************************************************************/ 27#include "../80211core/cprecomp.h" 28#include "hpani.h" 29#include "hpreg.h" 30#include "hpusb.h" 31 32#define HAL_MODE_11A_TURBO HAL_MODE_108A 33#define HAL_MODE_11G_TURBO HAL_MODE_108G 34 35 36/* 37 * The following are flags for different requirements per reg domain. 38 * These requirements are either inhereted from the reg domain pair or 39 * from the unitary reg domain if the reg domain pair flags value is 40 * 0 41 */ 42 43enum { 44 NO_REQ = 0x00000000, 45 DISALLOW_ADHOC_11A = 0x00000001, 46 DISALLOW_ADHOC_11A_TURB = 0x00000002, 47 NEED_NFC = 0x00000004, 48 49 ADHOC_PER_11D = 0x00000008, /* Start Ad-Hoc mode */ 50 ADHOC_NO_11A = 0x00000010, 51 52 PUBLIC_SAFETY_DOMAIN = 0x00000020, /* public safety domain */ 53 LIMIT_FRAME_4MS = 0x00000040, /* 4msec limit on the frame length */ 54}; 55 56#define MKK5GHZ_FLAG1 (DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS) 57#define MKK5GHZ_FLAG2 (DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS) 58 59typedef enum { 60 DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 61 DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 62 DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 63} HAL_DFS_DOMAIN; 64 65/* 66 * Used to set the RegDomain bitmask which chooses which frequency 67 * band specs are used. 68 */ 69 70#define BMLEN 2 /* Use 2 64 bit uint for channel bitmask 71 NB: Must agree with macro below (BM) */ 72#define BMZERO {(u64_t) 0, (u64_t) 0} /* BMLEN zeros */ 73 74 75#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \ 76 {((((_fa >= 0) && (_fa < 64)) ? (((u64_t) 1) << (_fa&0x3f)) : (u64_t) 0) | \ 77 (((_fb >= 0) && (_fb < 64)) ? (((u64_t) 1) << (_fb&0x3f)) : (u64_t) 0) | \ 78 (((_fc >= 0) && (_fc < 64)) ? (((u64_t) 1) << (_fc&0x3f)) : (u64_t) 0) | \ 79 (((_fd >= 0) && (_fd < 64)) ? (((u64_t) 1) << (_fd&0x3f)) : (u64_t) 0) | \ 80 (((_fe >= 0) && (_fe < 64)) ? (((u64_t) 1) << (_fe&0x3f)) : (u64_t) 0) | \ 81 (((_ff >= 0) && (_ff < 64)) ? (((u64_t) 1) << (_ff&0x3f)) : (u64_t) 0) | \ 82 (((_fg >= 0) && (_fg < 64)) ? (((u64_t) 1) << (_fg&0x3f)) : (u64_t) 0) | \ 83 (((_fh >= 0) && (_fh < 64)) ? (((u64_t) 1) << (_fh&0x3f)) : (u64_t) 0) | \ 84 (((_fi >= 0) && (_fi < 64)) ? (((u64_t) 1) << (_fi&0x3f)) : (u64_t) 0) | \ 85 (((_fj >= 0) && (_fj < 64)) ? (((u64_t) 1) << (_fj&0x3f)) : (u64_t) 0) | \ 86 (((_fk >= 0) && (_fk < 64)) ? (((u64_t) 1) << (_fk&0x3f)) : (u64_t) 0) | \ 87 (((_fl >= 0) && (_fl < 64)) ? (((u64_t) 1) << (_fl&0x3f)) : (u64_t) 0) | \ 88 ((((_fa > 63) && (_fa < 128)) ? (((u64_t) 1) << ((_fa - 64)&0x3f)) : (u64_t) 0) | \ 89 (((_fb > 63) && (_fb < 128)) ? (((u64_t) 1) << ((_fb - 64)&0x3f)) : (u64_t) 0) | \ 90 (((_fc > 63) && (_fc < 128)) ? (((u64_t) 1) << ((_fc - 64)&0x3f)) : (u64_t) 0) | \ 91 (((_fd > 63) && (_fd < 128)) ? (((u64_t) 1) << ((_fd - 64)&0x3f)) : (u64_t) 0) | \ 92 (((_fe > 63) && (_fe < 128)) ? (((u64_t) 1) << ((_fe - 64)&0x3f)) : (u64_t) 0) | \ 93 (((_ff > 63) && (_ff < 128)) ? (((u64_t) 1) << ((_ff - 64)&0x3f)) : (u64_t) 0) | \ 94 (((_fg > 63) && (_fg < 128)) ? (((u64_t) 1) << ((_fg - 64)&0x3f)) : (u64_t) 0) | \ 95 (((_fh > 63) && (_fh < 128)) ? (((u64_t) 1) << ((_fh - 64)&0x3f)) : (u64_t) 0) | \ 96 (((_fi > 63) && (_fi < 128)) ? (((u64_t) 1) << ((_fi - 64)&0x3f)) : (u64_t) 0) | \ 97 (((_fj > 63) && (_fj < 128)) ? (((u64_t) 1) << ((_fj - 64)&0x3f)) : (u64_t) 0) | \ 98 (((_fk > 63) && (_fk < 128)) ? (((u64_t) 1) << ((_fk - 64)&0x3f)) : (u64_t) 0) | \ 99 (((_fl > 63) && (_fl < 128)) ? (((u64_t) 1) << ((_fl - 64)&0x3f)) : (u64_t) 0)))} 100 101/* Mask to check whether a domain is a multidomain or a single 102 domain */ 103 104#define MULTI_DOMAIN_MASK 0xFF00 105 106 107/* 108 * The following describe the bit masks for different passive scan 109 * capability/requirements per regdomain. 110 */ 111#define NO_PSCAN 0x0ULL 112#define PSCAN_FCC 0x0000000000000001ULL 113#define PSCAN_FCC_T 0x0000000000000002ULL 114#define PSCAN_ETSI 0x0000000000000004ULL 115#define PSCAN_MKK1 0x0000000000000008ULL 116#define PSCAN_MKK2 0x0000000000000010ULL 117#define PSCAN_MKKA 0x0000000000000020ULL 118#define PSCAN_MKKA_G 0x0000000000000040ULL 119#define PSCAN_ETSIA 0x0000000000000080ULL 120#define PSCAN_ETSIB 0x0000000000000100ULL 121#define PSCAN_ETSIC 0x0000000000000200ULL 122#define PSCAN_WWR 0x0000000000000400ULL 123#define PSCAN_MKKA1 0x0000000000000800ULL 124#define PSCAN_MKKA1_G 0x0000000000001000ULL 125#define PSCAN_MKKA2 0x0000000000002000ULL 126#define PSCAN_MKKA2_G 0x0000000000004000ULL 127#define PSCAN_MKK3 0x0000000000008000ULL 128#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL 129#define IS_ECM_CHAN 0x8000000000000000ULL 130 131/* 132 * THE following table is the mapping of regdomain pairs specified by 133 * an 8 bit regdomain value to the individual unitary reg domains 134 */ 135 136typedef struct reg_dmn_pair_mapping { 137 u16_t regDmnEnum; /* 16 bit reg domain pair */ 138 u16_t regDmn5GHz; /* 5GHz reg domain */ 139 u16_t regDmn2GHz; /* 2GHz reg domain */ 140 u32_t flags5GHz; /* Requirements flags (AdHoc 141 disallow, noise floor cal needed, 142 etc) */ 143 u32_t flags2GHz; /* Requirements flags (AdHoc 144 disallow, noise floor cal needed, 145 etc) */ 146 u64_t pscanMask; /* Passive Scan flags which 147 can override unitary domain 148 passive scan flags. This 149 value is used as a mask on 150 the unitary flags*/ 151 u16_t singleCC; /* Country code of single country if 152 a one-on-one mapping exists */ 153} REG_DMN_PAIR_MAPPING; 154 155static REG_DMN_PAIR_MAPPING regDomainPairs[] = { 156 {NO_ENUMRD, FCC2, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 157 {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 158 {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 159 {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 160 161 {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 162 {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 163 {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 164 {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 165 {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 166 {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 167 {FCC5_FCCA, FCC5, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 168 {FCC6_FCCA, FCC6, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 169 {FCC6_WORLD, FCC6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 170 171 {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 172 {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 173 {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 174 {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 175 {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 176 {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 177 178 {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 179 {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 180 181 {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 182 {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 183 {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 184 {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 185 {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 186 {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 187 {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 188 {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 189 {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 190 {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 191 192 {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 193 {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 194 {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 195 {APL2_FCCA, APL2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 196 {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0}, 197 {APL7_FCCA, APL7, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 198 199 {MKK1_MKKA, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN }, 200 {MKK1_MKKB, MKK1, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 }, 201 {MKK1_FCCA, MKK1, FCCA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 }, 202 {MKK1_MKKA1, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 }, 203 {MKK1_MKKA2, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 }, 204 {MKK1_MKKC, MKK1, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 }, 205 206 /* MKK2 */ 207 {MKK2_MKKA, MKK2, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 }, 208 209 /* MKK3 */ 210 {MKK3_MKKA, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN25 }, 211 {MKK3_MKKB, MKK3, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 }, 212 {MKK3_MKKA1, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN26 }, 213 {MKK3_MKKA2, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 }, 214 {MKK3_MKKC, MKK3, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 }, 215 {MKK3_FCCA, MKK3, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN27 }, 216 217 /* MKK4 */ 218 {MKK4_MKKB, MKK4, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 }, 219 {MKK4_MKKA1, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN28 }, 220 {MKK4_MKKA2, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 }, 221 {MKK4_MKKC, MKK4, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 }, 222 {MKK4_FCCA, MKK4, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN29 }, 223 {MKK4_MKKA, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA, CTRY_JAPAN36 }, 224 225 /* MKK5 */ 226 {MKK5_MKKB, MKK5, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 }, 227 {MKK5_MKKA2, MKK5, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 }, 228 {MKK5_MKKC, MKK5, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 }, 229 230 /* MKK6 */ 231 {MKK6_MKKB, MKK6, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 }, 232 {MKK6_MKKA2, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 }, 233 {MKK6_MKKC, MKK6, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 }, 234 {MKK6_MKKA1, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN30 }, 235 {MKK6_FCCA, MKK6, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN31 }, 236 237 /* MKK7 */ 238 {MKK7_MKKB, MKK7, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 }, 239 {MKK7_MKKA, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 }, 240 {MKK7_MKKC, MKK7, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 }, 241 {MKK7_MKKA1, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN32 }, 242 {MKK7_FCCA, MKK7, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN33 }, 243 244 /* MKK8 */ 245 {MKK8_MKKB, MKK8, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 }, 246 {MKK8_MKKA2, MKK8, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 }, 247 {MKK8_MKKC, MKK8, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 }, 248 249 /* MKK9 */ 250 {MKK9_MKKA, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN34 }, 251 {MKK9_FCCA, MKK9, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN37 }, 252 {MKK9_MKKA1, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN38 }, 253 {MKK9_MKKC, MKK9, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN39 }, 254 {MKK9_MKKA2, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN40 }, 255 256 /* MKK10 */ 257 {MKK10_MKKA, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN35 }, 258 {MKK10_FCCA, MKK10, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN41 }, 259 {MKK10_MKKA1, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN42 }, 260 {MKK10_MKKC, MKK10, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN43 }, 261 {MKK10_MKKA2, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN44 }, 262 263 /* MKK11 */ 264 {MKK11_MKKA, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN45 }, 265 {MKK11_FCCA, MKK11, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN46 }, 266 {MKK11_MKKA1, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN47 }, 267 {MKK11_MKKC, MKK11, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN48 }, 268 {MKK11_MKKA2, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN49 }, 269 270 /* MKK12 */ 271 {MKK12_MKKA, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN50 }, 272 {MKK12_FCCA, MKK12, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN51 }, 273 {MKK12_MKKA1, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN52 }, 274 {MKK12_MKKC, MKK12, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN53 }, 275 {MKK12_MKKA2, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN54 }, 276 277 278 /* These are super domains */ 279 {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 280 {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 281 {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 282 {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 283 {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 284 {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 285 {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 286 {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 287 {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, 288 {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 289 {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, 290}; 291 292/* 293 * The following table is the master list for all different freqeuncy 294 * bands with the complete matrix of all possible flags and settings 295 * for each band if it is used in ANY reg domain. 296 */ 297 298#define DEF_REGDMN FCC1_FCCA 299#define DEF_DMN_5 FCC1 300#define DEF_DMN_2 FCCA 301#define COUNTRY_ERD_FLAG 0x8000 302#define WORLDWIDE_ROAMING_FLAG 0x4000 303#define SUPER_DOMAIN_MASK 0x0fff 304#define COUNTRY_CODE_MASK 0x03ff 305#define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT) 306#define CHANNEL_14 (2484) /* 802.11g operation is not permitted on channel 14 */ 307#define IS_11G_CH14(_ch, _cf) \ 308 (((_ch) == CHANNEL_14) && ((_cf) == CHANNEL_G)) 309 310#define YES TRUE 311#define NO FALSE 312 313enum { 314 CTRY_DEBUG = 0x1ff, /* debug country code */ 315 CTRY_DEFAULT = 0 /* default country code */ 316}; 317 318typedef struct { 319 HAL_CTRY_CODE countryCode; 320 HAL_REG_DOMAIN regDmnEnum; 321 const char *isoName; 322 const char *name; 323 HAL_BOOL allow11g; 324 HAL_BOOL allow11aTurbo; 325 HAL_BOOL allow11gTurbo; 326 HAL_BOOL allow11na; /* HT-40 allowed in 5GHz? */ 327 HAL_BOOL allow11ng; /* HT-40 allowed in 2GHz? */ 328 u16_t outdoorChanStart; 329} COUNTRY_CODE_TO_ENUM_RD; 330 331static COUNTRY_CODE_TO_ENUM_RD allCountries[] = { 332 {CTRY_DEBUG, NO_ENUMRD, "DB", "DEBUG", YES, YES, YES, YES, YES, 7000 }, 333 {CTRY_DEFAULT, DEF_REGDMN, "NA", "NO_COUNTRY_SET", YES, YES, YES, YES, YES, 7000 }, 334 {CTRY_ALBANIA, NULL1_WORLD, "AL", "ALBANIA", YES, NO, YES, NO, YES, 7000 }, 335 {CTRY_ALGERIA, NULL1_WORLD, "DZ", "ALGERIA", YES, NO, YES, NO, YES, 7000 }, 336 {CTRY_ARGENTINA, APL3_WORLD, "AR", "ARGENTINA", YES, NO, NO, NO, NO, 7000 }, 337 {CTRY_ARMENIA, ETSI4_WORLD, "AM", "ARMENIA", YES, NO, YES, NO, YES, 7000 }, 338 {CTRY_AUSTRALIA, FCC6_WORLD, "AU", "AUSTRALIA", YES, YES, YES, YES, YES, 7000 }, 339 {CTRY_AUSTRIA, ETSI2_WORLD, "AT", "AUSTRIA", YES, NO, YES, YES, YES, 7000 }, 340 {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ", "AZERBAIJAN", YES, YES, YES, YES, YES, 7000 }, 341 {CTRY_BAHRAIN, APL6_WORLD, "BH", "BAHRAIN", YES, NO, YES, NO, YES, 7000 }, 342 {CTRY_BELARUS, ETSI1_WORLD, "BY", "BELARUS", YES, NO, YES, YES, YES, 7000 }, 343 {CTRY_BELGIUM, ETSI1_WORLD, "BE", "BELGIUM", YES, NO, YES, YES, YES, 7000 }, 344 {CTRY_BELIZE, APL1_ETSIC, "BZ", "BELIZE", YES, YES, YES, YES, YES, 7000 }, 345 {CTRY_BOLIVIA, APL1_ETSIC, "BO", "BOLVIA", YES, YES, YES, YES, YES, 7000 }, 346 {CTRY_BRAZIL, FCC3_WORLD, "BR", "BRAZIL", NO, NO, NO, NO, NO, 7000 }, 347 {CTRY_BRUNEI_DARUSSALAM, APL1_WORLD, "BN", "BRUNEI DARUSSALAM", YES, YES, YES, YES, YES, 7000 }, 348 {CTRY_BULGARIA, ETSI6_WORLD, "BG", "BULGARIA", YES, NO, YES, YES, YES, 7000 }, 349 {CTRY_CANADA, FCC6_FCCA, "CA", "CANADA", YES, YES, YES, YES, YES, 7000 }, 350 {CTRY_CHILE, APL6_WORLD, "CL", "CHILE", YES, YES, YES, YES, YES, 7000 }, 351 {CTRY_CHINA, APL1_WORLD, "CN", "CHINA", YES, YES, YES, YES, YES, 7000 }, 352 {CTRY_COLOMBIA, FCC1_FCCA, "CO", "COLOMBIA", YES, NO, YES, NO, YES, 7000 }, 353 {CTRY_COSTA_RICA, FCC1_WORLD, "CR", "COSTA RICA", YES, NO, YES, NO, YES, 7000 }, 354 {CTRY_CROATIA, ETSI3_WORLD, "HR", "CROATIA", YES, NO, YES, NO, YES, 7000 }, 355 {CTRY_CYPRUS, ETSI3_WORLD, "CY", "CYPRUS", YES, YES, YES, YES, YES, 7000 }, 356 {CTRY_CZECH, ETSI3_WORLD, "CZ", "CZECH REPUBLIC", YES, NO, YES, YES, YES, 7000 }, 357 {CTRY_DENMARK, ETSI1_WORLD, "DK", "DENMARK", YES, NO, YES, YES, YES, 7000 }, 358 {CTRY_DOMINICAN_REPUBLIC, FCC1_FCCA, "DO", "DOMINICAN REPUBLIC", YES, YES, YES, YES, YES, 7000 }, 359 {CTRY_ECUADOR, FCC1_WORLD, "EC", "ECUADOR", YES, NO, NO, NO, YES, 7000 }, 360 {CTRY_EGYPT, ETSI3_WORLD, "EG", "EGYPT", YES, NO, YES, NO, YES, 7000 }, 361 {CTRY_EL_SALVADOR, FCC1_WORLD, "SV", "EL SALVADOR", YES, NO, YES, NO, YES, 7000 }, 362 {CTRY_ESTONIA, ETSI1_WORLD, "EE", "ESTONIA", YES, NO, YES, YES, YES, 7000 }, 363 {CTRY_FINLAND, ETSI1_WORLD, "FI", "FINLAND", YES, NO, YES, YES, YES, 7000 }, 364 {CTRY_FRANCE, ETSI1_WORLD, "FR", "FRANCE", YES, NO, YES, YES, YES, 7000 }, 365 {CTRY_FRANCE2, ETSI3_WORLD, "F2", "FRANCE_RES", YES, NO, YES, YES, YES, 7000 }, 366 {CTRY_GEORGIA, ETSI4_WORLD, "GE", "GEORGIA", YES, YES, YES, YES, YES, 7000 }, 367 {CTRY_GERMANY, ETSI1_WORLD, "DE", "GERMANY", YES, NO, YES, YES, YES, 7000 }, 368 {CTRY_GREECE, ETSI1_WORLD, "GR", "GREECE", YES, NO, YES, YES, YES, 7000 }, 369 {CTRY_GUATEMALA, FCC1_FCCA, "GT", "GUATEMALA", YES, YES, YES, YES, YES, 7000 }, 370 {CTRY_HONDURAS, NULL1_WORLD, "HN", "HONDURAS", YES, NO, YES, NO, YES, 7000 }, 371 {CTRY_HONG_KONG, FCC2_WORLD, "HK", "HONG KONG", YES, YES, YES, YES, YES, 7000 }, 372 {CTRY_HUNGARY, ETSI4_WORLD, "HU", "HUNGARY", YES, NO, YES, YES, YES, 7000 }, 373 {CTRY_ICELAND, ETSI1_WORLD, "IS", "ICELAND", YES, NO, YES, YES, YES, 7000 }, 374 {CTRY_INDIA, APL6_WORLD, "IN", "INDIA", YES, NO, YES, NO, YES, 7000 }, 375 {CTRY_INDONESIA, APL1_WORLD, "ID", "INDONESIA", YES, NO, YES, NO, YES, 7000 }, 376 {CTRY_IRAN, APL1_WORLD, "IR", "IRAN", YES, YES, YES, YES, YES, 7000 }, 377 {CTRY_IRELAND, ETSI1_WORLD, "IE", "IRELAND", YES, NO, YES, YES, YES, 7000 }, 378 {CTRY_ISRAEL, ETSI3_WORLD, "IL", "ISRAEL", YES, NO, YES, NO, YES, 7000 }, 379 {CTRY_ISRAEL2, NULL1_ETSIB, "ISR", "ISRAEL_RES", YES, NO, YES, NO, YES, 7000 }, 380 {CTRY_ITALY, ETSI1_WORLD, "IT", "ITALY", YES, NO, YES, YES, YES, 7000 }, 381 {CTRY_JAMAICA, ETSI1_WORLD, "JM", "JAMAICA", YES, NO, YES, YES, YES, 7000 }, 382 {CTRY_JAPAN, MKK1_MKKA, "JP", "JAPAN", YES, NO, NO, NO, NO, 7000 }, 383 {CTRY_JAPAN1, MKK1_MKKB, "J1", "JAPAN1", YES, NO, NO, NO, NO, 7000 }, 384 {CTRY_JAPAN2, MKK1_FCCA, "J2", "JAPAN2", YES, NO, NO, NO, NO, 7000 }, 385 {CTRY_JAPAN3, MKK2_MKKA, "J3", "JAPAN3", YES, NO, NO, NO, NO, 7000 }, 386 {CTRY_JAPAN4, MKK1_MKKA1, "J4", "JAPAN4", YES, NO, NO, NO, NO, 7000 }, 387 {CTRY_JAPAN5, MKK1_MKKA2, "J5", "JAPAN5", YES, NO, NO, NO, NO, 7000 }, 388 {CTRY_JAPAN6, MKK1_MKKC, "J6", "JAPAN6", YES, NO, NO, NO, NO, 7000 }, 389 {CTRY_JAPAN7, MKK3_MKKB, "J7", "JAPAN7", YES, NO, NO, NO, NO, 7000 }, 390 {CTRY_JAPAN8, MKK3_MKKA2, "J8", "JAPAN8", YES, NO, NO, NO, NO, 7000 }, 391 {CTRY_JAPAN9, MKK3_MKKC, "J9", "JAPAN9", YES, NO, NO, NO, NO, 7000 }, 392 {CTRY_JAPAN10, MKK4_MKKB, "J10", "JAPAN10", YES, NO, NO, NO, NO, 7000 }, 393 {CTRY_JAPAN11, MKK4_MKKA2, "J11", "JAPAN11", YES, NO, NO, NO, NO, 7000 }, 394 {CTRY_JAPAN12, MKK4_MKKC, "J12", "JAPAN12", YES, NO, NO, NO, NO, 7000 }, 395 {CTRY_JAPAN13, MKK5_MKKB, "J13", "JAPAN13", YES, NO, NO, NO, NO, 7000 }, 396 {CTRY_JAPAN14, MKK5_MKKA2, "J14", "JAPAN14", YES, NO, NO, NO, NO, 7000 }, 397 {CTRY_JAPAN15, MKK5_MKKC, "J15", "JAPAN15", YES, NO, NO, NO, NO, 7000 }, 398 {CTRY_JAPAN16, MKK6_MKKB, "J16", "JAPAN16", YES, NO, NO, NO, NO, 7000 }, 399 {CTRY_JAPAN17, MKK6_MKKA2, "J17", "JAPAN17", YES, NO, NO, NO, NO, 7000 }, 400 {CTRY_JAPAN18, MKK6_MKKC, "J18", "JAPAN18", YES, NO, NO, NO, NO, 7000 }, 401 {CTRY_JAPAN19, MKK7_MKKB, "J19", "JAPAN19", YES, NO, NO, NO, NO, 7000 }, 402 {CTRY_JAPAN20, MKK7_MKKA, "J20", "JAPAN20", YES, NO, NO, NO, NO, 7000 }, 403 {CTRY_JAPAN21, MKK7_MKKC, "J21", "JAPAN21", YES, NO, NO, NO, NO, 7000 }, 404 {CTRY_JAPAN22, MKK8_MKKB, "J22", "JAPAN22", YES, NO, NO, NO, NO, 7000 }, 405 {CTRY_JAPAN23, MKK8_MKKA2, "J23", "JAPAN23", YES, NO, NO, NO, NO, 7000 }, 406 {CTRY_JAPAN24, MKK8_MKKC, "J24", "JAPAN24", YES, NO, NO, NO, NO, 7000 }, 407 {CTRY_JAPAN25, MKK3_MKKA, "J25", "JAPAN25", YES, NO, NO, NO, NO, 7000 }, 408 {CTRY_JAPAN26, MKK3_MKKA1, "J26", "JAPAN26", YES, NO, NO, NO, NO, 7000 }, 409 {CTRY_JAPAN27, MKK3_FCCA, "J27", "JAPAN27", YES, NO, NO, NO, NO, 7000 }, 410 {CTRY_JAPAN28, MKK4_MKKA1, "J28", "JAPAN28", YES, NO, NO, NO, NO, 7000 }, 411 {CTRY_JAPAN29, MKK4_FCCA, "J29", "JAPAN29", YES, NO, NO, NO, NO, 7000 }, 412 {CTRY_JAPAN30, MKK6_MKKA1, "J30", "JAPAN30", YES, NO, NO, NO, NO, 7000 }, 413 {CTRY_JAPAN31, MKK6_FCCA, "J31", "JAPAN31", YES, NO, NO, NO, NO, 7000 }, 414 {CTRY_JAPAN32, MKK7_MKKA1, "J32", "JAPAN32", YES, NO, NO, NO, NO, 7000 }, 415 {CTRY_JAPAN33, MKK7_FCCA, "J33", "JAPAN33", YES, NO, NO, NO, NO, 7000 }, 416 {CTRY_JAPAN34, MKK9_MKKA, "J34", "JAPAN34", YES, NO, NO, NO, NO, 7000 }, 417 {CTRY_JAPAN35, MKK10_MKKA, "J35", "JAPAN35", YES, NO, NO, NO, NO, 7000 }, 418 {CTRY_JAPAN36, MKK4_MKKA, "J36", "JAPAN36", YES, NO, NO, NO, NO, 7000 }, 419 {CTRY_JAPAN37, MKK9_FCCA, "J37", "JAPAN37", YES, NO, NO, NO, NO, 7000 }, 420 {CTRY_JAPAN38, MKK9_MKKA1, "J38", "JAPAN38", YES, NO, NO, NO, NO, 7000 }, 421 {CTRY_JAPAN39, MKK9_MKKC, "J39", "JAPAN39", YES, NO, NO, NO, NO, 7000 }, 422 {CTRY_JAPAN40, MKK10_MKKA2, "J40", "JAPAN40", YES, NO, NO, NO, NO, 7000 }, 423 {CTRY_JAPAN41, MKK10_FCCA, "J41", "JAPAN41", YES, NO, NO, NO, NO, 7000 }, 424 {CTRY_JAPAN42, MKK10_MKKA1, "J42", "JAPAN42", YES, NO, NO, NO, NO, 7000 }, 425 {CTRY_JAPAN43, MKK10_MKKC, "J43", "JAPAN43", YES, NO, NO, NO, NO, 7000 }, 426 {CTRY_JAPAN44, MKK10_MKKA2, "J44", "JAPAN44", YES, NO, NO, NO, NO, 7000 }, 427 {CTRY_JAPAN45, MKK11_MKKA, "J45", "JAPAN45", YES, NO, NO, NO, NO, 7000 }, 428 {CTRY_JAPAN46, MKK11_FCCA, "J46", "JAPAN46", YES, NO, NO, NO, NO, 7000 }, 429 {CTRY_JAPAN47, MKK11_MKKA1, "J47", "JAPAN47", YES, NO, NO, NO, NO, 7000 }, 430 {CTRY_JAPAN48, MKK11_MKKC, "J48", "JAPAN48", YES, NO, NO, NO, NO, 7000 }, 431 {CTRY_JAPAN49, MKK11_MKKA2, "J49", "JAPAN49", YES, NO, NO, NO, NO, 7000 }, 432 {CTRY_JAPAN50, MKK12_MKKA, "J50", "JAPAN50", YES, NO, NO, NO, NO, 7000 }, 433 {CTRY_JAPAN51, MKK12_FCCA, "J51", "JAPAN51", YES, NO, NO, NO, NO, 7000 }, 434 {CTRY_JAPAN52, MKK12_MKKA1, "J52", "JAPAN52", YES, NO, NO, NO, NO, 7000 }, 435 {CTRY_JAPAN53, MKK12_MKKC, "J53", "JAPAN53", YES, NO, NO, NO, NO, 7000 }, 436 {CTRY_JAPAN54, MKK12_MKKA2, "J54", "JAPAN54", YES, NO, NO, NO, NO, 7000 }, 437 {CTRY_JORDAN, ETSI2_WORLD, "JO", "JORDAN", YES, NO, YES, NO, YES, 7000 }, 438 {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ", "KAZAKHSTAN", YES, NO, YES, NO, YES, 7000 }, 439 {CTRY_KOREA_NORTH, APL9_WORLD, "KP", "NORTH KOREA", YES, NO, NO, YES, YES, 7000 }, 440 {CTRY_KOREA_ROC, APL9_WORLD, "KR", "KOREA REPUBLIC", YES, NO, NO, NO, NO, 7000 }, 441 {CTRY_KOREA_ROC2, APL2_APLD, "K2", "KOREA REPUBLIC2", YES, NO, NO, NO, NO, 7000 }, 442 {CTRY_KOREA_ROC3, APL9_WORLD, "K3", "KOREA REPUBLIC3", YES, NO, NO, NO, NO, 7000 }, 443 {CTRY_KUWAIT, NULL1_WORLD, "KW", "KUWAIT", YES, NO, YES, NO, YES, 7000 }, 444 {CTRY_LATVIA, ETSI1_WORLD, "LV", "LATVIA", YES, NO, YES, YES, YES, 7000 }, 445 {CTRY_LEBANON, NULL1_WORLD, "LB", "LEBANON", YES, NO, YES, NO, YES, 7000 }, 446 {CTRY_LIECHTENSTEIN, ETSI1_WORLD, "LI", "LIECHTENSTEIN", YES, NO, YES, YES, YES, 7000 }, 447 {CTRY_LITHUANIA, ETSI1_WORLD, "LT", "LITHUANIA", YES, NO, YES, YES, YES, 7000 }, 448 {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU", "LUXEMBOURG", YES, NO, YES, YES, YES, 7000 }, 449 {CTRY_MACAU, FCC2_WORLD, "MO", "MACAU", YES, YES, YES, YES, YES, 7000 }, 450 {CTRY_MACEDONIA, NULL1_WORLD, "MK", "MACEDONIA", YES, NO, YES, NO, YES, 7000 }, 451 {CTRY_MALAYSIA, APL8_WORLD, "MY", "MALAYSIA", NO, NO, NO, NO, NO, 7000 }, 452 {CTRY_MALTA, ETSI1_WORLD, "MT", "MALTA", YES, NO, YES, YES, YES, 7000 }, 453 {CTRY_MEXICO, FCC1_FCCA, "MX", "MEXICO", YES, YES, YES, YES, YES, 7000 }, 454 {CTRY_MONACO, ETSI4_WORLD, "MC", "MONACO", YES, YES, YES, YES, YES, 7000 }, 455 {CTRY_MOROCCO, NULL1_WORLD, "MA", "MOROCCO", YES, NO, YES, NO, YES, 7000 }, 456 {CTRY_NETHERLANDS, ETSI1_WORLD, "NL", "NETHERLANDS", YES, NO, YES, YES, YES, 7000 }, 457 {CTRY_NETHERLANDS_ANT, ETSI1_WORLD, "AN", "NETHERLANDS-ANTILLES", YES, NO, YES, YES, YES, 7000 }, 458 {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ", "NEW ZEALAND", YES, NO, YES, NO, YES, 7000 }, 459 {CTRY_NORWAY, ETSI1_WORLD, "NO", "NORWAY", YES, NO, YES, YES, YES, 7000 }, 460 {CTRY_OMAN, APL6_WORLD, "OM", "OMAN", YES, NO, YES, NO, YES, 7000 }, 461 {CTRY_PAKISTAN, NULL1_WORLD, "PK", "PAKISTAN", YES, NO, YES, NO, YES, 7000 }, 462 {CTRY_PANAMA, FCC1_FCCA, "PA", "PANAMA", YES, YES, YES, YES, YES, 7000 }, 463 {CTRY_PERU, APL1_WORLD, "PE", "PERU", YES, NO, YES, NO, YES, 7000 }, 464 {CTRY_PHILIPPINES, APL1_WORLD, "PH", "PHILIPPINES", YES, YES, YES, YES, YES, 7000 }, 465 {CTRY_POLAND, ETSI1_WORLD, "PL", "POLAND", YES, NO, YES, YES, YES, 7000 }, 466 {CTRY_PORTUGAL, ETSI1_WORLD, "PT", "PORTUGAL", YES, NO, YES, YES, YES, 7000 }, 467 {CTRY_PUERTO_RICO, FCC1_FCCA, "PR", "PUERTO RICO", YES, YES, YES, YES, YES, 7000 }, 468 {CTRY_QATAR, NULL1_WORLD, "QA", "QATAR", YES, NO, YES, NO, YES, 7000 }, 469 {CTRY_ROMANIA, NULL1_WORLD, "RO", "ROMANIA", YES, NO, YES, NO, YES, 7000 }, 470 {CTRY_RUSSIA, NULL1_WORLD, "RU", "RUSSIA", YES, NO, YES, NO, YES, 7000 }, 471 {CTRY_SAUDI_ARABIA, NULL1_WORLD, "SA", "SAUDI ARABIA", YES, NO, YES, NO, YES, 7000 }, 472 {CTRY_SERBIA_MONT, ETSI1_WORLD, "CS", "SERBIA & MONTENEGRO", YES, NO, YES, YES, YES, 7000 }, 473 {CTRY_SINGAPORE, APL6_WORLD, "SG", "SINGAPORE", YES, YES, YES, YES, YES, 7000 }, 474 {CTRY_SLOVAKIA, ETSI1_WORLD, "SK", "SLOVAK REPUBLIC", YES, NO, YES, YES, YES, 7000 }, 475 {CTRY_SLOVENIA, ETSI1_WORLD, "SI", "SLOVENIA", YES, NO, YES, YES, YES, 7000 }, 476 {CTRY_SOUTH_AFRICA, FCC3_WORLD, "ZA", "SOUTH AFRICA", YES, NO, YES, NO, YES, 7000 }, 477 {CTRY_SPAIN, ETSI1_WORLD, "ES", "SPAIN", YES, NO, YES, YES, YES, 7000 }, 478 {CTRY_SRILANKA, FCC3_WORLD, "LK", "SRI LANKA", YES, NO, YES, NO, YES, 7000 }, 479 {CTRY_SWEDEN, ETSI1_WORLD, "SE", "SWEDEN", YES, NO, YES, YES, YES, 7000 }, 480 {CTRY_SWITZERLAND, ETSI1_WORLD, "CH", "SWITZERLAND", YES, NO, YES, YES, YES, 7000 }, 481 {CTRY_SYRIA, NULL1_WORLD, "SY", "SYRIA", YES, NO, YES, NO, YES, 7000 }, 482 {CTRY_TAIWAN, APL3_FCCA, "TW", "TAIWAN", YES, YES, YES, YES, YES, 7000 }, 483 {CTRY_THAILAND, NULL1_WORLD, "TH", "THAILAND", YES, NO, YES, NO, YES, 7000 }, 484 {CTRY_TRINIDAD_Y_TOBAGO, ETSI4_WORLD, "TT", "TRINIDAD & TOBAGO", YES, NO, YES, NO, YES, 7000 }, 485 {CTRY_TUNISIA, ETSI3_WORLD, "TN", "TUNISIA", YES, NO, YES, NO, YES, 7000 }, 486 {CTRY_TURKEY, ETSI3_WORLD, "TR", "TURKEY", YES, NO, YES, NO, YES, 7000 }, 487 {CTRY_UKRAINE, NULL1_WORLD, "UA", "UKRAINE", YES, NO, YES, NO, YES, 7000 }, 488 {CTRY_UAE, NULL1_WORLD, "AE", "UNITED ARAB EMIRATES", YES, NO, YES, NO, YES, 7000 }, 489 {CTRY_UNITED_KINGDOM, ETSI1_WORLD, "GB", "UNITED KINGDOM", YES, NO, YES, NO, YES, 7000 }, 490 {CTRY_UNITED_STATES, FCC3_FCCA, "US", "UNITED STATES", YES, YES, YES, YES, YES, 5825 }, 491 {CTRY_UNITED_STATES_FCC49, FCC4_FCCA, "PS", "UNITED STATES (PUBLIC SAFETY)", YES, YES, YES, YES, YES, 7000 }, 492 {CTRY_URUGUAY, FCC1_WORLD, "UY", "URUGUAY", YES, NO, YES, NO, YES, 7000 }, 493 {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ", "UZBEKISTAN", YES, YES, YES, YES, YES, 7000 }, 494 {CTRY_VENEZUELA, APL2_ETSIC, "VE", "VENEZUELA", YES, NO, YES, NO, YES, 7000 }, 495 {CTRY_VIET_NAM, NULL1_WORLD, "VN", "VIET NAM", YES, NO, YES, NO, YES, 7000 }, 496 {CTRY_YEMEN, NULL1_WORLD, "YE", "YEMEN", YES, NO, YES, NO, YES, 7000 }, 497 {CTRY_ZIMBABWE, NULL1_WORLD, "ZW", "ZIMBABWE", YES, NO, YES, NO, YES, 7000 } 498}; 499 500typedef struct RegDmnFreqBand { 501 u16_t lowChannel; /* Low channel center in MHz */ 502 u16_t highChannel; /* High Channel center in MHz */ 503 u8_t powerDfs; /* Max power (dBm) for channel 504 range when using DFS */ 505 u8_t antennaMax; /* Max allowed antenna gain */ 506 u8_t channelBW; /* Bandwidth of the channel */ 507 u8_t channelSep; /* Channel separation within 508 the band */ 509 u64_t useDfs; /* Use DFS in the RegDomain 510 if corresponding bit is set */ 511 u64_t usePassScan; /* Use Passive Scan in the RegDomain 512 if corresponding bit is set */ 513 u8_t regClassId; /* Regulatory class id */ 514 u8_t useExtChanDfs; /* Regulatory class id */ 515} REG_DMN_FREQ_BAND; 516 517/* Bit masks for DFS per regdomain */ 518 519enum { 520 NO_DFS = 0x0000000000000000ULL, 521 DFS_FCC3 = 0x0000000000000001ULL, 522 DFS_ETSI = 0x0000000000000002ULL, 523 DFS_MKK4 = 0x0000000000000004ULL, 524}; 525 526/* The table of frequency bands is indexed by a bitmask. The ordering 527 * must be consistent with the enum below. When adding a new 528 * frequency band, be sure to match the location in the enum with the 529 * comments 530 */ 531 532/* 533 * 5GHz 11A channel tags 534 */ 535 536enum { 537 F1_4915_4925, 538 F1_4935_4945, 539 F1_4920_4980, 540 F1_4942_4987, 541 F1_4945_4985, 542 F1_4950_4980, 543 F1_5035_5040, 544 F1_5040_5080, 545 F1_5055_5055, 546 547 F1_5120_5240, 548 549 F1_5170_5230, 550 F2_5170_5230, 551 552 F1_5180_5240, 553 F2_5180_5240, 554 F3_5180_5240, 555 F4_5180_5240, 556 F5_5180_5240, 557 F6_5180_5240, 558 F7_5180_5240, 559 560 F1_5180_5320, 561 562 F1_5240_5280, 563 564 F1_5260_5280, 565 566 F1_5260_5320, 567 F2_5260_5320, 568 F3_5260_5320, 569 F4_5260_5320, 570 F5_5260_5320, 571 F6_5260_5320, 572 F7_5260_5320, 573 574 F1_5260_5700, 575 576 F1_5280_5320, 577 578 F1_5500_5580, 579 580 F1_5500_5620, 581 582 F1_5500_5700, 583 F2_5500_5700, 584 F3_5500_5700, 585 F4_5500_5700, 586 587 F1_5660_5700, 588 589 F1_5745_5805, 590 F2_5745_5805, 591 F3_5745_5805, 592 593 F1_5745_5825, 594 F2_5745_5825, 595 F3_5745_5825, 596 F4_5745_5825, 597 F5_5745_5825, 598 F6_5745_5825, 599 600 W1_4920_4980, 601 W1_5040_5080, 602 W1_5170_5230, 603 W1_5180_5240, 604 W1_5260_5320, 605 W1_5745_5825, 606 W1_5500_5700, 607 W2_5260_5320, 608 W2_5180_5240, 609 W2_5825_5825, 610}; 611 612static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { 613 { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4915_4925 */ 614 { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4935_4945 */ 615 { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7, 0 }, /* F1_4920_4980 */ 616 { 4942, 4987, 27, 6, 5, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4942_4987 */ 617 { 4945, 4985, 30, 6, 10, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4945_4985 */ 618 { 4950, 4980, 33, 6, 20, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4950_4980 */ 619 { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5035_5040 */ 620 { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2, 0 }, /* F1_5040_5080 */ 621 { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5055_5055 */ 622 623 { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5120_5240 */ 624 625 { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F1_5170_5230 */ 626 { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F2_5170_5230 */ 627 628 { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5180_5240 */ 629 { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1, 0 }, /* F2_5180_5240 */ 630 { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5180_5240 */ 631 { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F4_5180_5240 */ 632 { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F5_5180_5240 */ 633 { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0, 0 }, /* F6_5180_5240 */ 634 { 5180, 5240, 23, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, /* F7_5180_5240 */ 635 636 { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5180_5320 */ 637 638 { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5240_5280 */ 639 640 { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5280 */ 641 642 { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5320 */ 643 644 { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0, 0 }, 645 /* F2_5260_5320 */ 646 647 { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F3_5260_5320 */ 648 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F4_5260_5320 */ 649 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F5_5260_5320 */ 650 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5260_5320 */ 651 { 5260, 5320, 17, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F7_5260_5320 */ 652 653 { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0, 0 }, /* F1_5260_5700 */ 654 655 { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F1_5280_5320 */ 656 657 { 5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5500_5580 */ 658 659 { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5500_5620 */ 660 661 { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4, 0 }, /* F1_5500_5700 */ 662 { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F2_5500_5700 */ 663 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5500_5700 */ 664 { 5500, 5700, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0, 0 }, 665 /* F4_5500_5700 */ 666 667 { 5660, 5700, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5660_5700 */ 668 669 { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5805 */ 670 { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5805 */ 671 { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F3_5745_5805 */ 672 { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5825 */ 673 { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5825 */ 674 { 5745, 5825, 20, 0, 20, 20, DFS_ETSI, NO_PSCAN, 0, 0 }, /* F3_5745_5825 */ 675 { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F4_5745_5825 */ 676 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3, 0 }, /* F5_5745_5825 */ 677 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5745_5825 */ 678 679 /* 680 * Below are the world roaming channels 681 * All WWR domains have no power limit, instead use the card's CTL 682 * or max power settings. 683 */ 684 { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_4920_4980 */ 685 { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, /* W1_5040_5080 */ 686 { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5170_5230 */ 687 { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5180_5240 */ 688 { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5260_5320 */ 689 { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_5745_5825 */ 690 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5500_5700 */ 691 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5260_5320 */ 692 { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5180_5240 */ 693 { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W2_5825_5825 */ 694}; 695/* 696 * 5GHz Turbo (dynamic & static) tags 697 */ 698 699enum { 700 T1_5130_5210, 701 T1_5250_5330, 702 T1_5370_5490, 703 T1_5530_5650, 704 705 T1_5150_5190, 706 T1_5230_5310, 707 T1_5350_5470, 708 T1_5510_5670, 709 710 T1_5200_5240, 711 T2_5200_5240, 712 T1_5210_5210, 713 T2_5210_5210, 714 715 T1_5280_5280, 716 T2_5280_5280, 717 T1_5250_5250, 718 T1_5290_5290, 719 T1_5250_5290, 720 T2_5250_5290, 721 722 T1_5540_5660, 723 T1_5760_5800, 724 T2_5760_5800, 725 726 T1_5765_5805, 727 728 WT1_5210_5250, 729 WT1_5290_5290, 730 WT1_5540_5660, 731 WT1_5760_5800, 732}; 733 734/* 735 * 2GHz 11b channel tags 736 */ 737enum { 738 F1_2312_2372, 739 F2_2312_2372, 740 741 F1_2412_2472, 742 F2_2412_2472, 743 F3_2412_2472, 744 745 F1_2412_2462, 746 F2_2412_2462, 747 748 F1_2432_2442, 749 750 F1_2457_2472, 751 752 F1_2467_2472, 753 754 F1_2484_2484, 755 F2_2484_2484, 756 757 F1_2512_2732, 758 759 W1_2312_2372, 760 W1_2412_2412, 761 W1_2417_2432, 762 W1_2437_2442, 763 W1_2447_2457, 764 W1_2462_2462, 765 W1_2467_2467, 766 W2_2467_2467, 767 W1_2472_2472, 768 W2_2472_2472, 769 W1_2484_2484, 770 W2_2484_2484, 771}; 772 773 774/* 775 * 2GHz 11g channel tags 776 */ 777 778enum { 779 G1_2312_2372, 780 G2_2312_2372, 781 782 G1_2412_2472, 783 G2_2412_2472, 784 G3_2412_2472, 785 786 G1_2412_2462, 787 G2_2412_2462, 788 789 G1_2432_2442, 790 791 G1_2457_2472, 792 793 G1_2512_2732, 794 795 G1_2467_2472 , 796 797 WG1_2312_2372, 798 WG1_2412_2412, 799 WG1_2417_2432, 800 WG1_2437_2442, 801 WG1_2447_2457, 802 WG1_2462_2462, 803 WG1_2467_2467, 804 WG2_2467_2467, 805 WG1_2472_2472, 806 WG2_2472_2472, 807 808}; 809static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { 810 { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2312_2372 */ 811 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G2_2312_2372 */ 812 813 { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2472 */ 814 { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2472 */ 815 { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G3_2412_2472 */ 816 817 { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2462 */ 818 { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2462 */ 819 { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2432_2442 */ 820 821 { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2457_2472 */ 822 823 { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2512_2732 */ 824 825 { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0, 0 }, /* G1_2467_2472 */ 826 827 /* 828 * WWR open up the power to 20dBm 829 */ 830 831 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2312_2372 */ 832 { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2412_2412 */ 833 { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2417_2432 */ 834 { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2437_2442 */ 835 { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2447_2457 */ 836 { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2462_2462 */ 837 { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2467_2467 */ 838 { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2467_2467 */ 839 { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2472_2472 */ 840 { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2472_2472 */ 841}; 842/* 843 * 2GHz Dynamic turbo tags 844 */ 845 846enum { 847 T1_2312_2372, 848 T1_2437_2437, 849 T2_2437_2437, 850 T3_2437_2437, 851 T1_2512_2732 852}; 853 854/* 855 * 2GHz 11n frequency tags 856 */ 857enum { 858 NG1_2422_2452, 859 NG2_2422_2452, 860 NG3_2422_2452, 861 862 NG_DEMO_ALL_CHANNELS, 863}; 864 865/* 866 * 5GHz 11n frequency tags 867 */ 868enum { 869 NA1_5190_5230, 870 NA2_5190_5230, 871 NA3_5190_5230, 872 NA4_5190_5230, 873 NA5_5190_5230, 874 875 NA1_5270_5270, 876 877 NA1_5270_5310, 878 NA2_5270_5310, 879 NA3_5270_5310, 880 NA4_5270_5310, 881 882 NA1_5310_5310, 883 884 NA1_5510_5630, 885 886 NA1_5510_5670, 887 NA2_5510_5670, 888 NA3_5510_5670, 889 890 NA1_5755_5795, 891 NA2_5755_5795, 892 NA3_5755_5795, 893 NA4_5755_5795, 894 NA5_5755_5795, 895 896 NA1_5795_5795, 897 898 NA_DEMO_ALL_CHANNELS, 899}; 900 901typedef struct regDomain { 902 u16_t regDmnEnum; /* value from EnumRd table */ 903 u8_t conformanceTestLimit; 904 u64_t dfsMask; /* DFS bitmask for 5Ghz tables */ 905 u64_t pscan; /* Bitmask for passive scan */ 906 u32_t flags; /* Requirement flags (AdHoc disallow, noise 907 floor cal needed, etc) */ 908 u64_t chan11a[BMLEN];/* 128 bit bitmask for channel/band 909 selection */ 910 u64_t chan11a_turbo[BMLEN];/* 128 bit bitmask for channel/band 911 selection */ 912 u64_t chan11a_dyn_turbo[BMLEN]; /* 128 bit bitmask for channel/band 913 selection */ 914 u64_t chan11b[BMLEN];/* 128 bit bitmask for channel/band 915 selection */ 916 u64_t chan11g[BMLEN];/* 128 bit bitmask for channel/band 917 selection */ 918 u64_t chan11g_turbo[BMLEN];/* 128 bit bitmask for channel/band 919 selection */ 920 u64_t chan11ng[BMLEN];/* 128 bit bitmask for 11n in 2GHz */ 921 u64_t chan11na[BMLEN];/* 128 bit bitmask for 11n in 5GHz */ 922} REG_DOMAIN; 923 924static REG_DOMAIN regDomains[] = { 925 926 {DEBUG_REG_DMN, FCC, NO_DFS, NO_PSCAN, NO_REQ, 927 BM(F1_5120_5240, F1_5260_5700, F1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), 928 BM(T1_5130_5210, T1_5250_5330, T1_5370_5490, T1_5530_5650, T1_5150_5190, T1_5230_5310, T1_5350_5470, T1_5510_5670, -1, -1, -1, -1), 929 BM(T1_5200_5240, T1_5280_5280, T1_5540_5660, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1), 930 BM(F1_2312_2372, F1_2412_2472, F1_2484_2484, F1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1), 931 BM(G1_2312_2372, G1_2412_2472, G1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1), 932 BM(T1_2312_2372, T1_2437_2437, T1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1), 933 BM(NG_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 934 BM(NA_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 935 936 {APL1, ETSI, NO_DFS, NO_PSCAN, NO_REQ, 937 BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 938 BMZERO, 939 BMZERO, 940 BMZERO, 941 BMZERO, 942 BMZERO, 943 BMZERO, 944 BM(NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 945 946 {APL2, ETSI, NO_DFS, NO_PSCAN, NO_REQ, 947 BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 948 BMZERO, 949 BMZERO, 950 BMZERO, 951 BMZERO, 952 BMZERO, 953 BMZERO, 954 BM(NA3_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 955 956 {APL3, FCC, NO_DFS, NO_PSCAN, NO_REQ, 957 BM(F1_5280_5320, F2_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 958 BMZERO, 959 BMZERO, 960 BMZERO, 961 BMZERO, 962 BMZERO, 963 BMZERO, 964 BM(NA1_5310_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 965 966 {APL4, ETSI, NO_DFS, NO_PSCAN, NO_REQ, 967 BM(F4_5180_5240, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 968 BMZERO, 969 BMZERO, 970 BMZERO, 971 BMZERO, 972 BMZERO, 973 BMZERO, 974 BM(NA4_5190_5230, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 975 976 {APL5, ETSI, NO_DFS, NO_PSCAN, NO_REQ, 977 BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 978 BMZERO, 979 BMZERO, 980 BMZERO, 981 BMZERO, 982 BMZERO, 983 BMZERO, 984 BM(NA1_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 985 986 {APL6, ETSI, DFS_ETSI, PSCAN_FCC_T | PSCAN_FCC , NO_REQ, 987 BM(F4_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), 988 BM(T2_5210_5210, T1_5250_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 989 BMZERO, 990 BMZERO, 991 BMZERO, 992 BMZERO, 993 BMZERO, 994 BM(NA4_5190_5230, NA2_5270_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 995 996 {APL7, FCC, NO_DFS, PSCAN_FCC_T | PSCAN_FCC , NO_REQ, 997 BM(F7_5260_5320, F4_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), 998 BMZERO, 999 BMZERO, 1000 BMZERO, 1001 BMZERO, 1002 BMZERO, 1003 BMZERO, 1004 BM(NA1_5310_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1005 {APL8, ETSI, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 1006 BM(F6_5260_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1007 BMZERO, 1008 BMZERO, 1009 BMZERO, 1010 BMZERO, 1011 BMZERO, 1012 BMZERO, 1013 BM(NA4_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1014 1015 {APL9, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 1016 BM(F1_5180_5320, F1_5500_5620, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1017 BMZERO, 1018 BMZERO, 1019 BMZERO, 1020 BMZERO, 1021 BMZERO, 1022 BMZERO, 1023 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5630, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)}, 1024 1025 {ETSI1, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1026 BM(W2_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1027 BMZERO, 1028 BMZERO, 1029 BMZERO, 1030 BMZERO, 1031 BMZERO, 1032 BMZERO, 1033 BM(NA4_5190_5230, NA2_5270_5310, NA2_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1034 1035 {ETSI2, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1036 BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1037 BMZERO, 1038 BMZERO, 1039 BMZERO, 1040 BMZERO, 1041 BMZERO, 1042 BMZERO, 1043 BM(NA3_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1044 1045 {ETSI3, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1046 BM(W2_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1047 BMZERO, 1048 BMZERO, 1049 BMZERO, 1050 BMZERO, 1051 BMZERO, 1052 BMZERO, 1053 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1054 1055 {ETSI4, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1056 BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1057 BMZERO, 1058 BMZERO, 1059 BMZERO, 1060 BMZERO, 1061 BMZERO, 1062 BMZERO, 1063 BM(NA3_5190_5230, NA1_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1064 1065 {ETSI5, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1066 BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1067 BMZERO, 1068 BMZERO, 1069 BMZERO, 1070 BMZERO, 1071 BMZERO, 1072 BMZERO, 1073 BM(NA1_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1074 1075 {ETSI6, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1076 BM(F5_5180_5240, F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1077 BMZERO, 1078 BMZERO, 1079 BMZERO, 1080 BMZERO, 1081 BMZERO, 1082 BMZERO, 1083 BM(NA5_5190_5230, NA1_5270_5270, NA3_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1084 1085 {FCC1, FCC, NO_DFS, NO_PSCAN, NO_REQ, 1086 BM(F2_5180_5240, F4_5260_5320, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1087 BM(T1_5210_5210, T2_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1088 BM(T1_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1089 BMZERO, 1090 BMZERO, 1091 BMZERO, 1092 BMZERO, 1093 BM(NA2_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1094 1095 {FCC2, FCC, NO_DFS, NO_PSCAN, NO_REQ, 1096 BM(F6_5180_5240, F5_5260_5320, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1097 BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1098 BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1099 BMZERO, 1100 BMZERO, 1101 BMZERO, 1102 BMZERO, 1103 BM(NA5_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1104 1105 {FCC3, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, 1106 BM(F2_5180_5240, F3_5260_5320, F1_5500_5700, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1), 1107 BM(T1_5210_5210, T1_5250_5250, T1_5290_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1), 1108 BM(T1_5200_5240, T2_5280_5280, T1_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1109 BMZERO, 1110 BMZERO, 1111 BMZERO, 1112 BMZERO, 1113 BM(NA2_5190_5230, NA2_5270_5310, NA3_5510_5670, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)}, 1114 1115 {FCC4, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ, 1116 BM(F1_4942_4987, F1_4945_4985, F1_4950_4980, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1117 BMZERO, 1118 BMZERO, 1119 BMZERO, 1120 BMZERO, 1121 BMZERO, 1122 BMZERO, 1123 BMZERO}, 1124 1125 {FCC5, FCC, NO_DFS, NO_PSCAN, NO_REQ, 1126 BM(F2_5180_5240, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1127 BMZERO, 1128 BMZERO, 1129 BMZERO, 1130 BMZERO, 1131 BMZERO, 1132 BMZERO, 1133 BM(NA2_5190_5230, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1134 1135 {FCC6, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ, 1136 BM(F7_5180_5240, F5_5260_5320, F1_5500_5580, F1_5660_5700, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1), 1137 BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1138 BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1139 BMZERO, 1140 BMZERO, 1141 BMZERO, 1142 BMZERO, 1143 BM(NA5_5190_5230, NA5_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1144 1145 {MKK1, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, 1146 BM(F1_5170_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1147 BMZERO, 1148 BMZERO, 1149 BMZERO, 1150 BMZERO, 1151 BMZERO, 1152 BMZERO, 1153 BMZERO}, 1154 1155 {MKK2, MKK, NO_DFS, PSCAN_MKK2, DISALLOW_ADHOC_11A_TURB, 1156 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, -1, -1, -1, -1, -1), 1157 BMZERO, 1158 BMZERO, 1159 BMZERO, 1160 BMZERO, 1161 BMZERO, 1162 BMZERO, 1163 BMZERO}, 1164 1165 /* UNI-1 even */ 1166 {MKK3, MKK, NO_DFS, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, 1167 BM(F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1168 BMZERO, 1169 BMZERO, 1170 BMZERO, 1171 BMZERO, 1172 BMZERO, 1173 BMZERO, 1174 BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1175 1176 /* UNI-1 even + UNI-2 */ 1177 {MKK4, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, 1178 BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1179 BMZERO, 1180 BMZERO, 1181 BMZERO, 1182 BMZERO, 1183 BMZERO, 1184 BMZERO, 1185 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1186 1187 /* UNI-1 even + UNI-2 + mid-band */ 1188 {MKK5, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, 1189 BM(F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1190 BMZERO, 1191 BMZERO, 1192 BMZERO, 1193 BMZERO, 1194 BMZERO, 1195 BMZERO, 1196 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1197 1198 /* UNI-1 odd + even */ 1199 {MKK6, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB, 1200 BM(F2_5170_5230, F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1201 BMZERO, 1202 BMZERO, 1203 BMZERO, 1204 BMZERO, 1205 BMZERO, 1206 BMZERO, 1207 BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1208 1209 /* UNI-1 odd + UNI-1 even + UNI-2 */ 1210 {MKK7, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB, 1211 BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1212 BMZERO, 1213 BMZERO, 1214 BMZERO, 1215 BMZERO, 1216 BMZERO, 1217 BMZERO, 1218 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1219 1220 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 1221 {MKK8, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB, 1222 BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1), 1223 BMZERO, 1224 BMZERO, 1225 BMZERO, 1226 BMZERO, 1227 BMZERO, 1228 BMZERO, 1229 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)}, 1230 1231 /* UNI-1 even + 4.9 GHZ */ 1232 {MKK9, MKK, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A_TURB, 1233 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, -1, -1, -1, -1, -1), 1234 BMZERO, 1235 BMZERO, 1236 BMZERO, 1237 BMZERO, 1238 BMZERO, 1239 BMZERO, 1240 BMZERO}, 1241 1242 /* UNI-1 even + UNI-2 + 4.9 GHZ */ 1243 {MKK10, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, 1244 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1), 1245 BMZERO, 1246 BMZERO, 1247 BMZERO, 1248 BMZERO, 1249 BMZERO, 1250 BMZERO, 1251 BMZERO}, 1252 1253 /* UNI-1 even + UNI-2 + 4.9 GHZ + mid-band */ 1254 {MKK11, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, 1255 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1), 1256 BMZERO, 1257 BMZERO, 1258 BMZERO, 1259 BMZERO, 1260 BMZERO, 1261 BMZERO, 1262 BMZERO}, 1263 1264 /* UNI-1 even + UNI-1 odd + UNI-2 + 4.9 GHZ + mid-band */ 1265 {MKK12, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB, 1266 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1), 1267 BMZERO, 1268 BMZERO, 1269 BMZERO, 1270 BMZERO, 1271 BMZERO, 1272 BMZERO, 1273 BMZERO}, 1274 1275 /* Defined here to use when 2G channels are authorised for country K2 */ 1276 {APLD, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, 1277 BMZERO, 1278 BMZERO, 1279 BMZERO, 1280 BM(F2_2312_2372, F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1281 BM(G2_2312_2372, G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1282 BMZERO, 1283 BMZERO, 1284 BMZERO}, 1285 1286 {ETSIA, NO_CTL, NO_DFS, PSCAN_ETSIA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1287 BMZERO, 1288 BMZERO, 1289 BMZERO, 1290 BM(F1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1291 BM(G1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1292 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1293 BMZERO, 1294 BMZERO}, 1295 1296 {ETSIB, ETSI, NO_DFS, PSCAN_ETSIB, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1297 BMZERO, 1298 BMZERO, 1299 BMZERO, 1300 BM(F1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1301 BM(G1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1302 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1303 BMZERO, 1304 BMZERO}, 1305 1306 {ETSIC, ETSI, NO_DFS, PSCAN_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1307 BMZERO, 1308 BMZERO, 1309 BMZERO, 1310 BM(F3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1311 BM(G3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1312 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1313 BMZERO, 1314 BMZERO}, 1315 1316 {FCCA, FCC, NO_DFS, NO_PSCAN, NO_REQ, 1317 BMZERO, 1318 BMZERO, 1319 BMZERO, 1320 BM(F1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1321 BM(G1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1322 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1323 BM(NG2_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1324 BMZERO}, 1325 1326 {MKKA, MKK, NO_DFS, PSCAN_MKKA | PSCAN_MKKA_G | PSCAN_MKKA1 | PSCAN_MKKA1_G | PSCAN_MKKA2 | PSCAN_MKKA2_G, DISALLOW_ADHOC_11A_TURB, 1327 BMZERO, 1328 BMZERO, 1329 BMZERO, 1330 BM(F2_2412_2462, F1_2467_2472, F2_2484_2484, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1331 BM(G2_2412_2462, G1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1332 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1333 BM(NG1_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1334 BMZERO}, 1335 1336 {MKKC, MKK, NO_DFS, NO_PSCAN, NO_REQ, 1337 BMZERO, 1338 BMZERO, 1339 BMZERO, 1340 BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1341 BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1342 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1343 BM(NG1_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1344 BMZERO}, 1345 1346 {WORLD, ETSI, NO_DFS, NO_PSCAN, NO_REQ, 1347 BMZERO, 1348 BMZERO, 1349 BMZERO, 1350 BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1351 BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1352 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1353 BM(NG1_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1354 BMZERO}, 1355 1356 {WOR0_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, 1357 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), 1358 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1359 BMZERO, 1360 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), 1361 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), 1362 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1363 BMZERO, 1364 BMZERO}, 1365 1366 {WOR01_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, 1367 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), 1368 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1369 BMZERO, 1370 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), 1371 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1), 1372 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1373 BMZERO, 1374 BMZERO}, 1375 1376 {WOR02_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, 1377 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), 1378 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1379 BMZERO, 1380 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), 1381 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), 1382 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1383 BMZERO, 1384 BMZERO}, 1385 1386 {EU1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, 1387 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), 1388 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1389 BMZERO, 1390 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1), 1391 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG2_2472_2472, WG1_2417_2432, WG1_2447_2457, WG2_2467_2467, -1, -1, -1, -1, -1), 1392 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1393 BMZERO, 1394 BMZERO}, 1395 1396 {WOR1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, 1397 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), 1398 BMZERO, 1399 BMZERO, 1400 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), 1401 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), 1402 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1403 BMZERO, 1404 BMZERO}, 1405 1406 {WOR2_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, 1407 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1), 1408 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1409 BMZERO, 1410 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1), 1411 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), 1412 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1413 BMZERO, 1414 BMZERO}, 1415 1416 {WOR3_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D, 1417 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1), 1418 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1419 BMZERO, 1420 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), 1421 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), 1422 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1423 BMZERO, 1424 BMZERO}, 1425 1426 {WOR4_WORLD, NO_CTL, DFS_FCC3, PSCAN_WWR, ADHOC_NO_11A, 1427 BM(W2_5260_5320, W2_5180_5240, F2_5745_5805, W2_5825_5825, -1, -1, -1, -1, -1, -1, -1, -1), 1428 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1429 BMZERO, 1430 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), 1431 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1), 1432 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1433 BMZERO, 1434 BMZERO}, 1435 1436 {WOR5_ETSIC, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, 1437 BM(W1_5260_5320, W2_5180_5240, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1438 BMZERO, 1439 BMZERO, 1440 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1), 1441 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), 1442 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1443 BMZERO, 1444 BMZERO}, 1445 1446 {WOR9_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, 1447 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1), 1448 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1449 BMZERO, 1450 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1), 1451 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1), 1452 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1453 BMZERO, 1454 BMZERO}, 1455 1456 {WORA_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A, 1457 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1), 1458 BMZERO, 1459 BMZERO, 1460 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1), 1461 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1), 1462 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1), 1463 BMZERO, 1464 BMZERO}, 1465 1466 {NULL1, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ, 1467 BMZERO, 1468 BMZERO, 1469 BMZERO, 1470 BMZERO, 1471 BMZERO, 1472 BMZERO, 1473 BMZERO, 1474 BMZERO}, 1475}; 1476 1477struct cmode { 1478 u16_t mode; 1479 u32_t flags; 1480}; 1481 1482static const struct cmode modes[] = { 1483 { HAL_MODE_TURBO, CHANNEL_ST}, /* TURBO means 11a Static Turbo */ 1484 { HAL_MODE_11A, CHANNEL_A}, 1485 { HAL_MODE_11B, CHANNEL_B}, 1486 { HAL_MODE_11G, CHANNEL_G}, 1487 { HAL_MODE_11G_TURBO, CHANNEL_108G}, 1488 { HAL_MODE_11A_TURBO, CHANNEL_108A}, 1489 { HAL_MODE_11NA, CHANNEL_A_HT40}, 1490 { HAL_MODE_11NA, CHANNEL_A_HT20}, 1491 { HAL_MODE_11NG, CHANNEL_G_HT40}, 1492 { HAL_MODE_11NG, CHANNEL_G_HT20}, 1493}; 1494 1495/* 1496 * Return the Wireless Mode Regulatory Domain based 1497 * on the country code and the wireless mode. 1498 */ 1499u8_t GetWmRD(u16_t regionCode, u16_t channelFlag, REG_DOMAIN *rd) 1500{ 1501 s16_t i, found, regDmn; 1502 u64_t flags = NO_REQ; 1503 REG_DMN_PAIR_MAPPING *regPair = NULL; 1504 1505 for (i = 0, found = 0; (i < ARRAY_SIZE(regDomainPairs)) && (!found); i++) { 1506 if (regDomainPairs[i].regDmnEnum == regionCode) { 1507 regPair = ®DomainPairs[i]; 1508 found = 1; 1509 } 1510 } 1511 if (!found) { 1512 zm_debug_msg1("Failed to find reg domain pair ", regionCode); 1513 return FALSE; 1514 } 1515 1516 if (channelFlag & ZM_REG_FLAG_CHANNEL_2GHZ) { 1517 regDmn = regPair->regDmn2GHz; 1518 flags = regPair->flags2GHz; 1519 } else { 1520 regDmn = regPair->regDmn5GHz; 1521 flags = regPair->flags5GHz; 1522 } 1523 1524 /* 1525 * We either started with a unitary reg domain or we've found the 1526 * unitary reg domain of the pair 1527 */ 1528 1529 for (i = 0 ; i < ARRAY_SIZE(regDomains) ; i++) { 1530 if (regDomains[i].regDmnEnum == regDmn) { 1531 if (rd != NULL) { 1532 zfMemoryCopy((u8_t *)rd, (u8_t *)®Domains[i], 1533 sizeof(REG_DOMAIN)); 1534 } 1535 } 1536 } 1537 rd->pscan &= regPair->pscanMask; 1538 rd->flags = (u32_t)flags; 1539 return TRUE; 1540} 1541 1542/* 1543 * Test to see if the bitmask array is all zeros 1544 */ 1545u8_t isChanBitMaskZero(u64_t *bitmask) 1546{ 1547 u16_t i; 1548 1549 for (i = 0; i < BMLEN; i++) { 1550 if (bitmask[i] != 0) 1551 return FALSE; 1552 } 1553 return TRUE; 1554} 1555 1556u8_t IS_BIT_SET(u32_t bit, u64_t *bitmask) 1557{ 1558 u32_t byteOffset, bitnum; 1559 u64_t val; 1560 1561 byteOffset = bit/64; 1562 bitnum = bit - byteOffset*64; 1563 val = ((u64_t) 1) << bitnum; 1564 if (bitmask[byteOffset] & val) 1565 return TRUE; 1566 else 1567 return FALSE; 1568} 1569 1570 1571void zfHpGetRegulationTable(zdev_t *dev, u16_t regionCode, u16_t c_lo, u16_t c_hi) 1572{ 1573 REG_DOMAIN rd5GHz, rd2GHz; 1574 const struct cmode *cm; 1575 s16_t next = 0, b; 1576 struct zsHpPriv *hpPriv; 1577 1578 zmw_get_wlan_dev(dev); 1579 hpPriv = wd->hpPrivate; 1580 1581 zmw_declare_for_critical_section(); 1582 1583 if (!GetWmRD(regionCode, ~ZM_REG_FLAG_CHANNEL_2GHZ, &rd5GHz)) { 1584 zm_debug_msg1("couldn't find unitary 5GHz reg domain for Region Code ", regionCode); 1585 return; 1586 } 1587 if (!GetWmRD(regionCode, ZM_REG_FLAG_CHANNEL_2GHZ, &rd2GHz)) { 1588 zm_debug_msg1("couldn't find unitary 2GHz reg domain for Region Code ", regionCode); 1589 return; 1590 } 1591 if (wd->regulationTable.regionCode == regionCode) { 1592 zm_debug_msg1("current region code is the same with Region Code ", regionCode); 1593 return; 1594 } else 1595 wd->regulationTable.regionCode = regionCode; 1596 1597 next = 0; 1598 1599 zmw_enter_critical_section(dev); 1600 1601 for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) { 1602 u16_t c; 1603 u64_t *channelBM = NULL; 1604 REG_DOMAIN *rd = NULL; 1605 REG_DMN_FREQ_BAND *fband = NULL, *freqs = NULL; 1606 1607 switch (cm->mode) { 1608 case HAL_MODE_TURBO: 1609 /* we don't have turbo mode so we disable it 1610 //zm_debug_msg0("CWY - HAL_MODE_TURBO"); */ 1611 channelBM = NULL; 1612 /* rd = &rd5GHz; 1613 channelBM = rd->chan11a_turbo; 1614 freqs = ®Dmn5GhzTurboFreq[0]; 1615 ctl = rd->conformanceTestLimit | CTL_TURBO; */ 1616 break; 1617 case HAL_MODE_11A: 1618 if ((hpPriv->OpFlags & 0x1) != 0) { 1619 rd = &rd5GHz; 1620 channelBM = rd->chan11a; 1621 freqs = ®Dmn5GhzFreq[0]; 1622 c_lo = 4920; /* from channel 184 */ 1623 c_hi = 5825; /* to channel 165 */ 1624 /* ctl = rd->conformanceTestLimit; 1625 zm_debug_msg2("CWY - HAL_MODE_11A, channelBM = 0x", *channelBM); */ 1626 } 1627 /* else 1628 channelBM = NULL; 1629 */ 1630 break; 1631 case HAL_MODE_11B: 1632 /* Disable 11B mode because it only has difference with 11G in PowerDFS Data, 1633 and we don't use this now. 1634 zm_debug_msg0("CWY - HAL_MODE_11B"); */ 1635 channelBM = NULL; 1636 /* rd = &rd2GHz; 1637 channelBM = rd->chan11b; 1638 freqs = ®Dmn2GhzFreq[0]; 1639 ctl = rd->conformanceTestLimit | CTL_11B; 1640 zm_debug_msg2("CWY - HAL_MODE_11B, channelBM = 0x", *channelBM); */ 1641 break; 1642 case HAL_MODE_11G: 1643 if ((hpPriv->OpFlags & 0x2) != 0) { 1644 rd = &rd2GHz; 1645 channelBM = rd->chan11g; 1646 freqs = ®Dmn2Ghz11gFreq[0]; 1647 c_lo = 2412; /* from channel 1 */ 1648 /* c_hi = 2462; to channel 11 */ 1649 c_hi = 2472; /* to channel 13 */ 1650 /* ctl = rd->conformanceTestLimit | CTL_11G; */ 1651 /* zm_debug_msg2("CWY - HAL_MODE_11G, channelBM = 0x", *channelBM); */ 1652 } 1653 /* else 1654 channelBM = NULL; 1655 */ 1656 break; 1657 case HAL_MODE_11G_TURBO: 1658 /* we don't have turbo mode so we disable it 1659 zm_debug_msg0("CWY - HAL_MODE_11G_TURBO"); */ 1660 channelBM = NULL; 1661 /* rd = &rd2GHz; 1662 channelBM = rd->chan11g_turbo; 1663 freqs = ®Dmn2Ghz11gTurboFreq[0]; 1664 ctl = rd->conformanceTestLimit | CTL_108G; */ 1665 break; 1666 case HAL_MODE_11A_TURBO: 1667 /* we don't have turbo mode so we disable it 1668 zm_debug_msg0("CWY - HAL_MODE_11A_TURBO"); */ 1669 channelBM = NULL; 1670 /* rd = &rd5GHz; 1671 channelBM = rd->chan11a_dyn_turbo; 1672 freqs = ®Dmn5GhzTurboFreq[0]; 1673 ctl = rd->conformanceTestLimit | CTL_108G; */ 1674 break; 1675 default: 1676 zm_debug_msg1("Unkonwn HAL mode ", cm->mode); 1677 continue; 1678 } 1679 1680 if (channelBM == NULL) { 1681 /* zm_debug_msg0("CWY - channelBM is NULL"); */ 1682 continue; 1683 } 1684 1685 if (isChanBitMaskZero(channelBM)) { 1686 /* zm_debug_msg0("CWY - BitMask is Zero"); */ 1687 continue; 1688 } 1689 1690 /* RAY:Is it ok?? */ 1691 if (freqs == NULL) 1692 continue; 1693 1694 for (b = 0 ; b < 64*BMLEN ; b++) { 1695 if (IS_BIT_SET(b, channelBM)) { 1696 fband = &freqs[b]; 1697 1698 /* zm_debug_msg1("CWY - lowChannel = ", fband->lowChannel); 1699 zm_debug_msg1("CWY - highChannel = ", fband->highChannel); 1700 zm_debug_msg1("CWY - channelSep = ", fband->channelSep); */ 1701 for (c = fband->lowChannel; c <= fband->highChannel; 1702 c += fband->channelSep) { 1703 ZM_HAL_CHANNEL icv; 1704 1705 /* Disable all DFS channel */ 1706 if ((hpPriv->disableDfsCh == 0) || (!(fband->useDfs & rd->dfsMask))) { 1707 if (fband->channelBW < 20) { 1708 /**************************************************************/ 1709 /* */ 1710 /* Temporary discard channel that BW < 20MHz (5 or 10MHz) */ 1711 /* Our architecture does not implemnt it !!! */ 1712 /* */ 1713 /**************************************************************/ 1714 continue; 1715 } 1716 if ((c >= c_lo) && (c <= c_hi)) { 1717 icv.channel = c; 1718 icv.channelFlags = cm->flags; 1719 icv.maxRegTxPower = fband->powerDfs; 1720 if (fband->usePassScan & rd->pscan) 1721 icv.channelFlags |= ZM_REG_FLAG_CHANNEL_PASSIVE; 1722 else 1723 icv.channelFlags &= ~ZM_REG_FLAG_CHANNEL_PASSIVE; 1724 if (fband->useDfs & rd->dfsMask) 1725 icv.privFlags = ZM_REG_FLAG_CHANNEL_DFS; 1726 else 1727 icv.privFlags = 0; 1728 1729 /* For now disable radar for FCC3 */ 1730 if (fband->useDfs & rd->dfsMask & DFS_FCC3) { 1731 icv.privFlags &= ~ZM_REG_FLAG_CHANNEL_DFS; 1732 icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR; 1733 } 1734 1735 if (rd->flags & LIMIT_FRAME_4MS) 1736 icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR; 1737 1738 icv.minTxPower = 0; 1739 icv.maxTxPower = 0; 1740 1741 zm_assert(next < 60); 1742 1743 wd->regulationTable.allowChannel[next++] = icv; 1744 } 1745 } 1746 } 1747 } 1748 } 1749 } 1750 wd->regulationTable.allowChannelCnt = next; 1751 1752 1753 zmw_leave_critical_section(dev); 1754} 1755 1756void zfHpGetRegulationTablefromRegionCode(zdev_t *dev, u16_t regionCode) 1757{ 1758 u16_t c_lo = 2000, c_hi = 6000; /* default channel is all enable */ 1759 u8_t isoName[3] = {'N', 'A', 0}; 1760 1761 zfCoreSetIsoName(dev, isoName); 1762 1763 zfHpGetRegulationTable(dev, regionCode, c_lo, c_hi); 1764} 1765 1766void zfHpGetRegulationTablefromCountry(zdev_t *dev, u16_t CountryCode) 1767{ 1768 u16_t i; 1769 u16_t c_lo = 2000, c_hi = 6000; /* default channel is all enable */ 1770 u16_t RegDomain; 1771 1772 zmw_get_wlan_dev(dev); 1773 1774 zmw_declare_for_critical_section(); 1775 1776 for (i = 0; i < ARRAY_SIZE(allCountries); i++) { 1777 if (CountryCode == allCountries[i].countryCode) { 1778 RegDomain = allCountries[i].regDmnEnum; 1779 1780 /* read the ACU country code from EEPROM */ 1781 zfCoreSetIsoName(dev, (u8_t *)allCountries[i].isoName); 1782 1783 /* zm_debug_msg_s("CWY - Country Name = ", allCountries[i].name); */ 1784 1785 if (wd->regulationTable.regionCode != RegDomain) { 1786 /* zm_debug_msg0("CWY - Change regulatory table"); */ 1787 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi); 1788 } 1789 return; 1790 } 1791 } 1792 zm_debug_msg1("Invalid CountryCode = ", CountryCode); 1793} 1794 1795u8_t zfHpGetRegulationTablefromISO(zdev_t *dev, u8_t *countryInfo, u8_t length) 1796{ 1797 u16_t i; 1798 u16_t RegDomain; 1799 u16_t c_lo = 2000, c_hi = 6000; /* default channel is all enable */ 1800 /* u8_t strLen = 2; */ 1801 1802 zmw_get_wlan_dev(dev); 1803 1804 zmw_declare_for_critical_section(); 1805 1806 if (countryInfo[4] != 0x20) { 1807 /* with (I)ndoor/(O)utdoor info 1808 strLen = 3; */ 1809 } 1810 /* zm_debug_msg_s("Desired iso name = ", isoName); */ 1811 for (i = 0; i < ARRAY_SIZE(allCountries); i++) { 1812 /* zm_debug_msg_s("Current iso name = ", allCountries[i].isoName); */ 1813 if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, (u8_t *)&countryInfo[2], length-1)) { 1814 /* DbgPrint("Set current iso name = %s\n", allCountries[i].isoName); */ 1815 /* zm_debug_msg0("iso name hit!!"); */ 1816 1817 RegDomain = allCountries[i].regDmnEnum; 1818 1819 if (wd->regulationTable.regionCode != RegDomain) 1820 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi); 1821 /* 1822 while (index < (countryInfo[1]+2)) { 1823 if (countryInfo[index] <= 14) { 1824 // calculate 2.4GHz low boundary channel frequency 1825 ch = countryInfo[index]; 1826 if ( ch == 14 ) 1827 c_lo = ZM_CH_G_14; 1828 else 1829 c_lo = ZM_CH_G_1 + (ch - 1) * 5; 1830 // calculate 2.4GHz high boundary channel frequency 1831 ch = countryInfo[index] + countryInfo[index + 1] - 1; 1832 if ( ch == 14 ) 1833 c_hi = ZM_CH_G_14; 1834 else 1835 c_hi = ZM_CH_G_1 + (ch - 1) * 5; 1836 } else { 1837 // calculate 5GHz low boundary channel frequency 1838 ch = countryInfo[index]; 1839 if ( (ch >= 184)&&(ch <= 196) ) 1840 c_lo = 4000 + ch*5; 1841 else 1842 c_lo = 5000 + ch*5; 1843 // calculate 5GHz high boundary channel frequency 1844 ch = countryInfo[index] + countryInfo[index + 1] - 1; 1845 if ( (ch >= 184)&&(ch <= 196) ) 1846 c_hi = 4000 + ch*5; 1847 else 1848 c_hi = 5000 + ch*5; 1849 } 1850 1851 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi); 1852 1853 index+=3; 1854 } 1855 */ 1856 return 0; 1857 } 1858 } 1859 /* zm_debug_msg_s("Invalid iso name = ", &countryInfo[2]); */ 1860 return 1; 1861} 1862 1863const char *zfHpGetisoNamefromregionCode(zdev_t *dev, u16_t regionCode) 1864{ 1865 u16_t i; 1866 1867 for (i = 0; i < ARRAY_SIZE(allCountries); i++) { 1868 if (allCountries[i].regDmnEnum == regionCode) 1869 return allCountries[i].isoName; 1870 } 1871 /* no matching item, return default */ 1872 return allCountries[0].isoName; 1873} 1874 1875u16_t zfHpGetRegionCodeFromIsoName(zdev_t *dev, u8_t *countryIsoName) 1876{ 1877 u16_t i; 1878 u16_t regionCode; 1879 1880 /* if no matching item, return default */ 1881 regionCode = DEF_REGDMN; 1882 1883 for (i = 0; i < ARRAY_SIZE(allCountries); i++) { 1884 if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, countryIsoName, 2)) { 1885 regionCode = allCountries[i].regDmnEnum; 1886 break; 1887 } 1888 } 1889 1890 return regionCode; 1891} 1892 1893/************************************************************************/ 1894/* */ 1895/* FUNCTION DESCRIPTION zfHpDeleteAllowChannel */ 1896/* Delete Allow Channel. */ 1897/* */ 1898/* INPUTS */ 1899/* dev : device pointer */ 1900/* freq : frequency */ 1901/* */ 1902/* OUTPUTS */ 1903/* 0 : success */ 1904/* other : fail */ 1905/* */ 1906/* AUTHOR */ 1907/* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */ 1908/* */ 1909/************************************************************************/ 1910u16_t zfHpDeleteAllowChannel(zdev_t *dev, u16_t freq) 1911{ 1912 u16_t i, bandIndex = 0; 1913 u16_t dfs5GBand[][2] = { {5150, 5240}, {5260, 5350}, {5450, 5700}, {5725, 5825} }; 1914 1915 zmw_get_wlan_dev(dev); 1916 /* Find which band does this frequency belong */ 1917 for (i = 0; i < 4; i++) { 1918 if ((freq >= dfs5GBand[i][0]) && (freq <= dfs5GBand[i][1])) 1919 bandIndex = i + 1; 1920 } 1921 1922 if (bandIndex == 0) { 1923 /* 2.4G, don't care */ 1924 return 0; 1925 } else 1926 bandIndex--; 1927 /* Set all channels in this band to passive scan */ 1928 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) { 1929 if ((wd->regulationTable.allowChannel[i].channel >= dfs5GBand[bandIndex][0]) && 1930 (wd->regulationTable.allowChannel[i].channel <= dfs5GBand[bandIndex][1])) { 1931 /* if channel is not passive, set it to be passive and mark it */ 1932 if ((wd->regulationTable.allowChannel[i].channelFlags & 1933 ZM_REG_FLAG_CHANNEL_PASSIVE) == 0) { 1934 wd->regulationTable.allowChannel[i].channelFlags |= 1935 (ZM_REG_FLAG_CHANNEL_PASSIVE | ZM_REG_FLAG_CHANNEL_CSA); 1936 } 1937 } 1938 } 1939 1940 return 0; 1941} 1942 1943u16_t zfHpAddAllowChannel(zdev_t *dev, u16_t freq) 1944{ 1945 u16_t i, j, arrayIndex; 1946 1947 zmw_get_wlan_dev(dev); 1948 1949 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) { 1950 if (wd->regulationTable.allowChannel[i].channel == freq) 1951 break; 1952 } 1953 1954 if (i == wd->regulationTable.allowChannelCnt) { 1955 for (j = 0; j < wd->regulationTable.allowChannelCnt; j++) { 1956 if (wd->regulationTable.allowChannel[j].channel > freq) 1957 break; 1958 } 1959 1960 /* zm_debug_msg1("CWY - add frequency = ", freq); 1961 zm_debug_msg1("CWY - channel array index = ", j); */ 1962 1963 arrayIndex = j; 1964 1965 if (arrayIndex < wd->regulationTable.allowChannelCnt) { 1966 for (j = wd->regulationTable.allowChannelCnt; j > arrayIndex; j--) 1967 wd->regulationTable.allowChannel[j] = wd->regulationTable.allowChannel[j - 1]; 1968 } 1969 wd->regulationTable.allowChannel[arrayIndex].channel = freq; 1970 1971 wd->regulationTable.allowChannelCnt++; 1972 } 1973 1974 return 0; 1975} 1976 1977u16_t zfHpIsDfsChannelNCS(zdev_t *dev, u16_t freq) 1978{ 1979 u8_t flag = ZM_REG_FLAG_CHANNEL_DFS; 1980 u16_t i; 1981 zmw_get_wlan_dev(dev); 1982 1983 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) { 1984 /* DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel); */ 1985 if (wd->regulationTable.allowChannel[i].channel == freq) { 1986 flag = wd->regulationTable.allowChannel[i].privFlags; 1987 break; } 1988 } 1989 1990 return flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR); 1991} 1992 1993u16_t zfHpIsDfsChannel(zdev_t *dev, u16_t freq) 1994{ 1995 u8_t flag = ZM_REG_FLAG_CHANNEL_DFS; 1996 u16_t i; 1997 zmw_get_wlan_dev(dev); 1998 1999 zmw_declare_for_critical_section(); 2000 2001 zmw_enter_critical_section(dev); 2002 2003 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) { 2004 /* DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel); */ 2005 if (wd->regulationTable.allowChannel[i].channel == freq) { 2006 flag = wd->regulationTable.allowChannel[i].privFlags; 2007 break; 2008 } 2009 } 2010 2011 zmw_leave_critical_section(dev); 2012 2013 return flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR); 2014} 2015 2016u16_t zfHpIsAllowedChannel(zdev_t *dev, u16_t freq) 2017{ 2018 u16_t i; 2019 zmw_get_wlan_dev(dev); 2020 2021 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) { 2022 if (wd->regulationTable.allowChannel[i].channel == freq) 2023 return 1; 2024 } 2025 2026 return 0; 2027} 2028 2029u16_t zfHpFindFirstNonDfsChannel(zdev_t *dev, u16_t aBand) 2030{ 2031 u16_t chan = 2412; 2032 u16_t i; 2033 zmw_get_wlan_dev(dev); 2034 2035 zmw_declare_for_critical_section(); 2036 2037 zmw_enter_critical_section(dev); 2038 2039 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) { 2040 if ((wd->regulationTable.allowChannel[i].privFlags & ZM_REG_FLAG_CHANNEL_DFS) != 0) { 2041 if (aBand) { 2042 if (wd->regulationTable.allowChannel[i].channel > 3000) { 2043 chan = wd->regulationTable.allowChannel[i].channel; 2044 break; 2045 } 2046 } else { 2047 if (wd->regulationTable.allowChannel[i].channel < 3000) { 2048 chan = wd->regulationTable.allowChannel[i].channel; 2049 break; 2050 } 2051 } 2052 } 2053 } 2054 2055 zmw_leave_critical_section(dev); 2056 2057 return chan; 2058} 2059 2060 2061/* porting from ACU */ 2062/* save RegulatoryDomain in hpriv */ 2063u8_t zfHpGetRegulatoryDomain(zdev_t *dev) 2064{ 2065 zmw_get_wlan_dev(dev); 2066 2067 switch (wd->regulationTable.regionCode) { 2068 case NO_ENUMRD: 2069 return 0; 2070 break; 2071 case FCC1_FCCA: 2072 case FCC1_WORLD: 2073 case FCC4_FCCA: 2074 case FCC5_FCCA: 2075 case FCC2_WORLD: 2076 case FCC2_ETSIC: 2077 case FCC3_FCCA: 2078 case FCC3_WORLD: 2079 case FCC1: 2080 case FCC2: 2081 case FCC3: 2082 case FCC4: 2083 case FCC5: 2084 case FCCA: 2085 return 0x10;/* WG_AMERICAS DOT11_REG_DOMAIN_FCC United States */ 2086 break; 2087 2088 case FCC2_FCCA: 2089 return 0x20;/* DOT11_REG_DOMAIN_DOC Canada */ 2090 break; 2091 2092 case ETSI1_WORLD: 2093 case ETSI3_ETSIA: 2094 case ETSI2_WORLD: 2095 case ETSI3_WORLD: 2096 case ETSI4_WORLD: 2097 case ETSI4_ETSIC: 2098 case ETSI5_WORLD: 2099 case ETSI6_WORLD: 2100 case ETSI_RESERVED: 2101 case ETSI1: 2102 case ETSI2: 2103 case ETSI3: 2104 case ETSI4: 2105 case ETSI5: 2106 case ETSI6: 2107 case ETSIA: 2108 case ETSIB: 2109 case ETSIC: 2110 return 0x30;/* WG_EMEA DOT11_REG_DOMAIN_ETSI Most of Europe */ 2111 break; 2112 2113 case MKK1_MKKA: 2114 case MKK1_MKKB: 2115 case MKK2_MKKA: 2116 case MKK1_FCCA: 2117 case MKK1_MKKA1: 2118 case MKK1_MKKA2: 2119 case MKK1_MKKC: 2120 case MKK3_MKKB: 2121 case MKK3_MKKA2: 2122 case MKK3_MKKC: 2123 case MKK4_MKKB: 2124 case MKK4_MKKA2: 2125 case MKK4_MKKC: 2126 case MKK5_MKKB: 2127 case MKK5_MKKA2: 2128 case MKK5_MKKC: 2129 case MKK6_MKKB: 2130 case MKK6_MKKA2: 2131 case MKK6_MKKC: 2132 case MKK7_MKKB: 2133 case MKK7_MKKA: 2134 case MKK7_MKKC: 2135 case MKK8_MKKB: 2136 case MKK8_MKKA2: 2137 case MKK8_MKKC: 2138 case MKK6_MKKA1: 2139 case MKK6_FCCA: 2140 case MKK7_MKKA1: 2141 case MKK7_FCCA: 2142 case MKK9_FCCA: 2143 case MKK9_MKKA1: 2144 case MKK9_MKKC: 2145 case MKK9_MKKA2: 2146 case MKK10_FCCA: 2147 case MKK10_MKKA1: 2148 case MKK10_MKKC: 2149 case MKK10_MKKA2: 2150 case MKK11_MKKA: 2151 case MKK11_FCCA: 2152 case MKK11_MKKA1: 2153 case MKK11_MKKC: 2154 case MKK11_MKKA2: 2155 case MKK12_MKKA: 2156 case MKK12_FCCA: 2157 case MKK12_MKKA1: 2158 case MKK12_MKKC: 2159 case MKK12_MKKA2: 2160 case MKK3_MKKA: 2161 case MKK3_MKKA1: 2162 case MKK3_FCCA: 2163 case MKK4_MKKA: 2164 case MKK4_MKKA1: 2165 case MKK4_FCCA: 2166 case MKK9_MKKA: 2167 case MKK10_MKKA: 2168 case MKK1: 2169 case MKK2: 2170 case MKK3: 2171 case MKK4: 2172 case MKK5: 2173 case MKK6: 2174 case MKK7: 2175 case MKK8: 2176 case MKK9: 2177 case MKK10: 2178 case MKK11: 2179 case MKK12: 2180 case MKKA: 2181 case MKKC: 2182 return 0x40;/* WG_JAPAN DOT11_REG_DOMAIN_MKK Japan */ 2183 break; 2184 2185 default: 2186 break; 2187 } 2188 2189 return 0xFF; /* Didn't input RegDmn by mean to distinguish by customer */ 2190} 2191 2192void zfHpDisableDfsChannel(zdev_t *dev, u8_t disableFlag) 2193{ 2194 struct zsHpPriv *hpPriv; 2195 2196 zmw_get_wlan_dev(dev); 2197 hpPriv = wd->hpPrivate; 2198 hpPriv->disableDfsCh = disableFlag; 2199 return; 2200} 2201