1#ifndef _INC_PMCC4_PRIVATE_H_ 2#define _INC_PMCC4_PRIVATE_H_ 3 4/*----------------------------------------------------------------------------- 5 * pmcc4_private.h - 6 * 7 * Copyright (C) 2005 SBE, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 21#include <linux/kernel.h> 22#include <linux/sched.h> 23#include <linux/semaphore.h> 24#include <linux/spinlock.h> 25#include <linux/interrupt.h> /* support for tasklets */ 26#include <linux/timer.h> /* support for timer */ 27#include <linux/workqueue.h> 28#include <linux/hdlc.h> 29 30#include "libsbew.h" 31#include "pmcc4_defs.h" 32#include "pmcc4_cpld.h" 33#include "musycc.h" 34#include "sbe_promformat.h" 35#include "comet.h" 36 37 38/* driver state */ 39#define SBE_DRVR_INIT 0x0 40#define SBE_DRVR_AVAILABLE 0x69734F4E 41#define SBE_DRVR_DOWN 0x1 42 43/****************************************************************************** 44 * MUSYCC Message Descriptor - coupled to hardware implementation, the first 45 * three u_int32 must not be reordered. 46 */ 47 48struct mdesc 49{ 50 volatile u_int32_t status; /* Buffer Descriptor */ 51 u_int32_t data; /* Data Pointer */ 52 u_int32_t next; /* MUSYCC view of Next Pointer */ 53 void *mem_token; /* Data */ 54 struct mdesc *snext; 55}; 56 57 58/************************************************************************* 59 * Private driver data structures, internal use only. 60 */ 61 62struct c4_chan_info 63{ 64 int gchan; /* channel number within group/port 0-31 */ 65 int channum; /* absolute channel number 0-128 */ 66 u_int8_t status; 67#define TX_RECOVERY_MASK 0x0f 68#define TX_ONR_RECOVERY 0x01 69#define TX_BUFF_RECOVERY 0x02 70#define RX_RECOVERY_MASK 0xf0 71#define RX_ONR_RECOVERY 0x10 72 73 unsigned char ch_start_rx; 74#define CH_START_RX_NOW 1 75#define CH_START_RX_ONR 2 76#define CH_START_RX_BUF 3 77 78 unsigned char ch_start_tx; 79#define CH_START_TX_1ST 1 80#define CH_START_TX_ONR 2 81#define CH_START_TX_BUF 3 82 83 char tx_full; /* boolean */ 84 short txd_free; /* count of TX Desc available */ 85 short txd_required; /* count of TX Desc needed by mesg */ 86 unsigned short rxd_num; /* must support range up to 2000 */ 87 unsigned short txd_num; /* must support range up to 1000 */ 88 int rxix_irq_srv; 89 90 enum 91 { 92 UNASSIGNED, /* AVAILABLE, NOTINUSE */ 93 DOWN, /* ASSIGNED, NOTINUSE */ 94 UP /* ASSIGNED and INUSE */ 95 } state; 96 97 struct c4_port_info *up; 98 void *user; 99 100 struct work_struct ch_work; 101 struct mdesc *mdt; 102 struct mdesc *mdr; 103 struct mdesc *txd_irq_srv; 104 struct mdesc *txd_usr_add; 105 106 spinlock_t ch_rxlock; 107 spinlock_t ch_txlock; 108 atomic_t tx_pending; 109 110 struct sbecom_chan_stats s; 111 struct sbecom_chan_param p; 112}; 113typedef struct c4_chan_info mch_t; 114 115struct c4_port_info 116{ 117 118 struct musycc_globalr *reg; 119 struct musycc_groupr *regram; 120 void *regram_saved; /* Original malloc value may have non-2KB 121 * boundary. Need to save for use when 122 * freeing. */ 123 comet_t *cometbase; 124 struct sbe_card_info *up; 125 126 /* 127 * The workqueue is used for TX restart of ONR'd channels when in 128 * Transparent mode. 129 */ 130 131 struct workqueue_struct *wq_port; /* chan restart work queue */ 132 struct semaphore sr_sem_busy; /* service request exclusion 133 * semaphore */ 134 struct semaphore sr_sem_wait; /* service request handshake 135 * semaphore */ 136 u_int32_t sr_last; 137 short openchans; 138 char portnum; 139 char group_is_set; /* GROUP_INIT command issued to MUSYCC, 140 * otherwise SET_CHAN Ioctl fails */ 141 142 mch_t *chan[MUSYCC_NCHANS]; 143 struct sbecom_port_param p; 144 145 /* 146 * The MUSYCC timeslot mappings are maintained within the driver and are 147 * modified and reloaded as each of a group's channels are configured. 148 */ 149 u_int8_t tsm[32]; /* tsm (time slot map) */ 150 int fifomap[32]; 151}; 152typedef struct c4_port_info mpi_t; 153 154 155#define COMET_OFFSET(x) (0x80000+(x)*0x10000) 156#define EEPROM_OFFSET 0xC0000 157#define ISPLD_OFFSET 0xD0000 158 159/* iSPLD control chip registers */ 160#define ISPLD_MCSR 0x0 161#define ISPLD_MCLK 0x1 162#define ISPLD_LEDS 0x2 163#define ISPLD_INTR 0x3 164#define ISPLD_MAX 0x3 165 166struct sbe_card_info 167{ 168 struct musycc_globalr *reg; 169 struct musycc_groupr *regram; 170 u_int32_t *iqd_p; /* pointer to dword aligned interrupt queue 171 * descriptors */ 172 void *iqd_p_saved; /* Original malloc value may have non-dword 173 * aligned boundary. Need to save for use 174 * when freeing. */ 175 unsigned int iqp_headx, iqp_tailx; 176 177 struct semaphore sem_wdbusy;/* watchdog exclusion semaphore */ 178 struct watchdog wd; /* statically allocated watchdog structure */ 179 atomic_t bh_pending; /* bh queued, but not yet running */ 180 u_int32_t brd_id; /* unique PCI ID */ 181 u_int16_t hdw_bid; /* on/board hardware ID */ 182 unsigned short wdcount; 183 unsigned char max_port; 184 unsigned char brdno; /* our board number */ 185 unsigned char wd_notify; 186#define WD_NOTIFY_1TX 1 187#define WD_NOTIFY_BUF 2 188#define WD_NOTIFY_ONR 4 189 enum /* state as regards interrupt processing */ 190 { 191 C_INIT, /* of-board-address not configured or are in 192 * process of being removed, don't access 193 * hardware */ 194 C_IDLE, /* off-board-addresses are configured, but 195 * don't service interrupts, just clear them 196 * from hardware */ 197 C_RUNNING /* life is good, service away */ 198 } state; 199 200 struct sbe_card_info *next; 201 u_int32_t *eeprombase; /* mapped address of board's EEPROM */ 202 c4cpld_t *cpldbase; /* mapped address of board's CPLD hardware */ 203 char *release; /* SBE ID string w/in sbeRelease.c */ 204 void *hdw_info; 205#ifdef CONFIG_PROC_FS 206 struct proc_dir_entry *dir_dev; 207#endif 208 209 /* saved off interface assignments which bound a board */ 210 hdlc_device *first_if; 211 hdlc_device *last_if; 212 short first_channum, last_channum; 213 214 struct intlog 215 { 216 u_int32_t this_status_new; 217 u_int32_t last_status_new; 218 u_int32_t drvr_intr_thcount; 219 u_int32_t drvr_intr_bhcount; 220 u_int32_t drvr_int_failure; 221 } intlog; 222 223 mpi_t port[MUSYCC_NPORTS]; 224 char devname[SBE_IFACETMPL_SIZE + 1]; 225 atomic_t tx_pending; 226 u_int32_t alarmed[4]; /* dpm211 */ 227 228#if defined(SBE_ISR_TASKLET) 229 struct tasklet_struct ci_musycc_isr_tasklet; 230#elif defined(SBE_ISR_IMMEDIATE) 231 struct tq_struct ci_musycc_isr_tq; 232#endif 233}; 234typedef struct sbe_card_info ci_t; 235 236struct s_hdw_info 237{ 238 u_int8_t pci_busno; 239 u_int8_t pci_slot; 240 u_int8_t pci_pin[2]; 241 u_int8_t revid[2]; 242 u_int8_t mfg_info_sts; 243#define EEPROM_OK 0x00 244#define EEPROM_CRCERR 0x01 245 char promfmt; /* prom type, from sbe_promformat.h */ 246 247 char devname[SBE_IFACETMPL_SIZE]; 248 struct pci_bus *bus; 249 struct net_device *ndev; 250 struct pci_dev *pdev[2]; 251 252 unsigned long addr[2]; 253 unsigned long addr_mapped[2]; 254 unsigned long len[2]; 255 256 union 257 { 258 char data[128]; 259 FLD_TYPE1 pft1; /* prom field, type #1 */ 260 FLD_TYPE2 pft2; /* prom field, type #2 */ 261 } mfg_info; 262}; 263typedef struct s_hdw_info hdw_info_t; 264 265/*****************************************************************/ 266 267struct c4_priv 268{ 269 int channum; 270 struct sbe_card_info *ci; 271}; 272 273 274/*****************************************************************/ 275 276extern ci_t *c4_list; 277 278mch_t *c4_find_chan (int); 279int c4_set_chan (int channum, struct sbecom_chan_param *); 280int c4_get_chan (int channum, struct sbecom_chan_param *); 281int c4_get_chan_stats (int channum, struct sbecom_chan_stats *); 282 283#endif /* _INC_PMCC4_PRIVATE_H_ */ 284