1/* 2 comedi/drivers/ni_mio_common.c 3 Hardware driver for DAQ-STC based boards 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org> 7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 23*/ 24 25/* 26 This file is meant to be included by another file, e.g., 27 ni_atmio.c or ni_pcimio.c. 28 29 Interrupt support originally added by Truxton Fulton 30 <trux@truxton.com> 31 32 References (from ftp://ftp.natinst.com/support/manuals): 33 34 340747b.pdf AT-MIO E series Register Level Programmer Manual 35 341079b.pdf PCI E Series RLPM 36 340934b.pdf DAQ-STC reference manual 37 67xx and 611x registers (from http://www.ni.com/pdf/daq/us) 38 release_ni611x.pdf 39 release_ni67xx.pdf 40 Other possibly relevant info: 41 42 320517c.pdf User manual (obsolete) 43 320517f.pdf User manual (new) 44 320889a.pdf delete 45 320906c.pdf maximum signal ratings 46 321066a.pdf about 16x 47 321791a.pdf discontinuation of at-mio-16e-10 rev. c 48 321808a.pdf about at-mio-16e-10 rev P 49 321837a.pdf discontinuation of at-mio-16de-10 rev d 50 321838a.pdf about at-mio-16de-10 rev N 51 52 ISSUES: 53 54 - the interrupt routine needs to be cleaned up 55 56 2006-02-07: S-Series PCI-6143: Support has been added but is not 57 fully tested as yet. Terry Barnaby, BEAM Ltd. 58*/ 59 60/* #define DEBUG_INTERRUPT */ 61/* #define DEBUG_STATUS_A */ 62/* #define DEBUG_STATUS_B */ 63 64#include <linux/interrupt.h> 65#include <linux/sched.h> 66#include "8255.h" 67#include "mite.h" 68#include "comedi_fc.h" 69 70#ifndef MDPRINTK 71#define MDPRINTK(format, args...) 72#endif 73 74/* A timeout count */ 75#define NI_TIMEOUT 1000 76static const unsigned old_RTSI_clock_channel = 7; 77 78/* Note: this table must match the ai_gain_* definitions */ 79static const short ni_gainlkup[][16] = { 80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7, 81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, 82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107}, 83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7, 84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107}, 85 [ai_gain_4] = {0, 1, 4, 7}, 86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002, 87 0x003, 0x004, 0x005, 0x006}, 88 [ai_gain_622x] = {0, 1, 4, 5}, 89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7}, 90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 91}; 92 93static const struct comedi_lrange range_ni_E_ai = { 16, { 94 RANGE(-10, 10), 95 RANGE(-5, 5), 96 RANGE(-2.5, 2.5), 97 RANGE(-1, 1), 98 RANGE(-0.5, 0.5), 99 RANGE(-0.25, 0.25), 100 RANGE(-0.1, 0.1), 101 RANGE(-0.05, 0.05), 102 RANGE(0, 20), 103 RANGE(0, 10), 104 RANGE(0, 5), 105 RANGE(0, 2), 106 RANGE(0, 1), 107 RANGE(0, 0.5), 108 RANGE(0, 0.2), 109 RANGE(0, 0.1), 110 } 111}; 112 113static const struct comedi_lrange range_ni_E_ai_limited = { 8, { 114 RANGE(-10, 10), 115 RANGE(-5, 5), 116 RANGE(-1, 1), 117 RANGE(-0.1, 118 0.1), 119 RANGE(0, 10), 120 RANGE(0, 5), 121 RANGE(0, 1), 122 RANGE(0, 0.1), 123 } 124}; 125 126static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, { 127 RANGE(-10, 128 10), 129 RANGE(-5, 5), 130 RANGE(-2, 2), 131 RANGE(-1, 1), 132 RANGE(-0.5, 133 0.5), 134 RANGE(-0.2, 135 0.2), 136 RANGE(-0.1, 137 0.1), 138 RANGE(0, 10), 139 RANGE(0, 5), 140 RANGE(0, 2), 141 RANGE(0, 1), 142 RANGE(0, 143 0.5), 144 RANGE(0, 145 0.2), 146 RANGE(0, 147 0.1), 148 } 149}; 150 151static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, { 152 RANGE(-10, 10), 153 RANGE(-5, 5), 154 RANGE(-0.5, 155 0.5), 156 RANGE(-0.05, 157 0.05), 158 } 159}; 160 161static const struct comedi_lrange range_ni_E_ai_611x = { 8, { 162 RANGE(-50, 50), 163 RANGE(-20, 20), 164 RANGE(-10, 10), 165 RANGE(-5, 5), 166 RANGE(-2, 2), 167 RANGE(-1, 1), 168 RANGE(-0.5, 0.5), 169 RANGE(-0.2, 0.2), 170 } 171}; 172 173static const struct comedi_lrange range_ni_M_ai_622x = { 4, { 174 RANGE(-10, 10), 175 RANGE(-5, 5), 176 RANGE(-1, 1), 177 RANGE(-0.2, 0.2), 178 } 179}; 180 181static const struct comedi_lrange range_ni_M_ai_628x = { 7, { 182 RANGE(-10, 10), 183 RANGE(-5, 5), 184 RANGE(-2, 2), 185 RANGE(-1, 1), 186 RANGE(-0.5, 0.5), 187 RANGE(-0.2, 0.2), 188 RANGE(-0.1, 0.1), 189 } 190}; 191 192static const struct comedi_lrange range_ni_S_ai_6143 = { 1, { 193 RANGE(-5, +5), 194 } 195}; 196 197static const struct comedi_lrange range_ni_E_ao_ext = { 4, { 198 RANGE(-10, 10), 199 RANGE(0, 10), 200 RANGE_ext(-1, 1), 201 RANGE_ext(0, 1), 202 } 203}; 204 205static const struct comedi_lrange *const ni_range_lkup[] = { 206 [ai_gain_16] = &range_ni_E_ai, 207 [ai_gain_8] = &range_ni_E_ai_limited, 208 [ai_gain_14] = &range_ni_E_ai_limited14, 209 [ai_gain_4] = &range_ni_E_ai_bipolar4, 210 [ai_gain_611x] = &range_ni_E_ai_611x, 211 [ai_gain_622x] = &range_ni_M_ai_622x, 212 [ai_gain_628x] = &range_ni_M_ai_628x, 213 [ai_gain_6143] = &range_ni_S_ai_6143 214}; 215 216static int ni_dio_insn_config(struct comedi_device *dev, 217 struct comedi_subdevice *s, 218 struct comedi_insn *insn, unsigned int *data); 219static int ni_dio_insn_bits(struct comedi_device *dev, 220 struct comedi_subdevice *s, 221 struct comedi_insn *insn, unsigned int *data); 222static int ni_cdio_cmdtest(struct comedi_device *dev, 223 struct comedi_subdevice *s, struct comedi_cmd *cmd); 224static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 225static int ni_cdio_cancel(struct comedi_device *dev, 226 struct comedi_subdevice *s); 227static void handle_cdio_interrupt(struct comedi_device *dev); 228static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 229 unsigned int trignum); 230 231static int ni_serial_insn_config(struct comedi_device *dev, 232 struct comedi_subdevice *s, 233 struct comedi_insn *insn, unsigned int *data); 234static int ni_serial_hw_readwrite8(struct comedi_device *dev, 235 struct comedi_subdevice *s, 236 unsigned char data_out, 237 unsigned char *data_in); 238static int ni_serial_sw_readwrite8(struct comedi_device *dev, 239 struct comedi_subdevice *s, 240 unsigned char data_out, 241 unsigned char *data_in); 242 243static int ni_calib_insn_read(struct comedi_device *dev, 244 struct comedi_subdevice *s, 245 struct comedi_insn *insn, unsigned int *data); 246static int ni_calib_insn_write(struct comedi_device *dev, 247 struct comedi_subdevice *s, 248 struct comedi_insn *insn, unsigned int *data); 249 250static int ni_eeprom_insn_read(struct comedi_device *dev, 251 struct comedi_subdevice *s, 252 struct comedi_insn *insn, unsigned int *data); 253static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, 254 struct comedi_subdevice *s, 255 struct comedi_insn *insn, 256 unsigned int *data); 257 258static int ni_pfi_insn_bits(struct comedi_device *dev, 259 struct comedi_subdevice *s, 260 struct comedi_insn *insn, unsigned int *data); 261static int ni_pfi_insn_config(struct comedi_device *dev, 262 struct comedi_subdevice *s, 263 struct comedi_insn *insn, unsigned int *data); 264static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, 265 unsigned chan); 266 267static void ni_rtsi_init(struct comedi_device *dev); 268static int ni_rtsi_insn_bits(struct comedi_device *dev, 269 struct comedi_subdevice *s, 270 struct comedi_insn *insn, unsigned int *data); 271static int ni_rtsi_insn_config(struct comedi_device *dev, 272 struct comedi_subdevice *s, 273 struct comedi_insn *insn, unsigned int *data); 274 275static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s); 276static int ni_read_eeprom(struct comedi_device *dev, int addr); 277 278#ifdef DEBUG_STATUS_A 279static void ni_mio_print_status_a(int status); 280#else 281#define ni_mio_print_status_a(a) 282#endif 283#ifdef DEBUG_STATUS_B 284static void ni_mio_print_status_b(int status); 285#else 286#define ni_mio_print_status_b(a) 287#endif 288 289static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s); 290#ifndef PCIDMA 291static void ni_handle_fifo_half_full(struct comedi_device *dev); 292static int ni_ao_fifo_half_empty(struct comedi_device *dev, 293 struct comedi_subdevice *s); 294#endif 295static void ni_handle_fifo_dregs(struct comedi_device *dev); 296static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 297 unsigned int trignum); 298static void ni_load_channelgain_list(struct comedi_device *dev, 299 unsigned int n_chan, unsigned int *list); 300static void shutdown_ai_command(struct comedi_device *dev); 301 302static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 303 unsigned int trignum); 304 305static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s); 306 307static int ni_8255_callback(int dir, int port, int data, unsigned long arg); 308 309static int ni_gpct_insn_write(struct comedi_device *dev, 310 struct comedi_subdevice *s, 311 struct comedi_insn *insn, unsigned int *data); 312static int ni_gpct_insn_read(struct comedi_device *dev, 313 struct comedi_subdevice *s, 314 struct comedi_insn *insn, unsigned int *data); 315static int ni_gpct_insn_config(struct comedi_device *dev, 316 struct comedi_subdevice *s, 317 struct comedi_insn *insn, unsigned int *data); 318static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 319static int ni_gpct_cmdtest(struct comedi_device *dev, 320 struct comedi_subdevice *s, struct comedi_cmd *cmd); 321static int ni_gpct_cancel(struct comedi_device *dev, 322 struct comedi_subdevice *s); 323static void handle_gpct_interrupt(struct comedi_device *dev, 324 unsigned short counter_index); 325 326static int init_cs5529(struct comedi_device *dev); 327static int cs5529_do_conversion(struct comedi_device *dev, 328 unsigned short *data); 329static int cs5529_ai_insn_read(struct comedi_device *dev, 330 struct comedi_subdevice *s, 331 struct comedi_insn *insn, unsigned int *data); 332#ifdef NI_CS5529_DEBUG 333static unsigned int cs5529_config_read(struct comedi_device *dev, 334 unsigned int reg_select_bits); 335#endif 336static void cs5529_config_write(struct comedi_device *dev, unsigned int value, 337 unsigned int reg_select_bits); 338 339static int ni_m_series_pwm_config(struct comedi_device *dev, 340 struct comedi_subdevice *s, 341 struct comedi_insn *insn, unsigned int *data); 342static int ni_6143_pwm_config(struct comedi_device *dev, 343 struct comedi_subdevice *s, 344 struct comedi_insn *insn, unsigned int *data); 345 346static int ni_set_master_clock(struct comedi_device *dev, unsigned source, 347 unsigned period_ns); 348static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status); 349static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status); 350 351enum aimodes { 352 AIMODE_NONE = 0, 353 AIMODE_HALF_FULL = 1, 354 AIMODE_SCAN = 2, 355 AIMODE_SAMPLE = 3, 356}; 357 358enum ni_common_subdevices { 359 NI_AI_SUBDEV, 360 NI_AO_SUBDEV, 361 NI_DIO_SUBDEV, 362 NI_8255_DIO_SUBDEV, 363 NI_UNUSED_SUBDEV, 364 NI_CALIBRATION_SUBDEV, 365 NI_EEPROM_SUBDEV, 366 NI_PFI_DIO_SUBDEV, 367 NI_CS5529_CALIBRATION_SUBDEV, 368 NI_SERIAL_SUBDEV, 369 NI_RTSI_SUBDEV, 370 NI_GPCT0_SUBDEV, 371 NI_GPCT1_SUBDEV, 372 NI_FREQ_OUT_SUBDEV, 373 NI_NUM_SUBDEVICES 374}; 375static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index) 376{ 377 switch (counter_index) { 378 case 0: 379 return NI_GPCT0_SUBDEV; 380 break; 381 case 1: 382 return NI_GPCT1_SUBDEV; 383 break; 384 default: 385 break; 386 } 387 BUG(); 388 return NI_GPCT0_SUBDEV; 389} 390 391enum timebase_nanoseconds { 392 TIMEBASE_1_NS = 50, 393 TIMEBASE_2_NS = 10000 394}; 395 396#define SERIAL_DISABLED 0 397#define SERIAL_600NS 600 398#define SERIAL_1_2US 1200 399#define SERIAL_10US 10000 400 401static const int num_adc_stages_611x = 3; 402 403static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, 404 unsigned ai_mite_status); 405static void handle_b_interrupt(struct comedi_device *dev, unsigned short status, 406 unsigned ao_mite_status); 407static void get_last_sample_611x(struct comedi_device *dev); 408static void get_last_sample_6143(struct comedi_device *dev); 409 410static inline void ni_set_bitfield(struct comedi_device *dev, int reg, 411 unsigned bit_mask, unsigned bit_values) 412{ 413 unsigned long flags; 414 415 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 416 switch (reg) { 417 case Interrupt_A_Enable_Register: 418 devpriv->int_a_enable_reg &= ~bit_mask; 419 devpriv->int_a_enable_reg |= bit_values & bit_mask; 420 devpriv->stc_writew(dev, devpriv->int_a_enable_reg, 421 Interrupt_A_Enable_Register); 422 break; 423 case Interrupt_B_Enable_Register: 424 devpriv->int_b_enable_reg &= ~bit_mask; 425 devpriv->int_b_enable_reg |= bit_values & bit_mask; 426 devpriv->stc_writew(dev, devpriv->int_b_enable_reg, 427 Interrupt_B_Enable_Register); 428 break; 429 case IO_Bidirection_Pin_Register: 430 devpriv->io_bidirection_pin_reg &= ~bit_mask; 431 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; 432 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg, 433 IO_Bidirection_Pin_Register); 434 break; 435 case AI_AO_Select: 436 devpriv->ai_ao_select_reg &= ~bit_mask; 437 devpriv->ai_ao_select_reg |= bit_values & bit_mask; 438 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); 439 break; 440 case G0_G1_Select: 441 devpriv->g0_g1_select_reg &= ~bit_mask; 442 devpriv->g0_g1_select_reg |= bit_values & bit_mask; 443 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); 444 break; 445 default: 446 printk("Warning %s() called with invalid register\n", __func__); 447 printk("reg is %d\n", reg); 448 break; 449 } 450 mmiowb(); 451 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 452} 453 454#ifdef PCIDMA 455static int ni_ai_drain_dma(struct comedi_device *dev); 456 457/* DMA channel setup */ 458 459/* negative channel means no channel */ 460static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel) 461{ 462 unsigned bitfield; 463 464 if (channel >= 0) { 465 bitfield = 466 (ni_stc_dma_channel_select_bitfield(channel) << 467 AI_DMA_Select_Shift) & AI_DMA_Select_Mask; 468 } else { 469 bitfield = 0; 470 } 471 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield); 472} 473 474/* negative channel means no channel */ 475static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel) 476{ 477 unsigned bitfield; 478 479 if (channel >= 0) { 480 bitfield = 481 (ni_stc_dma_channel_select_bitfield(channel) << 482 AO_DMA_Select_Shift) & AO_DMA_Select_Mask; 483 } else { 484 bitfield = 0; 485 } 486 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield); 487} 488 489/* negative mite_channel means no channel */ 490static inline void ni_set_gpct_dma_channel(struct comedi_device *dev, 491 unsigned gpct_index, 492 int mite_channel) 493{ 494 unsigned bitfield; 495 496 if (mite_channel >= 0) { 497 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel); 498 } else { 499 bitfield = 0; 500 } 501 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index), 502 bitfield); 503} 504 505/* negative mite_channel means no channel */ 506static inline void ni_set_cdo_dma_channel(struct comedi_device *dev, 507 int mite_channel) 508{ 509 unsigned long flags; 510 511 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 512 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask; 513 if (mite_channel >= 0) { 514 devpriv->cdio_dma_select_reg |= 515 (ni_stc_dma_channel_select_bitfield(mite_channel) << 516 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask; 517 } 518 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); 519 mmiowb(); 520 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); 521} 522 523static int ni_request_ai_mite_channel(struct comedi_device *dev) 524{ 525 unsigned long flags; 526 527 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 528 BUG_ON(devpriv->ai_mite_chan); 529 devpriv->ai_mite_chan = 530 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); 531 if (devpriv->ai_mite_chan == NULL) { 532 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 533 comedi_error(dev, 534 "failed to reserve mite dma channel for analog input."); 535 return -EBUSY; 536 } 537 devpriv->ai_mite_chan->dir = COMEDI_INPUT; 538 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel); 539 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 540 return 0; 541} 542 543static int ni_request_ao_mite_channel(struct comedi_device *dev) 544{ 545 unsigned long flags; 546 547 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 548 BUG_ON(devpriv->ao_mite_chan); 549 devpriv->ao_mite_chan = 550 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); 551 if (devpriv->ao_mite_chan == NULL) { 552 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 553 comedi_error(dev, 554 "failed to reserve mite dma channel for analog outut."); 555 return -EBUSY; 556 } 557 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT; 558 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel); 559 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 560 return 0; 561} 562 563static int ni_request_gpct_mite_channel(struct comedi_device *dev, 564 unsigned gpct_index, 565 enum comedi_io_direction direction) 566{ 567 unsigned long flags; 568 struct mite_channel *mite_chan; 569 570 BUG_ON(gpct_index >= NUM_GPCT); 571 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 572 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan); 573 mite_chan = 574 mite_request_channel(devpriv->mite, 575 devpriv->gpct_mite_ring[gpct_index]); 576 if (mite_chan == NULL) { 577 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 578 comedi_error(dev, 579 "failed to reserve mite dma channel for counter."); 580 return -EBUSY; 581 } 582 mite_chan->dir = direction; 583 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], 584 mite_chan); 585 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel); 586 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 587 return 0; 588} 589 590#endif /* PCIDMA */ 591 592static int ni_request_cdo_mite_channel(struct comedi_device *dev) 593{ 594#ifdef PCIDMA 595 unsigned long flags; 596 597 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 598 BUG_ON(devpriv->cdo_mite_chan); 599 devpriv->cdo_mite_chan = 600 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); 601 if (devpriv->cdo_mite_chan == NULL) { 602 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 603 comedi_error(dev, 604 "failed to reserve mite dma channel for correlated digital outut."); 605 return -EBUSY; 606 } 607 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT; 608 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel); 609 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 610#endif /* PCIDMA */ 611 return 0; 612} 613 614static void ni_release_ai_mite_channel(struct comedi_device *dev) 615{ 616#ifdef PCIDMA 617 unsigned long flags; 618 619 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 620 if (devpriv->ai_mite_chan) { 621 ni_set_ai_dma_channel(dev, -1); 622 mite_release_channel(devpriv->ai_mite_chan); 623 devpriv->ai_mite_chan = NULL; 624 } 625 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 626#endif /* PCIDMA */ 627} 628 629static void ni_release_ao_mite_channel(struct comedi_device *dev) 630{ 631#ifdef PCIDMA 632 unsigned long flags; 633 634 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 635 if (devpriv->ao_mite_chan) { 636 ni_set_ao_dma_channel(dev, -1); 637 mite_release_channel(devpriv->ao_mite_chan); 638 devpriv->ao_mite_chan = NULL; 639 } 640 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 641#endif /* PCIDMA */ 642} 643 644void ni_release_gpct_mite_channel(struct comedi_device *dev, 645 unsigned gpct_index) 646{ 647#ifdef PCIDMA 648 unsigned long flags; 649 650 BUG_ON(gpct_index >= NUM_GPCT); 651 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 652 if (devpriv->counter_dev->counters[gpct_index].mite_chan) { 653 struct mite_channel *mite_chan = 654 devpriv->counter_dev->counters[gpct_index].mite_chan; 655 656 ni_set_gpct_dma_channel(dev, gpct_index, -1); 657 ni_tio_set_mite_channel(&devpriv-> 658 counter_dev->counters[gpct_index], 659 NULL); 660 mite_release_channel(mite_chan); 661 } 662 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 663#endif /* PCIDMA */ 664} 665 666static void ni_release_cdo_mite_channel(struct comedi_device *dev) 667{ 668#ifdef PCIDMA 669 unsigned long flags; 670 671 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 672 if (devpriv->cdo_mite_chan) { 673 ni_set_cdo_dma_channel(dev, -1); 674 mite_release_channel(devpriv->cdo_mite_chan); 675 devpriv->cdo_mite_chan = NULL; 676 } 677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 678#endif /* PCIDMA */ 679} 680 681/* e-series boards use the second irq signals to generate dma requests for their counters */ 682#ifdef PCIDMA 683static void ni_e_series_enable_second_irq(struct comedi_device *dev, 684 unsigned gpct_index, short enable) 685{ 686 if (boardtype.reg_type & ni_reg_m_series_mask) 687 return; 688 switch (gpct_index) { 689 case 0: 690 if (enable) { 691 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable, 692 Second_IRQ_A_Enable_Register); 693 } else { 694 devpriv->stc_writew(dev, 0, 695 Second_IRQ_A_Enable_Register); 696 } 697 break; 698 case 1: 699 if (enable) { 700 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable, 701 Second_IRQ_B_Enable_Register); 702 } else { 703 devpriv->stc_writew(dev, 0, 704 Second_IRQ_B_Enable_Register); 705 } 706 break; 707 default: 708 BUG(); 709 break; 710 } 711} 712#endif /* PCIDMA */ 713 714static void ni_clear_ai_fifo(struct comedi_device *dev) 715{ 716 if (boardtype.reg_type == ni_reg_6143) { 717 /* Flush the 6143 data FIFO */ 718 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */ 719 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */ 720 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */ 721 } else { 722 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear); 723 if (boardtype.reg_type == ni_reg_625x) { 724 ni_writeb(0, M_Offset_Static_AI_Control(0)); 725 ni_writeb(1, M_Offset_Static_AI_Control(0)); 726 } 727 } 728} 729 730static void win_out2(struct comedi_device *dev, uint32_t data, int reg) 731{ 732 devpriv->stc_writew(dev, data >> 16, reg); 733 devpriv->stc_writew(dev, data & 0xffff, reg + 1); 734} 735 736static uint32_t win_in2(struct comedi_device *dev, int reg) 737{ 738 uint32_t bits; 739 bits = devpriv->stc_readw(dev, reg) << 16; 740 bits |= devpriv->stc_readw(dev, reg + 1); 741 return bits; 742} 743 744#define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr) 745static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, 746 int addr) 747{ 748 unsigned long flags; 749 750 spin_lock_irqsave(&devpriv->window_lock, flags); 751 ni_writew(addr, AO_Window_Address_611x); 752 ni_writew(data, AO_Window_Data_611x); 753 spin_unlock_irqrestore(&devpriv->window_lock, flags); 754} 755 756static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data, 757 int addr) 758{ 759 unsigned long flags; 760 761 spin_lock_irqsave(&devpriv->window_lock, flags); 762 ni_writew(addr, AO_Window_Address_611x); 763 ni_writel(data, AO_Window_Data_611x); 764 spin_unlock_irqrestore(&devpriv->window_lock, flags); 765} 766 767static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) 768{ 769 unsigned long flags; 770 unsigned short data; 771 772 spin_lock_irqsave(&devpriv->window_lock, flags); 773 ni_writew(addr, AO_Window_Address_611x); 774 data = ni_readw(AO_Window_Data_611x); 775 spin_unlock_irqrestore(&devpriv->window_lock, flags); 776 return data; 777} 778 779/* ni_set_bits( ) allows different parts of the ni_mio_common driver to 780* share registers (such as Interrupt_A_Register) without interfering with 781* each other. 782* 783* NOTE: the switch/case statements are optimized out for a constant argument 784* so this is actually quite fast--- If you must wrap another function around this 785* make it inline to avoid a large speed penalty. 786* 787* value should only be 1 or 0. 788*/ 789static inline void ni_set_bits(struct comedi_device *dev, int reg, 790 unsigned bits, unsigned value) 791{ 792 unsigned bit_values; 793 794 if (value) 795 bit_values = bits; 796 else 797 bit_values = 0; 798 ni_set_bitfield(dev, reg, bits, bit_values); 799} 800 801static irqreturn_t ni_E_interrupt(int irq, void *d) 802{ 803 struct comedi_device *dev = d; 804 unsigned short a_status; 805 unsigned short b_status; 806 unsigned int ai_mite_status = 0; 807 unsigned int ao_mite_status = 0; 808 unsigned long flags; 809#ifdef PCIDMA 810 struct mite_struct *mite = devpriv->mite; 811#endif 812 813 if (dev->attached == 0) 814 return IRQ_NONE; 815 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */ 816 817 /* lock to avoid race with comedi_poll */ 818 spin_lock_irqsave(&dev->spinlock, flags); 819 a_status = devpriv->stc_readw(dev, AI_Status_1_Register); 820 b_status = devpriv->stc_readw(dev, AO_Status_1_Register); 821#ifdef PCIDMA 822 if (mite) { 823 unsigned long flags_too; 824 825 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); 826 if (devpriv->ai_mite_chan) { 827 ai_mite_status = mite_get_status(devpriv->ai_mite_chan); 828 if (ai_mite_status & CHSR_LINKC) 829 writel(CHOR_CLRLC, 830 devpriv->mite->mite_io_addr + 831 MITE_CHOR(devpriv-> 832 ai_mite_chan->channel)); 833 } 834 if (devpriv->ao_mite_chan) { 835 ao_mite_status = mite_get_status(devpriv->ao_mite_chan); 836 if (ao_mite_status & CHSR_LINKC) 837 writel(CHOR_CLRLC, 838 mite->mite_io_addr + 839 MITE_CHOR(devpriv-> 840 ao_mite_chan->channel)); 841 } 842 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); 843 } 844#endif 845 ack_a_interrupt(dev, a_status); 846 ack_b_interrupt(dev, b_status); 847 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT)) 848 handle_a_interrupt(dev, a_status, ai_mite_status); 849 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT)) 850 handle_b_interrupt(dev, b_status, ao_mite_status); 851 handle_gpct_interrupt(dev, 0); 852 handle_gpct_interrupt(dev, 1); 853 handle_cdio_interrupt(dev); 854 855 spin_unlock_irqrestore(&dev->spinlock, flags); 856 return IRQ_HANDLED; 857} 858 859#ifdef PCIDMA 860static void ni_sync_ai_dma(struct comedi_device *dev) 861{ 862 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 863 unsigned long flags; 864 865 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 866 if (devpriv->ai_mite_chan) 867 mite_sync_input_dma(devpriv->ai_mite_chan, s->async); 868 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 869} 870 871static void mite_handle_b_linkc(struct mite_struct *mite, 872 struct comedi_device *dev) 873{ 874 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV; 875 unsigned long flags; 876 877 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 878 if (devpriv->ao_mite_chan) { 879 mite_sync_output_dma(devpriv->ao_mite_chan, s->async); 880 } 881 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 882} 883 884static int ni_ao_wait_for_dma_load(struct comedi_device *dev) 885{ 886 static const int timeout = 10000; 887 int i; 888 for (i = 0; i < timeout; i++) { 889 unsigned short b_status; 890 891 b_status = devpriv->stc_readw(dev, AO_Status_1_Register); 892 if (b_status & AO_FIFO_Half_Full_St) 893 break; 894 /* if we poll too often, the pci bus activity seems 895 to slow the dma transfer down */ 896 udelay(10); 897 } 898 if (i == timeout) { 899 comedi_error(dev, "timed out waiting for dma load"); 900 return -EPIPE; 901 } 902 return 0; 903} 904 905#endif /* PCIDMA */ 906static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s) 907{ 908 if (devpriv->aimode == AIMODE_SCAN) { 909#ifdef PCIDMA 910 static const int timeout = 10; 911 int i; 912 913 for (i = 0; i < timeout; i++) { 914 ni_sync_ai_dma(dev); 915 if ((s->async->events & COMEDI_CB_EOS)) 916 break; 917 udelay(1); 918 } 919#else 920 ni_handle_fifo_dregs(dev); 921 s->async->events |= COMEDI_CB_EOS; 922#endif 923 } 924 /* handle special case of single scan using AI_End_On_End_Of_Scan */ 925 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) { 926 shutdown_ai_command(dev); 927 } 928} 929 930static void shutdown_ai_command(struct comedi_device *dev) 931{ 932 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 933 934#ifdef PCIDMA 935 ni_ai_drain_dma(dev); 936#endif 937 ni_handle_fifo_dregs(dev); 938 get_last_sample_611x(dev); 939 get_last_sample_6143(dev); 940 941 s->async->events |= COMEDI_CB_EOA; 942} 943 944static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s) 945{ 946 if (s-> 947 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | 948 COMEDI_CB_EOA)) { 949 switch (s - dev->subdevices) { 950 case NI_AI_SUBDEV: 951 ni_ai_reset(dev, s); 952 break; 953 case NI_AO_SUBDEV: 954 ni_ao_reset(dev, s); 955 break; 956 case NI_GPCT0_SUBDEV: 957 case NI_GPCT1_SUBDEV: 958 ni_gpct_cancel(dev, s); 959 break; 960 case NI_DIO_SUBDEV: 961 ni_cdio_cancel(dev, s); 962 break; 963 default: 964 break; 965 } 966 } 967 comedi_event(dev, s); 968} 969 970static void handle_gpct_interrupt(struct comedi_device *dev, 971 unsigned short counter_index) 972{ 973#ifdef PCIDMA 974 struct comedi_subdevice *s = 975 dev->subdevices + NI_GPCT_SUBDEV(counter_index); 976 977 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], 978 s); 979 if (s->async->events) 980 ni_event(dev, s); 981#endif 982} 983 984static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) 985{ 986 unsigned short ack = 0; 987 988 if (a_status & AI_SC_TC_St) { 989 ack |= AI_SC_TC_Interrupt_Ack; 990 } 991 if (a_status & AI_START1_St) { 992 ack |= AI_START1_Interrupt_Ack; 993 } 994 if (a_status & AI_START_St) { 995 ack |= AI_START_Interrupt_Ack; 996 } 997 if (a_status & AI_STOP_St) { 998 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */ 999 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ; 1000 } 1001 if (ack) 1002 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register); 1003} 1004 1005static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, 1006 unsigned ai_mite_status) 1007{ 1008 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1009 1010 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */ 1011 if (s->type == COMEDI_SUBD_UNUSED) 1012 return; 1013 1014#ifdef DEBUG_INTERRUPT 1015 printk 1016 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n", 1017 status, ai_mite_status); 1018 ni_mio_print_status_a(status); 1019#endif 1020#ifdef PCIDMA 1021 if (ai_mite_status & CHSR_LINKC) { 1022 ni_sync_ai_dma(dev); 1023 } 1024 1025 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | 1026 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | 1027 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { 1028 printk 1029 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n", 1030 ai_mite_status); 1031 /* mite_print_chsr(ai_mite_status); */ 1032 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1033 /* disable_irq(dev->irq); */ 1034 } 1035#endif 1036 1037 /* test for all uncommon interrupt events at the same time */ 1038 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St | 1039 AI_SC_TC_St | AI_START1_St)) { 1040 if (status == 0xffff) { 1041 printk 1042 ("ni_mio_common: a_status=0xffff. Card removed?\n"); 1043 /* we probably aren't even running a command now, 1044 * so it's a good idea to be careful. */ 1045 if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) { 1046 s->async->events |= 1047 COMEDI_CB_ERROR | COMEDI_CB_EOA; 1048 ni_event(dev, s); 1049 } 1050 return; 1051 } 1052 if (status & (AI_Overrun_St | AI_Overflow_St | 1053 AI_SC_TC_Error_St)) { 1054 printk("ni_mio_common: ai error a_status=%04x\n", 1055 status); 1056 ni_mio_print_status_a(status); 1057 1058 shutdown_ai_command(dev); 1059 1060 s->async->events |= COMEDI_CB_ERROR; 1061 if (status & (AI_Overrun_St | AI_Overflow_St)) 1062 s->async->events |= COMEDI_CB_OVERFLOW; 1063 1064 ni_event(dev, s); 1065 1066 return; 1067 } 1068 if (status & AI_SC_TC_St) { 1069#ifdef DEBUG_INTERRUPT 1070 printk("ni_mio_common: SC_TC interrupt\n"); 1071#endif 1072 if (!devpriv->ai_continuous) { 1073 shutdown_ai_command(dev); 1074 } 1075 } 1076 } 1077#ifndef PCIDMA 1078 if (status & AI_FIFO_Half_Full_St) { 1079 int i; 1080 static const int timeout = 10; 1081 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we 1082 *fail to get the fifo less than half full, so loop to be sure.*/ 1083 for (i = 0; i < timeout; ++i) { 1084 ni_handle_fifo_half_full(dev); 1085 if ((devpriv->stc_readw(dev, 1086 AI_Status_1_Register) & 1087 AI_FIFO_Half_Full_St) == 0) 1088 break; 1089 } 1090 } 1091#endif /* !PCIDMA */ 1092 1093 if ((status & AI_STOP_St)) { 1094 ni_handle_eos(dev, s); 1095 } 1096 1097 ni_event(dev, s); 1098 1099#ifdef DEBUG_INTERRUPT 1100 status = devpriv->stc_readw(dev, AI_Status_1_Register); 1101 if (status & Interrupt_A_St) { 1102 printk 1103 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", 1104 status); 1105 } 1106#endif 1107} 1108 1109static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) 1110{ 1111 unsigned short ack = 0; 1112 if (b_status & AO_BC_TC_St) { 1113 ack |= AO_BC_TC_Interrupt_Ack; 1114 } 1115 if (b_status & AO_Overrun_St) { 1116 ack |= AO_Error_Interrupt_Ack; 1117 } 1118 if (b_status & AO_START_St) { 1119 ack |= AO_START_Interrupt_Ack; 1120 } 1121 if (b_status & AO_START1_St) { 1122 ack |= AO_START1_Interrupt_Ack; 1123 } 1124 if (b_status & AO_UC_TC_St) { 1125 ack |= AO_UC_TC_Interrupt_Ack; 1126 } 1127 if (b_status & AO_UI2_TC_St) { 1128 ack |= AO_UI2_TC_Interrupt_Ack; 1129 } 1130 if (b_status & AO_UPDATE_St) { 1131 ack |= AO_UPDATE_Interrupt_Ack; 1132 } 1133 if (ack) 1134 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register); 1135} 1136 1137static void handle_b_interrupt(struct comedi_device *dev, 1138 unsigned short b_status, unsigned ao_mite_status) 1139{ 1140 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV; 1141 /* unsigned short ack=0; */ 1142#ifdef DEBUG_INTERRUPT 1143 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n", 1144 b_status, ao_mite_status); 1145 ni_mio_print_status_b(b_status); 1146#endif 1147 1148#ifdef PCIDMA 1149 /* Currently, mite.c requires us to handle LINKC */ 1150 if (ao_mite_status & CHSR_LINKC) { 1151 mite_handle_b_linkc(devpriv->mite, dev); 1152 } 1153 1154 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | 1155 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | 1156 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { 1157 printk 1158 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n", 1159 ao_mite_status); 1160 /* mite_print_chsr(ao_mite_status); */ 1161 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 1162 } 1163#endif 1164 1165 if (b_status == 0xffff) 1166 return; 1167 if (b_status & AO_Overrun_St) { 1168 printk 1169 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n", 1170 b_status, devpriv->stc_readw(dev, AO_Status_2_Register)); 1171 s->async->events |= COMEDI_CB_OVERFLOW; 1172 } 1173 1174 if (b_status & AO_BC_TC_St) { 1175 MDPRINTK 1176 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n", 1177 b_status, devpriv->stc_readw(dev, AO_Status_2_Register)); 1178 s->async->events |= COMEDI_CB_EOA; 1179 } 1180#ifndef PCIDMA 1181 if (b_status & AO_FIFO_Request_St) { 1182 int ret; 1183 1184 ret = ni_ao_fifo_half_empty(dev, s); 1185 if (!ret) { 1186 printk("ni_mio_common: AO buffer underrun\n"); 1187 ni_set_bits(dev, Interrupt_B_Enable_Register, 1188 AO_FIFO_Interrupt_Enable | 1189 AO_Error_Interrupt_Enable, 0); 1190 s->async->events |= COMEDI_CB_OVERFLOW; 1191 } 1192 } 1193#endif 1194 1195 ni_event(dev, s); 1196} 1197 1198#ifdef DEBUG_STATUS_A 1199static const char *const status_a_strings[] = { 1200 "passthru0", "fifo", "G0_gate", "G0_TC", 1201 "stop", "start", "sc_tc", "start1", 1202 "start2", "sc_tc_error", "overflow", "overrun", 1203 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a" 1204}; 1205 1206static void ni_mio_print_status_a(int status) 1207{ 1208 int i; 1209 1210 printk("A status:"); 1211 for (i = 15; i >= 0; i--) { 1212 if (status & (1 << i)) { 1213 printk(" %s", status_a_strings[i]); 1214 } 1215 } 1216 printk("\n"); 1217} 1218#endif 1219 1220#ifdef DEBUG_STATUS_B 1221static const char *const status_b_strings[] = { 1222 "passthru1", "fifo", "G1_gate", "G1_TC", 1223 "UI2_TC", "UPDATE", "UC_TC", "BC_TC", 1224 "start1", "overrun", "start", "bc_tc_error", 1225 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b" 1226}; 1227 1228static void ni_mio_print_status_b(int status) 1229{ 1230 int i; 1231 1232 printk("B status:"); 1233 for (i = 15; i >= 0; i--) { 1234 if (status & (1 << i)) { 1235 printk(" %s", status_b_strings[i]); 1236 } 1237 } 1238 printk("\n"); 1239} 1240#endif 1241 1242#ifndef PCIDMA 1243 1244static void ni_ao_fifo_load(struct comedi_device *dev, 1245 struct comedi_subdevice *s, int n) 1246{ 1247 struct comedi_async *async = s->async; 1248 struct comedi_cmd *cmd = &async->cmd; 1249 int chan; 1250 int i; 1251 short d; 1252 u32 packed_data; 1253 int range; 1254 int err = 1; 1255 1256 chan = async->cur_chan; 1257 for (i = 0; i < n; i++) { 1258 err &= comedi_buf_get(async, &d); 1259 if (err == 0) 1260 break; 1261 1262 range = CR_RANGE(cmd->chanlist[chan]); 1263 1264 if (boardtype.reg_type & ni_reg_6xxx_mask) { 1265 packed_data = d & 0xffff; 1266 /* 6711 only has 16 bit wide ao fifo */ 1267 if (boardtype.reg_type != ni_reg_6711) { 1268 err &= comedi_buf_get(async, &d); 1269 if (err == 0) 1270 break; 1271 chan++; 1272 i++; 1273 packed_data |= (d << 16) & 0xffff0000; 1274 } 1275 ni_writel(packed_data, DAC_FIFO_Data_611x); 1276 } else { 1277 ni_writew(d, DAC_FIFO_Data); 1278 } 1279 chan++; 1280 chan %= cmd->chanlist_len; 1281 } 1282 async->cur_chan = chan; 1283 if (err == 0) { 1284 async->events |= COMEDI_CB_OVERFLOW; 1285 } 1286} 1287 1288/* 1289 * There's a small problem if the FIFO gets really low and we 1290 * don't have the data to fill it. Basically, if after we fill 1291 * the FIFO with all the data available, the FIFO is _still_ 1292 * less than half full, we never clear the interrupt. If the 1293 * IRQ is in edge mode, we never get another interrupt, because 1294 * this one wasn't cleared. If in level mode, we get flooded 1295 * with interrupts that we can't fulfill, because nothing ever 1296 * gets put into the buffer. 1297 * 1298 * This kind of situation is recoverable, but it is easier to 1299 * just pretend we had a FIFO underrun, since there is a good 1300 * chance it will happen anyway. This is _not_ the case for 1301 * RT code, as RT code might purposely be running close to the 1302 * metal. Needs to be fixed eventually. 1303 */ 1304static int ni_ao_fifo_half_empty(struct comedi_device *dev, 1305 struct comedi_subdevice *s) 1306{ 1307 int n; 1308 1309 n = comedi_buf_read_n_available(s->async); 1310 if (n == 0) { 1311 s->async->events |= COMEDI_CB_OVERFLOW; 1312 return 0; 1313 } 1314 1315 n /= sizeof(short); 1316 if (n > boardtype.ao_fifo_depth / 2) 1317 n = boardtype.ao_fifo_depth / 2; 1318 1319 ni_ao_fifo_load(dev, s, n); 1320 1321 s->async->events |= COMEDI_CB_BLOCK; 1322 1323 return 1; 1324} 1325 1326static int ni_ao_prep_fifo(struct comedi_device *dev, 1327 struct comedi_subdevice *s) 1328{ 1329 int n; 1330 1331 /* reset fifo */ 1332 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear); 1333 if (boardtype.reg_type & ni_reg_6xxx_mask) 1334 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); 1335 1336 /* load some data */ 1337 n = comedi_buf_read_n_available(s->async); 1338 if (n == 0) 1339 return 0; 1340 1341 n /= sizeof(short); 1342 if (n > boardtype.ao_fifo_depth) 1343 n = boardtype.ao_fifo_depth; 1344 1345 ni_ao_fifo_load(dev, s, n); 1346 1347 return n; 1348} 1349 1350static void ni_ai_fifo_read(struct comedi_device *dev, 1351 struct comedi_subdevice *s, int n) 1352{ 1353 struct comedi_async *async = s->async; 1354 int i; 1355 1356 if (boardtype.reg_type == ni_reg_611x) { 1357 short data[2]; 1358 u32 dl; 1359 1360 for (i = 0; i < n / 2; i++) { 1361 dl = ni_readl(ADC_FIFO_Data_611x); 1362 /* This may get the hi/lo data in the wrong order */ 1363 data[0] = (dl >> 16) & 0xffff; 1364 data[1] = dl & 0xffff; 1365 cfc_write_array_to_buffer(s, data, sizeof(data)); 1366 } 1367 /* Check if there's a single sample stuck in the FIFO */ 1368 if (n % 2) { 1369 dl = ni_readl(ADC_FIFO_Data_611x); 1370 data[0] = dl & 0xffff; 1371 cfc_write_to_buffer(s, data[0]); 1372 } 1373 } else if (boardtype.reg_type == ni_reg_6143) { 1374 short data[2]; 1375 u32 dl; 1376 1377 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ 1378 for (i = 0; i < n / 2; i++) { 1379 dl = ni_readl(AIFIFO_Data_6143); 1380 1381 data[0] = (dl >> 16) & 0xffff; 1382 data[1] = dl & 0xffff; 1383 cfc_write_array_to_buffer(s, data, sizeof(data)); 1384 } 1385 if (n % 2) { 1386 /* Assume there is a single sample stuck in the FIFO */ 1387 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1388 dl = ni_readl(AIFIFO_Data_6143); 1389 data[0] = (dl >> 16) & 0xffff; 1390 cfc_write_to_buffer(s, data[0]); 1391 } 1392 } else { 1393 if (n > sizeof(devpriv->ai_fifo_buffer) / 1394 sizeof(devpriv->ai_fifo_buffer[0])) { 1395 comedi_error(dev, "bug! ai_fifo_buffer too small"); 1396 async->events |= COMEDI_CB_ERROR; 1397 return; 1398 } 1399 for (i = 0; i < n; i++) { 1400 devpriv->ai_fifo_buffer[i] = 1401 ni_readw(ADC_FIFO_Data_Register); 1402 } 1403 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 1404 n * 1405 sizeof(devpriv->ai_fifo_buffer[0])); 1406 } 1407} 1408 1409static void ni_handle_fifo_half_full(struct comedi_device *dev) 1410{ 1411 int n; 1412 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1413 1414 n = boardtype.ai_fifo_depth / 2; 1415 1416 ni_ai_fifo_read(dev, s, n); 1417} 1418#endif 1419 1420#ifdef PCIDMA 1421static int ni_ai_drain_dma(struct comedi_device *dev) 1422{ 1423 int i; 1424 static const int timeout = 10000; 1425 unsigned long flags; 1426 int retval = 0; 1427 1428 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1429 if (devpriv->ai_mite_chan) { 1430 for (i = 0; i < timeout; i++) { 1431 if ((devpriv->stc_readw(dev, 1432 AI_Status_1_Register) & 1433 AI_FIFO_Empty_St) 1434 && mite_bytes_in_transit(devpriv->ai_mite_chan) == 1435 0) 1436 break; 1437 udelay(5); 1438 } 1439 if (i == timeout) { 1440 printk("ni_mio_common: wait for dma drain timed out\n"); 1441 printk 1442 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n", 1443 mite_bytes_in_transit(devpriv->ai_mite_chan), 1444 devpriv->stc_readw(dev, AI_Status_1_Register)); 1445 retval = -1; 1446 } 1447 } 1448 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1449 1450 ni_sync_ai_dma(dev); 1451 1452 return retval; 1453} 1454#endif 1455/* 1456 Empties the AI fifo 1457*/ 1458static void ni_handle_fifo_dregs(struct comedi_device *dev) 1459{ 1460 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1461 short data[2]; 1462 u32 dl; 1463 short fifo_empty; 1464 int i; 1465 1466 if (boardtype.reg_type == ni_reg_611x) { 1467 while ((devpriv->stc_readw(dev, 1468 AI_Status_1_Register) & 1469 AI_FIFO_Empty_St) == 0) { 1470 dl = ni_readl(ADC_FIFO_Data_611x); 1471 1472 /* This may get the hi/lo data in the wrong order */ 1473 data[0] = (dl >> 16); 1474 data[1] = (dl & 0xffff); 1475 cfc_write_array_to_buffer(s, data, sizeof(data)); 1476 } 1477 } else if (boardtype.reg_type == ni_reg_6143) { 1478 i = 0; 1479 while (ni_readl(AIFIFO_Status_6143) & 0x04) { 1480 dl = ni_readl(AIFIFO_Data_6143); 1481 1482 /* This may get the hi/lo data in the wrong order */ 1483 data[0] = (dl >> 16); 1484 data[1] = (dl & 0xffff); 1485 cfc_write_array_to_buffer(s, data, sizeof(data)); 1486 i += 2; 1487 } 1488 /* Check if stranded sample is present */ 1489 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1490 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1491 dl = ni_readl(AIFIFO_Data_6143); 1492 data[0] = (dl >> 16) & 0xffff; 1493 cfc_write_to_buffer(s, data[0]); 1494 } 1495 1496 } else { 1497 fifo_empty = 1498 devpriv->stc_readw(dev, 1499 AI_Status_1_Register) & AI_FIFO_Empty_St; 1500 while (fifo_empty == 0) { 1501 for (i = 0; 1502 i < 1503 sizeof(devpriv->ai_fifo_buffer) / 1504 sizeof(devpriv->ai_fifo_buffer[0]); i++) { 1505 fifo_empty = 1506 devpriv->stc_readw(dev, 1507 AI_Status_1_Register) & 1508 AI_FIFO_Empty_St; 1509 if (fifo_empty) 1510 break; 1511 devpriv->ai_fifo_buffer[i] = 1512 ni_readw(ADC_FIFO_Data_Register); 1513 } 1514 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, 1515 i * 1516 sizeof(devpriv-> 1517 ai_fifo_buffer[0])); 1518 } 1519 } 1520} 1521 1522static void get_last_sample_611x(struct comedi_device *dev) 1523{ 1524 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1525 short data; 1526 u32 dl; 1527 1528 if (boardtype.reg_type != ni_reg_611x) 1529 return; 1530 1531 /* Check if there's a single sample stuck in the FIFO */ 1532 if (ni_readb(XXX_Status) & 0x80) { 1533 dl = ni_readl(ADC_FIFO_Data_611x); 1534 data = (dl & 0xffff); 1535 cfc_write_to_buffer(s, data); 1536 } 1537} 1538 1539static void get_last_sample_6143(struct comedi_device *dev) 1540{ 1541 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1542 short data; 1543 u32 dl; 1544 1545 if (boardtype.reg_type != ni_reg_6143) 1546 return; 1547 1548 /* Check if there's a single sample stuck in the FIFO */ 1549 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1550 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1551 dl = ni_readl(AIFIFO_Data_6143); 1552 1553 /* This may get the hi/lo data in the wrong order */ 1554 data = (dl >> 16) & 0xffff; 1555 cfc_write_to_buffer(s, data); 1556 } 1557} 1558 1559static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, 1560 void *data, unsigned int num_bytes, 1561 unsigned int chan_index) 1562{ 1563 struct comedi_async *async = s->async; 1564 unsigned int i; 1565 unsigned int length = num_bytes / bytes_per_sample(s); 1566 short *array = data; 1567 unsigned int *larray = data; 1568 for (i = 0; i < length; i++) { 1569#ifdef PCIDMA 1570 if (s->subdev_flags & SDF_LSAMPL) 1571 larray[i] = le32_to_cpu(larray[i]); 1572 else 1573 array[i] = le16_to_cpu(array[i]); 1574#endif 1575 if (s->subdev_flags & SDF_LSAMPL) 1576 larray[i] += devpriv->ai_offset[chan_index]; 1577 else 1578 array[i] += devpriv->ai_offset[chan_index]; 1579 chan_index++; 1580 chan_index %= async->cmd.chanlist_len; 1581 } 1582} 1583 1584#ifdef PCIDMA 1585 1586static int ni_ai_setup_MITE_dma(struct comedi_device *dev) 1587{ 1588 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV; 1589 int retval; 1590 unsigned long flags; 1591 1592 retval = ni_request_ai_mite_channel(dev); 1593 if (retval) 1594 return retval; 1595/* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */ 1596 1597 /* write alloc the entire buffer */ 1598 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz); 1599 1600 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1601 if (devpriv->ai_mite_chan == NULL) { 1602 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1603 return -EIO; 1604 } 1605 1606 switch (boardtype.reg_type) { 1607 case ni_reg_611x: 1608 case ni_reg_6143: 1609 mite_prep_dma(devpriv->ai_mite_chan, 32, 16); 1610 break; 1611 case ni_reg_628x: 1612 mite_prep_dma(devpriv->ai_mite_chan, 32, 32); 1613 break; 1614 default: 1615 mite_prep_dma(devpriv->ai_mite_chan, 16, 16); 1616 break; 1617 }; 1618 /*start the MITE */ 1619 mite_dma_arm(devpriv->ai_mite_chan); 1620 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1621 1622 return 0; 1623} 1624 1625static int ni_ao_setup_MITE_dma(struct comedi_device *dev) 1626{ 1627 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV; 1628 int retval; 1629 unsigned long flags; 1630 1631 retval = ni_request_ao_mite_channel(dev); 1632 if (retval) 1633 return retval; 1634 1635 /* read alloc the entire buffer */ 1636 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz); 1637 1638 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 1639 if (devpriv->ao_mite_chan) { 1640 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) { 1641 mite_prep_dma(devpriv->ao_mite_chan, 32, 32); 1642 } else { 1643 /* doing 32 instead of 16 bit wide transfers from memory 1644 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */ 1645 mite_prep_dma(devpriv->ao_mite_chan, 16, 32); 1646 } 1647 mite_dma_arm(devpriv->ao_mite_chan); 1648 } else 1649 retval = -EIO; 1650 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 1651 1652 return retval; 1653} 1654 1655#endif /* PCIDMA */ 1656 1657/* 1658 used for both cancel ioctl and board initialization 1659 1660 this is pretty harsh for a cancel, but it works... 1661 */ 1662 1663static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) 1664{ 1665 ni_release_ai_mite_channel(dev); 1666 /* ai configuration */ 1667 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, 1668 Joint_Reset_Register); 1669 1670 ni_set_bits(dev, Interrupt_A_Enable_Register, 1671 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable | 1672 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable | 1673 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable | 1674 AI_FIFO_Interrupt_Enable, 0); 1675 1676 ni_clear_ai_fifo(dev); 1677 1678 if (boardtype.reg_type != ni_reg_6143) 1679 ni_writeb(0, Misc_Command); 1680 1681 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */ 1682 devpriv->stc_writew(dev, 1683 AI_Start_Stop | AI_Mode_1_Reserved 1684 /*| AI_Trigger_Once */ , 1685 AI_Mode_1_Register); 1686 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register); 1687 /* generate FIFO interrupts on non-empty */ 1688 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register); 1689 if (boardtype.reg_type == ni_reg_611x) { 1690 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | 1691 AI_SOC_Polarity | 1692 AI_LOCALMUX_CLK_Pulse_Width, 1693 AI_Personal_Register); 1694 devpriv->stc_writew(dev, 1695 AI_SCAN_IN_PROG_Output_Select(3) | 1696 AI_EXTMUX_CLK_Output_Select(0) | 1697 AI_LOCALMUX_CLK_Output_Select(2) | 1698 AI_SC_TC_Output_Select(3) | 1699 AI_CONVERT_Output_Select 1700 (AI_CONVERT_Output_Enable_High), 1701 AI_Output_Control_Register); 1702 } else if (boardtype.reg_type == ni_reg_6143) { 1703 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | 1704 AI_SOC_Polarity | 1705 AI_LOCALMUX_CLK_Pulse_Width, 1706 AI_Personal_Register); 1707 devpriv->stc_writew(dev, 1708 AI_SCAN_IN_PROG_Output_Select(3) | 1709 AI_EXTMUX_CLK_Output_Select(0) | 1710 AI_LOCALMUX_CLK_Output_Select(2) | 1711 AI_SC_TC_Output_Select(3) | 1712 AI_CONVERT_Output_Select 1713 (AI_CONVERT_Output_Enable_Low), 1714 AI_Output_Control_Register); 1715 } else { 1716 unsigned ai_output_control_bits; 1717 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | 1718 AI_SOC_Polarity | 1719 AI_CONVERT_Pulse_Width | 1720 AI_LOCALMUX_CLK_Pulse_Width, 1721 AI_Personal_Register); 1722 ai_output_control_bits = 1723 AI_SCAN_IN_PROG_Output_Select(3) | 1724 AI_EXTMUX_CLK_Output_Select(0) | 1725 AI_LOCALMUX_CLK_Output_Select(2) | 1726 AI_SC_TC_Output_Select(3); 1727 if (boardtype.reg_type == ni_reg_622x) 1728 ai_output_control_bits |= 1729 AI_CONVERT_Output_Select 1730 (AI_CONVERT_Output_Enable_High); 1731 else 1732 ai_output_control_bits |= 1733 AI_CONVERT_Output_Select 1734 (AI_CONVERT_Output_Enable_Low); 1735 devpriv->stc_writew(dev, ai_output_control_bits, 1736 AI_Output_Control_Register); 1737 } 1738 /* the following registers should not be changed, because there 1739 * are no backup registers in devpriv. If you want to change 1740 * any of these, add a backup register and other appropriate code: 1741 * AI_Mode_1_Register 1742 * AI_Mode_3_Register 1743 * AI_Personal_Register 1744 * AI_Output_Control_Register 1745 */ 1746 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */ 1747 1748 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); 1749 1750 return 0; 1751} 1752 1753static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s) 1754{ 1755 unsigned long flags = 0; 1756 int count; 1757 1758 /* lock to avoid race with interrupt handler */ 1759 if (in_interrupt() == 0) 1760 spin_lock_irqsave(&dev->spinlock, flags); 1761#ifndef PCIDMA 1762 ni_handle_fifo_dregs(dev); 1763#else 1764 ni_sync_ai_dma(dev); 1765#endif 1766 count = s->async->buf_write_count - s->async->buf_read_count; 1767 if (in_interrupt() == 0) 1768 spin_unlock_irqrestore(&dev->spinlock, flags); 1769 1770 return count; 1771} 1772 1773static int ni_ai_insn_read(struct comedi_device *dev, 1774 struct comedi_subdevice *s, struct comedi_insn *insn, 1775 unsigned int *data) 1776{ 1777 int i, n; 1778 const unsigned int mask = (1 << boardtype.adbits) - 1; 1779 unsigned signbits; 1780 unsigned short d; 1781 unsigned long dl; 1782 1783 ni_load_channelgain_list(dev, 1, &insn->chanspec); 1784 1785 ni_clear_ai_fifo(dev); 1786 1787 signbits = devpriv->ai_offset[0]; 1788 if (boardtype.reg_type == ni_reg_611x) { 1789 for (n = 0; n < num_adc_stages_611x; n++) { 1790 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1791 AI_Command_1_Register); 1792 udelay(1); 1793 } 1794 for (n = 0; n < insn->n; n++) { 1795 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1796 AI_Command_1_Register); 1797 /* The 611x has screwy 32-bit FIFOs. */ 1798 d = 0; 1799 for (i = 0; i < NI_TIMEOUT; i++) { 1800 if (ni_readb(XXX_Status) & 0x80) { 1801 d = (ni_readl(ADC_FIFO_Data_611x) >> 16) 1802 & 0xffff; 1803 break; 1804 } 1805 if (!(devpriv->stc_readw(dev, 1806 AI_Status_1_Register) & 1807 AI_FIFO_Empty_St)) { 1808 d = ni_readl(ADC_FIFO_Data_611x) & 1809 0xffff; 1810 break; 1811 } 1812 } 1813 if (i == NI_TIMEOUT) { 1814 printk 1815 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n"); 1816 return -ETIME; 1817 } 1818 d += signbits; 1819 data[n] = d; 1820 } 1821 } else if (boardtype.reg_type == ni_reg_6143) { 1822 for (n = 0; n < insn->n; n++) { 1823 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1824 AI_Command_1_Register); 1825 1826 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ 1827 dl = 0; 1828 for (i = 0; i < NI_TIMEOUT; i++) { 1829 if (ni_readl(AIFIFO_Status_6143) & 0x01) { 1830 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ 1831 dl = ni_readl(AIFIFO_Data_6143); 1832 break; 1833 } 1834 } 1835 if (i == NI_TIMEOUT) { 1836 printk 1837 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n"); 1838 return -ETIME; 1839 } 1840 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF; 1841 } 1842 } else { 1843 for (n = 0; n < insn->n; n++) { 1844 devpriv->stc_writew(dev, AI_CONVERT_Pulse, 1845 AI_Command_1_Register); 1846 for (i = 0; i < NI_TIMEOUT; i++) { 1847 if (!(devpriv->stc_readw(dev, 1848 AI_Status_1_Register) & 1849 AI_FIFO_Empty_St)) 1850 break; 1851 } 1852 if (i == NI_TIMEOUT) { 1853 printk 1854 ("ni_mio_common: timeout in ni_ai_insn_read\n"); 1855 return -ETIME; 1856 } 1857 if (boardtype.reg_type & ni_reg_m_series_mask) { 1858 data[n] = 1859 ni_readl(M_Offset_AI_FIFO_Data) & mask; 1860 } else { 1861 d = ni_readw(ADC_FIFO_Data_Register); 1862 d += signbits; /* subtle: needs to be short addition */ 1863 data[n] = d; 1864 } 1865 } 1866 } 1867 return insn->n; 1868} 1869 1870void ni_prime_channelgain_list(struct comedi_device *dev) 1871{ 1872 int i; 1873 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register); 1874 for (i = 0; i < NI_TIMEOUT; ++i) { 1875 if (!(devpriv->stc_readw(dev, 1876 AI_Status_1_Register) & 1877 AI_FIFO_Empty_St)) { 1878 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear); 1879 return; 1880 } 1881 udelay(1); 1882 } 1883 printk("ni_mio_common: timeout loading channel/gain list\n"); 1884} 1885 1886static void ni_m_series_load_channelgain_list(struct comedi_device *dev, 1887 unsigned int n_chan, 1888 unsigned int *list) 1889{ 1890 unsigned int chan, range, aref; 1891 unsigned int i; 1892 unsigned offset; 1893 unsigned int dither; 1894 unsigned range_code; 1895 1896 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear); 1897 1898/* offset = 1 << (boardtype.adbits - 1); */ 1899 if ((list[0] & CR_ALT_SOURCE)) { 1900 unsigned bypass_bits; 1901 chan = CR_CHAN(list[0]); 1902 range = CR_RANGE(list[0]); 1903 range_code = ni_gainlkup[boardtype.gainlkup][range]; 1904 dither = ((list[0] & CR_ALT_FILTER) != 0); 1905 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit; 1906 bypass_bits |= chan; 1907 bypass_bits |= 1908 (devpriv->ai_calib_source) & 1909 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask | 1910 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | 1911 MSeries_AI_Bypass_Mode_Mux_Mask | 1912 MSeries_AO_Bypass_AO_Cal_Sel_Mask); 1913 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code); 1914 if (dither) 1915 bypass_bits |= MSeries_AI_Bypass_Dither_Bit; 1916 /* don't use 2's complement encoding */ 1917 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit; 1918 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass); 1919 } else { 1920 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass); 1921 } 1922 offset = 0; 1923 for (i = 0; i < n_chan; i++) { 1924 unsigned config_bits = 0; 1925 chan = CR_CHAN(list[i]); 1926 aref = CR_AREF(list[i]); 1927 range = CR_RANGE(list[i]); 1928 dither = ((list[i] & CR_ALT_FILTER) != 0); 1929 1930 range_code = ni_gainlkup[boardtype.gainlkup][range]; 1931 devpriv->ai_offset[i] = offset; 1932 switch (aref) { 1933 case AREF_DIFF: 1934 config_bits |= 1935 MSeries_AI_Config_Channel_Type_Differential_Bits; 1936 break; 1937 case AREF_COMMON: 1938 config_bits |= 1939 MSeries_AI_Config_Channel_Type_Common_Ref_Bits; 1940 break; 1941 case AREF_GROUND: 1942 config_bits |= 1943 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits; 1944 break; 1945 case AREF_OTHER: 1946 break; 1947 } 1948 config_bits |= MSeries_AI_Config_Channel_Bits(chan); 1949 config_bits |= 1950 MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan); 1951 config_bits |= MSeries_AI_Config_Gain_Bits(range_code); 1952 if (i == n_chan - 1) 1953 config_bits |= MSeries_AI_Config_Last_Channel_Bit; 1954 if (dither) 1955 config_bits |= MSeries_AI_Config_Dither_Bit; 1956 /* don't use 2's complement encoding */ 1957 config_bits |= MSeries_AI_Config_Polarity_Bit; 1958 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data); 1959 } 1960 ni_prime_channelgain_list(dev); 1961} 1962 1963/* 1964 * Notes on the 6110 and 6111: 1965 * These boards a slightly different than the rest of the series, since 1966 * they have multiple A/D converters. 1967 * From the driver side, the configuration memory is a 1968 * little different. 1969 * Configuration Memory Low: 1970 * bits 15-9: same 1971 * bit 8: unipolar/bipolar (should be 0 for bipolar) 1972 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards 1973 * 1001 gain=0.1 (+/- 50) 1974 * 1010 0.2 1975 * 1011 0.1 1976 * 0001 1 1977 * 0010 2 1978 * 0011 5 1979 * 0100 10 1980 * 0101 20 1981 * 0110 50 1982 * Configuration Memory High: 1983 * bits 12-14: Channel Type 1984 * 001 for differential 1985 * 000 for calibration 1986 * bit 11: coupling (this is not currently handled) 1987 * 1 AC coupling 1988 * 0 DC coupling 1989 * bits 0-2: channel 1990 * valid channels are 0-3 1991 */ 1992static void ni_load_channelgain_list(struct comedi_device *dev, 1993 unsigned int n_chan, unsigned int *list) 1994{ 1995 unsigned int chan, range, aref; 1996 unsigned int i; 1997 unsigned int hi, lo; 1998 unsigned offset; 1999 unsigned int dither; 2000 2001 if (boardtype.reg_type & ni_reg_m_series_mask) { 2002 ni_m_series_load_channelgain_list(dev, n_chan, list); 2003 return; 2004 } 2005 if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x) 2006 && (boardtype.reg_type != ni_reg_6143)) { 2007 if (devpriv->changain_state 2008 && devpriv->changain_spec == list[0]) { 2009 /* ready to go. */ 2010 return; 2011 } 2012 devpriv->changain_state = 1; 2013 devpriv->changain_spec = list[0]; 2014 } else { 2015 devpriv->changain_state = 0; 2016 } 2017 2018 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear); 2019 2020 /* Set up Calibration mode if required */ 2021 if (boardtype.reg_type == ni_reg_6143) { 2022 if ((list[0] & CR_ALT_SOURCE) 2023 && !devpriv->ai_calib_source_enabled) { 2024 /* Strobe Relay enable bit */ 2025 ni_writew(devpriv->ai_calib_source | 2026 Calibration_Channel_6143_RelayOn, 2027 Calibration_Channel_6143); 2028 ni_writew(devpriv->ai_calib_source, 2029 Calibration_Channel_6143); 2030 devpriv->ai_calib_source_enabled = 1; 2031 msleep_interruptible(100); /* Allow relays to change */ 2032 } else if (!(list[0] & CR_ALT_SOURCE) 2033 && devpriv->ai_calib_source_enabled) { 2034 /* Strobe Relay disable bit */ 2035 ni_writew(devpriv->ai_calib_source | 2036 Calibration_Channel_6143_RelayOff, 2037 Calibration_Channel_6143); 2038 ni_writew(devpriv->ai_calib_source, 2039 Calibration_Channel_6143); 2040 devpriv->ai_calib_source_enabled = 0; 2041 msleep_interruptible(100); /* Allow relays to change */ 2042 } 2043 } 2044 2045 offset = 1 << (boardtype.adbits - 1); 2046 for (i = 0; i < n_chan; i++) { 2047 if ((boardtype.reg_type != ni_reg_6143) 2048 && (list[i] & CR_ALT_SOURCE)) { 2049 chan = devpriv->ai_calib_source; 2050 } else { 2051 chan = CR_CHAN(list[i]); 2052 } 2053 aref = CR_AREF(list[i]); 2054 range = CR_RANGE(list[i]); 2055 dither = ((list[i] & CR_ALT_FILTER) != 0); 2056 2057 /* fix the external/internal range differences */ 2058 range = ni_gainlkup[boardtype.gainlkup][range]; 2059 if (boardtype.reg_type == ni_reg_611x) 2060 devpriv->ai_offset[i] = offset; 2061 else 2062 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; 2063 2064 hi = 0; 2065 if ((list[i] & CR_ALT_SOURCE)) { 2066 if (boardtype.reg_type == ni_reg_611x) 2067 ni_writew(CR_CHAN(list[i]) & 0x0003, 2068 Calibration_Channel_Select_611x); 2069 } else { 2070 if (boardtype.reg_type == ni_reg_611x) 2071 aref = AREF_DIFF; 2072 else if (boardtype.reg_type == ni_reg_6143) 2073 aref = AREF_OTHER; 2074 switch (aref) { 2075 case AREF_DIFF: 2076 hi |= AI_DIFFERENTIAL; 2077 break; 2078 case AREF_COMMON: 2079 hi |= AI_COMMON; 2080 break; 2081 case AREF_GROUND: 2082 hi |= AI_GROUND; 2083 break; 2084 case AREF_OTHER: 2085 break; 2086 } 2087 } 2088 hi |= AI_CONFIG_CHANNEL(chan); 2089 2090 ni_writew(hi, Configuration_Memory_High); 2091 2092 if (boardtype.reg_type != ni_reg_6143) { 2093 lo = range; 2094 if (i == n_chan - 1) 2095 lo |= AI_LAST_CHANNEL; 2096 if (dither) 2097 lo |= AI_DITHER; 2098 2099 ni_writew(lo, Configuration_Memory_Low); 2100 } 2101 } 2102 2103 /* prime the channel/gain list */ 2104 if ((boardtype.reg_type != ni_reg_611x) 2105 && (boardtype.reg_type != ni_reg_6143)) { 2106 ni_prime_channelgain_list(dev); 2107 } 2108} 2109 2110static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, 2111 int round_mode) 2112{ 2113 int divider; 2114 switch (round_mode) { 2115 case TRIG_ROUND_NEAREST: 2116 default: 2117 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns; 2118 break; 2119 case TRIG_ROUND_DOWN: 2120 divider = (nanosec) / devpriv->clock_ns; 2121 break; 2122 case TRIG_ROUND_UP: 2123 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns; 2124 break; 2125 } 2126 return divider - 1; 2127} 2128 2129static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer) 2130{ 2131 return devpriv->clock_ns * (timer + 1); 2132} 2133 2134static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev, 2135 unsigned num_channels) 2136{ 2137 switch (boardtype.reg_type) { 2138 case ni_reg_611x: 2139 case ni_reg_6143: 2140 /* simultaneously-sampled inputs */ 2141 return boardtype.ai_speed; 2142 break; 2143 default: 2144 /* multiplexed inputs */ 2145 break; 2146 }; 2147 return boardtype.ai_speed * num_channels; 2148} 2149 2150static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 2151 struct comedi_cmd *cmd) 2152{ 2153 int err = 0; 2154 int tmp; 2155 int sources; 2156 2157 /* step 1: make sure trigger sources are trivially valid */ 2158 2159 if ((cmd->flags & CMDF_WRITE)) { 2160 cmd->flags &= ~CMDF_WRITE; 2161 } 2162 2163 tmp = cmd->start_src; 2164 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT; 2165 if (!cmd->start_src || tmp != cmd->start_src) 2166 err++; 2167 2168 tmp = cmd->scan_begin_src; 2169 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 2170 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 2171 err++; 2172 2173 tmp = cmd->convert_src; 2174 sources = TRIG_TIMER | TRIG_EXT; 2175 if ((boardtype.reg_type == ni_reg_611x) 2176 || (boardtype.reg_type == ni_reg_6143)) 2177 sources |= TRIG_NOW; 2178 cmd->convert_src &= sources; 2179 if (!cmd->convert_src || tmp != cmd->convert_src) 2180 err++; 2181 2182 tmp = cmd->scan_end_src; 2183 cmd->scan_end_src &= TRIG_COUNT; 2184 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 2185 err++; 2186 2187 tmp = cmd->stop_src; 2188 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 2189 if (!cmd->stop_src || tmp != cmd->stop_src) 2190 err++; 2191 2192 if (err) 2193 return 1; 2194 2195 /* step 2: make sure trigger sources are unique and mutually compatible */ 2196 2197 /* note that mutual compatibility is not an issue here */ 2198 if (cmd->start_src != TRIG_NOW && 2199 cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT) 2200 err++; 2201 if (cmd->scan_begin_src != TRIG_TIMER && 2202 cmd->scan_begin_src != TRIG_EXT && 2203 cmd->scan_begin_src != TRIG_OTHER) 2204 err++; 2205 if (cmd->convert_src != TRIG_TIMER && 2206 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW) 2207 err++; 2208 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 2209 err++; 2210 2211 if (err) 2212 return 2; 2213 2214 /* step 3: make sure arguments are trivially compatible */ 2215 2216 if (cmd->start_src == TRIG_EXT) { 2217 /* external trigger */ 2218 unsigned int tmp = CR_CHAN(cmd->start_arg); 2219 2220 if (tmp > 16) 2221 tmp = 16; 2222 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); 2223 if (cmd->start_arg != tmp) { 2224 cmd->start_arg = tmp; 2225 err++; 2226 } 2227 } else { 2228 if (cmd->start_arg != 0) { 2229 /* true for both TRIG_NOW and TRIG_INT */ 2230 cmd->start_arg = 0; 2231 err++; 2232 } 2233 } 2234 if (cmd->scan_begin_src == TRIG_TIMER) { 2235 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev, 2236 cmd-> 2237 chanlist_len)) 2238 { 2239 cmd->scan_begin_arg = 2240 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len); 2241 err++; 2242 } 2243 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { 2244 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff; 2245 err++; 2246 } 2247 } else if (cmd->scan_begin_src == TRIG_EXT) { 2248 /* external trigger */ 2249 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg); 2250 2251 if (tmp > 16) 2252 tmp = 16; 2253 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE)); 2254 if (cmd->scan_begin_arg != tmp) { 2255 cmd->scan_begin_arg = tmp; 2256 err++; 2257 } 2258 } else { /* TRIG_OTHER */ 2259 if (cmd->scan_begin_arg) { 2260 cmd->scan_begin_arg = 0; 2261 err++; 2262 } 2263 } 2264 if (cmd->convert_src == TRIG_TIMER) { 2265 if ((boardtype.reg_type == ni_reg_611x) 2266 || (boardtype.reg_type == ni_reg_6143)) { 2267 if (cmd->convert_arg != 0) { 2268 cmd->convert_arg = 0; 2269 err++; 2270 } 2271 } else { 2272 if (cmd->convert_arg < boardtype.ai_speed) { 2273 cmd->convert_arg = boardtype.ai_speed; 2274 err++; 2275 } 2276 if (cmd->convert_arg > devpriv->clock_ns * 0xffff) { 2277 cmd->convert_arg = devpriv->clock_ns * 0xffff; 2278 err++; 2279 } 2280 } 2281 } else if (cmd->convert_src == TRIG_EXT) { 2282 /* external trigger */ 2283 unsigned int tmp = CR_CHAN(cmd->convert_arg); 2284 2285 if (tmp > 16) 2286 tmp = 16; 2287 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT)); 2288 if (cmd->convert_arg != tmp) { 2289 cmd->convert_arg = tmp; 2290 err++; 2291 } 2292 } else if (cmd->convert_src == TRIG_NOW) { 2293 if (cmd->convert_arg != 0) { 2294 cmd->convert_arg = 0; 2295 err++; 2296 } 2297 } 2298 2299 if (cmd->scan_end_arg != cmd->chanlist_len) { 2300 cmd->scan_end_arg = cmd->chanlist_len; 2301 err++; 2302 } 2303 if (cmd->stop_src == TRIG_COUNT) { 2304 unsigned int max_count = 0x01000000; 2305 2306 if (boardtype.reg_type == ni_reg_611x) 2307 max_count -= num_adc_stages_611x; 2308 if (cmd->stop_arg > max_count) { 2309 cmd->stop_arg = max_count; 2310 err++; 2311 } 2312 if (cmd->stop_arg < 1) { 2313 cmd->stop_arg = 1; 2314 err++; 2315 } 2316 } else { 2317 /* TRIG_NONE */ 2318 if (cmd->stop_arg != 0) { 2319 cmd->stop_arg = 0; 2320 err++; 2321 } 2322 } 2323 2324 if (err) 2325 return 3; 2326 2327 /* step 4: fix up any arguments */ 2328 2329 if (cmd->scan_begin_src == TRIG_TIMER) { 2330 tmp = cmd->scan_begin_arg; 2331 cmd->scan_begin_arg = 2332 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 2333 cmd->scan_begin_arg, 2334 cmd-> 2335 flags & 2336 TRIG_ROUND_MASK)); 2337 if (tmp != cmd->scan_begin_arg) 2338 err++; 2339 } 2340 if (cmd->convert_src == TRIG_TIMER) { 2341 if ((boardtype.reg_type != ni_reg_611x) 2342 && (boardtype.reg_type != ni_reg_6143)) { 2343 tmp = cmd->convert_arg; 2344 cmd->convert_arg = 2345 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 2346 cmd->convert_arg, 2347 cmd-> 2348 flags & 2349 TRIG_ROUND_MASK)); 2350 if (tmp != cmd->convert_arg) 2351 err++; 2352 if (cmd->scan_begin_src == TRIG_TIMER && 2353 cmd->scan_begin_arg < 2354 cmd->convert_arg * cmd->scan_end_arg) { 2355 cmd->scan_begin_arg = 2356 cmd->convert_arg * cmd->scan_end_arg; 2357 err++; 2358 } 2359 } 2360 } 2361 2362 if (err) 2363 return 4; 2364 2365 return 0; 2366} 2367 2368static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 2369{ 2370 const struct comedi_cmd *cmd = &s->async->cmd; 2371 int timer; 2372 int mode1 = 0; /* mode1 is needed for both stop and convert */ 2373 int mode2 = 0; 2374 int start_stop_select = 0; 2375 unsigned int stop_count; 2376 int interrupt_a_enable = 0; 2377 2378 MDPRINTK("ni_ai_cmd\n"); 2379 if (dev->irq == 0) { 2380 comedi_error(dev, "cannot run command without an irq"); 2381 return -EIO; 2382 } 2383 ni_clear_ai_fifo(dev); 2384 2385 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist); 2386 2387 /* start configuration */ 2388 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register); 2389 2390 /* disable analog triggering for now, since it 2391 * interferes with the use of pfi0 */ 2392 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable; 2393 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, 2394 Analog_Trigger_Etc_Register); 2395 2396 switch (cmd->start_src) { 2397 case TRIG_INT: 2398 case TRIG_NOW: 2399 devpriv->stc_writew(dev, AI_START2_Select(0) | 2400 AI_START1_Sync | AI_START1_Edge | 2401 AI_START1_Select(0), 2402 AI_Trigger_Select_Register); 2403 break; 2404 case TRIG_EXT: 2405 { 2406 int chan = CR_CHAN(cmd->start_arg); 2407 unsigned int bits = AI_START2_Select(0) | 2408 AI_START1_Sync | AI_START1_Select(chan + 1); 2409 2410 if (cmd->start_arg & CR_INVERT) 2411 bits |= AI_START1_Polarity; 2412 if (cmd->start_arg & CR_EDGE) 2413 bits |= AI_START1_Edge; 2414 devpriv->stc_writew(dev, bits, 2415 AI_Trigger_Select_Register); 2416 break; 2417 } 2418 } 2419 2420 mode2 &= ~AI_Pre_Trigger; 2421 mode2 &= ~AI_SC_Initial_Load_Source; 2422 mode2 &= ~AI_SC_Reload_Mode; 2423 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2424 2425 if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) 2426 || (boardtype.reg_type == ni_reg_6143)) { 2427 start_stop_select |= AI_STOP_Polarity; 2428 start_stop_select |= AI_STOP_Select(31); /* logic low */ 2429 start_stop_select |= AI_STOP_Sync; 2430 } else { 2431 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */ 2432 } 2433 devpriv->stc_writew(dev, start_stop_select, 2434 AI_START_STOP_Select_Register); 2435 2436 devpriv->ai_cmd2 = 0; 2437 switch (cmd->stop_src) { 2438 case TRIG_COUNT: 2439 stop_count = cmd->stop_arg - 1; 2440 2441 if (boardtype.reg_type == ni_reg_611x) { 2442 /* have to take 3 stage adc pipeline into account */ 2443 stop_count += num_adc_stages_611x; 2444 } 2445 /* stage number of scans */ 2446 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers); 2447 2448 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once; 2449 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); 2450 /* load SC (Scan Count) */ 2451 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register); 2452 2453 devpriv->ai_continuous = 0; 2454 if (stop_count == 0) { 2455 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan; 2456 interrupt_a_enable |= AI_STOP_Interrupt_Enable; 2457 /* this is required to get the last sample for chanlist_len > 1, not sure why */ 2458 if (cmd->chanlist_len > 1) 2459 start_stop_select |= 2460 AI_STOP_Polarity | AI_STOP_Edge; 2461 } 2462 break; 2463 case TRIG_NONE: 2464 /* stage number of scans */ 2465 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers); 2466 2467 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous; 2468 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); 2469 2470 /* load SC (Scan Count) */ 2471 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register); 2472 2473 devpriv->ai_continuous = 1; 2474 2475 break; 2476 } 2477 2478 switch (cmd->scan_begin_src) { 2479 case TRIG_TIMER: 2480 /* 2481 stop bits for non 611x boards 2482 AI_SI_Special_Trigger_Delay=0 2483 AI_Pre_Trigger=0 2484 AI_START_STOP_Select_Register: 2485 AI_START_Polarity=0 (?) rising edge 2486 AI_START_Edge=1 edge triggered 2487 AI_START_Sync=1 (?) 2488 AI_START_Select=0 SI_TC 2489 AI_STOP_Polarity=0 rising edge 2490 AI_STOP_Edge=0 level 2491 AI_STOP_Sync=1 2492 AI_STOP_Select=19 external pin (configuration mem) 2493 */ 2494 start_stop_select |= AI_START_Edge | AI_START_Sync; 2495 devpriv->stc_writew(dev, start_stop_select, 2496 AI_START_STOP_Select_Register); 2497 2498 mode2 |= AI_SI_Reload_Mode(0); 2499 /* AI_SI_Initial_Load_Source=A */ 2500 mode2 &= ~AI_SI_Initial_Load_Source; 2501 /* mode2 |= AI_SC_Reload_Mode; */ 2502 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2503 2504 /* load SI */ 2505 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, 2506 TRIG_ROUND_NEAREST); 2507 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers); 2508 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register); 2509 break; 2510 case TRIG_EXT: 2511 if (cmd->scan_begin_arg & CR_EDGE) 2512 start_stop_select |= AI_START_Edge; 2513 /* AI_START_Polarity==1 is falling edge */ 2514 if (cmd->scan_begin_arg & CR_INVERT) 2515 start_stop_select |= AI_START_Polarity; 2516 if (cmd->scan_begin_src != cmd->convert_src || 2517 (cmd->scan_begin_arg & ~CR_EDGE) != 2518 (cmd->convert_arg & ~CR_EDGE)) 2519 start_stop_select |= AI_START_Sync; 2520 start_stop_select |= 2521 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg)); 2522 devpriv->stc_writew(dev, start_stop_select, 2523 AI_START_STOP_Select_Register); 2524 break; 2525 } 2526 2527 switch (cmd->convert_src) { 2528 case TRIG_TIMER: 2529 case TRIG_NOW: 2530 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW) 2531 timer = 1; 2532 else 2533 timer = ni_ns_to_timer(dev, cmd->convert_arg, 2534 TRIG_ROUND_NEAREST); 2535 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */ 2536 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register); 2537 2538 /* AI_SI2_Reload_Mode = alternate */ 2539 /* AI_SI2_Initial_Load_Source = A */ 2540 mode2 &= ~AI_SI2_Initial_Load_Source; 2541 mode2 |= AI_SI2_Reload_Mode; 2542 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2543 2544 /* AI_SI2_Load */ 2545 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register); 2546 2547 mode2 |= AI_SI2_Reload_Mode; /* alternate */ 2548 mode2 |= AI_SI2_Initial_Load_Source; /* B */ 2549 2550 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2551 break; 2552 case TRIG_EXT: 2553 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg); 2554 if ((cmd->convert_arg & CR_INVERT) == 0) 2555 mode1 |= AI_CONVERT_Source_Polarity; 2556 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); 2557 2558 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable; 2559 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); 2560 2561 break; 2562 } 2563 2564 if (dev->irq) { 2565 2566 /* interrupt on FIFO, errors, SC_TC */ 2567 interrupt_a_enable |= AI_Error_Interrupt_Enable | 2568 AI_SC_TC_Interrupt_Enable; 2569 2570#ifndef PCIDMA 2571 interrupt_a_enable |= AI_FIFO_Interrupt_Enable; 2572#endif 2573 2574 if (cmd->flags & TRIG_WAKE_EOS 2575 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) { 2576 /* wake on end-of-scan */ 2577 devpriv->aimode = AIMODE_SCAN; 2578 } else { 2579 devpriv->aimode = AIMODE_HALF_FULL; 2580 } 2581 2582 switch (devpriv->aimode) { 2583 case AIMODE_HALF_FULL: 2584 /*generate FIFO interrupts and DMA requests on half-full */ 2585#ifdef PCIDMA 2586 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, 2587 AI_Mode_3_Register); 2588#else 2589 devpriv->stc_writew(dev, AI_FIFO_Mode_HF, 2590 AI_Mode_3_Register); 2591#endif 2592 break; 2593 case AIMODE_SAMPLE: 2594 /*generate FIFO interrupts on non-empty */ 2595 devpriv->stc_writew(dev, AI_FIFO_Mode_NE, 2596 AI_Mode_3_Register); 2597 break; 2598 case AIMODE_SCAN: 2599#ifdef PCIDMA 2600 devpriv->stc_writew(dev, AI_FIFO_Mode_NE, 2601 AI_Mode_3_Register); 2602#else 2603 devpriv->stc_writew(dev, AI_FIFO_Mode_HF, 2604 AI_Mode_3_Register); 2605#endif 2606 interrupt_a_enable |= AI_STOP_Interrupt_Enable; 2607 break; 2608 default: 2609 break; 2610 } 2611 2612 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */ 2613 2614 ni_set_bits(dev, Interrupt_A_Enable_Register, 2615 interrupt_a_enable, 1); 2616 2617 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n", 2618 devpriv->int_a_enable_reg); 2619 } else { 2620 /* interrupt on nothing */ 2621 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0); 2622 2623 MDPRINTK("interrupting on nothing\n"); 2624 } 2625 2626 /* end configuration */ 2627 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); 2628 2629 switch (cmd->scan_begin_src) { 2630 case TRIG_TIMER: 2631 devpriv->stc_writew(dev, 2632 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | 2633 AI_SC_Arm, AI_Command_1_Register); 2634 break; 2635 case TRIG_EXT: 2636 devpriv->stc_writew(dev, 2637 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | 2638 AI_SC_Arm, AI_Command_1_Register); 2639 break; 2640 } 2641 2642#ifdef PCIDMA 2643 { 2644 int retval = ni_ai_setup_MITE_dma(dev); 2645 if (retval) 2646 return retval; 2647 } 2648 /* mite_dump_regs(devpriv->mite); */ 2649#endif 2650 2651 switch (cmd->start_src) { 2652 case TRIG_NOW: 2653 /* AI_START1_Pulse */ 2654 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, 2655 AI_Command_2_Register); 2656 s->async->inttrig = NULL; 2657 break; 2658 case TRIG_EXT: 2659 s->async->inttrig = NULL; 2660 break; 2661 case TRIG_INT: 2662 s->async->inttrig = &ni_ai_inttrig; 2663 break; 2664 } 2665 2666 MDPRINTK("exit ni_ai_cmd\n"); 2667 2668 return 0; 2669} 2670 2671static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 2672 unsigned int trignum) 2673{ 2674 if (trignum != 0) 2675 return -EINVAL; 2676 2677 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, 2678 AI_Command_2_Register); 2679 s->async->inttrig = NULL; 2680 2681 return 1; 2682} 2683 2684static int ni_ai_config_analog_trig(struct comedi_device *dev, 2685 struct comedi_subdevice *s, 2686 struct comedi_insn *insn, 2687 unsigned int *data); 2688 2689static int ni_ai_insn_config(struct comedi_device *dev, 2690 struct comedi_subdevice *s, 2691 struct comedi_insn *insn, unsigned int *data) 2692{ 2693 if (insn->n < 1) 2694 return -EINVAL; 2695 2696 switch (data[0]) { 2697 case INSN_CONFIG_ANALOG_TRIG: 2698 return ni_ai_config_analog_trig(dev, s, insn, data); 2699 case INSN_CONFIG_ALT_SOURCE: 2700 if (boardtype.reg_type & ni_reg_m_series_mask) { 2701 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask | 2702 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | 2703 MSeries_AI_Bypass_Mode_Mux_Mask | 2704 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) { 2705 return -EINVAL; 2706 } 2707 devpriv->ai_calib_source = data[1]; 2708 } else if (boardtype.reg_type == ni_reg_6143) { 2709 unsigned int calib_source; 2710 2711 calib_source = data[1] & 0xf; 2712 2713 if (calib_source > 0xF) 2714 return -EINVAL; 2715 2716 devpriv->ai_calib_source = calib_source; 2717 ni_writew(calib_source, Calibration_Channel_6143); 2718 } else { 2719 unsigned int calib_source; 2720 unsigned int calib_source_adjust; 2721 2722 calib_source = data[1] & 0xf; 2723 calib_source_adjust = (data[1] >> 4) & 0xff; 2724 2725 if (calib_source >= 8) 2726 return -EINVAL; 2727 devpriv->ai_calib_source = calib_source; 2728 if (boardtype.reg_type == ni_reg_611x) { 2729 ni_writeb(calib_source_adjust, 2730 Cal_Gain_Select_611x); 2731 } 2732 } 2733 return 2; 2734 default: 2735 break; 2736 } 2737 2738 return -EINVAL; 2739} 2740 2741static int ni_ai_config_analog_trig(struct comedi_device *dev, 2742 struct comedi_subdevice *s, 2743 struct comedi_insn *insn, 2744 unsigned int *data) 2745{ 2746 unsigned int a, b, modebits; 2747 int err = 0; 2748 2749 /* data[1] is flags 2750 * data[2] is analog line 2751 * data[3] is set level 2752 * data[4] is reset level */ 2753 if (!boardtype.has_analog_trig) 2754 return -EINVAL; 2755 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) { 2756 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff); 2757 err++; 2758 } 2759 if (data[2] >= boardtype.n_adchan) { 2760 data[2] = boardtype.n_adchan - 1; 2761 err++; 2762 } 2763 if (data[3] > 255) { /* a */ 2764 data[3] = 255; 2765 err++; 2766 } 2767 if (data[4] > 255) { /* b */ 2768 data[4] = 255; 2769 err++; 2770 } 2771 /* 2772 * 00 ignore 2773 * 01 set 2774 * 10 reset 2775 * 2776 * modes: 2777 * 1 level: +b- +a- 2778 * high mode 00 00 01 10 2779 * low mode 00 00 10 01 2780 * 2 level: (a<b) 2781 * hysteresis low mode 10 00 00 01 2782 * hysteresis high mode 01 00 00 10 2783 * middle mode 10 01 01 10 2784 */ 2785 2786 a = data[3]; 2787 b = data[4]; 2788 modebits = data[1] & 0xff; 2789 if (modebits & 0xf0) { 2790 /* two level mode */ 2791 if (b < a) { 2792 /* swap order */ 2793 a = data[4]; 2794 b = data[3]; 2795 modebits = 2796 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4); 2797 } 2798 devpriv->atrig_low = a; 2799 devpriv->atrig_high = b; 2800 switch (modebits) { 2801 case 0x81: /* low hysteresis mode */ 2802 devpriv->atrig_mode = 6; 2803 break; 2804 case 0x42: /* high hysteresis mode */ 2805 devpriv->atrig_mode = 3; 2806 break; 2807 case 0x96: /* middle window mode */ 2808 devpriv->atrig_mode = 2; 2809 break; 2810 default: 2811 data[1] &= ~0xff; 2812 err++; 2813 } 2814 } else { 2815 /* one level mode */ 2816 if (b != 0) { 2817 data[4] = 0; 2818 err++; 2819 } 2820 switch (modebits) { 2821 case 0x06: /* high window mode */ 2822 devpriv->atrig_high = a; 2823 devpriv->atrig_mode = 0; 2824 break; 2825 case 0x09: /* low window mode */ 2826 devpriv->atrig_low = a; 2827 devpriv->atrig_mode = 1; 2828 break; 2829 default: 2830 data[1] &= ~0xff; 2831 err++; 2832 } 2833 } 2834 if (err) 2835 return -EAGAIN; 2836 return 5; 2837} 2838 2839/* munge data from unsigned to 2's complement for analog output bipolar modes */ 2840static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s, 2841 void *data, unsigned int num_bytes, 2842 unsigned int chan_index) 2843{ 2844 struct comedi_async *async = s->async; 2845 unsigned int range; 2846 unsigned int i; 2847 unsigned int offset; 2848 unsigned int length = num_bytes / sizeof(short); 2849 short *array = data; 2850 2851 offset = 1 << (boardtype.aobits - 1); 2852 for (i = 0; i < length; i++) { 2853 range = CR_RANGE(async->cmd.chanlist[chan_index]); 2854 if (boardtype.ao_unipolar == 0 || (range & 1) == 0) 2855 array[i] -= offset; 2856#ifdef PCIDMA 2857 array[i] = cpu_to_le16(array[i]); 2858#endif 2859 chan_index++; 2860 chan_index %= async->cmd.chanlist_len; 2861 } 2862} 2863 2864static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, 2865 struct comedi_subdevice *s, 2866 unsigned int chanspec[], 2867 unsigned int n_chans, int timed) 2868{ 2869 unsigned int range; 2870 unsigned int chan; 2871 unsigned int conf; 2872 int i; 2873 int invert = 0; 2874 2875 if (timed) { 2876 for (i = 0; i < boardtype.n_aochan; ++i) { 2877 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit; 2878 ni_writeb(devpriv->ao_conf[i], 2879 M_Offset_AO_Config_Bank(i)); 2880 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i)); 2881 } 2882 } 2883 for (i = 0; i < n_chans; i++) { 2884 const struct comedi_krange *krange; 2885 chan = CR_CHAN(chanspec[i]); 2886 range = CR_RANGE(chanspec[i]); 2887 krange = s->range_table->range + range; 2888 invert = 0; 2889 conf = 0; 2890 switch (krange->max - krange->min) { 2891 case 20000000: 2892 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2893 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); 2894 break; 2895 case 10000000: 2896 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2897 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); 2898 break; 2899 case 4000000: 2900 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; 2901 ni_writeb(MSeries_Attenuate_x5_Bit, 2902 M_Offset_AO_Reference_Attenuation(chan)); 2903 break; 2904 case 2000000: 2905 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; 2906 ni_writeb(MSeries_Attenuate_x5_Bit, 2907 M_Offset_AO_Reference_Attenuation(chan)); 2908 break; 2909 default: 2910 printk("%s: bug! unhandled ao reference voltage\n", 2911 __func__); 2912 break; 2913 } 2914 switch (krange->max + krange->min) { 2915 case 0: 2916 conf |= MSeries_AO_DAC_Offset_0V_Bits; 2917 break; 2918 case 10000000: 2919 conf |= MSeries_AO_DAC_Offset_5V_Bits; 2920 break; 2921 default: 2922 printk("%s: bug! unhandled ao offset voltage\n", 2923 __func__); 2924 break; 2925 } 2926 if (timed) 2927 conf |= MSeries_AO_Update_Timed_Bit; 2928 ni_writeb(conf, M_Offset_AO_Config_Bank(chan)); 2929 devpriv->ao_conf[chan] = conf; 2930 ni_writeb(i, M_Offset_AO_Waveform_Order(chan)); 2931 } 2932 return invert; 2933} 2934 2935static int ni_old_ao_config_chanlist(struct comedi_device *dev, 2936 struct comedi_subdevice *s, 2937 unsigned int chanspec[], 2938 unsigned int n_chans) 2939{ 2940 unsigned int range; 2941 unsigned int chan; 2942 unsigned int conf; 2943 int i; 2944 int invert = 0; 2945 2946 for (i = 0; i < n_chans; i++) { 2947 chan = CR_CHAN(chanspec[i]); 2948 range = CR_RANGE(chanspec[i]); 2949 conf = AO_Channel(chan); 2950 2951 if (boardtype.ao_unipolar) { 2952 if ((range & 1) == 0) { 2953 conf |= AO_Bipolar; 2954 invert = (1 << (boardtype.aobits - 1)); 2955 } else { 2956 invert = 0; 2957 } 2958 if (range & 2) 2959 conf |= AO_Ext_Ref; 2960 } else { 2961 conf |= AO_Bipolar; 2962 invert = (1 << (boardtype.aobits - 1)); 2963 } 2964 2965 /* not all boards can deglitch, but this shouldn't hurt */ 2966 if (chanspec[i] & CR_DEGLITCH) 2967 conf |= AO_Deglitch; 2968 2969 /* analog reference */ 2970 /* AREF_OTHER connects AO ground to AI ground, i think */ 2971 conf |= (CR_AREF(chanspec[i]) == 2972 AREF_OTHER) ? AO_Ground_Ref : 0; 2973 2974 ni_writew(conf, AO_Configuration); 2975 devpriv->ao_conf[chan] = conf; 2976 } 2977 return invert; 2978} 2979 2980static int ni_ao_config_chanlist(struct comedi_device *dev, 2981 struct comedi_subdevice *s, 2982 unsigned int chanspec[], unsigned int n_chans, 2983 int timed) 2984{ 2985 if (boardtype.reg_type & ni_reg_m_series_mask) 2986 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, 2987 timed); 2988 else 2989 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans); 2990} 2991 2992static int ni_ao_insn_read(struct comedi_device *dev, 2993 struct comedi_subdevice *s, struct comedi_insn *insn, 2994 unsigned int *data) 2995{ 2996 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)]; 2997 2998 return 1; 2999} 3000 3001static int ni_ao_insn_write(struct comedi_device *dev, 3002 struct comedi_subdevice *s, 3003 struct comedi_insn *insn, unsigned int *data) 3004{ 3005 unsigned int chan = CR_CHAN(insn->chanspec); 3006 unsigned int invert; 3007 3008 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); 3009 3010 devpriv->ao[chan] = data[0]; 3011 3012 if (boardtype.reg_type & ni_reg_m_series_mask) { 3013 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan)); 3014 } else 3015 ni_writew(data[0] ^ invert, 3016 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data); 3017 3018 return 1; 3019} 3020 3021static int ni_ao_insn_write_671x(struct comedi_device *dev, 3022 struct comedi_subdevice *s, 3023 struct comedi_insn *insn, unsigned int *data) 3024{ 3025 unsigned int chan = CR_CHAN(insn->chanspec); 3026 unsigned int invert; 3027 3028 ao_win_out(1 << chan, AO_Immediate_671x); 3029 invert = 1 << (boardtype.aobits - 1); 3030 3031 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); 3032 3033 devpriv->ao[chan] = data[0]; 3034 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan)); 3035 3036 return 1; 3037} 3038 3039static int ni_ao_insn_config(struct comedi_device *dev, 3040 struct comedi_subdevice *s, 3041 struct comedi_insn *insn, unsigned int *data) 3042{ 3043 switch (data[0]) { 3044 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE: 3045 switch (data[1]) { 3046 case COMEDI_OUTPUT: 3047 data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short); 3048 if (devpriv->mite) 3049 data[2] += devpriv->mite->fifo_size; 3050 break; 3051 case COMEDI_INPUT: 3052 data[2] = 0; 3053 break; 3054 default: 3055 return -EINVAL; 3056 break; 3057 } 3058 return 0; 3059 default: 3060 break; 3061 } 3062 3063 return -EINVAL; 3064} 3065 3066static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 3067 unsigned int trignum) 3068{ 3069 int ret; 3070 int interrupt_b_bits; 3071 int i; 3072 static const int timeout = 1000; 3073 3074 if (trignum != 0) 3075 return -EINVAL; 3076 3077 /* Null trig at beginning prevent ao start trigger from executing more than 3078 once per command (and doing things like trying to allocate the ao dma channel 3079 multiple times) */ 3080 s->async->inttrig = NULL; 3081 3082 ni_set_bits(dev, Interrupt_B_Enable_Register, 3083 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0); 3084 interrupt_b_bits = AO_Error_Interrupt_Enable; 3085#ifdef PCIDMA 3086 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear); 3087 if (boardtype.reg_type & ni_reg_6xxx_mask) 3088 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); 3089 ret = ni_ao_setup_MITE_dma(dev); 3090 if (ret) 3091 return ret; 3092 ret = ni_ao_wait_for_dma_load(dev); 3093 if (ret < 0) 3094 return ret; 3095#else 3096 ret = ni_ao_prep_fifo(dev, s); 3097 if (ret == 0) 3098 return -EPIPE; 3099 3100 interrupt_b_bits |= AO_FIFO_Interrupt_Enable; 3101#endif 3102 3103 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE, 3104 AO_Mode_3_Register); 3105 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3106 /* wait for DACs to be loaded */ 3107 for (i = 0; i < timeout; i++) { 3108 udelay(1); 3109 if ((devpriv->stc_readw(dev, 3110 Joint_Status_2_Register) & 3111 AO_TMRDACWRs_In_Progress_St) == 0) 3112 break; 3113 } 3114 if (i == timeout) { 3115 comedi_error(dev, 3116 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear"); 3117 return -EIO; 3118 } 3119 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */ 3120 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, 3121 Interrupt_B_Ack_Register); 3122 3123 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1); 3124 3125 devpriv->stc_writew(dev, 3126 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm 3127 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode, 3128 AO_Command_1_Register); 3129 3130 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse, 3131 AO_Command_2_Register); 3132 3133 return 0; 3134} 3135 3136static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3137{ 3138 const struct comedi_cmd *cmd = &s->async->cmd; 3139 int bits; 3140 int i; 3141 unsigned trigvar; 3142 3143 if (dev->irq == 0) { 3144 comedi_error(dev, "cannot run command without an irq"); 3145 return -EIO; 3146 } 3147 3148 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); 3149 3150 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register); 3151 3152 if (boardtype.reg_type & ni_reg_6xxx_mask) { 3153 ao_win_out(CLEAR_WG, AO_Misc_611x); 3154 3155 bits = 0; 3156 for (i = 0; i < cmd->chanlist_len; i++) { 3157 int chan; 3158 3159 chan = CR_CHAN(cmd->chanlist[i]); 3160 bits |= 1 << chan; 3161 ao_win_out(chan, AO_Waveform_Generation_611x); 3162 } 3163 ao_win_out(bits, AO_Timed_611x); 3164 } 3165 3166 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); 3167 3168 if (cmd->stop_src == TRIG_NONE) { 3169 devpriv->ao_mode1 |= AO_Continuous; 3170 devpriv->ao_mode1 &= ~AO_Trigger_Once; 3171 } else { 3172 devpriv->ao_mode1 &= ~AO_Continuous; 3173 devpriv->ao_mode1 |= AO_Trigger_Once; 3174 } 3175 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3176 switch (cmd->start_src) { 3177 case TRIG_INT: 3178 case TRIG_NOW: 3179 devpriv->ao_trigger_select &= 3180 ~(AO_START1_Polarity | AO_START1_Select(-1)); 3181 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync; 3182 devpriv->stc_writew(dev, devpriv->ao_trigger_select, 3183 AO_Trigger_Select_Register); 3184 break; 3185 case TRIG_EXT: 3186 devpriv->ao_trigger_select = 3187 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1); 3188 if (cmd->start_arg & CR_INVERT) 3189 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ 3190 if (cmd->start_arg & CR_EDGE) 3191 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */ 3192 devpriv->stc_writew(dev, devpriv->ao_trigger_select, 3193 AO_Trigger_Select_Register); 3194 break; 3195 default: 3196 BUG(); 3197 break; 3198 } 3199 devpriv->ao_mode3 &= ~AO_Trigger_Length; 3200 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3201 3202 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3203 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source; 3204 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3205 if (cmd->stop_src == TRIG_NONE) { 3206 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register); 3207 } else { 3208 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register); 3209 } 3210 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register); 3211 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source; 3212 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3213 switch (cmd->stop_src) { 3214 case TRIG_COUNT: 3215 if (boardtype.reg_type & ni_reg_m_series_mask) { 3216 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */ 3217 devpriv->stc_writel(dev, cmd->stop_arg - 1, 3218 AO_UC_Load_A_Register); 3219 devpriv->stc_writew(dev, AO_UC_Load, 3220 AO_Command_1_Register); 3221 } else { 3222 devpriv->stc_writel(dev, cmd->stop_arg, 3223 AO_UC_Load_A_Register); 3224 devpriv->stc_writew(dev, AO_UC_Load, 3225 AO_Command_1_Register); 3226 devpriv->stc_writel(dev, cmd->stop_arg - 1, 3227 AO_UC_Load_A_Register); 3228 } 3229 break; 3230 case TRIG_NONE: 3231 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); 3232 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3233 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); 3234 break; 3235 default: 3236 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register); 3237 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); 3238 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register); 3239 } 3240 3241 devpriv->ao_mode1 &= 3242 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity | 3243 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity); 3244 switch (cmd->scan_begin_src) { 3245 case TRIG_TIMER: 3246 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable; 3247 trigvar = 3248 ni_ns_to_timer(dev, cmd->scan_begin_arg, 3249 TRIG_ROUND_NEAREST); 3250 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register); 3251 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register); 3252 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register); 3253 break; 3254 case TRIG_EXT: 3255 devpriv->ao_mode1 |= 3256 AO_UPDATE_Source_Select(cmd->scan_begin_arg); 3257 if (cmd->scan_begin_arg & CR_INVERT) 3258 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity; 3259 devpriv->ao_cmd2 |= AO_BC_Gate_Enable; 3260 break; 3261 default: 3262 BUG(); 3263 break; 3264 } 3265 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); 3266 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3267 devpriv->ao_mode2 &= 3268 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source); 3269 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3270 3271 if (cmd->scan_end_arg > 1) { 3272 devpriv->ao_mode1 |= AO_Multiple_Channels; 3273 devpriv->stc_writew(dev, 3274 AO_Number_Of_Channels(cmd->scan_end_arg - 3275 1) | 3276 AO_UPDATE_Output_Select 3277 (AO_Update_Output_High_Z), 3278 AO_Output_Control_Register); 3279 } else { 3280 unsigned bits; 3281 devpriv->ao_mode1 &= ~AO_Multiple_Channels; 3282 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z); 3283 if (boardtype. 3284 reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) { 3285 bits |= AO_Number_Of_Channels(0); 3286 } else { 3287 bits |= 3288 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0])); 3289 } 3290 devpriv->stc_writew(dev, bits, AO_Output_Control_Register); 3291 } 3292 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3293 3294 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode, 3295 AO_Command_1_Register); 3296 3297 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error; 3298 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3299 3300 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask; 3301#ifdef PCIDMA 3302 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F; 3303#else 3304 devpriv->ao_mode2 |= AO_FIFO_Mode_HF; 3305#endif 3306 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable; 3307 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3308 3309 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width | 3310 AO_TMRDACWR_Pulse_Width; 3311 if (boardtype.ao_fifo_depth) 3312 bits |= AO_FIFO_Enable; 3313 else 3314 bits |= AO_DMA_PIO_Control; 3315 devpriv->stc_writew(dev, bits, AO_Personal_Register); 3316 /* enable sending of ao dma requests */ 3317 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register); 3318 3319 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); 3320 3321 if (cmd->stop_src == TRIG_COUNT) { 3322 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack, 3323 Interrupt_B_Ack_Register); 3324 ni_set_bits(dev, Interrupt_B_Enable_Register, 3325 AO_BC_TC_Interrupt_Enable, 1); 3326 } 3327 3328 s->async->inttrig = &ni_ao_inttrig; 3329 3330 return 0; 3331} 3332 3333static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, 3334 struct comedi_cmd *cmd) 3335{ 3336 int err = 0; 3337 int tmp; 3338 3339 /* step 1: make sure trigger sources are trivially valid */ 3340 3341 if ((cmd->flags & CMDF_WRITE) == 0) { 3342 cmd->flags |= CMDF_WRITE; 3343 } 3344 3345 tmp = cmd->start_src; 3346 cmd->start_src &= TRIG_INT | TRIG_EXT; 3347 if (!cmd->start_src || tmp != cmd->start_src) 3348 err++; 3349 3350 tmp = cmd->scan_begin_src; 3351 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 3352 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 3353 err++; 3354 3355 tmp = cmd->convert_src; 3356 cmd->convert_src &= TRIG_NOW; 3357 if (!cmd->convert_src || tmp != cmd->convert_src) 3358 err++; 3359 3360 tmp = cmd->scan_end_src; 3361 cmd->scan_end_src &= TRIG_COUNT; 3362 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 3363 err++; 3364 3365 tmp = cmd->stop_src; 3366 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 3367 if (!cmd->stop_src || tmp != cmd->stop_src) 3368 err++; 3369 3370 if (err) 3371 return 1; 3372 3373 /* step 2: make sure trigger sources are unique and mutually compatible */ 3374 3375 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 3376 err++; 3377 3378 if (err) 3379 return 2; 3380 3381 /* step 3: make sure arguments are trivially compatible */ 3382 3383 if (cmd->start_src == TRIG_EXT) { 3384 /* external trigger */ 3385 unsigned int tmp = CR_CHAN(cmd->start_arg); 3386 3387 if (tmp > 18) 3388 tmp = 18; 3389 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE)); 3390 if (cmd->start_arg != tmp) { 3391 cmd->start_arg = tmp; 3392 err++; 3393 } 3394 } else { 3395 if (cmd->start_arg != 0) { 3396 /* true for both TRIG_NOW and TRIG_INT */ 3397 cmd->start_arg = 0; 3398 err++; 3399 } 3400 } 3401 if (cmd->scan_begin_src == TRIG_TIMER) { 3402 if (cmd->scan_begin_arg < boardtype.ao_speed) { 3403 cmd->scan_begin_arg = boardtype.ao_speed; 3404 err++; 3405 } 3406 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { 3407 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff; 3408 err++; 3409 } 3410 } 3411 if (cmd->convert_arg != 0) { 3412 cmd->convert_arg = 0; 3413 err++; 3414 } 3415 if (cmd->scan_end_arg != cmd->chanlist_len) { 3416 cmd->scan_end_arg = cmd->chanlist_len; 3417 err++; 3418 } 3419 if (cmd->stop_src == TRIG_COUNT) { 3420 if (cmd->stop_arg > 0x00ffffff) { 3421 cmd->stop_arg = 0x00ffffff; 3422 err++; 3423 } 3424 } else { 3425 /* TRIG_NONE */ 3426 if (cmd->stop_arg != 0) { 3427 cmd->stop_arg = 0; 3428 err++; 3429 } 3430 } 3431 3432 if (err) 3433 return 3; 3434 3435 /* step 4: fix up any arguments */ 3436 if (cmd->scan_begin_src == TRIG_TIMER) { 3437 tmp = cmd->scan_begin_arg; 3438 cmd->scan_begin_arg = 3439 ni_timer_to_ns(dev, ni_ns_to_timer(dev, 3440 cmd->scan_begin_arg, 3441 cmd-> 3442 flags & 3443 TRIG_ROUND_MASK)); 3444 if (tmp != cmd->scan_begin_arg) 3445 err++; 3446 } 3447 if (err) 3448 return 4; 3449 3450 /* step 5: fix up chanlist */ 3451 3452 if (err) 3453 return 5; 3454 3455 return 0; 3456} 3457 3458static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) 3459{ 3460 /* devpriv->ao0p=0x0000; */ 3461 /* ni_writew(devpriv->ao0p,AO_Configuration); */ 3462 3463 /* devpriv->ao1p=AO_Channel(1); */ 3464 /* ni_writew(devpriv->ao1p,AO_Configuration); */ 3465 3466 ni_release_ao_mite_channel(dev); 3467 3468 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); 3469 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register); 3470 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0); 3471 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register); 3472 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register); 3473 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width | 3474 AO_TMRDACWR_Pulse_Width, AO_Personal_Register); 3475 devpriv->stc_writew(dev, 0, AO_Output_Control_Register); 3476 devpriv->stc_writew(dev, 0, AO_Start_Select_Register); 3477 devpriv->ao_cmd1 = 0; 3478 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register); 3479 devpriv->ao_cmd2 = 0; 3480 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); 3481 devpriv->ao_mode1 = 0; 3482 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); 3483 devpriv->ao_mode2 = 0; 3484 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); 3485 if (boardtype.reg_type & ni_reg_m_series_mask) 3486 devpriv->ao_mode3 = AO_Last_Gate_Disable; 3487 else 3488 devpriv->ao_mode3 = 0; 3489 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); 3490 devpriv->ao_trigger_select = 0; 3491 devpriv->stc_writew(dev, devpriv->ao_trigger_select, 3492 AO_Trigger_Select_Register); 3493 if (boardtype.reg_type & ni_reg_6xxx_mask) { 3494 unsigned immediate_bits = 0; 3495 unsigned i; 3496 for (i = 0; i < s->n_chan; ++i) { 3497 immediate_bits |= 1 << i; 3498 } 3499 ao_win_out(immediate_bits, AO_Immediate_671x); 3500 ao_win_out(CLEAR_WG, AO_Misc_611x); 3501 } 3502 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); 3503 3504 return 0; 3505} 3506 3507/* digital io */ 3508 3509static int ni_dio_insn_config(struct comedi_device *dev, 3510 struct comedi_subdevice *s, 3511 struct comedi_insn *insn, unsigned int *data) 3512{ 3513#ifdef DEBUG_DIO 3514 printk("ni_dio_insn_config() chan=%d io=%d\n", 3515 CR_CHAN(insn->chanspec), data[0]); 3516#endif 3517 switch (data[0]) { 3518 case INSN_CONFIG_DIO_OUTPUT: 3519 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 3520 break; 3521 case INSN_CONFIG_DIO_INPUT: 3522 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 3523 break; 3524 case INSN_CONFIG_DIO_QUERY: 3525 data[1] = 3526 (s-> 3527 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : 3528 COMEDI_INPUT; 3529 return insn->n; 3530 break; 3531 default: 3532 return -EINVAL; 3533 } 3534 3535 devpriv->dio_control &= ~DIO_Pins_Dir_Mask; 3536 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits); 3537 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3538 3539 return 1; 3540} 3541 3542static int ni_dio_insn_bits(struct comedi_device *dev, 3543 struct comedi_subdevice *s, 3544 struct comedi_insn *insn, unsigned int *data) 3545{ 3546#ifdef DEBUG_DIO 3547 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]); 3548#endif 3549 if (insn->n != 2) 3550 return -EINVAL; 3551 if (data[0]) { 3552 /* Perform check to make sure we're not using the 3553 serial part of the dio */ 3554 if ((data[0] & (DIO_SDIN | DIO_SDOUT)) 3555 && devpriv->serial_interval_ns) 3556 return -EBUSY; 3557 3558 s->state &= ~data[0]; 3559 s->state |= (data[0] & data[1]); 3560 devpriv->dio_output &= ~DIO_Parallel_Data_Mask; 3561 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state); 3562 devpriv->stc_writew(dev, devpriv->dio_output, 3563 DIO_Output_Register); 3564 } 3565 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register); 3566 3567 return 2; 3568} 3569 3570static int ni_m_series_dio_insn_config(struct comedi_device *dev, 3571 struct comedi_subdevice *s, 3572 struct comedi_insn *insn, 3573 unsigned int *data) 3574{ 3575#ifdef DEBUG_DIO 3576 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n", 3577 CR_CHAN(insn->chanspec), data[0]); 3578#endif 3579 switch (data[0]) { 3580 case INSN_CONFIG_DIO_OUTPUT: 3581 s->io_bits |= 1 << CR_CHAN(insn->chanspec); 3582 break; 3583 case INSN_CONFIG_DIO_INPUT: 3584 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec)); 3585 break; 3586 case INSN_CONFIG_DIO_QUERY: 3587 data[1] = 3588 (s-> 3589 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : 3590 COMEDI_INPUT; 3591 return insn->n; 3592 break; 3593 default: 3594 return -EINVAL; 3595 } 3596 3597 ni_writel(s->io_bits, M_Offset_DIO_Direction); 3598 3599 return 1; 3600} 3601 3602static int ni_m_series_dio_insn_bits(struct comedi_device *dev, 3603 struct comedi_subdevice *s, 3604 struct comedi_insn *insn, 3605 unsigned int *data) 3606{ 3607#ifdef DEBUG_DIO 3608 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], 3609 data[1]); 3610#endif 3611 if (insn->n != 2) 3612 return -EINVAL; 3613 if (data[0]) { 3614 s->state &= ~data[0]; 3615 s->state |= (data[0] & data[1]); 3616 ni_writel(s->state, M_Offset_Static_Digital_Output); 3617 } 3618 data[1] = ni_readl(M_Offset_Static_Digital_Input); 3619 3620 return 2; 3621} 3622 3623static int ni_cdio_cmdtest(struct comedi_device *dev, 3624 struct comedi_subdevice *s, struct comedi_cmd *cmd) 3625{ 3626 int err = 0; 3627 int tmp; 3628 int sources; 3629 unsigned i; 3630 3631 /* step 1: make sure trigger sources are trivially valid */ 3632 3633 tmp = cmd->start_src; 3634 sources = TRIG_INT; 3635 cmd->start_src &= sources; 3636 if (!cmd->start_src || tmp != cmd->start_src) 3637 err++; 3638 3639 tmp = cmd->scan_begin_src; 3640 cmd->scan_begin_src &= TRIG_EXT; 3641 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 3642 err++; 3643 3644 tmp = cmd->convert_src; 3645 cmd->convert_src &= TRIG_NOW; 3646 if (!cmd->convert_src || tmp != cmd->convert_src) 3647 err++; 3648 3649 tmp = cmd->scan_end_src; 3650 cmd->scan_end_src &= TRIG_COUNT; 3651 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 3652 err++; 3653 3654 tmp = cmd->stop_src; 3655 cmd->stop_src &= TRIG_NONE; 3656 if (!cmd->stop_src || tmp != cmd->stop_src) 3657 err++; 3658 3659 if (err) 3660 return 1; 3661 3662 /* step 2: make sure trigger sources are unique... */ 3663 3664 if (cmd->start_src != TRIG_INT) 3665 err++; 3666 if (cmd->scan_begin_src != TRIG_EXT) 3667 err++; 3668 if (cmd->convert_src != TRIG_NOW) 3669 err++; 3670 if (cmd->stop_src != TRIG_NONE) 3671 err++; 3672 /* ... and mutually compatible */ 3673 3674 if (err) 3675 return 2; 3676 3677 /* step 3: make sure arguments are trivially compatible */ 3678 if (cmd->start_src == TRIG_INT) { 3679 if (cmd->start_arg != 0) { 3680 cmd->start_arg = 0; 3681 err++; 3682 } 3683 } 3684 if (cmd->scan_begin_src == TRIG_EXT) { 3685 tmp = cmd->scan_begin_arg; 3686 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, 3687 CR_INVERT); 3688 if (tmp != cmd->scan_begin_arg) { 3689 err++; 3690 } 3691 } 3692 if (cmd->convert_src == TRIG_NOW) { 3693 if (cmd->convert_arg) { 3694 cmd->convert_arg = 0; 3695 err++; 3696 } 3697 } 3698 3699 if (cmd->scan_end_arg != cmd->chanlist_len) { 3700 cmd->scan_end_arg = cmd->chanlist_len; 3701 err++; 3702 } 3703 3704 if (cmd->stop_src == TRIG_NONE) { 3705 if (cmd->stop_arg != 0) { 3706 cmd->stop_arg = 0; 3707 err++; 3708 } 3709 } 3710 3711 if (err) 3712 return 3; 3713 3714 /* step 4: fix up any arguments */ 3715 3716 if (err) 3717 return 4; 3718 3719 /* step 5: check chanlist */ 3720 3721 for (i = 0; i < cmd->chanlist_len; ++i) { 3722 if (cmd->chanlist[i] != i) 3723 err = 1; 3724 } 3725 3726 if (err) 3727 return 5; 3728 3729 return 0; 3730} 3731 3732static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 3733{ 3734 const struct comedi_cmd *cmd = &s->async->cmd; 3735 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; 3736 int retval; 3737 3738 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command); 3739 switch (cmd->scan_begin_src) { 3740 case TRIG_EXT: 3741 cdo_mode_bits |= 3742 CR_CHAN(cmd->scan_begin_arg) & 3743 CDO_Sample_Source_Select_Mask; 3744 break; 3745 default: 3746 BUG(); 3747 break; 3748 } 3749 if (cmd->scan_begin_arg & CR_INVERT) 3750 cdo_mode_bits |= CDO_Polarity_Bit; 3751 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode); 3752 if (s->io_bits) { 3753 ni_writel(s->state, M_Offset_CDO_FIFO_Data); 3754 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command); 3755 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable); 3756 } else { 3757 comedi_error(dev, 3758 "attempted to run digital output command with no lines configured as outputs"); 3759 return -EIO; 3760 } 3761 retval = ni_request_cdo_mite_channel(dev); 3762 if (retval < 0) { 3763 return retval; 3764 } 3765 s->async->inttrig = &ni_cdo_inttrig; 3766 return 0; 3767} 3768 3769static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, 3770 unsigned int trignum) 3771{ 3772#ifdef PCIDMA 3773 unsigned long flags; 3774#endif 3775 int retval = 0; 3776 unsigned i; 3777 const unsigned timeout = 1000; 3778 3779 s->async->inttrig = NULL; 3780 3781 /* read alloc the entire buffer */ 3782 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz); 3783 3784#ifdef PCIDMA 3785 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 3786 if (devpriv->cdo_mite_chan) { 3787 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); 3788 mite_dma_arm(devpriv->cdo_mite_chan); 3789 } else { 3790 comedi_error(dev, "BUG: no cdo mite channel?"); 3791 retval = -EIO; 3792 } 3793 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 3794 if (retval < 0) 3795 return retval; 3796#endif 3797 for (i = 0; i < timeout; ++i) { 3798 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) 3799 break; 3800 udelay(10); 3801 } 3802 if (i == timeout) { 3803 comedi_error(dev, "dma failed to fill cdo fifo!"); 3804 ni_cdio_cancel(dev, s); 3805 return -EIO; 3806 } 3807 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | 3808 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, 3809 M_Offset_CDIO_Command); 3810 return retval; 3811} 3812 3813static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 3814{ 3815 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | 3816 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | 3817 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, 3818 M_Offset_CDIO_Command); 3819 ni_writel(0, M_Offset_CDO_Mask_Enable); 3820 ni_release_cdo_mite_channel(dev); 3821 return 0; 3822} 3823 3824static void handle_cdio_interrupt(struct comedi_device *dev) 3825{ 3826 unsigned cdio_status; 3827 struct comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV; 3828#ifdef PCIDMA 3829 unsigned long flags; 3830#endif 3831 3832 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) { 3833 return; 3834 } 3835#ifdef PCIDMA 3836 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); 3837 if (devpriv->cdo_mite_chan) { 3838 unsigned cdo_mite_status = 3839 mite_get_status(devpriv->cdo_mite_chan); 3840 if (cdo_mite_status & CHSR_LINKC) { 3841 writel(CHOR_CLRLC, 3842 devpriv->mite->mite_io_addr + 3843 MITE_CHOR(devpriv->cdo_mite_chan->channel)); 3844 } 3845 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async); 3846 } 3847 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); 3848#endif 3849 3850 cdio_status = ni_readl(M_Offset_CDIO_Status); 3851 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) { 3852/* printk("cdio error: statux=0x%x\n", cdio_status); */ 3853 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); 3854 s->async->events |= COMEDI_CB_OVERFLOW; 3855 } 3856 if (cdio_status & CDO_FIFO_Empty_Bit) { 3857/* printk("cdio fifo empty\n"); */ 3858 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, 3859 M_Offset_CDIO_Command); 3860/* s->async->events |= COMEDI_CB_EOA; */ 3861 } 3862 ni_event(dev, s); 3863} 3864 3865static int ni_serial_insn_config(struct comedi_device *dev, 3866 struct comedi_subdevice *s, 3867 struct comedi_insn *insn, unsigned int *data) 3868{ 3869 int err = insn->n; 3870 unsigned char byte_out, byte_in = 0; 3871 3872 if (insn->n != 2) 3873 return -EINVAL; 3874 3875 switch (data[0]) { 3876 case INSN_CONFIG_SERIAL_CLOCK: 3877 3878#ifdef DEBUG_DIO 3879 printk("SPI serial clock Config cd\n", data[1]); 3880#endif 3881 devpriv->serial_hw_mode = 1; 3882 devpriv->dio_control |= DIO_HW_Serial_Enable; 3883 3884 if (data[1] == SERIAL_DISABLED) { 3885 devpriv->serial_hw_mode = 0; 3886 devpriv->dio_control &= ~(DIO_HW_Serial_Enable | 3887 DIO_Software_Serial_Control); 3888 data[1] = SERIAL_DISABLED; 3889 devpriv->serial_interval_ns = data[1]; 3890 } else if (data[1] <= SERIAL_600NS) { 3891 /* Warning: this clock speed is too fast to reliably 3892 control SCXI. */ 3893 devpriv->dio_control &= ~DIO_HW_Serial_Timebase; 3894 devpriv->clock_and_fout |= Slow_Internal_Timebase; 3895 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2; 3896 data[1] = SERIAL_600NS; 3897 devpriv->serial_interval_ns = data[1]; 3898 } else if (data[1] <= SERIAL_1_2US) { 3899 devpriv->dio_control &= ~DIO_HW_Serial_Timebase; 3900 devpriv->clock_and_fout |= Slow_Internal_Timebase | 3901 DIO_Serial_Out_Divide_By_2; 3902 data[1] = SERIAL_1_2US; 3903 devpriv->serial_interval_ns = data[1]; 3904 } else if (data[1] <= SERIAL_10US) { 3905 devpriv->dio_control |= DIO_HW_Serial_Timebase; 3906 devpriv->clock_and_fout |= Slow_Internal_Timebase | 3907 DIO_Serial_Out_Divide_By_2; 3908 /* Note: DIO_Serial_Out_Divide_By_2 only affects 3909 600ns/1.2us. If you turn divide_by_2 off with the 3910 slow clock, you will still get 10us, except then 3911 all your delays are wrong. */ 3912 data[1] = SERIAL_10US; 3913 devpriv->serial_interval_ns = data[1]; 3914 } else { 3915 devpriv->dio_control &= ~(DIO_HW_Serial_Enable | 3916 DIO_Software_Serial_Control); 3917 devpriv->serial_hw_mode = 0; 3918 data[1] = (data[1] / 1000) * 1000; 3919 devpriv->serial_interval_ns = data[1]; 3920 } 3921 3922 devpriv->stc_writew(dev, devpriv->dio_control, 3923 DIO_Control_Register); 3924 devpriv->stc_writew(dev, devpriv->clock_and_fout, 3925 Clock_and_FOUT_Register); 3926 return 1; 3927 3928 break; 3929 3930 case INSN_CONFIG_BIDIRECTIONAL_DATA: 3931 3932 if (devpriv->serial_interval_ns == 0) { 3933 return -EINVAL; 3934 } 3935 3936 byte_out = data[1] & 0xFF; 3937 3938 if (devpriv->serial_hw_mode) { 3939 err = ni_serial_hw_readwrite8(dev, s, byte_out, 3940 &byte_in); 3941 } else if (devpriv->serial_interval_ns > 0) { 3942 err = ni_serial_sw_readwrite8(dev, s, byte_out, 3943 &byte_in); 3944 } else { 3945 printk("ni_serial_insn_config: serial disabled!\n"); 3946 return -EINVAL; 3947 } 3948 if (err < 0) 3949 return err; 3950 data[1] = byte_in & 0xFF; 3951 return insn->n; 3952 3953 break; 3954 default: 3955 return -EINVAL; 3956 } 3957 3958} 3959 3960static int ni_serial_hw_readwrite8(struct comedi_device *dev, 3961 struct comedi_subdevice *s, 3962 unsigned char data_out, 3963 unsigned char *data_in) 3964{ 3965 unsigned int status1; 3966 int err = 0, count = 20; 3967 3968#ifdef DEBUG_DIO 3969 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out); 3970#endif 3971 3972 devpriv->dio_output &= ~DIO_Serial_Data_Mask; 3973 devpriv->dio_output |= DIO_Serial_Data_Out(data_out); 3974 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register); 3975 3976 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register); 3977 if (status1 & DIO_Serial_IO_In_Progress_St) { 3978 err = -EBUSY; 3979 goto Error; 3980 } 3981 3982 devpriv->dio_control |= DIO_HW_Serial_Start; 3983 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 3984 devpriv->dio_control &= ~DIO_HW_Serial_Start; 3985 3986 /* Wait until STC says we're done, but don't loop infinitely. */ 3987 while ((status1 = 3988 devpriv->stc_readw(dev, 3989 Joint_Status_1_Register)) & 3990 DIO_Serial_IO_In_Progress_St) { 3991 /* Delay one bit per loop */ 3992 udelay((devpriv->serial_interval_ns + 999) / 1000); 3993 if (--count < 0) { 3994 printk 3995 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n"); 3996 err = -ETIME; 3997 goto Error; 3998 } 3999 } 4000 4001 /* Delay for last bit. This delay is absolutely necessary, because 4002 DIO_Serial_IO_In_Progress_St goes high one bit too early. */ 4003 udelay((devpriv->serial_interval_ns + 999) / 1000); 4004 4005 if (data_in != NULL) { 4006 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register); 4007#ifdef DEBUG_DIO 4008 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in); 4009#endif 4010 } 4011 4012Error: 4013 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); 4014 4015 return err; 4016} 4017 4018static int ni_serial_sw_readwrite8(struct comedi_device *dev, 4019 struct comedi_subdevice *s, 4020 unsigned char data_out, 4021 unsigned char *data_in) 4022{ 4023 unsigned char mask, input = 0; 4024 4025#ifdef DEBUG_DIO 4026 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out); 4027#endif 4028 4029 /* Wait for one bit before transfer */ 4030 udelay((devpriv->serial_interval_ns + 999) / 1000); 4031 4032 for (mask = 0x80; mask; mask >>= 1) { 4033 /* Output current bit; note that we cannot touch s->state 4034 because it is a per-subdevice field, and serial is 4035 a separate subdevice from DIO. */ 4036 devpriv->dio_output &= ~DIO_SDOUT; 4037 if (data_out & mask) { 4038 devpriv->dio_output |= DIO_SDOUT; 4039 } 4040 devpriv->stc_writew(dev, devpriv->dio_output, 4041 DIO_Output_Register); 4042 4043 /* Assert SDCLK (active low, inverted), wait for half of 4044 the delay, deassert SDCLK, and wait for the other half. */ 4045 devpriv->dio_control |= DIO_Software_Serial_Control; 4046 devpriv->stc_writew(dev, devpriv->dio_control, 4047 DIO_Control_Register); 4048 4049 udelay((devpriv->serial_interval_ns + 999) / 2000); 4050 4051 devpriv->dio_control &= ~DIO_Software_Serial_Control; 4052 devpriv->stc_writew(dev, devpriv->dio_control, 4053 DIO_Control_Register); 4054 4055 udelay((devpriv->serial_interval_ns + 999) / 2000); 4056 4057 /* Input current bit */ 4058 if (devpriv->stc_readw(dev, 4059 DIO_Parallel_Input_Register) & DIO_SDIN) 4060 { 4061/* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */ 4062 input |= mask; 4063 } 4064 } 4065#ifdef DEBUG_DIO 4066 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input); 4067#endif 4068 if (data_in) 4069 *data_in = input; 4070 4071 return 0; 4072} 4073 4074static void mio_common_detach(struct comedi_device *dev) 4075{ 4076 if (dev->private) { 4077 if (devpriv->counter_dev) { 4078 ni_gpct_device_destroy(devpriv->counter_dev); 4079 } 4080 } 4081 if (dev->subdevices && boardtype.has_8255) 4082 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV); 4083} 4084 4085static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s) 4086{ 4087 int i; 4088 4089 for (i = 0; i < s->n_chan; i++) { 4090 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, 4091 AO_Configuration_2_67xx); 4092 } 4093 ao_win_out(0x0, AO_Later_Single_Point_Updates); 4094} 4095 4096static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg) 4097{ 4098 unsigned stc_register; 4099 switch (reg) { 4100 case NITIO_G0_Autoincrement_Reg: 4101 stc_register = G_Autoincrement_Register(0); 4102 break; 4103 case NITIO_G1_Autoincrement_Reg: 4104 stc_register = G_Autoincrement_Register(1); 4105 break; 4106 case NITIO_G0_Command_Reg: 4107 stc_register = G_Command_Register(0); 4108 break; 4109 case NITIO_G1_Command_Reg: 4110 stc_register = G_Command_Register(1); 4111 break; 4112 case NITIO_G0_HW_Save_Reg: 4113 stc_register = G_HW_Save_Register(0); 4114 break; 4115 case NITIO_G1_HW_Save_Reg: 4116 stc_register = G_HW_Save_Register(1); 4117 break; 4118 case NITIO_G0_SW_Save_Reg: 4119 stc_register = G_Save_Register(0); 4120 break; 4121 case NITIO_G1_SW_Save_Reg: 4122 stc_register = G_Save_Register(1); 4123 break; 4124 case NITIO_G0_Mode_Reg: 4125 stc_register = G_Mode_Register(0); 4126 break; 4127 case NITIO_G1_Mode_Reg: 4128 stc_register = G_Mode_Register(1); 4129 break; 4130 case NITIO_G0_LoadA_Reg: 4131 stc_register = G_Load_A_Register(0); 4132 break; 4133 case NITIO_G1_LoadA_Reg: 4134 stc_register = G_Load_A_Register(1); 4135 break; 4136 case NITIO_G0_LoadB_Reg: 4137 stc_register = G_Load_B_Register(0); 4138 break; 4139 case NITIO_G1_LoadB_Reg: 4140 stc_register = G_Load_B_Register(1); 4141 break; 4142 case NITIO_G0_Input_Select_Reg: 4143 stc_register = G_Input_Select_Register(0); 4144 break; 4145 case NITIO_G1_Input_Select_Reg: 4146 stc_register = G_Input_Select_Register(1); 4147 break; 4148 case NITIO_G01_Status_Reg: 4149 stc_register = G_Status_Register; 4150 break; 4151 case NITIO_G01_Joint_Reset_Reg: 4152 stc_register = Joint_Reset_Register; 4153 break; 4154 case NITIO_G01_Joint_Status1_Reg: 4155 stc_register = Joint_Status_1_Register; 4156 break; 4157 case NITIO_G01_Joint_Status2_Reg: 4158 stc_register = Joint_Status_2_Register; 4159 break; 4160 case NITIO_G0_Interrupt_Acknowledge_Reg: 4161 stc_register = Interrupt_A_Ack_Register; 4162 break; 4163 case NITIO_G1_Interrupt_Acknowledge_Reg: 4164 stc_register = Interrupt_B_Ack_Register; 4165 break; 4166 case NITIO_G0_Status_Reg: 4167 stc_register = AI_Status_1_Register; 4168 break; 4169 case NITIO_G1_Status_Reg: 4170 stc_register = AO_Status_1_Register; 4171 break; 4172 case NITIO_G0_Interrupt_Enable_Reg: 4173 stc_register = Interrupt_A_Enable_Register; 4174 break; 4175 case NITIO_G1_Interrupt_Enable_Reg: 4176 stc_register = Interrupt_B_Enable_Register; 4177 break; 4178 default: 4179 printk("%s: unhandled register 0x%x in switch.\n", 4180 __func__, reg); 4181 BUG(); 4182 return 0; 4183 break; 4184 } 4185 return stc_register; 4186} 4187 4188static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, 4189 enum ni_gpct_register reg) 4190{ 4191 struct comedi_device *dev = counter->counter_dev->dev; 4192 unsigned stc_register; 4193 /* bits in the join reset register which are relevant to counters */ 4194 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset; 4195 static const unsigned gpct_interrupt_a_enable_mask = 4196 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable; 4197 static const unsigned gpct_interrupt_b_enable_mask = 4198 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable; 4199 4200 switch (reg) { 4201 /* m-series-only registers */ 4202 case NITIO_G0_Counting_Mode_Reg: 4203 ni_writew(bits, M_Offset_G0_Counting_Mode); 4204 break; 4205 case NITIO_G1_Counting_Mode_Reg: 4206 ni_writew(bits, M_Offset_G1_Counting_Mode); 4207 break; 4208 case NITIO_G0_Second_Gate_Reg: 4209 ni_writew(bits, M_Offset_G0_Second_Gate); 4210 break; 4211 case NITIO_G1_Second_Gate_Reg: 4212 ni_writew(bits, M_Offset_G1_Second_Gate); 4213 break; 4214 case NITIO_G0_DMA_Config_Reg: 4215 ni_writew(bits, M_Offset_G0_DMA_Config); 4216 break; 4217 case NITIO_G1_DMA_Config_Reg: 4218 ni_writew(bits, M_Offset_G1_DMA_Config); 4219 break; 4220 case NITIO_G0_ABZ_Reg: 4221 ni_writew(bits, M_Offset_G0_MSeries_ABZ); 4222 break; 4223 case NITIO_G1_ABZ_Reg: 4224 ni_writew(bits, M_Offset_G1_MSeries_ABZ); 4225 break; 4226 4227 /* 32 bit registers */ 4228 case NITIO_G0_LoadA_Reg: 4229 case NITIO_G1_LoadA_Reg: 4230 case NITIO_G0_LoadB_Reg: 4231 case NITIO_G1_LoadB_Reg: 4232 stc_register = ni_gpct_to_stc_register(reg); 4233 devpriv->stc_writel(dev, bits, stc_register); 4234 break; 4235 4236 /* 16 bit registers */ 4237 case NITIO_G0_Interrupt_Enable_Reg: 4238 BUG_ON(bits & ~gpct_interrupt_a_enable_mask); 4239 ni_set_bitfield(dev, Interrupt_A_Enable_Register, 4240 gpct_interrupt_a_enable_mask, bits); 4241 break; 4242 case NITIO_G1_Interrupt_Enable_Reg: 4243 BUG_ON(bits & ~gpct_interrupt_b_enable_mask); 4244 ni_set_bitfield(dev, Interrupt_B_Enable_Register, 4245 gpct_interrupt_b_enable_mask, bits); 4246 break; 4247 case NITIO_G01_Joint_Reset_Reg: 4248 BUG_ON(bits & ~gpct_joint_reset_mask); 4249 /* fall-through */ 4250 default: 4251 stc_register = ni_gpct_to_stc_register(reg); 4252 devpriv->stc_writew(dev, bits, stc_register); 4253 } 4254} 4255 4256static unsigned ni_gpct_read_register(struct ni_gpct *counter, 4257 enum ni_gpct_register reg) 4258{ 4259 struct comedi_device *dev = counter->counter_dev->dev; 4260 unsigned stc_register; 4261 switch (reg) { 4262 /* m-series only registers */ 4263 case NITIO_G0_DMA_Status_Reg: 4264 return ni_readw(M_Offset_G0_DMA_Status); 4265 break; 4266 case NITIO_G1_DMA_Status_Reg: 4267 return ni_readw(M_Offset_G1_DMA_Status); 4268 break; 4269 4270 /* 32 bit registers */ 4271 case NITIO_G0_HW_Save_Reg: 4272 case NITIO_G1_HW_Save_Reg: 4273 case NITIO_G0_SW_Save_Reg: 4274 case NITIO_G1_SW_Save_Reg: 4275 stc_register = ni_gpct_to_stc_register(reg); 4276 return devpriv->stc_readl(dev, stc_register); 4277 break; 4278 4279 /* 16 bit registers */ 4280 default: 4281 stc_register = ni_gpct_to_stc_register(reg); 4282 return devpriv->stc_readw(dev, stc_register); 4283 break; 4284 } 4285 return 0; 4286} 4287 4288static int ni_freq_out_insn_read(struct comedi_device *dev, 4289 struct comedi_subdevice *s, 4290 struct comedi_insn *insn, unsigned int *data) 4291{ 4292 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask; 4293 return 1; 4294} 4295 4296static int ni_freq_out_insn_write(struct comedi_device *dev, 4297 struct comedi_subdevice *s, 4298 struct comedi_insn *insn, unsigned int *data) 4299{ 4300 devpriv->clock_and_fout &= ~FOUT_Enable; 4301 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4302 Clock_and_FOUT_Register); 4303 devpriv->clock_and_fout &= ~FOUT_Divider_mask; 4304 devpriv->clock_and_fout |= FOUT_Divider(data[0]); 4305 devpriv->clock_and_fout |= FOUT_Enable; 4306 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4307 Clock_and_FOUT_Register); 4308 return insn->n; 4309} 4310 4311static int ni_set_freq_out_clock(struct comedi_device *dev, 4312 unsigned int clock_source) 4313{ 4314 switch (clock_source) { 4315 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC: 4316 devpriv->clock_and_fout &= ~FOUT_Timebase_Select; 4317 break; 4318 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC: 4319 devpriv->clock_and_fout |= FOUT_Timebase_Select; 4320 break; 4321 default: 4322 return -EINVAL; 4323 } 4324 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4325 Clock_and_FOUT_Register); 4326 return 3; 4327} 4328 4329static void ni_get_freq_out_clock(struct comedi_device *dev, 4330 unsigned int *clock_source, 4331 unsigned int *clock_period_ns) 4332{ 4333 if (devpriv->clock_and_fout & FOUT_Timebase_Select) { 4334 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC; 4335 *clock_period_ns = TIMEBASE_2_NS; 4336 } else { 4337 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC; 4338 *clock_period_ns = TIMEBASE_1_NS * 2; 4339 } 4340} 4341 4342static int ni_freq_out_insn_config(struct comedi_device *dev, 4343 struct comedi_subdevice *s, 4344 struct comedi_insn *insn, unsigned int *data) 4345{ 4346 switch (data[0]) { 4347 case INSN_CONFIG_SET_CLOCK_SRC: 4348 return ni_set_freq_out_clock(dev, data[1]); 4349 break; 4350 case INSN_CONFIG_GET_CLOCK_SRC: 4351 ni_get_freq_out_clock(dev, &data[1], &data[2]); 4352 return 3; 4353 default: 4354 break; 4355 } 4356 return -EINVAL; 4357} 4358 4359static int ni_alloc_private(struct comedi_device *dev) 4360{ 4361 int ret; 4362 4363 ret = alloc_private(dev, sizeof(struct ni_private)); 4364 if (ret < 0) 4365 return ret; 4366 4367 spin_lock_init(&devpriv->window_lock); 4368 spin_lock_init(&devpriv->soft_reg_copy_lock); 4369 spin_lock_init(&devpriv->mite_channel_lock); 4370 4371 return 0; 4372}; 4373 4374static int ni_E_init(struct comedi_device *dev, struct comedi_devconfig *it) 4375{ 4376 struct comedi_subdevice *s; 4377 unsigned j; 4378 enum ni_gpct_variant counter_variant; 4379 4380 if (boardtype.n_aochan > MAX_N_AO_CHAN) { 4381 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n"); 4382 return -EINVAL; 4383 } 4384 4385 if (alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0) 4386 return -ENOMEM; 4387 4388 /* analog input subdevice */ 4389 4390 s = dev->subdevices + NI_AI_SUBDEV; 4391 dev->read_subdev = s; 4392 if (boardtype.n_adchan) { 4393 s->type = COMEDI_SUBD_AI; 4394 s->subdev_flags = 4395 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ; 4396 if (boardtype.reg_type != ni_reg_611x) 4397 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; 4398 if (boardtype.adbits > 16) 4399 s->subdev_flags |= SDF_LSAMPL; 4400 if (boardtype.reg_type & ni_reg_m_series_mask) 4401 s->subdev_flags |= SDF_SOFT_CALIBRATED; 4402 s->n_chan = boardtype.n_adchan; 4403 s->len_chanlist = 512; 4404 s->maxdata = (1 << boardtype.adbits) - 1; 4405 s->range_table = ni_range_lkup[boardtype.gainlkup]; 4406 s->insn_read = &ni_ai_insn_read; 4407 s->insn_config = &ni_ai_insn_config; 4408 s->do_cmdtest = &ni_ai_cmdtest; 4409 s->do_cmd = &ni_ai_cmd; 4410 s->cancel = &ni_ai_reset; 4411 s->poll = &ni_ai_poll; 4412 s->munge = &ni_ai_munge; 4413#ifdef PCIDMA 4414 s->async_dma_dir = DMA_FROM_DEVICE; 4415#endif 4416 } else { 4417 s->type = COMEDI_SUBD_UNUSED; 4418 } 4419 4420 /* analog output subdevice */ 4421 4422 s = dev->subdevices + NI_AO_SUBDEV; 4423 if (boardtype.n_aochan) { 4424 s->type = COMEDI_SUBD_AO; 4425 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; 4426 if (boardtype.reg_type & ni_reg_m_series_mask) 4427 s->subdev_flags |= SDF_SOFT_CALIBRATED; 4428 s->n_chan = boardtype.n_aochan; 4429 s->maxdata = (1 << boardtype.aobits) - 1; 4430 s->range_table = boardtype.ao_range_table; 4431 s->insn_read = &ni_ao_insn_read; 4432 if (boardtype.reg_type & ni_reg_6xxx_mask) { 4433 s->insn_write = &ni_ao_insn_write_671x; 4434 } else { 4435 s->insn_write = &ni_ao_insn_write; 4436 } 4437 s->insn_config = &ni_ao_insn_config; 4438#ifdef PCIDMA 4439 if (boardtype.n_aochan) { 4440 s->async_dma_dir = DMA_TO_DEVICE; 4441#else 4442 if (boardtype.ao_fifo_depth) { 4443#endif 4444 dev->write_subdev = s; 4445 s->subdev_flags |= SDF_CMD_WRITE; 4446 s->do_cmd = &ni_ao_cmd; 4447 s->do_cmdtest = &ni_ao_cmdtest; 4448 s->len_chanlist = boardtype.n_aochan; 4449 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) 4450 s->munge = ni_ao_munge; 4451 } 4452 s->cancel = &ni_ao_reset; 4453 } else { 4454 s->type = COMEDI_SUBD_UNUSED; 4455 } 4456 if ((boardtype.reg_type & ni_reg_67xx_mask)) 4457 init_ao_67xx(dev, s); 4458 4459 /* digital i/o subdevice */ 4460 4461 s = dev->subdevices + NI_DIO_SUBDEV; 4462 s->type = COMEDI_SUBD_DIO; 4463 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 4464 s->maxdata = 1; 4465 s->io_bits = 0; /* all bits input */ 4466 s->range_table = &range_digital; 4467 s->n_chan = boardtype.num_p0_dio_channels; 4468 if (boardtype.reg_type & ni_reg_m_series_mask) { 4469 s->subdev_flags |= 4470 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ; 4471 s->insn_bits = &ni_m_series_dio_insn_bits; 4472 s->insn_config = &ni_m_series_dio_insn_config; 4473 s->do_cmd = &ni_cdio_cmd; 4474 s->do_cmdtest = &ni_cdio_cmdtest; 4475 s->cancel = &ni_cdio_cancel; 4476 s->async_dma_dir = DMA_BIDIRECTIONAL; 4477 s->len_chanlist = s->n_chan; 4478 4479 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command); 4480 ni_writel(s->io_bits, M_Offset_DIO_Direction); 4481 } else { 4482 s->insn_bits = &ni_dio_insn_bits; 4483 s->insn_config = &ni_dio_insn_config; 4484 devpriv->dio_control = DIO_Pins_Dir(s->io_bits); 4485 ni_writew(devpriv->dio_control, DIO_Control_Register); 4486 } 4487 4488 /* 8255 device */ 4489 s = dev->subdevices + NI_8255_DIO_SUBDEV; 4490 if (boardtype.has_8255) { 4491 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev); 4492 } else { 4493 s->type = COMEDI_SUBD_UNUSED; 4494 } 4495 4496 /* formerly general purpose counter/timer device, but no longer used */ 4497 s = dev->subdevices + NI_UNUSED_SUBDEV; 4498 s->type = COMEDI_SUBD_UNUSED; 4499 4500 /* calibration subdevice -- ai and ao */ 4501 s = dev->subdevices + NI_CALIBRATION_SUBDEV; 4502 s->type = COMEDI_SUBD_CALIB; 4503 if (boardtype.reg_type & ni_reg_m_series_mask) { 4504 /* internal PWM analog output used for AI nonlinearity calibration */ 4505 s->subdev_flags = SDF_INTERNAL; 4506 s->insn_config = &ni_m_series_pwm_config; 4507 s->n_chan = 1; 4508 s->maxdata = 0; 4509 ni_writel(0x0, M_Offset_Cal_PWM); 4510 } else if (boardtype.reg_type == ni_reg_6143) { 4511 /* internal PWM analog output used for AI nonlinearity calibration */ 4512 s->subdev_flags = SDF_INTERNAL; 4513 s->insn_config = &ni_6143_pwm_config; 4514 s->n_chan = 1; 4515 s->maxdata = 0; 4516 } else { 4517 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL; 4518 s->insn_read = &ni_calib_insn_read; 4519 s->insn_write = &ni_calib_insn_write; 4520 caldac_setup(dev, s); 4521 } 4522 4523 /* EEPROM */ 4524 s = dev->subdevices + NI_EEPROM_SUBDEV; 4525 s->type = COMEDI_SUBD_MEMORY; 4526 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 4527 s->maxdata = 0xff; 4528 if (boardtype.reg_type & ni_reg_m_series_mask) { 4529 s->n_chan = M_SERIES_EEPROM_SIZE; 4530 s->insn_read = &ni_m_series_eeprom_insn_read; 4531 } else { 4532 s->n_chan = 512; 4533 s->insn_read = &ni_eeprom_insn_read; 4534 } 4535 4536 /* PFI */ 4537 s = dev->subdevices + NI_PFI_DIO_SUBDEV; 4538 s->type = COMEDI_SUBD_DIO; 4539 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 4540 if (boardtype.reg_type & ni_reg_m_series_mask) { 4541 unsigned i; 4542 s->n_chan = 16; 4543 ni_writew(s->state, M_Offset_PFI_DO); 4544 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { 4545 ni_writew(devpriv->pfi_output_select_reg[i], 4546 M_Offset_PFI_Output_Select(i + 1)); 4547 } 4548 } else { 4549 s->n_chan = 10; 4550 } 4551 s->maxdata = 1; 4552 if (boardtype.reg_type & ni_reg_m_series_mask) { 4553 s->insn_bits = &ni_pfi_insn_bits; 4554 } 4555 s->insn_config = &ni_pfi_insn_config; 4556 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0); 4557 4558 /* cs5529 calibration adc */ 4559 s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV; 4560 if (boardtype.reg_type & ni_reg_67xx_mask) { 4561 s->type = COMEDI_SUBD_AI; 4562 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; 4563 /* one channel for each analog output channel */ 4564 s->n_chan = boardtype.n_aochan; 4565 s->maxdata = (1 << 16) - 1; 4566 s->range_table = &range_unknown; 4567 s->insn_read = cs5529_ai_insn_read; 4568 s->insn_config = NULL; 4569 init_cs5529(dev); 4570 } else { 4571 s->type = COMEDI_SUBD_UNUSED; 4572 } 4573 4574 /* Serial */ 4575 s = dev->subdevices + NI_SERIAL_SUBDEV; 4576 s->type = COMEDI_SUBD_SERIAL; 4577 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 4578 s->n_chan = 1; 4579 s->maxdata = 0xff; 4580 s->insn_config = ni_serial_insn_config; 4581 devpriv->serial_interval_ns = 0; 4582 devpriv->serial_hw_mode = 0; 4583 4584 /* RTSI */ 4585 s = dev->subdevices + NI_RTSI_SUBDEV; 4586 s->type = COMEDI_SUBD_DIO; 4587 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 4588 s->n_chan = 8; 4589 s->maxdata = 1; 4590 s->insn_bits = ni_rtsi_insn_bits; 4591 s->insn_config = ni_rtsi_insn_config; 4592 ni_rtsi_init(dev); 4593 4594 if (boardtype.reg_type & ni_reg_m_series_mask) { 4595 counter_variant = ni_gpct_variant_m_series; 4596 } else { 4597 counter_variant = ni_gpct_variant_e_series; 4598 } 4599 devpriv->counter_dev = ni_gpct_device_construct(dev, 4600 &ni_gpct_write_register, 4601 &ni_gpct_read_register, 4602 counter_variant, 4603 NUM_GPCT); 4604 /* General purpose counters */ 4605 for (j = 0; j < NUM_GPCT; ++j) { 4606 s = dev->subdevices + NI_GPCT_SUBDEV(j); 4607 s->type = COMEDI_SUBD_COUNTER; 4608 s->subdev_flags = 4609 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ 4610 /* | SDF_CMD_WRITE */ ; 4611 s->n_chan = 3; 4612 if (boardtype.reg_type & ni_reg_m_series_mask) 4613 s->maxdata = 0xffffffff; 4614 else 4615 s->maxdata = 0xffffff; 4616 s->insn_read = &ni_gpct_insn_read; 4617 s->insn_write = &ni_gpct_insn_write; 4618 s->insn_config = &ni_gpct_insn_config; 4619 s->do_cmd = &ni_gpct_cmd; 4620 s->len_chanlist = 1; 4621 s->do_cmdtest = &ni_gpct_cmdtest; 4622 s->cancel = &ni_gpct_cancel; 4623 s->async_dma_dir = DMA_BIDIRECTIONAL; 4624 s->private = &devpriv->counter_dev->counters[j]; 4625 4626 devpriv->counter_dev->counters[j].chip_index = 0; 4627 devpriv->counter_dev->counters[j].counter_index = j; 4628 ni_tio_init_counter(&devpriv->counter_dev->counters[j]); 4629 } 4630 4631 /* Frequency output */ 4632 s = dev->subdevices + NI_FREQ_OUT_SUBDEV; 4633 s->type = COMEDI_SUBD_COUNTER; 4634 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 4635 s->n_chan = 1; 4636 s->maxdata = 0xf; 4637 s->insn_read = &ni_freq_out_insn_read; 4638 s->insn_write = &ni_freq_out_insn_write; 4639 s->insn_config = &ni_freq_out_insn_config; 4640 4641 /* ai configuration */ 4642 ni_ai_reset(dev, dev->subdevices + NI_AI_SUBDEV); 4643 if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) { 4644 /* BEAM is this needed for PCI-6143 ?? */ 4645 devpriv->clock_and_fout = 4646 Slow_Internal_Time_Divide_By_2 | 4647 Slow_Internal_Timebase | 4648 Clock_To_Board_Divide_By_2 | 4649 Clock_To_Board | 4650 AI_Output_Divide_By_2 | AO_Output_Divide_By_2; 4651 } else { 4652 devpriv->clock_and_fout = 4653 Slow_Internal_Time_Divide_By_2 | 4654 Slow_Internal_Timebase | 4655 Clock_To_Board_Divide_By_2 | Clock_To_Board; 4656 } 4657 devpriv->stc_writew(dev, devpriv->clock_and_fout, 4658 Clock_and_FOUT_Register); 4659 4660 /* analog output configuration */ 4661 ni_ao_reset(dev, dev->subdevices + NI_AO_SUBDEV); 4662 4663 if (dev->irq) { 4664 devpriv->stc_writew(dev, 4665 (IRQ_POLARITY ? Interrupt_Output_Polarity : 4666 0) | (Interrupt_Output_On_3_Pins & 0) | 4667 Interrupt_A_Enable | Interrupt_B_Enable | 4668 Interrupt_A_Output_Select(interrupt_pin 4669 (dev->irq)) | 4670 Interrupt_B_Output_Select(interrupt_pin 4671 (dev->irq)), 4672 Interrupt_Control_Register); 4673 } 4674 4675 /* DMA setup */ 4676 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); 4677 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); 4678 4679 if (boardtype.reg_type & ni_reg_6xxx_mask) { 4680 ni_writeb(0, Magic_611x); 4681 } else if (boardtype.reg_type & ni_reg_m_series_mask) { 4682 int channel; 4683 for (channel = 0; channel < boardtype.n_aochan; ++channel) { 4684 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel)); 4685 ni_writeb(0x0, 4686 M_Offset_AO_Reference_Attenuation(channel)); 4687 } 4688 ni_writeb(0x0, M_Offset_AO_Calibration); 4689 } 4690 4691 printk("\n"); 4692 return 0; 4693} 4694 4695static int ni_8255_callback(int dir, int port, int data, unsigned long arg) 4696{ 4697 struct comedi_device *dev = (struct comedi_device *)arg; 4698 4699 if (dir) { 4700 ni_writeb(data, Port_A + 2 * port); 4701 return 0; 4702 } else { 4703 return ni_readb(Port_A + 2 * port); 4704 } 4705} 4706 4707/* 4708 presents the EEPROM as a subdevice 4709*/ 4710 4711static int ni_eeprom_insn_read(struct comedi_device *dev, 4712 struct comedi_subdevice *s, 4713 struct comedi_insn *insn, unsigned int *data) 4714{ 4715 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); 4716 4717 return 1; 4718} 4719 4720/* 4721 reads bytes out of eeprom 4722*/ 4723 4724static int ni_read_eeprom(struct comedi_device *dev, int addr) 4725{ 4726 int bit; 4727 int bitstring; 4728 4729 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); 4730 ni_writeb(0x04, Serial_Command); 4731 for (bit = 0x8000; bit; bit >>= 1) { 4732 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0), 4733 Serial_Command); 4734 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0), 4735 Serial_Command); 4736 } 4737 bitstring = 0; 4738 for (bit = 0x80; bit; bit >>= 1) { 4739 ni_writeb(0x04, Serial_Command); 4740 ni_writeb(0x05, Serial_Command); 4741 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0); 4742 } 4743 ni_writeb(0x00, Serial_Command); 4744 4745 return bitstring; 4746} 4747 4748static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, 4749 struct comedi_subdevice *s, 4750 struct comedi_insn *insn, 4751 unsigned int *data) 4752{ 4753 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; 4754 4755 return 1; 4756} 4757 4758static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data) 4759{ 4760 data[1] = devpriv->pwm_up_count * devpriv->clock_ns; 4761 data[2] = devpriv->pwm_down_count * devpriv->clock_ns; 4762 return 3; 4763} 4764 4765static int ni_m_series_pwm_config(struct comedi_device *dev, 4766 struct comedi_subdevice *s, 4767 struct comedi_insn *insn, unsigned int *data) 4768{ 4769 unsigned up_count, down_count; 4770 switch (data[0]) { 4771 case INSN_CONFIG_PWM_OUTPUT: 4772 switch (data[1]) { 4773 case TRIG_ROUND_NEAREST: 4774 up_count = 4775 (data[2] + 4776 devpriv->clock_ns / 2) / devpriv->clock_ns; 4777 break; 4778 case TRIG_ROUND_DOWN: 4779 up_count = data[2] / devpriv->clock_ns; 4780 break; 4781 case TRIG_ROUND_UP: 4782 up_count = 4783 (data[2] + devpriv->clock_ns - 4784 1) / devpriv->clock_ns; 4785 break; 4786 default: 4787 return -EINVAL; 4788 break; 4789 } 4790 switch (data[3]) { 4791 case TRIG_ROUND_NEAREST: 4792 down_count = 4793 (data[4] + 4794 devpriv->clock_ns / 2) / devpriv->clock_ns; 4795 break; 4796 case TRIG_ROUND_DOWN: 4797 down_count = data[4] / devpriv->clock_ns; 4798 break; 4799 case TRIG_ROUND_UP: 4800 down_count = 4801 (data[4] + devpriv->clock_ns - 4802 1) / devpriv->clock_ns; 4803 break; 4804 default: 4805 return -EINVAL; 4806 break; 4807 } 4808 if (up_count * devpriv->clock_ns != data[2] || 4809 down_count * devpriv->clock_ns != data[4]) { 4810 data[2] = up_count * devpriv->clock_ns; 4811 data[4] = down_count * devpriv->clock_ns; 4812 return -EAGAIN; 4813 } 4814 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | 4815 MSeries_Cal_PWM_Low_Time_Bits(down_count), 4816 M_Offset_Cal_PWM); 4817 devpriv->pwm_up_count = up_count; 4818 devpriv->pwm_down_count = down_count; 4819 return 5; 4820 break; 4821 case INSN_CONFIG_GET_PWM_OUTPUT: 4822 return ni_get_pwm_config(dev, data); 4823 break; 4824 default: 4825 return -EINVAL; 4826 break; 4827 } 4828 return 0; 4829} 4830 4831static int ni_6143_pwm_config(struct comedi_device *dev, 4832 struct comedi_subdevice *s, 4833 struct comedi_insn *insn, unsigned int *data) 4834{ 4835 unsigned up_count, down_count; 4836 switch (data[0]) { 4837 case INSN_CONFIG_PWM_OUTPUT: 4838 switch (data[1]) { 4839 case TRIG_ROUND_NEAREST: 4840 up_count = 4841 (data[2] + 4842 devpriv->clock_ns / 2) / devpriv->clock_ns; 4843 break; 4844 case TRIG_ROUND_DOWN: 4845 up_count = data[2] / devpriv->clock_ns; 4846 break; 4847 case TRIG_ROUND_UP: 4848 up_count = 4849 (data[2] + devpriv->clock_ns - 4850 1) / devpriv->clock_ns; 4851 break; 4852 default: 4853 return -EINVAL; 4854 break; 4855 } 4856 switch (data[3]) { 4857 case TRIG_ROUND_NEAREST: 4858 down_count = 4859 (data[4] + 4860 devpriv->clock_ns / 2) / devpriv->clock_ns; 4861 break; 4862 case TRIG_ROUND_DOWN: 4863 down_count = data[4] / devpriv->clock_ns; 4864 break; 4865 case TRIG_ROUND_UP: 4866 down_count = 4867 (data[4] + devpriv->clock_ns - 4868 1) / devpriv->clock_ns; 4869 break; 4870 default: 4871 return -EINVAL; 4872 break; 4873 } 4874 if (up_count * devpriv->clock_ns != data[2] || 4875 down_count * devpriv->clock_ns != data[4]) { 4876 data[2] = up_count * devpriv->clock_ns; 4877 data[4] = down_count * devpriv->clock_ns; 4878 return -EAGAIN; 4879 } 4880 ni_writel(up_count, Calibration_HighTime_6143); 4881 devpriv->pwm_up_count = up_count; 4882 ni_writel(down_count, Calibration_LowTime_6143); 4883 devpriv->pwm_down_count = down_count; 4884 return 5; 4885 break; 4886 case INSN_CONFIG_GET_PWM_OUTPUT: 4887 return ni_get_pwm_config(dev, data); 4888 default: 4889 return -EINVAL; 4890 break; 4891 } 4892 return 0; 4893} 4894 4895static void ni_write_caldac(struct comedi_device *dev, int addr, int val); 4896/* 4897 calibration subdevice 4898*/ 4899static int ni_calib_insn_write(struct comedi_device *dev, 4900 struct comedi_subdevice *s, 4901 struct comedi_insn *insn, unsigned int *data) 4902{ 4903 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]); 4904 4905 return 1; 4906} 4907 4908static int ni_calib_insn_read(struct comedi_device *dev, 4909 struct comedi_subdevice *s, 4910 struct comedi_insn *insn, unsigned int *data) 4911{ 4912 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; 4913 4914 return 1; 4915} 4916 4917static int pack_mb88341(int addr, int val, int *bitstring); 4918static int pack_dac8800(int addr, int val, int *bitstring); 4919static int pack_dac8043(int addr, int val, int *bitstring); 4920static int pack_ad8522(int addr, int val, int *bitstring); 4921static int pack_ad8804(int addr, int val, int *bitstring); 4922static int pack_ad8842(int addr, int val, int *bitstring); 4923 4924struct caldac_struct { 4925 int n_chans; 4926 int n_bits; 4927 int (*packbits) (int, int, int *); 4928}; 4929 4930static struct caldac_struct caldacs[] = { 4931 [mb88341] = {12, 8, pack_mb88341}, 4932 [dac8800] = {8, 8, pack_dac8800}, 4933 [dac8043] = {1, 12, pack_dac8043}, 4934 [ad8522] = {2, 12, pack_ad8522}, 4935 [ad8804] = {12, 8, pack_ad8804}, 4936 [ad8842] = {8, 8, pack_ad8842}, 4937 [ad8804_debug] = {16, 8, pack_ad8804}, 4938}; 4939 4940static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) 4941{ 4942 int i, j; 4943 int n_dacs; 4944 int n_chans = 0; 4945 int n_bits; 4946 int diffbits = 0; 4947 int type; 4948 int chan; 4949 4950 type = boardtype.caldac[0]; 4951 if (type == caldac_none) 4952 return; 4953 n_bits = caldacs[type].n_bits; 4954 for (i = 0; i < 3; i++) { 4955 type = boardtype.caldac[i]; 4956 if (type == caldac_none) 4957 break; 4958 if (caldacs[type].n_bits != n_bits) 4959 diffbits = 1; 4960 n_chans += caldacs[type].n_chans; 4961 } 4962 n_dacs = i; 4963 s->n_chan = n_chans; 4964 4965 if (diffbits) { 4966 unsigned int *maxdata_list; 4967 4968 if (n_chans > MAX_N_CALDACS) { 4969 printk("BUG! MAX_N_CALDACS too small\n"); 4970 } 4971 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list; 4972 chan = 0; 4973 for (i = 0; i < n_dacs; i++) { 4974 type = boardtype.caldac[i]; 4975 for (j = 0; j < caldacs[type].n_chans; j++) { 4976 maxdata_list[chan] = 4977 (1 << caldacs[type].n_bits) - 1; 4978 chan++; 4979 } 4980 } 4981 4982 for (chan = 0; chan < s->n_chan; chan++) 4983 ni_write_caldac(dev, i, s->maxdata_list[i] / 2); 4984 } else { 4985 type = boardtype.caldac[0]; 4986 s->maxdata = (1 << caldacs[type].n_bits) - 1; 4987 4988 for (chan = 0; chan < s->n_chan; chan++) 4989 ni_write_caldac(dev, i, s->maxdata / 2); 4990 } 4991} 4992 4993static void ni_write_caldac(struct comedi_device *dev, int addr, int val) 4994{ 4995 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0; 4996 int i; 4997 int type; 4998 4999 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */ 5000 if (devpriv->caldacs[addr] == val) 5001 return; 5002 devpriv->caldacs[addr] = val; 5003 5004 for (i = 0; i < 3; i++) { 5005 type = boardtype.caldac[i]; 5006 if (type == caldac_none) 5007 break; 5008 if (addr < caldacs[type].n_chans) { 5009 bits = caldacs[type].packbits(addr, val, &bitstring); 5010 loadbit = SerDacLd(i); 5011 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */ 5012 break; 5013 } 5014 addr -= caldacs[type].n_chans; 5015 } 5016 5017 for (bit = 1 << (bits - 1); bit; bit >>= 1) { 5018 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command); 5019 udelay(1); 5020 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command); 5021 udelay(1); 5022 } 5023 ni_writeb(loadbit, Serial_Command); 5024 udelay(1); 5025 ni_writeb(0, Serial_Command); 5026} 5027 5028static int pack_mb88341(int addr, int val, int *bitstring) 5029{ 5030 /* 5031 Fujitsu MB 88341 5032 Note that address bits are reversed. Thanks to 5033 Ingo Keen for noticing this. 5034 5035 Note also that the 88341 expects address values from 5036 1-12, whereas we use channel numbers 0-11. The NI 5037 docs use 1-12, also, so be careful here. 5038 */ 5039 addr++; 5040 *bitstring = ((addr & 0x1) << 11) | 5041 ((addr & 0x2) << 9) | 5042 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff); 5043 return 12; 5044} 5045 5046static int pack_dac8800(int addr, int val, int *bitstring) 5047{ 5048 *bitstring = ((addr & 0x7) << 8) | (val & 0xff); 5049 return 11; 5050} 5051 5052static int pack_dac8043(int addr, int val, int *bitstring) 5053{ 5054 *bitstring = val & 0xfff; 5055 return 12; 5056} 5057 5058static int pack_ad8522(int addr, int val, int *bitstring) 5059{ 5060 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000); 5061 return 16; 5062} 5063 5064static int pack_ad8804(int addr, int val, int *bitstring) 5065{ 5066 *bitstring = ((addr & 0xf) << 8) | (val & 0xff); 5067 return 12; 5068} 5069 5070static int pack_ad8842(int addr, int val, int *bitstring) 5071{ 5072 *bitstring = ((addr + 1) << 8) | (val & 0xff); 5073 return 12; 5074} 5075 5076 5077static int ni_gpct_insn_config(struct comedi_device *dev, 5078 struct comedi_subdevice *s, 5079 struct comedi_insn *insn, unsigned int *data) 5080{ 5081 struct ni_gpct *counter = s->private; 5082 return ni_tio_insn_config(counter, insn, data); 5083} 5084 5085static int ni_gpct_insn_read(struct comedi_device *dev, 5086 struct comedi_subdevice *s, 5087 struct comedi_insn *insn, unsigned int *data) 5088{ 5089 struct ni_gpct *counter = s->private; 5090 return ni_tio_rinsn(counter, insn, data); 5091} 5092 5093static int ni_gpct_insn_write(struct comedi_device *dev, 5094 struct comedi_subdevice *s, 5095 struct comedi_insn *insn, unsigned int *data) 5096{ 5097 struct ni_gpct *counter = s->private; 5098 return ni_tio_winsn(counter, insn, data); 5099} 5100 5101static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 5102{ 5103 int retval; 5104#ifdef PCIDMA 5105 struct ni_gpct *counter = s->private; 5106/* const struct comedi_cmd *cmd = &s->async->cmd; */ 5107 5108 retval = ni_request_gpct_mite_channel(dev, counter->counter_index, 5109 COMEDI_INPUT); 5110 if (retval) { 5111 comedi_error(dev, 5112 "no dma channel available for use by counter"); 5113 return retval; 5114 } 5115 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL); 5116 ni_e_series_enable_second_irq(dev, counter->counter_index, 1); 5117 retval = ni_tio_cmd(counter, s->async); 5118#else 5119 retval = -ENOTSUPP; 5120#endif 5121 return retval; 5122} 5123 5124static int ni_gpct_cmdtest(struct comedi_device *dev, 5125 struct comedi_subdevice *s, struct comedi_cmd *cmd) 5126{ 5127#ifdef PCIDMA 5128 struct ni_gpct *counter = s->private; 5129 5130 return ni_tio_cmdtest(counter, cmd); 5131#else 5132 return -ENOTSUPP; 5133#endif 5134} 5135 5136static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 5137{ 5138#ifdef PCIDMA 5139 struct ni_gpct *counter = s->private; 5140 int retval; 5141 5142 retval = ni_tio_cancel(counter); 5143 ni_e_series_enable_second_irq(dev, counter->counter_index, 0); 5144 ni_release_gpct_mite_channel(dev, counter->counter_index); 5145 return retval; 5146#else 5147 return 0; 5148#endif 5149} 5150 5151/* 5152 * 5153 * Programmable Function Inputs 5154 * 5155 */ 5156 5157static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan, 5158 unsigned source) 5159{ 5160 unsigned pfi_reg_index; 5161 unsigned array_offset; 5162 if ((source & 0x1f) != source) 5163 return -EINVAL; 5164 pfi_reg_index = 1 + chan / 3; 5165 array_offset = pfi_reg_index - 1; 5166 devpriv->pfi_output_select_reg[array_offset] &= 5167 ~MSeries_PFI_Output_Select_Mask(chan); 5168 devpriv->pfi_output_select_reg[array_offset] |= 5169 MSeries_PFI_Output_Select_Bits(chan, source); 5170 ni_writew(devpriv->pfi_output_select_reg[array_offset], 5171 M_Offset_PFI_Output_Select(pfi_reg_index)); 5172 return 2; 5173} 5174 5175static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan, 5176 unsigned source) 5177{ 5178 /* pre-m-series boards have fixed signals on pfi pins */ 5179 if (source != ni_old_get_pfi_routing(dev, chan)) 5180 return -EINVAL; 5181 return 2; 5182} 5183 5184static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, 5185 unsigned source) 5186{ 5187 if (boardtype.reg_type & ni_reg_m_series_mask) 5188 return ni_m_series_set_pfi_routing(dev, chan, source); 5189 else 5190 return ni_old_set_pfi_routing(dev, chan, source); 5191} 5192 5193static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, 5194 unsigned chan) 5195{ 5196 const unsigned array_offset = chan / 3; 5197 return MSeries_PFI_Output_Select_Source(chan, 5198 devpriv-> 5199 pfi_output_select_reg 5200 [array_offset]); 5201} 5202 5203static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan) 5204{ 5205 /* pre-m-series boards have fixed signals on pfi pins */ 5206 switch (chan) { 5207 case 0: 5208 return NI_PFI_OUTPUT_AI_START1; 5209 break; 5210 case 1: 5211 return NI_PFI_OUTPUT_AI_START2; 5212 break; 5213 case 2: 5214 return NI_PFI_OUTPUT_AI_CONVERT; 5215 break; 5216 case 3: 5217 return NI_PFI_OUTPUT_G_SRC1; 5218 break; 5219 case 4: 5220 return NI_PFI_OUTPUT_G_GATE1; 5221 break; 5222 case 5: 5223 return NI_PFI_OUTPUT_AO_UPDATE_N; 5224 break; 5225 case 6: 5226 return NI_PFI_OUTPUT_AO_START1; 5227 break; 5228 case 7: 5229 return NI_PFI_OUTPUT_AI_START_PULSE; 5230 break; 5231 case 8: 5232 return NI_PFI_OUTPUT_G_SRC0; 5233 break; 5234 case 9: 5235 return NI_PFI_OUTPUT_G_GATE0; 5236 break; 5237 default: 5238 printk("%s: bug, unhandled case in switch.\n", __func__); 5239 break; 5240 } 5241 return 0; 5242} 5243 5244static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) 5245{ 5246 if (boardtype.reg_type & ni_reg_m_series_mask) 5247 return ni_m_series_get_pfi_routing(dev, chan); 5248 else 5249 return ni_old_get_pfi_routing(dev, chan); 5250} 5251 5252static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel, 5253 enum ni_pfi_filter_select filter) 5254{ 5255 unsigned bits; 5256 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) { 5257 return -ENOTSUPP; 5258 } 5259 bits = ni_readl(M_Offset_PFI_Filter); 5260 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel); 5261 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter); 5262 ni_writel(bits, M_Offset_PFI_Filter); 5263 return 0; 5264} 5265 5266static int ni_pfi_insn_bits(struct comedi_device *dev, 5267 struct comedi_subdevice *s, 5268 struct comedi_insn *insn, unsigned int *data) 5269{ 5270 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) { 5271 return -ENOTSUPP; 5272 } 5273 if (data[0]) { 5274 s->state &= ~data[0]; 5275 s->state |= (data[0] & data[1]); 5276 ni_writew(s->state, M_Offset_PFI_DO); 5277 } 5278 data[1] = ni_readw(M_Offset_PFI_DI); 5279 return 2; 5280} 5281 5282static int ni_pfi_insn_config(struct comedi_device *dev, 5283 struct comedi_subdevice *s, 5284 struct comedi_insn *insn, unsigned int *data) 5285{ 5286 unsigned int chan; 5287 5288 if (insn->n < 1) 5289 return -EINVAL; 5290 5291 chan = CR_CHAN(insn->chanspec); 5292 5293 switch (data[0]) { 5294 case COMEDI_OUTPUT: 5295 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1); 5296 break; 5297 case COMEDI_INPUT: 5298 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0); 5299 break; 5300 case INSN_CONFIG_DIO_QUERY: 5301 data[1] = 5302 (devpriv->io_bidirection_pin_reg & (1 << chan)) ? 5303 COMEDI_OUTPUT : COMEDI_INPUT; 5304 return 0; 5305 break; 5306 case INSN_CONFIG_SET_ROUTING: 5307 return ni_set_pfi_routing(dev, chan, data[1]); 5308 break; 5309 case INSN_CONFIG_GET_ROUTING: 5310 data[1] = ni_get_pfi_routing(dev, chan); 5311 break; 5312 case INSN_CONFIG_FILTER: 5313 return ni_config_filter(dev, chan, data[1]); 5314 break; 5315 default: 5316 return -EINVAL; 5317 } 5318 return 0; 5319} 5320 5321/* 5322 * 5323 * NI RTSI Bus Functions 5324 * 5325 */ 5326static void ni_rtsi_init(struct comedi_device *dev) 5327{ 5328 /* Initialises the RTSI bus signal switch to a default state */ 5329 5330 /* Set clock mode to internal */ 5331 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit; 5332 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) { 5333 printk("ni_set_master_clock failed, bug?"); 5334 } 5335 /* default internal lines routing to RTSI bus lines */ 5336 devpriv->rtsi_trig_a_output_reg = 5337 RTSI_Trig_Output_Bits(0, 5338 NI_RTSI_OUTPUT_ADR_START1) | 5339 RTSI_Trig_Output_Bits(1, 5340 NI_RTSI_OUTPUT_ADR_START2) | 5341 RTSI_Trig_Output_Bits(2, 5342 NI_RTSI_OUTPUT_SCLKG) | 5343 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN); 5344 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg, 5345 RTSI_Trig_A_Output_Register); 5346 devpriv->rtsi_trig_b_output_reg = 5347 RTSI_Trig_Output_Bits(4, 5348 NI_RTSI_OUTPUT_DA_START1) | 5349 RTSI_Trig_Output_Bits(5, 5350 NI_RTSI_OUTPUT_G_SRC0) | 5351 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0); 5352 if (boardtype.reg_type & ni_reg_m_series_mask) 5353 devpriv->rtsi_trig_b_output_reg |= 5354 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC); 5355 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg, 5356 RTSI_Trig_B_Output_Register); 5357 5358/* 5359* Sets the source and direction of the 4 on board lines 5360* devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register); 5361*/ 5362} 5363 5364static int ni_rtsi_insn_bits(struct comedi_device *dev, 5365 struct comedi_subdevice *s, 5366 struct comedi_insn *insn, unsigned int *data) 5367{ 5368 if (insn->n != 2) 5369 return -EINVAL; 5370 5371 data[1] = 0; 5372 5373 return 2; 5374} 5375 5376/* Find best multiplier/divider to try and get the PLL running at 80 MHz 5377 * given an arbitrary frequency input clock */ 5378static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, 5379 unsigned *freq_divider, 5380 unsigned *freq_multiplier, 5381 unsigned *actual_period_ns) 5382{ 5383 unsigned div; 5384 unsigned best_div = 1; 5385 static const unsigned max_div = 0x10; 5386 unsigned mult; 5387 unsigned best_mult = 1; 5388 static const unsigned max_mult = 0x100; 5389 static const unsigned pico_per_nano = 1000; 5390 5391 const unsigned reference_picosec = reference_period_ns * pico_per_nano; 5392 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to 5393 * 20 MHz for most timing clocks */ 5394 static const unsigned target_picosec = 12500; 5395 static const unsigned fudge_factor_80_to_20Mhz = 4; 5396 int best_period_picosec = 0; 5397 for (div = 1; div <= max_div; ++div) { 5398 for (mult = 1; mult <= max_mult; ++mult) { 5399 unsigned new_period_ps = 5400 (reference_picosec * div) / mult; 5401 if (abs(new_period_ps - target_picosec) < 5402 abs(best_period_picosec - target_picosec)) { 5403 best_period_picosec = new_period_ps; 5404 best_div = div; 5405 best_mult = mult; 5406 } 5407 } 5408 } 5409 if (best_period_picosec == 0) { 5410 printk("%s: bug, failed to find pll parameters\n", __func__); 5411 return -EIO; 5412 } 5413 *freq_divider = best_div; 5414 *freq_multiplier = best_mult; 5415 *actual_period_ns = 5416 (best_period_picosec * fudge_factor_80_to_20Mhz + 5417 (pico_per_nano / 2)) / pico_per_nano; 5418 return 0; 5419} 5420 5421static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev) 5422{ 5423 if (boardtype.reg_type & ni_reg_m_series_mask) 5424 return 8; 5425 else 5426 return 7; 5427} 5428 5429static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, 5430 unsigned source, unsigned period_ns) 5431{ 5432 static const unsigned min_period_ns = 50; 5433 static const unsigned max_period_ns = 1000; 5434 static const unsigned timeout = 1000; 5435 unsigned pll_control_bits; 5436 unsigned freq_divider; 5437 unsigned freq_multiplier; 5438 unsigned i; 5439 int retval; 5440 if (source == NI_MIO_PLL_PXI10_CLOCK) 5441 period_ns = 100; 5442 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */ 5443 if (period_ns < min_period_ns || period_ns > max_period_ns) { 5444 printk 5445 ("%s: you must specify an input clock frequency between %i and %i nanosec " 5446 "for the phased-lock loop.\n", __func__, 5447 min_period_ns, max_period_ns); 5448 return -EINVAL; 5449 } 5450 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; 5451 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5452 RTSI_Trig_Direction_Register); 5453 pll_control_bits = 5454 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; 5455 devpriv->clock_and_fout2 |= 5456 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit; 5457 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask; 5458 switch (source) { 5459 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: 5460 devpriv->clock_and_fout2 |= 5461 MSeries_PLL_In_Source_Select_Star_Trigger_Bits; 5462 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider, 5463 &freq_multiplier, 5464 &devpriv->clock_ns); 5465 if (retval < 0) 5466 return retval; 5467 break; 5468 case NI_MIO_PLL_PXI10_CLOCK: 5469 /* pxi clock is 10MHz */ 5470 devpriv->clock_and_fout2 |= 5471 MSeries_PLL_In_Source_Select_PXI_Clock10; 5472 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider, 5473 &freq_multiplier, 5474 &devpriv->clock_ns); 5475 if (retval < 0) 5476 return retval; 5477 break; 5478 default: 5479 { 5480 unsigned rtsi_channel; 5481 static const unsigned max_rtsi_channel = 7; 5482 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; 5483 ++rtsi_channel) { 5484 if (source == 5485 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) { 5486 devpriv->clock_and_fout2 |= 5487 MSeries_PLL_In_Source_Select_RTSI_Bits 5488 (rtsi_channel); 5489 break; 5490 } 5491 } 5492 if (rtsi_channel > max_rtsi_channel) 5493 return -EINVAL; 5494 retval = ni_mseries_get_pll_parameters(period_ns, 5495 &freq_divider, 5496 &freq_multiplier, 5497 &devpriv-> 5498 clock_ns); 5499 if (retval < 0) 5500 return retval; 5501 } 5502 break; 5503 } 5504 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); 5505 pll_control_bits |= 5506 MSeries_PLL_Divisor_Bits(freq_divider) | 5507 MSeries_PLL_Multiplier_Bits(freq_multiplier); 5508 5509 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n", 5510 * freq_divider, freq_multiplier, pll_control_bits); */ 5511 /* printk("clock_ns=%d\n", devpriv->clock_ns); */ 5512 ni_writew(pll_control_bits, M_Offset_PLL_Control); 5513 devpriv->clock_source = source; 5514 /* it seems to typically take a few hundred microseconds for PLL to lock */ 5515 for (i = 0; i < timeout; ++i) { 5516 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) { 5517 break; 5518 } 5519 udelay(1); 5520 } 5521 if (i == timeout) { 5522 printk 5523 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n", 5524 __func__, source, period_ns); 5525 return -ETIMEDOUT; 5526 } 5527 return 3; 5528} 5529 5530static int ni_set_master_clock(struct comedi_device *dev, unsigned source, 5531 unsigned period_ns) 5532{ 5533 if (source == NI_MIO_INTERNAL_CLOCK) { 5534 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; 5535 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5536 RTSI_Trig_Direction_Register); 5537 devpriv->clock_ns = TIMEBASE_1_NS; 5538 if (boardtype.reg_type & ni_reg_m_series_mask) { 5539 devpriv->clock_and_fout2 &= 5540 ~(MSeries_Timebase1_Select_Bit | 5541 MSeries_Timebase3_Select_Bit); 5542 ni_writew(devpriv->clock_and_fout2, 5543 M_Offset_Clock_and_Fout2); 5544 ni_writew(0, M_Offset_PLL_Control); 5545 } 5546 devpriv->clock_source = source; 5547 } else { 5548 if (boardtype.reg_type & ni_reg_m_series_mask) { 5549 return ni_mseries_set_pll_master_clock(dev, source, 5550 period_ns); 5551 } else { 5552 if (source == NI_MIO_RTSI_CLOCK) { 5553 devpriv->rtsi_trig_direction_reg |= 5554 Use_RTSI_Clock_Bit; 5555 devpriv->stc_writew(dev, 5556 devpriv-> 5557 rtsi_trig_direction_reg, 5558 RTSI_Trig_Direction_Register); 5559 if (period_ns == 0) { 5560 printk 5561 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n", 5562 __func__); 5563 return -EINVAL; 5564 } else { 5565 devpriv->clock_ns = period_ns; 5566 } 5567 devpriv->clock_source = source; 5568 } else 5569 return -EINVAL; 5570 } 5571 } 5572 return 3; 5573} 5574 5575static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan, 5576 unsigned source) 5577{ 5578 if (chan >= num_configurable_rtsi_channels(dev)) { 5579 if (chan == old_RTSI_clock_channel) { 5580 if (source == NI_RTSI_OUTPUT_RTSI_OSC) 5581 return 1; 5582 else { 5583 printk 5584 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n", 5585 __func__, chan, old_RTSI_clock_channel); 5586 return 0; 5587 } 5588 } 5589 return 0; 5590 } 5591 switch (source) { 5592 case NI_RTSI_OUTPUT_ADR_START1: 5593 case NI_RTSI_OUTPUT_ADR_START2: 5594 case NI_RTSI_OUTPUT_SCLKG: 5595 case NI_RTSI_OUTPUT_DACUPDN: 5596 case NI_RTSI_OUTPUT_DA_START1: 5597 case NI_RTSI_OUTPUT_G_SRC0: 5598 case NI_RTSI_OUTPUT_G_GATE0: 5599 case NI_RTSI_OUTPUT_RGOUT0: 5600 case NI_RTSI_OUTPUT_RTSI_BRD_0: 5601 return 1; 5602 break; 5603 case NI_RTSI_OUTPUT_RTSI_OSC: 5604 if (boardtype.reg_type & ni_reg_m_series_mask) 5605 return 1; 5606 else 5607 return 0; 5608 break; 5609 default: 5610 return 0; 5611 break; 5612 } 5613} 5614 5615static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan, 5616 unsigned source) 5617{ 5618 if (ni_valid_rtsi_output_source(dev, chan, source) == 0) 5619 return -EINVAL; 5620 if (chan < 4) { 5621 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan); 5622 devpriv->rtsi_trig_a_output_reg |= 5623 RTSI_Trig_Output_Bits(chan, source); 5624 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg, 5625 RTSI_Trig_A_Output_Register); 5626 } else if (chan < 8) { 5627 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan); 5628 devpriv->rtsi_trig_b_output_reg |= 5629 RTSI_Trig_Output_Bits(chan, source); 5630 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg, 5631 RTSI_Trig_B_Output_Register); 5632 } 5633 return 2; 5634} 5635 5636static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan) 5637{ 5638 if (chan < 4) { 5639 return RTSI_Trig_Output_Source(chan, 5640 devpriv->rtsi_trig_a_output_reg); 5641 } else if (chan < num_configurable_rtsi_channels(dev)) { 5642 return RTSI_Trig_Output_Source(chan, 5643 devpriv->rtsi_trig_b_output_reg); 5644 } else { 5645 if (chan == old_RTSI_clock_channel) 5646 return NI_RTSI_OUTPUT_RTSI_OSC; 5647 printk("%s: bug! should never get here?\n", __func__); 5648 return 0; 5649 } 5650} 5651 5652static int ni_rtsi_insn_config(struct comedi_device *dev, 5653 struct comedi_subdevice *s, 5654 struct comedi_insn *insn, unsigned int *data) 5655{ 5656 unsigned int chan = CR_CHAN(insn->chanspec); 5657 switch (data[0]) { 5658 case INSN_CONFIG_DIO_OUTPUT: 5659 if (chan < num_configurable_rtsi_channels(dev)) { 5660 devpriv->rtsi_trig_direction_reg |= 5661 RTSI_Output_Bit(chan, 5662 (boardtype. 5663 reg_type & ni_reg_m_series_mask) != 5664 0); 5665 } else if (chan == old_RTSI_clock_channel) { 5666 devpriv->rtsi_trig_direction_reg |= 5667 Drive_RTSI_Clock_Bit; 5668 } 5669 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5670 RTSI_Trig_Direction_Register); 5671 break; 5672 case INSN_CONFIG_DIO_INPUT: 5673 if (chan < num_configurable_rtsi_channels(dev)) { 5674 devpriv->rtsi_trig_direction_reg &= 5675 ~RTSI_Output_Bit(chan, 5676 (boardtype. 5677 reg_type & ni_reg_m_series_mask) 5678 != 0); 5679 } else if (chan == old_RTSI_clock_channel) { 5680 devpriv->rtsi_trig_direction_reg &= 5681 ~Drive_RTSI_Clock_Bit; 5682 } 5683 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, 5684 RTSI_Trig_Direction_Register); 5685 break; 5686 case INSN_CONFIG_DIO_QUERY: 5687 if (chan < num_configurable_rtsi_channels(dev)) { 5688 data[1] = 5689 (devpriv->rtsi_trig_direction_reg & 5690 RTSI_Output_Bit(chan, 5691 (boardtype.reg_type & 5692 ni_reg_m_series_mask) 5693 != 0)) ? INSN_CONFIG_DIO_OUTPUT : 5694 INSN_CONFIG_DIO_INPUT; 5695 } else if (chan == old_RTSI_clock_channel) { 5696 data[1] = 5697 (devpriv->rtsi_trig_direction_reg & 5698 Drive_RTSI_Clock_Bit) 5699 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT; 5700 } 5701 return 2; 5702 break; 5703 case INSN_CONFIG_SET_CLOCK_SRC: 5704 return ni_set_master_clock(dev, data[1], data[2]); 5705 break; 5706 case INSN_CONFIG_GET_CLOCK_SRC: 5707 data[1] = devpriv->clock_source; 5708 data[2] = devpriv->clock_ns; 5709 return 3; 5710 break; 5711 case INSN_CONFIG_SET_ROUTING: 5712 return ni_set_rtsi_routing(dev, chan, data[1]); 5713 break; 5714 case INSN_CONFIG_GET_ROUTING: 5715 data[1] = ni_get_rtsi_routing(dev, chan); 5716 return 2; 5717 break; 5718 default: 5719 return -EINVAL; 5720 break; 5721 } 5722 return 1; 5723} 5724 5725static int cs5529_wait_for_idle(struct comedi_device *dev) 5726{ 5727 unsigned short status; 5728 const int timeout = HZ; 5729 int i; 5730 5731 for (i = 0; i < timeout; i++) { 5732 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); 5733 if ((status & CSS_ADC_BUSY) == 0) { 5734 break; 5735 } 5736 set_current_state(TASK_INTERRUPTIBLE); 5737 if (schedule_timeout(1)) { 5738 return -EIO; 5739 } 5740 } 5741/* printk("looped %i times waiting for idle\n", i); */ 5742 if (i == timeout) { 5743 printk("%s: %s: timeout\n", __FILE__, __func__); 5744 return -ETIME; 5745 } 5746 return 0; 5747} 5748 5749static void cs5529_command(struct comedi_device *dev, unsigned short value) 5750{ 5751 static const int timeout = 100; 5752 int i; 5753 5754 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx); 5755 /* give time for command to start being serially clocked into cs5529. 5756 * this insures that the CSS_ADC_BUSY bit will get properly 5757 * set before we exit this function. 5758 */ 5759 for (i = 0; i < timeout; i++) { 5760 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY)) 5761 break; 5762 udelay(1); 5763 } 5764/* printk("looped %i times writing command to cs5529\n", i); */ 5765 if (i == timeout) { 5766 comedi_error(dev, "possible problem - never saw adc go busy?"); 5767 } 5768} 5769 5770/* write to cs5529 register */ 5771static void cs5529_config_write(struct comedi_device *dev, unsigned int value, 5772 unsigned int reg_select_bits) 5773{ 5774 ni_ao_win_outw(dev, ((value >> 16) & 0xff), 5775 CAL_ADC_Config_Data_High_Word_67xx); 5776 ni_ao_win_outw(dev, (value & 0xffff), 5777 CAL_ADC_Config_Data_Low_Word_67xx); 5778 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; 5779 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits); 5780 if (cs5529_wait_for_idle(dev)) 5781 comedi_error(dev, "time or signal in cs5529_config_write()"); 5782} 5783 5784#ifdef NI_CS5529_DEBUG 5785/* read from cs5529 register */ 5786static unsigned int cs5529_config_read(struct comedi_device *dev, 5787 unsigned int reg_select_bits) 5788{ 5789 unsigned int value; 5790 5791 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; 5792 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits); 5793 if (cs5529_wait_for_idle(dev)) 5794 comedi_error(dev, "timeout or signal in cs5529_config_read()"); 5795 value = (ni_ao_win_inw(dev, 5796 CAL_ADC_Config_Data_High_Word_67xx) << 16) & 5797 0xff0000; 5798 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff; 5799 return value; 5800} 5801#endif 5802 5803static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data) 5804{ 5805 int retval; 5806 unsigned short status; 5807 5808 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION); 5809 retval = cs5529_wait_for_idle(dev); 5810 if (retval) { 5811 comedi_error(dev, 5812 "timeout or signal in cs5529_do_conversion()"); 5813 return -ETIME; 5814 } 5815 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); 5816 if (status & CSS_OSC_DETECT) { 5817 printk 5818 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n"); 5819 return -EIO; 5820 } 5821 if (status & CSS_OVERRANGE) { 5822 printk 5823 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n"); 5824 } 5825 if (data) { 5826 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx); 5827 /* cs5529 returns 16 bit signed data in bipolar mode */ 5828 *data ^= (1 << 15); 5829 } 5830 return 0; 5831} 5832 5833static int cs5529_ai_insn_read(struct comedi_device *dev, 5834 struct comedi_subdevice *s, 5835 struct comedi_insn *insn, unsigned int *data) 5836{ 5837 int n, retval; 5838 unsigned short sample; 5839 unsigned int channel_select; 5840 const unsigned int INTERNAL_REF = 0x1000; 5841 5842 /* Set calibration adc source. Docs lie, reference select bits 8 to 11 5843 * do nothing. bit 12 seems to chooses internal reference voltage, bit 5844 * 13 causes the adc input to go overrange (maybe reads external reference?) */ 5845 if (insn->chanspec & CR_ALT_SOURCE) 5846 channel_select = INTERNAL_REF; 5847 else 5848 channel_select = CR_CHAN(insn->chanspec); 5849 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx); 5850 5851 for (n = 0; n < insn->n; n++) { 5852 retval = cs5529_do_conversion(dev, &sample); 5853 if (retval < 0) 5854 return retval; 5855 data[n] = sample; 5856 } 5857 return insn->n; 5858} 5859 5860static int init_cs5529(struct comedi_device *dev) 5861{ 5862 unsigned int config_bits = 5863 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES; 5864 5865 /* do self-calibration */ 5866 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, 5867 CSCMD_CONFIG_REGISTER); 5868 /* need to force a conversion for calibration to run */ 5869 cs5529_do_conversion(dev, NULL); 5870#ifdef NI_CS5529_DEBUG 5871 printk("config: 0x%x\n", cs5529_config_read(dev, 5872 CSCMD_CONFIG_REGISTER)); 5873 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER)); 5874 printk("offset: 0x%x\n", cs5529_config_read(dev, 5875 CSCMD_OFFSET_REGISTER)); 5876#endif 5877 return 0; 5878} 5879