1/* 2 * drivers/serial/sh-sci.c 3 * 4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 5 * 6 * Copyright (C) 2002 - 2008 Paul Mundt 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 * 18 * This file is subject to the terms and conditions of the GNU General Public 19 * License. See the file "COPYING" in the main directory of this archive 20 * for more details. 21 */ 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 23#define SUPPORT_SYSRQ 24#endif 25 26#undef DEBUG 27 28#include <linux/module.h> 29#include <linux/errno.h> 30#include <linux/timer.h> 31#include <linux/interrupt.h> 32#include <linux/tty.h> 33#include <linux/tty_flip.h> 34#include <linux/serial.h> 35#include <linux/major.h> 36#include <linux/string.h> 37#include <linux/sysrq.h> 38#include <linux/ioport.h> 39#include <linux/mm.h> 40#include <linux/init.h> 41#include <linux/delay.h> 42#include <linux/console.h> 43#include <linux/platform_device.h> 44#include <linux/serial_sci.h> 45#include <linux/notifier.h> 46#include <linux/cpufreq.h> 47#include <linux/clk.h> 48#include <linux/ctype.h> 49#include <linux/err.h> 50#include <linux/list.h> 51#include <linux/dmaengine.h> 52#include <linux/scatterlist.h> 53#include <linux/slab.h> 54 55#ifdef CONFIG_SUPERH 56#include <asm/sh_bios.h> 57#endif 58 59#ifdef CONFIG_H8300 60#include <asm/gpio.h> 61#endif 62 63#include "sh-sci.h" 64 65struct sci_port { 66 struct uart_port port; 67 68 /* Port type */ 69 unsigned int type; 70 71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ 72 unsigned int irqs[SCIx_NR_IRQS]; 73 74 /* Port enable callback */ 75 void (*enable)(struct uart_port *port); 76 77 /* Port disable callback */ 78 void (*disable)(struct uart_port *port); 79 80 /* Break timer */ 81 struct timer_list break_timer; 82 int break_flag; 83 84 /* Interface clock */ 85 struct clk *iclk; 86 /* Function clock */ 87 struct clk *fclk; 88 89 struct list_head node; 90 struct dma_chan *chan_tx; 91 struct dma_chan *chan_rx; 92#ifdef CONFIG_SERIAL_SH_SCI_DMA 93 struct device *dma_dev; 94 unsigned int slave_tx; 95 unsigned int slave_rx; 96 struct dma_async_tx_descriptor *desc_tx; 97 struct dma_async_tx_descriptor *desc_rx[2]; 98 dma_cookie_t cookie_tx; 99 dma_cookie_t cookie_rx[2]; 100 dma_cookie_t active_rx; 101 struct scatterlist sg_tx; 102 unsigned int sg_len_tx; 103 struct scatterlist sg_rx[2]; 104 size_t buf_len_rx; 105 struct sh_dmae_slave param_tx; 106 struct sh_dmae_slave param_rx; 107 struct work_struct work_tx; 108 struct work_struct work_rx; 109 struct timer_list rx_timer; 110 unsigned int rx_timeout; 111#endif 112}; 113 114struct sh_sci_priv { 115 spinlock_t lock; 116 struct list_head ports; 117 struct notifier_block clk_nb; 118}; 119 120/* Function prototypes */ 121static void sci_stop_tx(struct uart_port *port); 122 123#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 124 125static struct sci_port sci_ports[SCI_NPORTS]; 126static struct uart_driver sci_uart_driver; 127 128static inline struct sci_port * 129to_sci_port(struct uart_port *uart) 130{ 131 return container_of(uart, struct sci_port, port); 132} 133 134#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 135 136#ifdef CONFIG_CONSOLE_POLL 137static inline void handle_error(struct uart_port *port) 138{ 139 /* Clear error flags */ 140 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 141} 142 143static int sci_poll_get_char(struct uart_port *port) 144{ 145 unsigned short status; 146 int c; 147 148 do { 149 status = sci_in(port, SCxSR); 150 if (status & SCxSR_ERRORS(port)) { 151 handle_error(port); 152 continue; 153 } 154 break; 155 } while (1); 156 157 if (!(status & SCxSR_RDxF(port))) 158 return NO_POLL_CHAR; 159 160 c = sci_in(port, SCxRDR); 161 162 /* Dummy read */ 163 sci_in(port, SCxSR); 164 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 165 166 return c; 167} 168#endif 169 170static void sci_poll_put_char(struct uart_port *port, unsigned char c) 171{ 172 unsigned short status; 173 174 do { 175 status = sci_in(port, SCxSR); 176 } while (!(status & SCxSR_TDxE(port))); 177 178 sci_out(port, SCxTDR, c); 179 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 180} 181#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 182 183#if defined(__H8300H__) || defined(__H8300S__) 184static void sci_init_pins(struct uart_port *port, unsigned int cflag) 185{ 186 int ch = (port->mapbase - SMR0) >> 3; 187 188 /* set DDR regs */ 189 H8300_GPIO_DDR(h8300_sci_pins[ch].port, 190 h8300_sci_pins[ch].rx, 191 H8300_GPIO_INPUT); 192 H8300_GPIO_DDR(h8300_sci_pins[ch].port, 193 h8300_sci_pins[ch].tx, 194 H8300_GPIO_OUTPUT); 195 196 /* tx mark output*/ 197 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; 198} 199#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 200static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 201{ 202 if (port->mapbase == 0xA4400000) { 203 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); 204 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); 205 } else if (port->mapbase == 0xA4410000) 206 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); 207} 208#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) 209static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 210{ 211 unsigned short data; 212 213 if (cflag & CRTSCTS) { 214 /* enable RTS/CTS */ 215 if (port->mapbase == 0xa4430000) { /* SCIF0 */ 216 /* Clear PTCR bit 9-2; enable all scif pins but sck */ 217 data = __raw_readw(PORT_PTCR); 218 __raw_writew((data & 0xfc03), PORT_PTCR); 219 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ 220 /* Clear PVCR bit 9-2 */ 221 data = __raw_readw(PORT_PVCR); 222 __raw_writew((data & 0xfc03), PORT_PVCR); 223 } 224 } else { 225 if (port->mapbase == 0xa4430000) { /* SCIF0 */ 226 /* Clear PTCR bit 5-2; enable only tx and rx */ 227 data = __raw_readw(PORT_PTCR); 228 __raw_writew((data & 0xffc3), PORT_PTCR); 229 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ 230 /* Clear PVCR bit 5-2 */ 231 data = __raw_readw(PORT_PVCR); 232 __raw_writew((data & 0xffc3), PORT_PVCR); 233 } 234 } 235} 236#elif defined(CONFIG_CPU_SH3) 237/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ 238static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 239{ 240 unsigned short data; 241 242 /* We need to set SCPCR to enable RTS/CTS */ 243 data = __raw_readw(SCPCR); 244 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ 245 __raw_writew(data & 0x0fcf, SCPCR); 246 247 if (!(cflag & CRTSCTS)) { 248 /* We need to set SCPCR to enable RTS/CTS */ 249 data = __raw_readw(SCPCR); 250 /* Clear out SCP7MD1,0, SCP4MD1,0, 251 Set SCP6MD1,0 = {01} (output) */ 252 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); 253 254 data = __raw_readb(SCPDR); 255 /* Set /RTS2 (bit6) = 0 */ 256 __raw_writeb(data & 0xbf, SCPDR); 257 } 258} 259#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 260static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 261{ 262 unsigned short data; 263 264 if (port->mapbase == 0xffe00000) { 265 data = __raw_readw(PSCR); 266 data &= ~0x03cf; 267 if (!(cflag & CRTSCTS)) 268 data |= 0x0340; 269 270 __raw_writew(data, PSCR); 271 } 272} 273#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ 274 defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 275 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 276 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 277 defined(CONFIG_CPU_SUBTYPE_SH7786) || \ 278 defined(CONFIG_CPU_SUBTYPE_SHX3) 279static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 280{ 281 if (!(cflag & CRTSCTS)) 282 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ 283} 284#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) 285static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 286{ 287 if (!(cflag & CRTSCTS)) 288 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ 289} 290#else 291static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 292{ 293 /* Nothing to do */ 294} 295#endif 296 297#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 298 defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7786) 299static int scif_txfill(struct uart_port *port) 300{ 301 return sci_in(port, SCTFDR) & 0xff; 302} 303 304static int scif_txroom(struct uart_port *port) 305{ 306 return SCIF_TXROOM_MAX - scif_txfill(port); 307} 308 309static int scif_rxfill(struct uart_port *port) 310{ 311 return sci_in(port, SCRFDR) & 0xff; 312} 313#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 314static int scif_txfill(struct uart_port *port) 315{ 316 if (port->mapbase == 0xffe00000 || 317 port->mapbase == 0xffe08000) 318 /* SCIF0/1*/ 319 return sci_in(port, SCTFDR) & 0xff; 320 else 321 /* SCIF2 */ 322 return sci_in(port, SCFDR) >> 8; 323} 324 325static int scif_txroom(struct uart_port *port) 326{ 327 if (port->mapbase == 0xffe00000 || 328 port->mapbase == 0xffe08000) 329 /* SCIF0/1*/ 330 return SCIF_TXROOM_MAX - scif_txfill(port); 331 else 332 /* SCIF2 */ 333 return SCIF2_TXROOM_MAX - scif_txfill(port); 334} 335 336static int scif_rxfill(struct uart_port *port) 337{ 338 if ((port->mapbase == 0xffe00000) || 339 (port->mapbase == 0xffe08000)) { 340 /* SCIF0/1*/ 341 return sci_in(port, SCRFDR) & 0xff; 342 } else { 343 /* SCIF2 */ 344 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; 345 } 346} 347#elif defined(CONFIG_ARCH_SH7372) 348static int scif_txfill(struct uart_port *port) 349{ 350 if (port->type == PORT_SCIFA) 351 return sci_in(port, SCFDR) >> 8; 352 else 353 return sci_in(port, SCTFDR); 354} 355 356static int scif_txroom(struct uart_port *port) 357{ 358 return port->fifosize - scif_txfill(port); 359} 360 361static int scif_rxfill(struct uart_port *port) 362{ 363 if (port->type == PORT_SCIFA) 364 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 365 else 366 return sci_in(port, SCRFDR); 367} 368#else 369static int scif_txfill(struct uart_port *port) 370{ 371 return sci_in(port, SCFDR) >> 8; 372} 373 374static int scif_txroom(struct uart_port *port) 375{ 376 return SCIF_TXROOM_MAX - scif_txfill(port); 377} 378 379static int scif_rxfill(struct uart_port *port) 380{ 381 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 382} 383#endif 384 385static int sci_txfill(struct uart_port *port) 386{ 387 return !(sci_in(port, SCxSR) & SCI_TDRE); 388} 389 390static int sci_txroom(struct uart_port *port) 391{ 392 return !sci_txfill(port); 393} 394 395static int sci_rxfill(struct uart_port *port) 396{ 397 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 398} 399 400/* ********************************************************************** * 401 * the interrupt related routines * 402 * ********************************************************************** */ 403 404static void sci_transmit_chars(struct uart_port *port) 405{ 406 struct circ_buf *xmit = &port->state->xmit; 407 unsigned int stopped = uart_tx_stopped(port); 408 unsigned short status; 409 unsigned short ctrl; 410 int count; 411 412 status = sci_in(port, SCxSR); 413 if (!(status & SCxSR_TDxE(port))) { 414 ctrl = sci_in(port, SCSCR); 415 if (uart_circ_empty(xmit)) 416 ctrl &= ~SCI_CTRL_FLAGS_TIE; 417 else 418 ctrl |= SCI_CTRL_FLAGS_TIE; 419 sci_out(port, SCSCR, ctrl); 420 return; 421 } 422 423 if (port->type == PORT_SCI) 424 count = sci_txroom(port); 425 else 426 count = scif_txroom(port); 427 428 do { 429 unsigned char c; 430 431 if (port->x_char) { 432 c = port->x_char; 433 port->x_char = 0; 434 } else if (!uart_circ_empty(xmit) && !stopped) { 435 c = xmit->buf[xmit->tail]; 436 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 437 } else { 438 break; 439 } 440 441 sci_out(port, SCxTDR, c); 442 443 port->icount.tx++; 444 } while (--count > 0); 445 446 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 447 448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 449 uart_write_wakeup(port); 450 if (uart_circ_empty(xmit)) { 451 sci_stop_tx(port); 452 } else { 453 ctrl = sci_in(port, SCSCR); 454 455 if (port->type != PORT_SCI) { 456 sci_in(port, SCxSR); /* Dummy read */ 457 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 458 } 459 460 ctrl |= SCI_CTRL_FLAGS_TIE; 461 sci_out(port, SCSCR, ctrl); 462 } 463} 464 465/* On SH3, SCIF may read end-of-break as a space->mark char */ 466#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 467 468static inline void sci_receive_chars(struct uart_port *port) 469{ 470 struct sci_port *sci_port = to_sci_port(port); 471 struct tty_struct *tty = port->state->port.tty; 472 int i, count, copied = 0; 473 unsigned short status; 474 unsigned char flag; 475 476 status = sci_in(port, SCxSR); 477 if (!(status & SCxSR_RDxF(port))) 478 return; 479 480 while (1) { 481 if (port->type == PORT_SCI) 482 count = sci_rxfill(port); 483 else 484 count = scif_rxfill(port); 485 486 /* Don't copy more bytes than there is room for in the buffer */ 487 count = tty_buffer_request_room(tty, count); 488 489 /* If for any reason we can't copy more data, we're done! */ 490 if (count == 0) 491 break; 492 493 if (port->type == PORT_SCI) { 494 char c = sci_in(port, SCxRDR); 495 if (uart_handle_sysrq_char(port, c) || 496 sci_port->break_flag) 497 count = 0; 498 else 499 tty_insert_flip_char(tty, c, TTY_NORMAL); 500 } else { 501 for (i = 0; i < count; i++) { 502 char c = sci_in(port, SCxRDR); 503 status = sci_in(port, SCxSR); 504#if defined(CONFIG_CPU_SH3) 505 /* Skip "chars" during break */ 506 if (sci_port->break_flag) { 507 if ((c == 0) && 508 (status & SCxSR_FER(port))) { 509 count--; i--; 510 continue; 511 } 512 513 /* Nonzero => end-of-break */ 514 dev_dbg(port->dev, "debounce<%02x>\n", c); 515 sci_port->break_flag = 0; 516 517 if (STEPFN(c)) { 518 count--; i--; 519 continue; 520 } 521 } 522#endif /* CONFIG_CPU_SH3 */ 523 if (uart_handle_sysrq_char(port, c)) { 524 count--; i--; 525 continue; 526 } 527 528 /* Store data and status */ 529 if (status & SCxSR_FER(port)) { 530 flag = TTY_FRAME; 531 dev_notice(port->dev, "frame error\n"); 532 } else if (status & SCxSR_PER(port)) { 533 flag = TTY_PARITY; 534 dev_notice(port->dev, "parity error\n"); 535 } else 536 flag = TTY_NORMAL; 537 538 tty_insert_flip_char(tty, c, flag); 539 } 540 } 541 542 sci_in(port, SCxSR); /* dummy read */ 543 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 544 545 copied += count; 546 port->icount.rx += count; 547 } 548 549 if (copied) { 550 /* Tell the rest of the system the news. New characters! */ 551 tty_flip_buffer_push(tty); 552 } else { 553 sci_in(port, SCxSR); /* dummy read */ 554 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 555 } 556} 557 558#define SCI_BREAK_JIFFIES (HZ/20) 559/* The sci generates interrupts during the break, 560 * 1 per millisecond or so during the break period, for 9600 baud. 561 * So dont bother disabling interrupts. 562 * But dont want more than 1 break event. 563 * Use a kernel timer to periodically poll the rx line until 564 * the break is finished. 565 */ 566static void sci_schedule_break_timer(struct sci_port *port) 567{ 568 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; 569 add_timer(&port->break_timer); 570} 571/* Ensure that two consecutive samples find the break over. */ 572static void sci_break_timer(unsigned long data) 573{ 574 struct sci_port *port = (struct sci_port *)data; 575 576 if (sci_rxd_in(&port->port) == 0) { 577 port->break_flag = 1; 578 sci_schedule_break_timer(port); 579 } else if (port->break_flag == 1) { 580 /* break is over. */ 581 port->break_flag = 2; 582 sci_schedule_break_timer(port); 583 } else 584 port->break_flag = 0; 585} 586 587static inline int sci_handle_errors(struct uart_port *port) 588{ 589 int copied = 0; 590 unsigned short status = sci_in(port, SCxSR); 591 struct tty_struct *tty = port->state->port.tty; 592 593 if (status & SCxSR_ORER(port)) { 594 /* overrun error */ 595 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 596 copied++; 597 598 dev_notice(port->dev, "overrun error"); 599 } 600 601 if (status & SCxSR_FER(port)) { 602 if (sci_rxd_in(port) == 0) { 603 /* Notify of BREAK */ 604 struct sci_port *sci_port = to_sci_port(port); 605 606 if (!sci_port->break_flag) { 607 sci_port->break_flag = 1; 608 sci_schedule_break_timer(sci_port); 609 610 /* Do sysrq handling. */ 611 if (uart_handle_break(port)) 612 return 0; 613 614 dev_dbg(port->dev, "BREAK detected\n"); 615 616 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 617 copied++; 618 } 619 620 } else { 621 /* frame error */ 622 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 623 copied++; 624 625 dev_notice(port->dev, "frame error\n"); 626 } 627 } 628 629 if (status & SCxSR_PER(port)) { 630 /* parity error */ 631 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 632 copied++; 633 634 dev_notice(port->dev, "parity error"); 635 } 636 637 if (copied) 638 tty_flip_buffer_push(tty); 639 640 return copied; 641} 642 643static inline int sci_handle_fifo_overrun(struct uart_port *port) 644{ 645 struct tty_struct *tty = port->state->port.tty; 646 int copied = 0; 647 648 if (port->type != PORT_SCIF) 649 return 0; 650 651 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { 652 sci_out(port, SCLSR, 0); 653 654 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 655 tty_flip_buffer_push(tty); 656 657 dev_notice(port->dev, "overrun error\n"); 658 copied++; 659 } 660 661 return copied; 662} 663 664static inline int sci_handle_breaks(struct uart_port *port) 665{ 666 int copied = 0; 667 unsigned short status = sci_in(port, SCxSR); 668 struct tty_struct *tty = port->state->port.tty; 669 struct sci_port *s = to_sci_port(port); 670 671 if (uart_handle_break(port)) 672 return 0; 673 674 if (!s->break_flag && status & SCxSR_BRK(port)) { 675#if defined(CONFIG_CPU_SH3) 676 /* Debounce break */ 677 s->break_flag = 1; 678#endif 679 /* Notify of BREAK */ 680 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 681 copied++; 682 683 dev_dbg(port->dev, "BREAK detected\n"); 684 } 685 686 if (copied) 687 tty_flip_buffer_push(tty); 688 689 copied += sci_handle_fifo_overrun(port); 690 691 return copied; 692} 693 694static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 695{ 696#ifdef CONFIG_SERIAL_SH_SCI_DMA 697 struct uart_port *port = ptr; 698 struct sci_port *s = to_sci_port(port); 699 700 if (s->chan_rx) { 701 u16 scr = sci_in(port, SCSCR); 702 u16 ssr = sci_in(port, SCxSR); 703 704 /* Disable future Rx interrupts */ 705 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 706 disable_irq_nosync(irq); 707 scr |= 0x4000; 708 } else { 709 scr &= ~SCI_CTRL_FLAGS_RIE; 710 } 711 sci_out(port, SCSCR, scr); 712 /* Clear current interrupt */ 713 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 714 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 715 jiffies, s->rx_timeout); 716 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 717 718 return IRQ_HANDLED; 719 } 720#endif 721 722 /* I think sci_receive_chars has to be called irrespective 723 * of whether the I_IXOFF is set, otherwise, how is the interrupt 724 * to be disabled? 725 */ 726 sci_receive_chars(ptr); 727 728 return IRQ_HANDLED; 729} 730 731static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 732{ 733 struct uart_port *port = ptr; 734 unsigned long flags; 735 736 spin_lock_irqsave(&port->lock, flags); 737 sci_transmit_chars(port); 738 spin_unlock_irqrestore(&port->lock, flags); 739 740 return IRQ_HANDLED; 741} 742 743static irqreturn_t sci_er_interrupt(int irq, void *ptr) 744{ 745 struct uart_port *port = ptr; 746 747 /* Handle errors */ 748 if (port->type == PORT_SCI) { 749 if (sci_handle_errors(port)) { 750 /* discard character in rx buffer */ 751 sci_in(port, SCxSR); 752 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 753 } 754 } else { 755 sci_handle_fifo_overrun(port); 756 sci_rx_interrupt(irq, ptr); 757 } 758 759 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 760 761 /* Kick the transmission */ 762 sci_tx_interrupt(irq, ptr); 763 764 return IRQ_HANDLED; 765} 766 767static irqreturn_t sci_br_interrupt(int irq, void *ptr) 768{ 769 struct uart_port *port = ptr; 770 771 /* Handle BREAKs */ 772 sci_handle_breaks(port); 773 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 774 775 return IRQ_HANDLED; 776} 777 778static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 779{ 780 unsigned short ssr_status, scr_status, err_enabled; 781 struct uart_port *port = ptr; 782 struct sci_port *s = to_sci_port(port); 783 irqreturn_t ret = IRQ_NONE; 784 785 ssr_status = sci_in(port, SCxSR); 786 scr_status = sci_in(port, SCSCR); 787 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE); 788 789 /* Tx Interrupt */ 790 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) && 791 !s->chan_tx) 792 ret = sci_tx_interrupt(irq, ptr); 793 /* 794 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 795 * DR flags 796 */ 797 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 798 (scr_status & SCI_CTRL_FLAGS_RIE)) 799 ret = sci_rx_interrupt(irq, ptr); 800 /* Error Interrupt */ 801 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 802 ret = sci_er_interrupt(irq, ptr); 803 /* Break Interrupt */ 804 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 805 ret = sci_br_interrupt(irq, ptr); 806 807 return ret; 808} 809 810/* 811 * Here we define a transistion notifier so that we can update all of our 812 * ports' baud rate when the peripheral clock changes. 813 */ 814static int sci_notifier(struct notifier_block *self, 815 unsigned long phase, void *p) 816{ 817 struct sh_sci_priv *priv = container_of(self, 818 struct sh_sci_priv, clk_nb); 819 struct sci_port *sci_port; 820 unsigned long flags; 821 822 if ((phase == CPUFREQ_POSTCHANGE) || 823 (phase == CPUFREQ_RESUMECHANGE)) { 824 spin_lock_irqsave(&priv->lock, flags); 825 list_for_each_entry(sci_port, &priv->ports, node) 826 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 827 spin_unlock_irqrestore(&priv->lock, flags); 828 } 829 830 return NOTIFY_OK; 831} 832 833static void sci_clk_enable(struct uart_port *port) 834{ 835 struct sci_port *sci_port = to_sci_port(port); 836 837 clk_enable(sci_port->iclk); 838 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 839 clk_enable(sci_port->fclk); 840} 841 842static void sci_clk_disable(struct uart_port *port) 843{ 844 struct sci_port *sci_port = to_sci_port(port); 845 846 clk_disable(sci_port->fclk); 847 clk_disable(sci_port->iclk); 848} 849 850static int sci_request_irq(struct sci_port *port) 851{ 852 int i; 853 irqreturn_t (*handlers[4])(int irq, void *ptr) = { 854 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, 855 sci_br_interrupt, 856 }; 857 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", 858 "SCI Transmit Data Empty", "SCI Break" }; 859 860 if (port->irqs[0] == port->irqs[1]) { 861 if (unlikely(!port->irqs[0])) 862 return -ENODEV; 863 864 if (request_irq(port->irqs[0], sci_mpxed_interrupt, 865 IRQF_DISABLED, "sci", port)) { 866 dev_err(port->port.dev, "Can't allocate IRQ\n"); 867 return -ENODEV; 868 } 869 } else { 870 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 871 if (unlikely(!port->irqs[i])) 872 continue; 873 874 if (request_irq(port->irqs[i], handlers[i], 875 IRQF_DISABLED, desc[i], port)) { 876 dev_err(port->port.dev, "Can't allocate IRQ\n"); 877 return -ENODEV; 878 } 879 } 880 } 881 882 return 0; 883} 884 885static void sci_free_irq(struct sci_port *port) 886{ 887 int i; 888 889 if (port->irqs[0] == port->irqs[1]) 890 free_irq(port->irqs[0], port); 891 else { 892 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { 893 if (!port->irqs[i]) 894 continue; 895 896 free_irq(port->irqs[i], port); 897 } 898 } 899} 900 901static unsigned int sci_tx_empty(struct uart_port *port) 902{ 903 unsigned short status = sci_in(port, SCxSR); 904 unsigned short in_tx_fifo = scif_txfill(port); 905 906 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 907} 908 909static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 910{ 911 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ 912 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ 913 /* If you have signals for DTR and DCD, please implement here. */ 914} 915 916static unsigned int sci_get_mctrl(struct uart_port *port) 917{ 918 /* This routine is used for getting signals of: DTR, DCD, DSR, RI, 919 and CTS/RTS */ 920 921 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; 922} 923 924#ifdef CONFIG_SERIAL_SH_SCI_DMA 925static void sci_dma_tx_complete(void *arg) 926{ 927 struct sci_port *s = arg; 928 struct uart_port *port = &s->port; 929 struct circ_buf *xmit = &port->state->xmit; 930 unsigned long flags; 931 932 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 933 934 spin_lock_irqsave(&port->lock, flags); 935 936 xmit->tail += sg_dma_len(&s->sg_tx); 937 xmit->tail &= UART_XMIT_SIZE - 1; 938 939 port->icount.tx += sg_dma_len(&s->sg_tx); 940 941 async_tx_ack(s->desc_tx); 942 s->cookie_tx = -EINVAL; 943 s->desc_tx = NULL; 944 945 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 946 uart_write_wakeup(port); 947 948 if (!uart_circ_empty(xmit)) { 949 schedule_work(&s->work_tx); 950 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 951 u16 ctrl = sci_in(port, SCSCR); 952 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE); 953 } 954 955 spin_unlock_irqrestore(&port->lock, flags); 956} 957 958/* Locking: called with port lock held */ 959static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, 960 size_t count) 961{ 962 struct uart_port *port = &s->port; 963 int i, active, room; 964 965 room = tty_buffer_request_room(tty, count); 966 967 if (s->active_rx == s->cookie_rx[0]) { 968 active = 0; 969 } else if (s->active_rx == s->cookie_rx[1]) { 970 active = 1; 971 } else { 972 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 973 return 0; 974 } 975 976 if (room < count) 977 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 978 count - room); 979 if (!room) 980 return room; 981 982 for (i = 0; i < room; i++) 983 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 984 TTY_NORMAL); 985 986 port->icount.rx += room; 987 988 return room; 989} 990 991static void sci_dma_rx_complete(void *arg) 992{ 993 struct sci_port *s = arg; 994 struct uart_port *port = &s->port; 995 struct tty_struct *tty = port->state->port.tty; 996 unsigned long flags; 997 int count; 998 999 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1000 1001 spin_lock_irqsave(&port->lock, flags); 1002 1003 count = sci_dma_rx_push(s, tty, s->buf_len_rx); 1004 1005 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1006 1007 spin_unlock_irqrestore(&port->lock, flags); 1008 1009 if (count) 1010 tty_flip_buffer_push(tty); 1011 1012 schedule_work(&s->work_rx); 1013} 1014 1015static void sci_start_rx(struct uart_port *port); 1016static void sci_start_tx(struct uart_port *port); 1017 1018static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1019{ 1020 struct dma_chan *chan = s->chan_rx; 1021 struct uart_port *port = &s->port; 1022 1023 s->chan_rx = NULL; 1024 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1025 dma_release_channel(chan); 1026 if (sg_dma_address(&s->sg_rx[0])) 1027 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1028 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1029 if (enable_pio) 1030 sci_start_rx(port); 1031} 1032 1033static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1034{ 1035 struct dma_chan *chan = s->chan_tx; 1036 struct uart_port *port = &s->port; 1037 1038 s->chan_tx = NULL; 1039 s->cookie_tx = -EINVAL; 1040 dma_release_channel(chan); 1041 if (enable_pio) 1042 sci_start_tx(port); 1043} 1044 1045static void sci_submit_rx(struct sci_port *s) 1046{ 1047 struct dma_chan *chan = s->chan_rx; 1048 int i; 1049 1050 for (i = 0; i < 2; i++) { 1051 struct scatterlist *sg = &s->sg_rx[i]; 1052 struct dma_async_tx_descriptor *desc; 1053 1054 desc = chan->device->device_prep_slave_sg(chan, 1055 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); 1056 1057 if (desc) { 1058 s->desc_rx[i] = desc; 1059 desc->callback = sci_dma_rx_complete; 1060 desc->callback_param = s; 1061 s->cookie_rx[i] = desc->tx_submit(desc); 1062 } 1063 1064 if (!desc || s->cookie_rx[i] < 0) { 1065 if (i) { 1066 async_tx_ack(s->desc_rx[0]); 1067 s->cookie_rx[0] = -EINVAL; 1068 } 1069 if (desc) { 1070 async_tx_ack(desc); 1071 s->cookie_rx[i] = -EINVAL; 1072 } 1073 dev_warn(s->port.dev, 1074 "failed to re-start DMA, using PIO\n"); 1075 sci_rx_dma_release(s, true); 1076 return; 1077 } 1078 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1079 s->cookie_rx[i], i); 1080 } 1081 1082 s->active_rx = s->cookie_rx[0]; 1083 1084 dma_async_issue_pending(chan); 1085} 1086 1087static void work_fn_rx(struct work_struct *work) 1088{ 1089 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1090 struct uart_port *port = &s->port; 1091 struct dma_async_tx_descriptor *desc; 1092 int new; 1093 1094 if (s->active_rx == s->cookie_rx[0]) { 1095 new = 0; 1096 } else if (s->active_rx == s->cookie_rx[1]) { 1097 new = 1; 1098 } else { 1099 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1100 return; 1101 } 1102 desc = s->desc_rx[new]; 1103 1104 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1105 DMA_SUCCESS) { 1106 /* Handle incomplete DMA receive */ 1107 struct tty_struct *tty = port->state->port.tty; 1108 struct dma_chan *chan = s->chan_rx; 1109 struct sh_desc *sh_desc = container_of(desc, struct sh_desc, 1110 async_tx); 1111 unsigned long flags; 1112 int count; 1113 1114 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1115 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", 1116 sh_desc->partial, sh_desc->cookie); 1117 1118 spin_lock_irqsave(&port->lock, flags); 1119 count = sci_dma_rx_push(s, tty, sh_desc->partial); 1120 spin_unlock_irqrestore(&port->lock, flags); 1121 1122 if (count) 1123 tty_flip_buffer_push(tty); 1124 1125 sci_submit_rx(s); 1126 1127 return; 1128 } 1129 1130 s->cookie_rx[new] = desc->tx_submit(desc); 1131 if (s->cookie_rx[new] < 0) { 1132 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1133 sci_rx_dma_release(s, true); 1134 return; 1135 } 1136 1137 s->active_rx = s->cookie_rx[!new]; 1138 1139 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1140 s->cookie_rx[new], new, s->active_rx); 1141} 1142 1143static void work_fn_tx(struct work_struct *work) 1144{ 1145 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1146 struct dma_async_tx_descriptor *desc; 1147 struct dma_chan *chan = s->chan_tx; 1148 struct uart_port *port = &s->port; 1149 struct circ_buf *xmit = &port->state->xmit; 1150 struct scatterlist *sg = &s->sg_tx; 1151 1152 /* 1153 * DMA is idle now. 1154 * Port xmit buffer is already mapped, and it is one page... Just adjust 1155 * offsets and lengths. Since it is a circular buffer, we have to 1156 * transmit till the end, and then the rest. Take the port lock to get a 1157 * consistent xmit buffer state. 1158 */ 1159 spin_lock_irq(&port->lock); 1160 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1161 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1162 sg->offset; 1163 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1164 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1165 spin_unlock_irq(&port->lock); 1166 1167 BUG_ON(!sg_dma_len(sg)); 1168 1169 desc = chan->device->device_prep_slave_sg(chan, 1170 sg, s->sg_len_tx, DMA_TO_DEVICE, 1171 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1172 if (!desc) { 1173 /* switch to PIO */ 1174 sci_tx_dma_release(s, true); 1175 return; 1176 } 1177 1178 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1179 1180 spin_lock_irq(&port->lock); 1181 s->desc_tx = desc; 1182 desc->callback = sci_dma_tx_complete; 1183 desc->callback_param = s; 1184 spin_unlock_irq(&port->lock); 1185 s->cookie_tx = desc->tx_submit(desc); 1186 if (s->cookie_tx < 0) { 1187 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1188 /* switch to PIO */ 1189 sci_tx_dma_release(s, true); 1190 return; 1191 } 1192 1193 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1194 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1195 1196 dma_async_issue_pending(chan); 1197} 1198#endif 1199 1200static void sci_start_tx(struct uart_port *port) 1201{ 1202 struct sci_port *s = to_sci_port(port); 1203 unsigned short ctrl; 1204 1205#ifdef CONFIG_SERIAL_SH_SCI_DMA 1206 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1207 u16 new, scr = sci_in(port, SCSCR); 1208 if (s->chan_tx) 1209 new = scr | 0x8000; 1210 else 1211 new = scr & ~0x8000; 1212 if (new != scr) 1213 sci_out(port, SCSCR, new); 1214 } 1215 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1216 s->cookie_tx < 0) 1217 schedule_work(&s->work_tx); 1218#endif 1219 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1220 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1221 ctrl = sci_in(port, SCSCR); 1222 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE); 1223 } 1224} 1225 1226static void sci_stop_tx(struct uart_port *port) 1227{ 1228 unsigned short ctrl; 1229 1230 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1231 ctrl = sci_in(port, SCSCR); 1232 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1233 ctrl &= ~0x8000; 1234 ctrl &= ~SCI_CTRL_FLAGS_TIE; 1235 sci_out(port, SCSCR, ctrl); 1236} 1237 1238static void sci_start_rx(struct uart_port *port) 1239{ 1240 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; 1241 1242 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ 1243 ctrl |= sci_in(port, SCSCR); 1244 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1245 ctrl &= ~0x4000; 1246 sci_out(port, SCSCR, ctrl); 1247} 1248 1249static void sci_stop_rx(struct uart_port *port) 1250{ 1251 unsigned short ctrl; 1252 1253 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ 1254 ctrl = sci_in(port, SCSCR); 1255 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1256 ctrl &= ~0x4000; 1257 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); 1258 sci_out(port, SCSCR, ctrl); 1259} 1260 1261static void sci_enable_ms(struct uart_port *port) 1262{ 1263 /* Nothing here yet .. */ 1264} 1265 1266static void sci_break_ctl(struct uart_port *port, int break_state) 1267{ 1268 /* Nothing here yet .. */ 1269} 1270 1271#ifdef CONFIG_SERIAL_SH_SCI_DMA 1272static bool filter(struct dma_chan *chan, void *slave) 1273{ 1274 struct sh_dmae_slave *param = slave; 1275 1276 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1277 param->slave_id); 1278 1279 if (param->dma_dev == chan->device->dev) { 1280 chan->private = param; 1281 return true; 1282 } else { 1283 return false; 1284 } 1285} 1286 1287static void rx_timer_fn(unsigned long arg) 1288{ 1289 struct sci_port *s = (struct sci_port *)arg; 1290 struct uart_port *port = &s->port; 1291 u16 scr = sci_in(port, SCSCR); 1292 1293 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1294 scr &= ~0x4000; 1295 enable_irq(s->irqs[1]); 1296 } 1297 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE); 1298 dev_dbg(port->dev, "DMA Rx timed out\n"); 1299 schedule_work(&s->work_rx); 1300} 1301 1302static void sci_request_dma(struct uart_port *port) 1303{ 1304 struct sci_port *s = to_sci_port(port); 1305 struct sh_dmae_slave *param; 1306 struct dma_chan *chan; 1307 dma_cap_mask_t mask; 1308 int nent; 1309 1310 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__, 1311 port->line, s->dma_dev); 1312 1313 if (!s->dma_dev) 1314 return; 1315 1316 dma_cap_zero(mask); 1317 dma_cap_set(DMA_SLAVE, mask); 1318 1319 param = &s->param_tx; 1320 1321 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1322 param->slave_id = s->slave_tx; 1323 param->dma_dev = s->dma_dev; 1324 1325 s->cookie_tx = -EINVAL; 1326 chan = dma_request_channel(mask, filter, param); 1327 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1328 if (chan) { 1329 s->chan_tx = chan; 1330 sg_init_table(&s->sg_tx, 1); 1331 /* UART circular tx buffer is an aligned page. */ 1332 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1333 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1334 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); 1335 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1336 if (!nent) 1337 sci_tx_dma_release(s, false); 1338 else 1339 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1340 sg_dma_len(&s->sg_tx), 1341 port->state->xmit.buf, sg_dma_address(&s->sg_tx)); 1342 1343 s->sg_len_tx = nent; 1344 1345 INIT_WORK(&s->work_tx, work_fn_tx); 1346 } 1347 1348 param = &s->param_rx; 1349 1350 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1351 param->slave_id = s->slave_rx; 1352 param->dma_dev = s->dma_dev; 1353 1354 chan = dma_request_channel(mask, filter, param); 1355 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1356 if (chan) { 1357 dma_addr_t dma[2]; 1358 void *buf[2]; 1359 int i; 1360 1361 s->chan_rx = chan; 1362 1363 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1364 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1365 &dma[0], GFP_KERNEL); 1366 1367 if (!buf[0]) { 1368 dev_warn(port->dev, 1369 "failed to allocate dma buffer, using PIO\n"); 1370 sci_rx_dma_release(s, true); 1371 return; 1372 } 1373 1374 buf[1] = buf[0] + s->buf_len_rx; 1375 dma[1] = dma[0] + s->buf_len_rx; 1376 1377 for (i = 0; i < 2; i++) { 1378 struct scatterlist *sg = &s->sg_rx[i]; 1379 1380 sg_init_table(sg, 1); 1381 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1382 (int)buf[i] & ~PAGE_MASK); 1383 sg_dma_address(sg) = dma[i]; 1384 } 1385 1386 INIT_WORK(&s->work_rx, work_fn_rx); 1387 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1388 1389 sci_submit_rx(s); 1390 } 1391} 1392 1393static void sci_free_dma(struct uart_port *port) 1394{ 1395 struct sci_port *s = to_sci_port(port); 1396 1397 if (!s->dma_dev) 1398 return; 1399 1400 if (s->chan_tx) 1401 sci_tx_dma_release(s, false); 1402 if (s->chan_rx) 1403 sci_rx_dma_release(s, false); 1404} 1405#endif 1406 1407static int sci_startup(struct uart_port *port) 1408{ 1409 struct sci_port *s = to_sci_port(port); 1410 1411 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1412 1413 if (s->enable) 1414 s->enable(port); 1415 1416 sci_request_irq(s); 1417#ifdef CONFIG_SERIAL_SH_SCI_DMA 1418 sci_request_dma(port); 1419#endif 1420 sci_start_tx(port); 1421 sci_start_rx(port); 1422 1423 return 0; 1424} 1425 1426static void sci_shutdown(struct uart_port *port) 1427{ 1428 struct sci_port *s = to_sci_port(port); 1429 1430 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1431 1432 sci_stop_rx(port); 1433 sci_stop_tx(port); 1434#ifdef CONFIG_SERIAL_SH_SCI_DMA 1435 sci_free_dma(port); 1436#endif 1437 sci_free_irq(s); 1438 1439 if (s->disable) 1440 s->disable(port); 1441} 1442 1443static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1444 struct ktermios *old) 1445{ 1446#ifdef CONFIG_SERIAL_SH_SCI_DMA 1447 struct sci_port *s = to_sci_port(port); 1448#endif 1449 unsigned int status, baud, smr_val, max_baud; 1450 int t = -1; 1451 u16 scfcr = 0; 1452 1453 /* 1454 * earlyprintk comes here early on with port->uartclk set to zero. 1455 * the clock framework is not up and running at this point so here 1456 * we assume that 115200 is the maximum baud rate. please note that 1457 * the baud rate is not programmed during earlyprintk - it is assumed 1458 * that the previous boot loader has enabled required clocks and 1459 * setup the baud rate generator hardware for us already. 1460 */ 1461 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1462 1463 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1464 if (likely(baud && port->uartclk)) 1465 t = SCBRR_VALUE(baud, port->uartclk); 1466 1467 do { 1468 status = sci_in(port, SCxSR); 1469 } while (!(status & SCxSR_TEND(port))); 1470 1471 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1472 1473 if (port->type != PORT_SCI) 1474 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST); 1475 1476 smr_val = sci_in(port, SCSMR) & 3; 1477 if ((termios->c_cflag & CSIZE) == CS7) 1478 smr_val |= 0x40; 1479 if (termios->c_cflag & PARENB) 1480 smr_val |= 0x20; 1481 if (termios->c_cflag & PARODD) 1482 smr_val |= 0x30; 1483 if (termios->c_cflag & CSTOPB) 1484 smr_val |= 0x08; 1485 1486 uart_update_timeout(port, termios->c_cflag, baud); 1487 1488 sci_out(port, SCSMR, smr_val); 1489 1490 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, 1491 SCSCR_INIT(port)); 1492 1493 if (t > 0) { 1494 if (t >= 256) { 1495 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 1496 t >>= 2; 1497 } else 1498 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); 1499 1500 sci_out(port, SCBRR, t); 1501 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1502 } 1503 1504 sci_init_pins(port, termios->c_cflag); 1505 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); 1506 1507 sci_out(port, SCSCR, SCSCR_INIT(port)); 1508 1509#ifdef CONFIG_SERIAL_SH_SCI_DMA 1510 /* 1511 * Calculate delay for 1.5 DMA buffers: see 1512 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1513 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1514 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1515 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1516 * sizes), but it has been found out experimentally, that this is not 1517 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1518 * as a minimum seem to work perfectly. 1519 */ 1520 if (s->chan_rx) { 1521 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1522 port->fifosize / 2; 1523 dev_dbg(port->dev, 1524 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1525 s->rx_timeout * 1000 / HZ, port->timeout); 1526 if (s->rx_timeout < msecs_to_jiffies(20)) 1527 s->rx_timeout = msecs_to_jiffies(20); 1528 } 1529#endif 1530 1531 if ((termios->c_cflag & CREAD) != 0) 1532 sci_start_rx(port); 1533} 1534 1535static const char *sci_type(struct uart_port *port) 1536{ 1537 switch (port->type) { 1538 case PORT_IRDA: 1539 return "irda"; 1540 case PORT_SCI: 1541 return "sci"; 1542 case PORT_SCIF: 1543 return "scif"; 1544 case PORT_SCIFA: 1545 return "scifa"; 1546 case PORT_SCIFB: 1547 return "scifb"; 1548 } 1549 1550 return NULL; 1551} 1552 1553static void sci_release_port(struct uart_port *port) 1554{ 1555 /* Nothing here yet .. */ 1556} 1557 1558static int sci_request_port(struct uart_port *port) 1559{ 1560 /* Nothing here yet .. */ 1561 return 0; 1562} 1563 1564static void sci_config_port(struct uart_port *port, int flags) 1565{ 1566 struct sci_port *s = to_sci_port(port); 1567 1568 port->type = s->type; 1569 1570 if (port->membase) 1571 return; 1572 1573 if (port->flags & UPF_IOREMAP) { 1574 port->membase = ioremap_nocache(port->mapbase, 0x40); 1575 1576 if (IS_ERR(port->membase)) 1577 dev_err(port->dev, "can't remap port#%d\n", port->line); 1578 } else { 1579 /* 1580 * For the simple (and majority of) cases where we don't 1581 * need to do any remapping, just cast the cookie 1582 * directly. 1583 */ 1584 port->membase = (void __iomem *)port->mapbase; 1585 } 1586} 1587 1588static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 1589{ 1590 struct sci_port *s = to_sci_port(port); 1591 1592 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 1593 return -EINVAL; 1594 if (ser->baud_base < 2400) 1595 /* No paper tape reader for Mitch.. */ 1596 return -EINVAL; 1597 1598 return 0; 1599} 1600 1601static struct uart_ops sci_uart_ops = { 1602 .tx_empty = sci_tx_empty, 1603 .set_mctrl = sci_set_mctrl, 1604 .get_mctrl = sci_get_mctrl, 1605 .start_tx = sci_start_tx, 1606 .stop_tx = sci_stop_tx, 1607 .stop_rx = sci_stop_rx, 1608 .enable_ms = sci_enable_ms, 1609 .break_ctl = sci_break_ctl, 1610 .startup = sci_startup, 1611 .shutdown = sci_shutdown, 1612 .set_termios = sci_set_termios, 1613 .type = sci_type, 1614 .release_port = sci_release_port, 1615 .request_port = sci_request_port, 1616 .config_port = sci_config_port, 1617 .verify_port = sci_verify_port, 1618#ifdef CONFIG_CONSOLE_POLL 1619 .poll_get_char = sci_poll_get_char, 1620 .poll_put_char = sci_poll_put_char, 1621#endif 1622}; 1623 1624static int __devinit sci_init_single(struct platform_device *dev, 1625 struct sci_port *sci_port, 1626 unsigned int index, 1627 struct plat_sci_port *p) 1628{ 1629 struct uart_port *port = &sci_port->port; 1630 1631 port->ops = &sci_uart_ops; 1632 port->iotype = UPIO_MEM; 1633 port->line = index; 1634 1635 switch (p->type) { 1636 case PORT_SCIFB: 1637 port->fifosize = 256; 1638 break; 1639 case PORT_SCIFA: 1640 port->fifosize = 64; 1641 break; 1642 case PORT_SCIF: 1643 port->fifosize = 16; 1644 break; 1645 default: 1646 port->fifosize = 1; 1647 break; 1648 } 1649 1650 if (dev) { 1651 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 1652 if (IS_ERR(sci_port->iclk)) { 1653 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 1654 if (IS_ERR(sci_port->iclk)) { 1655 dev_err(&dev->dev, "can't get iclk\n"); 1656 return PTR_ERR(sci_port->iclk); 1657 } 1658 } 1659 1660 /* 1661 * The function clock is optional, ignore it if we can't 1662 * find it. 1663 */ 1664 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 1665 if (IS_ERR(sci_port->fclk)) 1666 sci_port->fclk = NULL; 1667 1668 sci_port->enable = sci_clk_enable; 1669 sci_port->disable = sci_clk_disable; 1670 port->dev = &dev->dev; 1671 } 1672 1673 sci_port->break_timer.data = (unsigned long)sci_port; 1674 sci_port->break_timer.function = sci_break_timer; 1675 init_timer(&sci_port->break_timer); 1676 1677 port->mapbase = p->mapbase; 1678 port->membase = p->membase; 1679 1680 port->irq = p->irqs[SCIx_TXI_IRQ]; 1681 port->flags = p->flags; 1682 sci_port->type = port->type = p->type; 1683 1684#ifdef CONFIG_SERIAL_SH_SCI_DMA 1685 sci_port->dma_dev = p->dma_dev; 1686 sci_port->slave_tx = p->dma_slave_tx; 1687 sci_port->slave_rx = p->dma_slave_rx; 1688 1689 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__, 1690 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); 1691#endif 1692 1693 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); 1694 return 0; 1695} 1696 1697#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1698static struct tty_driver *serial_console_device(struct console *co, int *index) 1699{ 1700 struct uart_driver *p = &sci_uart_driver; 1701 *index = co->index; 1702 return p->tty_driver; 1703} 1704 1705static void serial_console_putchar(struct uart_port *port, int ch) 1706{ 1707 sci_poll_put_char(port, ch); 1708} 1709 1710/* 1711 * Print a string to the serial port trying not to disturb 1712 * any possible real use of the port... 1713 */ 1714static void serial_console_write(struct console *co, const char *s, 1715 unsigned count) 1716{ 1717 struct uart_port *port = co->data; 1718 struct sci_port *sci_port = to_sci_port(port); 1719 unsigned short bits; 1720 1721 if (sci_port->enable) 1722 sci_port->enable(port); 1723 1724 uart_console_write(port, s, count, serial_console_putchar); 1725 1726 /* wait until fifo is empty and last bit has been transmitted */ 1727 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 1728 while ((sci_in(port, SCxSR) & bits) != bits) 1729 cpu_relax(); 1730 1731 if (sci_port->disable) 1732 sci_port->disable(port); 1733} 1734 1735static int __devinit serial_console_setup(struct console *co, char *options) 1736{ 1737 struct sci_port *sci_port; 1738 struct uart_port *port; 1739 int baud = 115200; 1740 int bits = 8; 1741 int parity = 'n'; 1742 int flow = 'n'; 1743 int ret; 1744 1745 /* 1746 * Check whether an invalid uart number has been specified, and 1747 * if so, search for the first available port that does have 1748 * console support. 1749 */ 1750 if (co->index >= SCI_NPORTS) 1751 co->index = 0; 1752 1753 if (co->data) { 1754 port = co->data; 1755 sci_port = to_sci_port(port); 1756 } else { 1757 sci_port = &sci_ports[co->index]; 1758 port = &sci_port->port; 1759 co->data = port; 1760 } 1761 1762 /* 1763 * Also need to check port->type, we don't actually have any 1764 * UPIO_PORT ports, but uart_report_port() handily misreports 1765 * it anyways if we don't have a port available by the time this is 1766 * called. 1767 */ 1768 if (!port->type) 1769 return -ENODEV; 1770 1771 sci_config_port(port, 0); 1772 1773 if (sci_port->enable) 1774 sci_port->enable(port); 1775 1776 if (options) 1777 uart_parse_options(options, &baud, &parity, &bits, &flow); 1778 1779 ret = uart_set_options(port, co, baud, parity, bits, flow); 1780#if defined(__H8300H__) || defined(__H8300S__) 1781 /* disable rx interrupt */ 1782 if (ret == 0) 1783 sci_stop_rx(port); 1784#endif 1785 /* TODO: disable clock */ 1786 return ret; 1787} 1788 1789static struct console serial_console = { 1790 .name = "ttySC", 1791 .device = serial_console_device, 1792 .write = serial_console_write, 1793 .setup = serial_console_setup, 1794 .flags = CON_PRINTBUFFER, 1795 .index = -1, 1796}; 1797 1798static int __init sci_console_init(void) 1799{ 1800 register_console(&serial_console); 1801 return 0; 1802} 1803console_initcall(sci_console_init); 1804 1805static struct sci_port early_serial_port; 1806static struct console early_serial_console = { 1807 .name = "early_ttySC", 1808 .write = serial_console_write, 1809 .flags = CON_PRINTBUFFER, 1810}; 1811static char early_serial_buf[32]; 1812 1813#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 1814 1815#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 1816#define SCI_CONSOLE (&serial_console) 1817#else 1818#define SCI_CONSOLE 0 1819#endif 1820 1821static char banner[] __initdata = 1822 KERN_INFO "SuperH SCI(F) driver initialized\n"; 1823 1824static struct uart_driver sci_uart_driver = { 1825 .owner = THIS_MODULE, 1826 .driver_name = "sci", 1827 .dev_name = "ttySC", 1828 .major = SCI_MAJOR, 1829 .minor = SCI_MINOR_START, 1830 .nr = SCI_NPORTS, 1831 .cons = SCI_CONSOLE, 1832}; 1833 1834 1835static int sci_remove(struct platform_device *dev) 1836{ 1837 struct sh_sci_priv *priv = platform_get_drvdata(dev); 1838 struct sci_port *p; 1839 unsigned long flags; 1840 1841 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); 1842 1843 spin_lock_irqsave(&priv->lock, flags); 1844 list_for_each_entry(p, &priv->ports, node) { 1845 uart_remove_one_port(&sci_uart_driver, &p->port); 1846 clk_put(p->iclk); 1847 clk_put(p->fclk); 1848 } 1849 spin_unlock_irqrestore(&priv->lock, flags); 1850 1851 kfree(priv); 1852 return 0; 1853} 1854 1855static int __devinit sci_probe_single(struct platform_device *dev, 1856 unsigned int index, 1857 struct plat_sci_port *p, 1858 struct sci_port *sciport) 1859{ 1860 struct sh_sci_priv *priv = platform_get_drvdata(dev); 1861 unsigned long flags; 1862 int ret; 1863 1864 /* Sanity check */ 1865 if (unlikely(index >= SCI_NPORTS)) { 1866 dev_notice(&dev->dev, "Attempting to register port " 1867 "%d when only %d are available.\n", 1868 index+1, SCI_NPORTS); 1869 dev_notice(&dev->dev, "Consider bumping " 1870 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 1871 return 0; 1872 } 1873 1874 ret = sci_init_single(dev, sciport, index, p); 1875 if (ret) 1876 return ret; 1877 1878 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 1879 if (ret) 1880 return ret; 1881 1882 INIT_LIST_HEAD(&sciport->node); 1883 1884 spin_lock_irqsave(&priv->lock, flags); 1885 list_add(&sciport->node, &priv->ports); 1886 spin_unlock_irqrestore(&priv->lock, flags); 1887 1888 return 0; 1889} 1890 1891/* 1892 * Register a set of serial devices attached to a platform device. The 1893 * list is terminated with a zero flags entry, which means we expect 1894 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need 1895 * remapping (such as sh64) should also set UPF_IOREMAP. 1896 */ 1897static int __devinit sci_probe(struct platform_device *dev) 1898{ 1899 struct plat_sci_port *p = dev->dev.platform_data; 1900 struct sh_sci_priv *priv; 1901 int i, ret = -EINVAL; 1902 1903#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1904 if (is_early_platform_device(dev)) { 1905 if (dev->id == -1) 1906 return -ENOTSUPP; 1907 early_serial_console.index = dev->id; 1908 early_serial_console.data = &early_serial_port.port; 1909 sci_init_single(NULL, &early_serial_port, dev->id, p); 1910 serial_console_setup(&early_serial_console, early_serial_buf); 1911 if (!strstr(early_serial_buf, "keep")) 1912 early_serial_console.flags |= CON_BOOT; 1913 register_console(&early_serial_console); 1914 return 0; 1915 } 1916#endif 1917 1918 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1919 if (!priv) 1920 return -ENOMEM; 1921 1922 INIT_LIST_HEAD(&priv->ports); 1923 spin_lock_init(&priv->lock); 1924 platform_set_drvdata(dev, priv); 1925 1926 priv->clk_nb.notifier_call = sci_notifier; 1927 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); 1928 1929 if (dev->id != -1) { 1930 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]); 1931 if (ret) 1932 goto err_unreg; 1933 } else { 1934 for (i = 0; p && p->flags != 0; p++, i++) { 1935 ret = sci_probe_single(dev, i, p, &sci_ports[i]); 1936 if (ret) 1937 goto err_unreg; 1938 } 1939 } 1940 1941#ifdef CONFIG_SH_STANDARD_BIOS 1942 sh_bios_gdb_detach(); 1943#endif 1944 1945 return 0; 1946 1947err_unreg: 1948 sci_remove(dev); 1949 return ret; 1950} 1951 1952static int sci_suspend(struct device *dev) 1953{ 1954 struct sh_sci_priv *priv = dev_get_drvdata(dev); 1955 struct sci_port *p; 1956 unsigned long flags; 1957 1958 spin_lock_irqsave(&priv->lock, flags); 1959 list_for_each_entry(p, &priv->ports, node) 1960 uart_suspend_port(&sci_uart_driver, &p->port); 1961 spin_unlock_irqrestore(&priv->lock, flags); 1962 1963 return 0; 1964} 1965 1966static int sci_resume(struct device *dev) 1967{ 1968 struct sh_sci_priv *priv = dev_get_drvdata(dev); 1969 struct sci_port *p; 1970 unsigned long flags; 1971 1972 spin_lock_irqsave(&priv->lock, flags); 1973 list_for_each_entry(p, &priv->ports, node) 1974 uart_resume_port(&sci_uart_driver, &p->port); 1975 spin_unlock_irqrestore(&priv->lock, flags); 1976 1977 return 0; 1978} 1979 1980static const struct dev_pm_ops sci_dev_pm_ops = { 1981 .suspend = sci_suspend, 1982 .resume = sci_resume, 1983}; 1984 1985static struct platform_driver sci_driver = { 1986 .probe = sci_probe, 1987 .remove = sci_remove, 1988 .driver = { 1989 .name = "sh-sci", 1990 .owner = THIS_MODULE, 1991 .pm = &sci_dev_pm_ops, 1992 }, 1993}; 1994 1995static int __init sci_init(void) 1996{ 1997 int ret; 1998 1999 printk(banner); 2000 2001 ret = uart_register_driver(&sci_uart_driver); 2002 if (likely(ret == 0)) { 2003 ret = platform_driver_register(&sci_driver); 2004 if (unlikely(ret)) 2005 uart_unregister_driver(&sci_uart_driver); 2006 } 2007 2008 return ret; 2009} 2010 2011static void __exit sci_exit(void) 2012{ 2013 platform_driver_unregister(&sci_driver); 2014 uart_unregister_driver(&sci_uart_driver); 2015} 2016 2017#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2018early_platform_init_buffer("earlyprintk", &sci_driver, 2019 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2020#endif 2021module_init(sci_init); 2022module_exit(sci_exit); 2023 2024MODULE_LICENSE("GPL"); 2025MODULE_ALIAS("platform:sh-sci"); 2026