1/* 2 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl) 3 * 4 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net) 5 * 6 * Adapted from mac_scsinew.c: 7 */ 8/* 9 * Generic Macintosh NCR5380 driver 10 * 11 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov> 12 * 13 * derived in part from: 14 */ 15/* 16 * Generic Generic NCR5380 driver 17 * 18 * Copyright 1995, Russell King 19 * 20 * ALPHA RELEASE 1. 21 * 22 * For more information, please consult 23 * 24 * NCR 5380 Family 25 * SCSI Protocol Controller 26 * Databook 27 * 28 * NCR Microelectronics 29 * 1635 Aeroplaza Drive 30 * Colorado Springs, CO 80916 31 * 1+ (719) 578-3400 32 * 1+ (800) 334-5454 33 */ 34 35 36/* 37 * This is from mac_scsi.h, but hey, maybe this is useful for Sun3 too! :) 38 * 39 * Options : 40 * 41 * PARITY - enable parity checking. Not supported. 42 * 43 * SCSI2 - enable support for SCSI-II tagged queueing. Untested. 44 * 45 * USLEEP - enable support for devices that don't disconnect. Untested. 46 */ 47 48/* 49 * $Log: sun3_NCR5380.c,v $ 50 */ 51 52#define AUTOSENSE 53 54#include <linux/types.h> 55#include <linux/stddef.h> 56#include <linux/ctype.h> 57#include <linux/delay.h> 58 59#include <linux/module.h> 60#include <linux/signal.h> 61#include <linux/ioport.h> 62#include <linux/init.h> 63#include <linux/blkdev.h> 64 65#include <asm/io.h> 66#include <asm/system.h> 67 68#include <asm/sun3ints.h> 69#include <asm/dvma.h> 70#include <asm/idprom.h> 71#include <asm/machines.h> 72 73/* dma on! */ 74#define REAL_DMA 75 76#include "scsi.h" 77#include "initio.h" 78#include <scsi/scsi_host.h> 79#include "sun3_scsi.h" 80 81static void NCR5380_print(struct Scsi_Host *instance); 82 83/* #define OLDDMA */ 84 85#define USE_WRAPPER 86/*#define RESET_BOOT */ 87#define DRIVER_SETUP 88 89#define NDEBUG 0 90 91/* 92 * BUG can be used to trigger a strange code-size related hang on 2.1 kernels 93 */ 94#ifdef BUG 95#undef RESET_BOOT 96#undef DRIVER_SETUP 97#endif 98 99/* #define SUPPORT_TAGS */ 100 101#define ENABLE_IRQ() enable_irq( IRQ_SUN3_SCSI ); 102 103 104static irqreturn_t scsi_sun3_intr(int irq, void *dummy); 105static inline unsigned char sun3scsi_read(int reg); 106static inline void sun3scsi_write(int reg, int value); 107 108static int setup_can_queue = -1; 109module_param(setup_can_queue, int, 0); 110static int setup_cmd_per_lun = -1; 111module_param(setup_cmd_per_lun, int, 0); 112static int setup_sg_tablesize = -1; 113module_param(setup_sg_tablesize, int, 0); 114#ifdef SUPPORT_TAGS 115static int setup_use_tagged_queuing = -1; 116module_param(setup_use_tagged_queuing, int, 0); 117#endif 118static int setup_hostid = -1; 119module_param(setup_hostid, int, 0); 120 121static struct scsi_cmnd *sun3_dma_setup_done = NULL; 122 123#define AFTER_RESET_DELAY (HZ/2) 124 125/* ms to wait after hitting dma regs */ 126#define SUN3_DMA_DELAY 10 127 128/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */ 129#define SUN3_DVMA_BUFSIZE 0xe000 130 131/* minimum number of bytes to do dma on */ 132#define SUN3_DMA_MINSIZE 128 133 134static volatile unsigned char *sun3_scsi_regp; 135static volatile struct sun3_dma_regs *dregs; 136#ifdef OLDDMA 137static unsigned char *dmabuf = NULL; /* dma memory buffer */ 138#endif 139static struct sun3_udc_regs *udc_regs = NULL; 140static unsigned char *sun3_dma_orig_addr = NULL; 141static unsigned long sun3_dma_orig_count = 0; 142static int sun3_dma_active = 0; 143static unsigned long last_residual = 0; 144 145/* 146 * NCR 5380 register access functions 147 */ 148 149static inline unsigned char sun3scsi_read(int reg) 150{ 151 return( sun3_scsi_regp[reg] ); 152} 153 154static inline void sun3scsi_write(int reg, int value) 155{ 156 sun3_scsi_regp[reg] = value; 157} 158 159/* dma controller register access functions */ 160 161static inline unsigned short sun3_udc_read(unsigned char reg) 162{ 163 unsigned short ret; 164 165 dregs->udc_addr = UDC_CSR; 166 udelay(SUN3_DMA_DELAY); 167 ret = dregs->udc_data; 168 udelay(SUN3_DMA_DELAY); 169 170 return ret; 171} 172 173static inline void sun3_udc_write(unsigned short val, unsigned char reg) 174{ 175 dregs->udc_addr = reg; 176 udelay(SUN3_DMA_DELAY); 177 dregs->udc_data = val; 178 udelay(SUN3_DMA_DELAY); 179} 180 181static struct Scsi_Host *default_instance; 182 183/* 184 * Function : int sun3scsi_detect(struct scsi_host_template * tpnt) 185 * 186 * Purpose : initializes mac NCR5380 driver based on the 187 * command line / compile time port and irq definitions. 188 * 189 * Inputs : tpnt - template for this SCSI adapter. 190 * 191 * Returns : 1 if a host adapter was found, 0 if not. 192 * 193 */ 194 195int sun3scsi_detect(struct scsi_host_template * tpnt) 196{ 197 unsigned long ioaddr; 198 static int called = 0; 199 struct Scsi_Host *instance; 200 201 /* check that this machine has an onboard 5380 */ 202 switch(idprom->id_machtype) { 203 case SM_SUN3|SM_3_50: 204 case SM_SUN3|SM_3_60: 205 break; 206 207 default: 208 return 0; 209 } 210 211 if(called) 212 return 0; 213 214 tpnt->proc_name = "Sun3 5380 SCSI"; 215 216 /* setup variables */ 217 tpnt->can_queue = 218 (setup_can_queue > 0) ? setup_can_queue : CAN_QUEUE; 219 tpnt->cmd_per_lun = 220 (setup_cmd_per_lun > 0) ? setup_cmd_per_lun : CMD_PER_LUN; 221 tpnt->sg_tablesize = 222 (setup_sg_tablesize >= 0) ? setup_sg_tablesize : SG_TABLESIZE; 223 224 if (setup_hostid >= 0) 225 tpnt->this_id = setup_hostid; 226 else { 227 /* use 7 as default */ 228 tpnt->this_id = 7; 229 } 230 231 ioaddr = (unsigned long)ioremap(IOBASE_SUN3_SCSI, PAGE_SIZE); 232 sun3_scsi_regp = (unsigned char *)ioaddr; 233 234 dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8); 235 236 if((udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs))) 237 == NULL) { 238 printk("SUN3 Scsi couldn't allocate DVMA memory!\n"); 239 return 0; 240 } 241#ifdef OLDDMA 242 if((dmabuf = dvma_malloc_align(SUN3_DVMA_BUFSIZE, 0x10000)) == NULL) { 243 printk("SUN3 Scsi couldn't allocate DVMA memory!\n"); 244 return 0; 245 } 246#endif 247#ifdef SUPPORT_TAGS 248 if (setup_use_tagged_queuing < 0) 249 setup_use_tagged_queuing = USE_TAGGED_QUEUING; 250#endif 251 252 instance = scsi_register (tpnt, sizeof(struct NCR5380_hostdata)); 253 if(instance == NULL) 254 return 0; 255 256 default_instance = instance; 257 258 instance->io_port = (unsigned long) ioaddr; 259 instance->irq = IRQ_SUN3_SCSI; 260 261 NCR5380_init(instance, 0); 262 263 instance->n_io_port = 32; 264 265 ((struct NCR5380_hostdata *)instance->hostdata)->ctrl = 0; 266 267 if (request_irq(instance->irq, scsi_sun3_intr, 268 0, "Sun3SCSI-5380", instance)) { 269#ifndef REAL_DMA 270 printk("scsi%d: IRQ%d not free, interrupts disabled\n", 271 instance->host_no, instance->irq); 272 instance->irq = SCSI_IRQ_NONE; 273#else 274 printk("scsi%d: IRQ%d not free, bailing out\n", 275 instance->host_no, instance->irq); 276 return 0; 277#endif 278 } 279 280 printk("scsi%d: Sun3 5380 at port %lX irq", instance->host_no, instance->io_port); 281 if (instance->irq == SCSI_IRQ_NONE) 282 printk ("s disabled"); 283 else 284 printk (" %d", instance->irq); 285 printk(" options CAN_QUEUE=%d CMD_PER_LUN=%d release=%d", 286 instance->can_queue, instance->cmd_per_lun, 287 SUN3SCSI_PUBLIC_RELEASE); 288 printk("\nscsi%d:", instance->host_no); 289 NCR5380_print_options(instance); 290 printk("\n"); 291 292 dregs->csr = 0; 293 udelay(SUN3_DMA_DELAY); 294 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; 295 udelay(SUN3_DMA_DELAY); 296 dregs->fifo_count = 0; 297 298 called = 1; 299 300#ifdef RESET_BOOT 301 sun3_scsi_reset_boot(instance); 302#endif 303 304 return 1; 305} 306 307int sun3scsi_release (struct Scsi_Host *shpnt) 308{ 309 if (shpnt->irq != SCSI_IRQ_NONE) 310 free_irq(shpnt->irq, shpnt); 311 312 iounmap((void *)sun3_scsi_regp); 313 314 return 0; 315} 316 317#ifdef RESET_BOOT 318/* 319 * Our 'bus reset on boot' function 320 */ 321 322static void sun3_scsi_reset_boot(struct Scsi_Host *instance) 323{ 324 unsigned long end; 325 326 NCR5380_local_declare(); 327 NCR5380_setup(instance); 328 329 /* 330 * Do a SCSI reset to clean up the bus during initialization. No 331 * messing with the queues, interrupts, or locks necessary here. 332 */ 333 334 printk( "Sun3 SCSI: resetting the SCSI bus..." ); 335 336 /* switch off SCSI IRQ - catch an interrupt without IRQ bit set else */ 337// sun3_disable_irq( IRQ_SUN3_SCSI ); 338 339 /* get in phase */ 340 NCR5380_write( TARGET_COMMAND_REG, 341 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); 342 343 /* assert RST */ 344 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST ); 345 346 /* The min. reset hold time is 25us, so 40us should be enough */ 347 udelay( 50 ); 348 349 /* reset RST and interrupt */ 350 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE ); 351 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); 352 353 for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); ) 354 barrier(); 355 356 /* switch on SCSI IRQ again */ 357// sun3_enable_irq( IRQ_SUN3_SCSI ); 358 359 printk( " done\n" ); 360} 361#endif 362 363const char * sun3scsi_info (struct Scsi_Host *spnt) { 364 return ""; 365} 366 367// safe bits for the CSR 368#define CSR_GOOD 0x060f 369 370static irqreturn_t scsi_sun3_intr(int irq, void *dummy) 371{ 372 unsigned short csr = dregs->csr; 373 int handled = 0; 374 375 if(csr & ~CSR_GOOD) { 376 if(csr & CSR_DMA_BUSERR) { 377 printk("scsi%d: bus error in dma\n", default_instance->host_no); 378 } 379 380 if(csr & CSR_DMA_CONFLICT) { 381 printk("scsi%d: dma conflict\n", default_instance->host_no); 382 } 383 handled = 1; 384 } 385 386 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { 387 NCR5380_intr(irq, dummy); 388 handled = 1; 389 } 390 391 return IRQ_RETVAL(handled); 392} 393 394/* 395 * Debug stuff - to be called on NMI, or sysrq key. Use at your own risk; 396 * reentering NCR5380_print_status seems to have ugly side effects 397 */ 398 399/* this doesn't seem to get used at all -- sam */ 400 401 402/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */ 403static unsigned long sun3scsi_dma_setup(void *data, unsigned long count, int write_flag) 404{ 405#ifdef OLDDMA 406 if(write_flag) 407 memcpy(dmabuf, data, count); 408 else { 409 sun3_dma_orig_addr = data; 410 sun3_dma_orig_count = count; 411 } 412#else 413 void *addr; 414 415 if(sun3_dma_orig_addr != NULL) 416 dvma_unmap(sun3_dma_orig_addr); 417 418// addr = sun3_dvma_page((unsigned long)data, (unsigned long)dmabuf); 419 addr = (void *)dvma_map((unsigned long) data, count); 420 421 sun3_dma_orig_addr = addr; 422 sun3_dma_orig_count = count; 423#endif 424 dregs->fifo_count = 0; 425 sun3_udc_write(UDC_RESET, UDC_CSR); 426 427 /* reset fifo */ 428 dregs->csr &= ~CSR_FIFO; 429 dregs->csr |= CSR_FIFO; 430 431 /* set direction */ 432 if(write_flag) 433 dregs->csr |= CSR_SEND; 434 else 435 dregs->csr &= ~CSR_SEND; 436 437 /* byte count for fifo */ 438 dregs->fifo_count = count; 439 440 sun3_udc_write(UDC_RESET, UDC_CSR); 441 442 /* reset fifo */ 443 dregs->csr &= ~CSR_FIFO; 444 dregs->csr |= CSR_FIFO; 445 446 if(dregs->fifo_count != count) { 447 printk("scsi%d: fifo_mismatch %04x not %04x\n", 448 default_instance->host_no, dregs->fifo_count, 449 (unsigned int) count); 450 NCR5380_print(default_instance); 451 } 452 453 /* setup udc */ 454#ifdef OLDDMA 455 udc_regs->addr_hi = ((dvma_vtob(dmabuf) & 0xff0000) >> 8); 456 udc_regs->addr_lo = (dvma_vtob(dmabuf) & 0xffff); 457#else 458 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8); 459 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff); 460#endif 461 udc_regs->count = count/2; /* count in words */ 462 udc_regs->mode_hi = UDC_MODE_HIWORD; 463 if(write_flag) { 464 if(count & 1) 465 udc_regs->count++; 466 udc_regs->mode_lo = UDC_MODE_LSEND; 467 udc_regs->rsel = UDC_RSEL_SEND; 468 } else { 469 udc_regs->mode_lo = UDC_MODE_LRECV; 470 udc_regs->rsel = UDC_RSEL_RECV; 471 } 472 473 /* announce location of regs block */ 474 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8), 475 UDC_CHN_HI); 476 477 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO); 478 479 /* set dma master on */ 480 sun3_udc_write(0xd, UDC_MODE); 481 482 /* interrupt enable */ 483 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR); 484 485 return count; 486 487} 488 489static inline unsigned long sun3scsi_dma_count(struct Scsi_Host *instance) 490{ 491 unsigned short resid; 492 493 dregs->udc_addr = 0x32; 494 udelay(SUN3_DMA_DELAY); 495 resid = dregs->udc_data; 496 udelay(SUN3_DMA_DELAY); 497 resid *= 2; 498 499 return (unsigned long) resid; 500} 501 502static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance) 503{ 504 return last_residual; 505} 506 507static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted, 508 struct scsi_cmnd *cmd, 509 int write_flag) 510{ 511 if (cmd->request->cmd_type == REQ_TYPE_FS) 512 return wanted; 513 else 514 return 0; 515} 516 517static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data) 518{ 519 520 sun3_udc_write(UDC_CHN_START, UDC_CSR); 521 522 return 0; 523} 524 525/* clean up after our dma is done */ 526static int sun3scsi_dma_finish(int write_flag) 527{ 528 unsigned short count; 529 unsigned short fifo; 530 int ret = 0; 531 532 sun3_dma_active = 0; 533 // check to empty the fifo on a read 534 if(!write_flag) { 535 int tmo = 20000; /* .2 sec */ 536 537 while(1) { 538 if(dregs->csr & CSR_FIFO_EMPTY) 539 break; 540 541 if(--tmo <= 0) { 542 printk("sun3scsi: fifo failed to empty!\n"); 543 return 1; 544 } 545 udelay(10); 546 } 547 } 548 549 count = sun3scsi_dma_count(default_instance); 550#ifdef OLDDMA 551 552 /* if we've finished a read, copy out the data we read */ 553 if(sun3_dma_orig_addr) { 554 /* check for residual bytes after dma end */ 555 if(count && (NCR5380_read(BUS_AND_STATUS_REG) & 556 (BASR_PHASE_MATCH | BASR_ACK))) { 557 printk("scsi%d: sun3_scsi_finish: read overrun baby... ", default_instance->host_no); 558 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG)); 559 ret = count; 560 } 561 562 /* copy in what we dma'd no matter what */ 563 memcpy(sun3_dma_orig_addr, dmabuf, sun3_dma_orig_count); 564 sun3_dma_orig_addr = NULL; 565 566 } 567#else 568 569 fifo = dregs->fifo_count; 570 last_residual = fifo; 571 572 /* empty bytes from the fifo which didn't make it */ 573 if((!write_flag) && (count - fifo) == 2) { 574 unsigned short data; 575 unsigned char *vaddr; 576 577 data = dregs->fifo_data; 578 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr); 579 580 vaddr += (sun3_dma_orig_count - fifo); 581 582 vaddr[-2] = (data & 0xff00) >> 8; 583 vaddr[-1] = (data & 0xff); 584 } 585 586 dvma_unmap(sun3_dma_orig_addr); 587 sun3_dma_orig_addr = NULL; 588#endif 589 sun3_udc_write(UDC_RESET, UDC_CSR); 590 dregs->fifo_count = 0; 591 dregs->csr &= ~CSR_SEND; 592 593 /* reset fifo */ 594 dregs->csr &= ~CSR_FIFO; 595 dregs->csr |= CSR_FIFO; 596 597 sun3_dma_setup_done = NULL; 598 599 return ret; 600 601} 602 603#include "sun3_NCR5380.c" 604 605static struct scsi_host_template driver_template = { 606 .name = SUN3_SCSI_NAME, 607 .detect = sun3scsi_detect, 608 .release = sun3scsi_release, 609 .info = sun3scsi_info, 610 .queuecommand = sun3scsi_queue_command, 611 .eh_abort_handler = sun3scsi_abort, 612 .eh_bus_reset_handler = sun3scsi_bus_reset, 613 .can_queue = CAN_QUEUE, 614 .this_id = 7, 615 .sg_tablesize = SG_TABLESIZE, 616 .cmd_per_lun = CMD_PER_LUN, 617 .use_clustering = DISABLE_CLUSTERING 618}; 619 620 621#include "scsi_module.c" 622 623MODULE_LICENSE("GPL"); 624