1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#ifndef __QLA_NX_H 8#define __QLA_NX_H 9 10/* 11 * Following are the states of the Phantom. Phantom will set them and 12 * Host will read to check if the fields are correct. 13*/ 14#define PHAN_INITIALIZE_FAILED 0xffff 15#define PHAN_INITIALIZE_COMPLETE 0xff01 16 17/* Host writes the following to notify that it has done the init-handshake */ 18#define PHAN_INITIALIZE_ACK 0xf00f 19#define PHAN_PEG_RCV_INITIALIZED 0xff01 20 21/*CRB_RELATED*/ 22#define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200) 23#define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X)) 24 25#define CRB_CMDPEG_STATE QLA82XX_REG(0x50) 26#define CRB_RCVPEG_STATE QLA82XX_REG(0x13c) 27#define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54) 28#define CRB_DMA_SHIFT QLA82XX_REG(0xcc) 29 30#define QLA82XX_HW_H0_CH_HUB_ADR 0x05 31#define QLA82XX_HW_H1_CH_HUB_ADR 0x0E 32#define QLA82XX_HW_H2_CH_HUB_ADR 0x03 33#define QLA82XX_HW_H3_CH_HUB_ADR 0x01 34#define QLA82XX_HW_H4_CH_HUB_ADR 0x06 35#define QLA82XX_HW_H5_CH_HUB_ADR 0x07 36#define QLA82XX_HW_H6_CH_HUB_ADR 0x08 37 38/* Hub 0 */ 39#define QLA82XX_HW_MN_CRB_AGT_ADR 0x15 40#define QLA82XX_HW_MS_CRB_AGT_ADR 0x25 41 42/* Hub 1 */ 43#define QLA82XX_HW_PS_CRB_AGT_ADR 0x73 44#define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00 45#define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b 46#define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01 47#define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02 48#define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03 49#define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04 50#define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58 51#define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59 52#define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a 53#define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a 54#define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c 55#define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f 56#define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12 57#define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18 58 59/* Hub 2 */ 60#define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31 61#define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19 62#define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29 63 64#define QLA82XX_HW_SN_CRB_AGT_ADR 0x10 65#define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20 66#define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22 67#define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21 68#define QLA82XX_HW_QM_CRB_AGT_ADR 0x66 69#define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60 70#define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61 71#define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62 72#define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63 73#define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09 74#define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d 75#define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e 76#define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11 77 78/* Hub 3 */ 79#define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A 80#define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50 81#define QLA82XX_HW_EG_CRB_AGT_ADR 0x51 82#define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08 83 84/* Hub 4 */ 85#define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40 86#define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41 87#define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42 88#define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43 89#define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44 90#define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45 91#define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46 92#define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47 93#define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48 94#define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49 95#define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a 96#define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b 97 98/* Hub 5 */ 99#define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40 100#define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41 101#define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42 102#define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43 103 104#define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44 105#define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45 106#define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46 107 108/* Hub 6 */ 109#define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46 110#define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47 111#define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48 112#define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49 113#define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16 114#define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17 115#define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05 116#define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06 117#define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07 118 119/* This field defines PCI/X adr [25:20] of agents on the CRB */ 120/* */ 121#define QLA82XX_HW_PX_MAP_CRB_PH 0 122#define QLA82XX_HW_PX_MAP_CRB_PS 1 123#define QLA82XX_HW_PX_MAP_CRB_MN 2 124#define QLA82XX_HW_PX_MAP_CRB_MS 3 125#define QLA82XX_HW_PX_MAP_CRB_SRE 5 126#define QLA82XX_HW_PX_MAP_CRB_NIU 6 127#define QLA82XX_HW_PX_MAP_CRB_QMN 7 128#define QLA82XX_HW_PX_MAP_CRB_SQN0 8 129#define QLA82XX_HW_PX_MAP_CRB_SQN1 9 130#define QLA82XX_HW_PX_MAP_CRB_SQN2 10 131#define QLA82XX_HW_PX_MAP_CRB_SQN3 11 132#define QLA82XX_HW_PX_MAP_CRB_QMS 12 133#define QLA82XX_HW_PX_MAP_CRB_SQS0 13 134#define QLA82XX_HW_PX_MAP_CRB_SQS1 14 135#define QLA82XX_HW_PX_MAP_CRB_SQS2 15 136#define QLA82XX_HW_PX_MAP_CRB_SQS3 16 137#define QLA82XX_HW_PX_MAP_CRB_PGN0 17 138#define QLA82XX_HW_PX_MAP_CRB_PGN1 18 139#define QLA82XX_HW_PX_MAP_CRB_PGN2 19 140#define QLA82XX_HW_PX_MAP_CRB_PGN3 20 141#define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2 142#define QLA82XX_HW_PX_MAP_CRB_PGND 21 143#define QLA82XX_HW_PX_MAP_CRB_PGNI 22 144#define QLA82XX_HW_PX_MAP_CRB_PGS0 23 145#define QLA82XX_HW_PX_MAP_CRB_PGS1 24 146#define QLA82XX_HW_PX_MAP_CRB_PGS2 25 147#define QLA82XX_HW_PX_MAP_CRB_PGS3 26 148#define QLA82XX_HW_PX_MAP_CRB_PGSD 27 149#define QLA82XX_HW_PX_MAP_CRB_PGSI 28 150#define QLA82XX_HW_PX_MAP_CRB_SN 29 151#define QLA82XX_HW_PX_MAP_CRB_EG 31 152#define QLA82XX_HW_PX_MAP_CRB_PH2 32 153#define QLA82XX_HW_PX_MAP_CRB_PS2 33 154#define QLA82XX_HW_PX_MAP_CRB_CAM 34 155#define QLA82XX_HW_PX_MAP_CRB_CAS0 35 156#define QLA82XX_HW_PX_MAP_CRB_CAS1 36 157#define QLA82XX_HW_PX_MAP_CRB_CAS2 37 158#define QLA82XX_HW_PX_MAP_CRB_C2C0 38 159#define QLA82XX_HW_PX_MAP_CRB_C2C1 39 160#define QLA82XX_HW_PX_MAP_CRB_TIMR 40 161#define QLA82XX_HW_PX_MAP_CRB_RPMX1 42 162#define QLA82XX_HW_PX_MAP_CRB_RPMX2 43 163#define QLA82XX_HW_PX_MAP_CRB_RPMX3 44 164#define QLA82XX_HW_PX_MAP_CRB_RPMX4 45 165#define QLA82XX_HW_PX_MAP_CRB_RPMX5 46 166#define QLA82XX_HW_PX_MAP_CRB_RPMX6 47 167#define QLA82XX_HW_PX_MAP_CRB_RPMX7 48 168#define QLA82XX_HW_PX_MAP_CRB_XDMA 49 169#define QLA82XX_HW_PX_MAP_CRB_I2Q 50 170#define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51 171#define QLA82XX_HW_PX_MAP_CRB_CAS3 52 172#define QLA82XX_HW_PX_MAP_CRB_RPMX0 53 173#define QLA82XX_HW_PX_MAP_CRB_RPMX8 54 174#define QLA82XX_HW_PX_MAP_CRB_RPMX9 55 175#define QLA82XX_HW_PX_MAP_CRB_OCM0 56 176#define QLA82XX_HW_PX_MAP_CRB_OCM1 57 177#define QLA82XX_HW_PX_MAP_CRB_SMB 58 178#define QLA82XX_HW_PX_MAP_CRB_I2C0 59 179#define QLA82XX_HW_PX_MAP_CRB_I2C1 60 180#define QLA82XX_HW_PX_MAP_CRB_LPC 61 181#define QLA82XX_HW_PX_MAP_CRB_PGNC 62 182#define QLA82XX_HW_PX_MAP_CRB_PGR0 63 183#define QLA82XX_HW_PX_MAP_CRB_PGR1 4 184#define QLA82XX_HW_PX_MAP_CRB_PGR2 30 185#define QLA82XX_HW_PX_MAP_CRB_PGR3 41 186 187/* This field defines CRB adr [31:20] of the agents */ 188/* */ 189 190#define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 191 QLA82XX_HW_MN_CRB_AGT_ADR) 192#define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 193 QLA82XX_HW_PH_CRB_AGT_ADR) 194#define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 195 QLA82XX_HW_MS_CRB_AGT_ADR) 196#define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 197 QLA82XX_HW_PS_CRB_AGT_ADR) 198#define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 199 QLA82XX_HW_SS_CRB_AGT_ADR) 200#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 201 QLA82XX_HW_RPMX3_CRB_AGT_ADR) 202#define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 203 QLA82XX_HW_QMS_CRB_AGT_ADR) 204#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 205 QLA82XX_HW_SQGS0_CRB_AGT_ADR) 206#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 207 QLA82XX_HW_SQGS1_CRB_AGT_ADR) 208#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 209 QLA82XX_HW_SQGS2_CRB_AGT_ADR) 210#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 211 QLA82XX_HW_SQGS3_CRB_AGT_ADR) 212#define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 213 QLA82XX_HW_C2C0_CRB_AGT_ADR) 214#define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 215 QLA82XX_HW_C2C1_CRB_AGT_ADR) 216#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 217 QLA82XX_HW_RPMX2_CRB_AGT_ADR) 218#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 219 QLA82XX_HW_RPMX4_CRB_AGT_ADR) 220#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 221 QLA82XX_HW_RPMX7_CRB_AGT_ADR) 222#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 223 QLA82XX_HW_RPMX9_CRB_AGT_ADR) 224#define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 225 QLA82XX_HW_SMB_CRB_AGT_ADR) 226 227#define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 228 QLA82XX_HW_NIU_CRB_AGT_ADR) 229#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 230 QLA82XX_HW_I2C0_CRB_AGT_ADR) 231#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 232 QLA82XX_HW_I2C1_CRB_AGT_ADR) 233 234#define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 235 QLA82XX_HW_SRE_CRB_AGT_ADR) 236#define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 237 QLA82XX_HW_EG_CRB_AGT_ADR) 238#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 239 QLA82XX_HW_RPMX0_CRB_AGT_ADR) 240#define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 241 QLA82XX_HW_QM_CRB_AGT_ADR) 242#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 243 QLA82XX_HW_SQG0_CRB_AGT_ADR) 244#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 245 QLA82XX_HW_SQG1_CRB_AGT_ADR) 246#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 247 QLA82XX_HW_SQG2_CRB_AGT_ADR) 248#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 249 QLA82XX_HW_SQG3_CRB_AGT_ADR) 250#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 251 QLA82XX_HW_RPMX1_CRB_AGT_ADR) 252#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 253 QLA82XX_HW_RPMX5_CRB_AGT_ADR) 254#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 255 QLA82XX_HW_RPMX6_CRB_AGT_ADR) 256#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 257 QLA82XX_HW_RPMX8_CRB_AGT_ADR) 258#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 259 QLA82XX_HW_CAS0_CRB_AGT_ADR) 260#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 261 QLA82XX_HW_CAS1_CRB_AGT_ADR) 262#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 263 QLA82XX_HW_CAS2_CRB_AGT_ADR) 264#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 265 QLA82XX_HW_CAS3_CRB_AGT_ADR) 266 267#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 268 QLA82XX_HW_PEGNI_CRB_AGT_ADR) 269#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 270 QLA82XX_HW_PEGND_CRB_AGT_ADR) 271#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 272 QLA82XX_HW_PEGN0_CRB_AGT_ADR) 273#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 274 QLA82XX_HW_PEGN1_CRB_AGT_ADR) 275#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 276 QLA82XX_HW_PEGN2_CRB_AGT_ADR) 277#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 278 QLA82XX_HW_PEGN3_CRB_AGT_ADR) 279#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 280 QLA82XX_HW_PEGN4_CRB_AGT_ADR) 281 282#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 283 QLA82XX_HW_PEGNC_CRB_AGT_ADR) 284#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 285 QLA82XX_HW_PEGR0_CRB_AGT_ADR) 286#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 287 QLA82XX_HW_PEGR1_CRB_AGT_ADR) 288#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 289 QLA82XX_HW_PEGR2_CRB_AGT_ADR) 290#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 291 QLA82XX_HW_PEGR3_CRB_AGT_ADR) 292 293#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 294 QLA82XX_HW_PEGSI_CRB_AGT_ADR) 295#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 296 QLA82XX_HW_PEGSD_CRB_AGT_ADR) 297#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 298 QLA82XX_HW_PEGS0_CRB_AGT_ADR) 299#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 300 QLA82XX_HW_PEGS1_CRB_AGT_ADR) 301#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 302 QLA82XX_HW_PEGS2_CRB_AGT_ADR) 303#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 304 QLA82XX_HW_PEGS3_CRB_AGT_ADR) 305#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 306 QLA82XX_HW_PEGSC_CRB_AGT_ADR) 307 308#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 309 QLA82XX_HW_NCM_CRB_AGT_ADR) 310#define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 311 QLA82XX_HW_TMR_CRB_AGT_ADR) 312#define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 313 QLA82XX_HW_XDMA_CRB_AGT_ADR) 314#define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 315 QLA82XX_HW_SN_CRB_AGT_ADR) 316#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 317 QLA82XX_HW_I2Q_CRB_AGT_ADR) 318#define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 319 QLA82XX_HW_ROMUSB_CRB_AGT_ADR) 320#define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 321 QLA82XX_HW_OCM0_CRB_AGT_ADR) 322#define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 323 QLA82XX_HW_OCM1_CRB_AGT_ADR) 324#define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 325 QLA82XX_HW_LPC_CRB_AGT_ADR) 326 327#define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000) 328#define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 329#define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 330#define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 331#define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 332#define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 333#define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 334#define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 335#define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 336 337#define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000) 338#define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 339#define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 340 341/* Lock IDs for ROM lock */ 342#define ROM_LOCK_DRIVER 0x0d417340 343 344#define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */ 345#define QLA82XX_PCI_CRB_WINDOW(A) (QLA82XX_PCI_CRBSPACE + \ 346 (A)*QLA82XX_PCI_CRB_WINDOWSIZE) 347 348#define QLA82XX_CRB_C2C_0 \ 349 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0) 350#define QLA82XX_CRB_C2C_1 \ 351 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1) 352#define QLA82XX_CRB_C2C_2 \ 353 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2) 354#define QLA82XX_CRB_CAM \ 355 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM) 356#define QLA82XX_CRB_CASPER \ 357 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS) 358#define QLA82XX_CRB_CASPER_0 \ 359 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0) 360#define QLA82XX_CRB_CASPER_1 \ 361 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1) 362#define QLA82XX_CRB_CASPER_2 \ 363 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2) 364#define QLA82XX_CRB_DDR_MD \ 365 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS) 366#define QLA82XX_CRB_DDR_NET \ 367 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN) 368#define QLA82XX_CRB_EPG \ 369 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG) 370#define QLA82XX_CRB_I2Q \ 371 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q) 372#define QLA82XX_CRB_NIU \ 373 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU) 374/* HACK upon HACK upon HACK (for PCIE builds) */ 375#define QLA82XX_CRB_PCIX_HOST \ 376 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH) 377#define QLA82XX_CRB_PCIX_HOST2 \ 378 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2) 379#define QLA82XX_CRB_PCIX_MD \ 380 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS) 381#define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD 382/* window 1 pcie slot */ 383#define QLA82XX_CRB_PCIE2 \ 384 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2) 385 386#define QLA82XX_CRB_PEG_MD_0 \ 387 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0) 388#define QLA82XX_CRB_PEG_MD_1 \ 389 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1) 390#define QLA82XX_CRB_PEG_MD_2 \ 391 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2) 392#define QLA82XX_CRB_PEG_MD_3 \ 393 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 394#define QLA82XX_CRB_PEG_MD_3 \ 395 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 396#define QLA82XX_CRB_PEG_MD_D \ 397 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD) 398#define QLA82XX_CRB_PEG_MD_I \ 399 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI) 400#define QLA82XX_CRB_PEG_NET_0 \ 401 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0) 402#define QLA82XX_CRB_PEG_NET_1 \ 403 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1) 404#define QLA82XX_CRB_PEG_NET_2 \ 405 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2) 406#define QLA82XX_CRB_PEG_NET_3 \ 407 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3) 408#define QLA82XX_CRB_PEG_NET_4 \ 409 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4) 410#define QLA82XX_CRB_PEG_NET_D \ 411 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND) 412#define QLA82XX_CRB_PEG_NET_I \ 413 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI) 414#define QLA82XX_CRB_PQM_MD \ 415 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS) 416#define QLA82XX_CRB_PQM_NET \ 417 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN) 418#define QLA82XX_CRB_QDR_MD \ 419 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS) 420#define QLA82XX_CRB_QDR_NET \ 421 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN) 422#define QLA82XX_CRB_ROMUSB \ 423 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB) 424#define QLA82XX_CRB_RPMX_0 \ 425 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0) 426#define QLA82XX_CRB_RPMX_1 \ 427 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1) 428#define QLA82XX_CRB_RPMX_2 \ 429 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2) 430#define QLA82XX_CRB_RPMX_3 \ 431 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3) 432#define QLA82XX_CRB_RPMX_4 \ 433 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4) 434#define QLA82XX_CRB_RPMX_5 \ 435 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5) 436#define QLA82XX_CRB_RPMX_6 \ 437 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6) 438#define QLA82XX_CRB_RPMX_7 \ 439 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7) 440#define QLA82XX_CRB_SQM_MD_0 \ 441 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0) 442#define QLA82XX_CRB_SQM_MD_1 \ 443 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1) 444#define QLA82XX_CRB_SQM_MD_2 \ 445 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2) 446#define QLA82XX_CRB_SQM_MD_3 \ 447 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3) 448#define QLA82XX_CRB_SQM_NET_0 \ 449 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0) 450#define QLA82XX_CRB_SQM_NET_1 \ 451 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1) 452#define QLA82XX_CRB_SQM_NET_2 \ 453 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2) 454#define QLA82XX_CRB_SQM_NET_3 \ 455 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3) 456#define QLA82XX_CRB_SRE \ 457 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE) 458#define QLA82XX_CRB_TIMER \ 459 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR) 460#define QLA82XX_CRB_XDMA \ 461 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA) 462#define QLA82XX_CRB_I2C0 \ 463 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0) 464#define QLA82XX_CRB_I2C1 \ 465 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1) 466#define QLA82XX_CRB_OCM0 \ 467 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0) 468#define QLA82XX_CRB_SMB \ 469 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB) 470 471#define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64) 472 473/* 474 * ====================== BASE ADDRESSES ON-CHIP ====================== 475 * Base addresses of major components on-chip. 476 * ====================== BASE ADDRESSES ON-CHIP ====================== 477 */ 478#define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL) 479#define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 480 481/* Imbus address bit used to indicate a host address. This bit is 482 * eliminated by the pcie bar and bar select before presentation 483 * over pcie. */ 484/* host memory via IMBUS */ 485#define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL) 486#define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL) 487#define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) 488#define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL) 489#define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL) 490#define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL) 491#define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL) 492#define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL) 493 494#define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) 495#define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) 496 497#define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000 498#define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000 499#define QLA82XX_PCI_CAMQM (unsigned long)0x04800000 500#define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff 501#define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000 502#define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000 503#define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff 504 505/* 506 * Register offsets for MN 507 */ 508#define MIU_CONTROL (0x000) 509#define MIU_TAG (0x004) 510#define MIU_TEST_AGT_CTRL (0x090) 511#define MIU_TEST_AGT_ADDR_LO (0x094) 512#define MIU_TEST_AGT_ADDR_HI (0x098) 513#define MIU_TEST_AGT_WRDATA_LO (0x0a0) 514#define MIU_TEST_AGT_WRDATA_HI (0x0a4) 515#define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) 516#define MIU_TEST_AGT_RDDATA_LO (0x0a8) 517#define MIU_TEST_AGT_RDDATA_HI (0x0ac) 518#define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) 519#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 520#define MIU_TEST_AGT_UPPER_ADDR(off) (0) 521 522/* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 523#define MIU_TA_CTL_START 1 524#define MIU_TA_CTL_ENABLE 2 525#define MIU_TA_CTL_WRITE 4 526#define MIU_TA_CTL_BUSY 8 527 528/*CAM RAM */ 529# define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000) 530# define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg)) 531 532#define QLA82XX_PEG_TUNE_MN_SPD_ZEROED 0x80000000 533#define QLA82XX_BOOT_LOADER_MN_ISSUE 0xff00ffff 534#define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24)) 535#define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8)) 536#define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac)) 537#define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0)) 538 539#define HALT_STATUS_UNRECOVERABLE 0x80000000 540#define HALT_STATUS_RECOVERABLE 0x40000000 541 542 543#define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100)) 544#define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124)) 545#define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150)) 546#define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154)) 547#define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158)) 548#define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg)) 549 550/* Driver Coexistence Defines */ 551#define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138)) 552#define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140)) 553#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) 554#define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174)) 555#define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144)) 556#define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148)) 557#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) 558 559/* Every driver should use these Device State */ 560#define QLA82XX_DEV_COLD 1 561#define QLA82XX_DEV_INITIALIZING 2 562#define QLA82XX_DEV_READY 3 563#define QLA82XX_DEV_NEED_RESET 4 564#define QLA82XX_DEV_NEED_QUIESCENT 5 565#define QLA82XX_DEV_FAILED 6 566#define QLA82XX_DEV_QUIESCENT 7 567#define MAX_STATES 8 /* Increment if new state added */ 568 569#define QLA82XX_IDC_VERSION 0x1 570#define ROM_DEV_INIT_TIMEOUT 30 571#define ROM_DRV_RESET_ACK_TIMEOUT 10 572 573#define PCIE_SETUP_FUNCTION (0x12040) 574#define PCIE_SETUP_FUNCTION2 (0x12048) 575 576#define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg)) 577#define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg)) 578 579#define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ 580#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ 581#define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */ 582#define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */ 583#define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ 584#define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ 585 586/* 587 * The PCI VendorID and DeviceID for our board. 588 */ 589#define QLA82XX_MSIX_TBL_SPACE 8192 590#define QLA82XX_PCI_REG_MSIX_TBL 0x44 591#define QLA82XX_PCI_MSIX_CONTROL 0x40 592 593struct crb_128M_2M_sub_block_map { 594 unsigned valid; 595 unsigned start_128M; 596 unsigned end_128M; 597 unsigned start_2M; 598}; 599 600struct crb_128M_2M_block_map { 601 struct crb_128M_2M_sub_block_map sub_block[16]; 602}; 603 604struct crb_addr_pair { 605 long addr; 606 long data; 607}; 608 609#define ADDR_ERROR ((unsigned long) 0xffffffff) 610#define MAX_CTL_CHECK 1000 611 612/*************************************************************************** 613 * PCI related defines. 614 **************************************************************************/ 615 616/* 617 * Interrupt related defines. 618 */ 619#define PCIX_TARGET_STATUS (0x10118) 620#define PCIX_TARGET_STATUS_F1 (0x10160) 621#define PCIX_TARGET_STATUS_F2 (0x10164) 622#define PCIX_TARGET_STATUS_F3 (0x10168) 623#define PCIX_TARGET_STATUS_F4 (0x10360) 624#define PCIX_TARGET_STATUS_F5 (0x10364) 625#define PCIX_TARGET_STATUS_F6 (0x10368) 626#define PCIX_TARGET_STATUS_F7 (0x1036c) 627 628#define PCIX_TARGET_MASK (0x10128) 629#define PCIX_TARGET_MASK_F1 (0x10170) 630#define PCIX_TARGET_MASK_F2 (0x10174) 631#define PCIX_TARGET_MASK_F3 (0x10178) 632#define PCIX_TARGET_MASK_F4 (0x10370) 633#define PCIX_TARGET_MASK_F5 (0x10374) 634#define PCIX_TARGET_MASK_F6 (0x10378) 635#define PCIX_TARGET_MASK_F7 (0x1037c) 636 637/* 638 * Message Signaled Interrupts 639 */ 640#define PCIX_MSI_F0 (0x13000) 641#define PCIX_MSI_F1 (0x13004) 642#define PCIX_MSI_F2 (0x13008) 643#define PCIX_MSI_F3 (0x1300c) 644#define PCIX_MSI_F4 (0x13010) 645#define PCIX_MSI_F5 (0x13014) 646#define PCIX_MSI_F6 (0x13018) 647#define PCIX_MSI_F7 (0x1301c) 648#define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4)) 649 650/* 651 * 652 */ 653#define PCIX_INT_VECTOR (0x10100) 654#define PCIX_INT_MASK (0x10104) 655 656/* 657 * Interrupt state machine and other bits. 658 */ 659#define PCIE_MISCCFG_RC (0x1206c) 660 661 662#define ISR_INT_TARGET_STATUS \ 663 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS)) 664#define ISR_INT_TARGET_STATUS_F1 \ 665 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) 666#define ISR_INT_TARGET_STATUS_F2 \ 667 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) 668#define ISR_INT_TARGET_STATUS_F3 \ 669 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 670#define ISR_INT_TARGET_STATUS_F4 \ 671 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) 672#define ISR_INT_TARGET_STATUS_F5 \ 673 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) 674#define ISR_INT_TARGET_STATUS_F6 \ 675 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) 676#define ISR_INT_TARGET_STATUS_F7 \ 677 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) 678 679#define ISR_INT_TARGET_MASK \ 680 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK)) 681#define ISR_INT_TARGET_MASK_F1 \ 682 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) 683#define ISR_INT_TARGET_MASK_F2 \ 684 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 685#define ISR_INT_TARGET_MASK_F3 \ 686 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 687#define ISR_INT_TARGET_MASK_F4 \ 688 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) 689#define ISR_INT_TARGET_MASK_F5 \ 690 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) 691#define ISR_INT_TARGET_MASK_F6 \ 692 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) 693#define ISR_INT_TARGET_MASK_F7 \ 694 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) 695 696#define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR)) 697#define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK)) 698#define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC)) 699 700#define ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 701 702 703#define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) 704#define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 705 706/* 707 * PCI Interrupt Vector Values. 708 */ 709#define PCIX_INT_VECTOR_BIT_F0 0x0080 710#define PCIX_INT_VECTOR_BIT_F1 0x0100 711#define PCIX_INT_VECTOR_BIT_F2 0x0200 712#define PCIX_INT_VECTOR_BIT_F3 0x0400 713#define PCIX_INT_VECTOR_BIT_F4 0x0800 714#define PCIX_INT_VECTOR_BIT_F5 0x1000 715#define PCIX_INT_VECTOR_BIT_F6 0x2000 716#define PCIX_INT_VECTOR_BIT_F7 0x4000 717 718/* struct qla4_8xxx_legacy_intr_set defined in ql4_def.h */ 719 720#define QLA82XX_LEGACY_INTR_CONFIG \ 721{ \ 722 { \ 723 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ 724 .tgt_status_reg = ISR_INT_TARGET_STATUS, \ 725 .tgt_mask_reg = ISR_INT_TARGET_MASK, \ 726 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ 727 \ 728 { \ 729 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ 730 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ 731 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ 732 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ 733 \ 734 { \ 735 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ 736 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ 737 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ 738 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ 739 \ 740 { \ 741 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ 742 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ 743 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ 744 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ 745 \ 746 { \ 747 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ 748 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ 749 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ 750 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ 751 \ 752 { \ 753 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ 754 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ 755 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ 756 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ 757 \ 758 { \ 759 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ 760 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ 761 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ 762 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ 763 \ 764 { \ 765 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ 766 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ 767 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ 768 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ 769} 770 771/* Magic number to let user know flash is programmed */ 772#define QLA82XX_BDINFO_MAGIC 0x12345678 773#define FW_SIZE_OFFSET (0x3e840c) 774 775/* QLA82XX additions */ 776#define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0) 777#define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4) 778 779#endif 780