1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#ifndef __QLA_FW_H 8#define __QLA_FW_H 9 10#define MBS_CHECKSUM_ERROR 0x4010 11#define MBS_INVALID_PRODUCT_KEY 0x4020 12 13/* 14 * Firmware Options. 15 */ 16#define FO1_ENABLE_PUREX BIT_10 17#define FO1_DISABLE_LED_CTRL BIT_6 18#define FO1_ENABLE_8016 BIT_0 19#define FO2_ENABLE_SEL_CLASS2 BIT_5 20#define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21#define FO3_HOLD_STS_IOCB BIT_12 22 23/* 24 * Port Database structure definition for ISP 24xx. 25 */ 26#define PDO_FORCE_ADISC BIT_1 27#define PDO_FORCE_PLOGI BIT_0 28 29 30#define PORT_DATABASE_24XX_SIZE 64 31struct port_database_24xx { 32 uint16_t flags; 33#define PDF_TASK_RETRY_ID BIT_14 34#define PDF_FC_TAPE BIT_7 35#define PDF_ACK0_CAPABLE BIT_6 36#define PDF_FCP2_CONF BIT_5 37#define PDF_CLASS_2 BIT_4 38#define PDF_HARD_ADDR BIT_1 39 40 uint8_t current_login_state; 41 uint8_t last_login_state; 42#define PDS_PLOGI_PENDING 0x03 43#define PDS_PLOGI_COMPLETE 0x04 44#define PDS_PRLI_PENDING 0x05 45#define PDS_PRLI_COMPLETE 0x06 46#define PDS_PORT_UNAVAILABLE 0x07 47#define PDS_PRLO_PENDING 0x09 48#define PDS_LOGO_PENDING 0x11 49#define PDS_PRLI2_PENDING 0x12 50 51 uint8_t hard_address[3]; 52 uint8_t reserved_1; 53 54 uint8_t port_id[3]; 55 uint8_t sequence_id; 56 57 uint16_t port_timer; 58 59 uint16_t nport_handle; /* N_PORT handle. */ 60 61 uint16_t receive_data_size; 62 uint16_t reserved_2; 63 64 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 65 /* Bits 15-0 of word 0 */ 66 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 67 /* Bits 15-0 of word 3 */ 68 69 uint8_t port_name[WWN_SIZE]; 70 uint8_t node_name[WWN_SIZE]; 71 72 uint8_t reserved_3[24]; 73}; 74 75struct vp_database_24xx { 76 uint16_t vp_status; 77 uint8_t options; 78 uint8_t id; 79 uint8_t port_name[WWN_SIZE]; 80 uint8_t node_name[WWN_SIZE]; 81 uint16_t port_id_low; 82 uint16_t port_id_high; 83}; 84 85struct nvram_24xx { 86 /* NVRAM header. */ 87 uint8_t id[4]; 88 uint16_t nvram_version; 89 uint16_t reserved_0; 90 91 /* Firmware Initialization Control Block. */ 92 uint16_t version; 93 uint16_t reserved_1; 94 uint16_t frame_payload_size; 95 uint16_t execution_throttle; 96 uint16_t exchange_count; 97 uint16_t hard_address; 98 99 uint8_t port_name[WWN_SIZE]; 100 uint8_t node_name[WWN_SIZE]; 101 102 uint16_t login_retry_count; 103 uint16_t link_down_on_nos; 104 uint16_t interrupt_delay_timer; 105 uint16_t login_timeout; 106 107 uint32_t firmware_options_1; 108 uint32_t firmware_options_2; 109 uint32_t firmware_options_3; 110 111 /* Offset 56. */ 112 113 /* 114 * BIT 0 = Control Enable 115 * BIT 1-15 = 116 * 117 * BIT 0-7 = Reserved 118 * BIT 8-10 = Output Swing 1G 119 * BIT 11-13 = Output Emphasis 1G 120 * BIT 14-15 = Reserved 121 * 122 * BIT 0-7 = Reserved 123 * BIT 8-10 = Output Swing 2G 124 * BIT 11-13 = Output Emphasis 2G 125 * BIT 14-15 = Reserved 126 * 127 * BIT 0-7 = Reserved 128 * BIT 8-10 = Output Swing 4G 129 * BIT 11-13 = Output Emphasis 4G 130 * BIT 14-15 = Reserved 131 */ 132 uint16_t seriallink_options[4]; 133 134 uint16_t reserved_2[16]; 135 136 /* Offset 96. */ 137 uint16_t reserved_3[16]; 138 139 /* PCIe table entries. */ 140 uint16_t reserved_4[16]; 141 142 /* Offset 160. */ 143 uint16_t reserved_5[16]; 144 145 /* Offset 192. */ 146 uint16_t reserved_6[16]; 147 148 /* Offset 224. */ 149 uint16_t reserved_7[16]; 150 151 /* 152 * BIT 0 = Enable spinup delay 153 * BIT 1 = Disable BIOS 154 * BIT 2 = Enable Memory Map BIOS 155 * BIT 3 = Enable Selectable Boot 156 * BIT 4 = Disable RISC code load 157 * BIT 5 = Disable Serdes 158 * BIT 6 = 159 * BIT 7 = 160 * 161 * BIT 8 = 162 * BIT 9 = 163 * BIT 10 = Enable lip full login 164 * BIT 11 = Enable target reset 165 * BIT 12 = 166 * BIT 13 = 167 * BIT 14 = 168 * BIT 15 = Enable alternate WWN 169 * 170 * BIT 16-31 = 171 */ 172 uint32_t host_p; 173 174 uint8_t alternate_port_name[WWN_SIZE]; 175 uint8_t alternate_node_name[WWN_SIZE]; 176 177 uint8_t boot_port_name[WWN_SIZE]; 178 uint16_t boot_lun_number; 179 uint16_t reserved_8; 180 181 uint8_t alt1_boot_port_name[WWN_SIZE]; 182 uint16_t alt1_boot_lun_number; 183 uint16_t reserved_9; 184 185 uint8_t alt2_boot_port_name[WWN_SIZE]; 186 uint16_t alt2_boot_lun_number; 187 uint16_t reserved_10; 188 189 uint8_t alt3_boot_port_name[WWN_SIZE]; 190 uint16_t alt3_boot_lun_number; 191 uint16_t reserved_11; 192 193 /* 194 * BIT 0 = Selective Login 195 * BIT 1 = Alt-Boot Enable 196 * BIT 2 = Reserved 197 * BIT 3 = Boot Order List 198 * BIT 4 = Reserved 199 * BIT 5 = Selective LUN 200 * BIT 6 = Reserved 201 * BIT 7-31 = 202 */ 203 uint32_t efi_parameters; 204 205 uint8_t reset_delay; 206 uint8_t reserved_12; 207 uint16_t reserved_13; 208 209 uint16_t boot_id_number; 210 uint16_t reserved_14; 211 212 uint16_t max_luns_per_target; 213 uint16_t reserved_15; 214 215 uint16_t port_down_retry_count; 216 uint16_t link_down_timeout; 217 218 /* FCode parameters. */ 219 uint16_t fcode_parameter; 220 221 uint16_t reserved_16[3]; 222 223 /* Offset 352. */ 224 uint8_t prev_drv_ver_major; 225 uint8_t prev_drv_ver_submajob; 226 uint8_t prev_drv_ver_minor; 227 uint8_t prev_drv_ver_subminor; 228 229 uint16_t prev_bios_ver_major; 230 uint16_t prev_bios_ver_minor; 231 232 uint16_t prev_efi_ver_major; 233 uint16_t prev_efi_ver_minor; 234 235 uint16_t prev_fw_ver_major; 236 uint8_t prev_fw_ver_minor; 237 uint8_t prev_fw_ver_subminor; 238 239 uint16_t reserved_17[8]; 240 241 /* Offset 384. */ 242 uint16_t reserved_18[16]; 243 244 /* Offset 416. */ 245 uint16_t reserved_19[16]; 246 247 /* Offset 448. */ 248 uint16_t reserved_20[16]; 249 250 /* Offset 480. */ 251 uint8_t model_name[16]; 252 253 uint16_t reserved_21[2]; 254 255 /* Offset 500. */ 256 /* HW Parameter Block. */ 257 uint16_t pcie_table_sig; 258 uint16_t pcie_table_offset; 259 260 uint16_t subsystem_vendor_id; 261 uint16_t subsystem_device_id; 262 263 uint32_t checksum; 264}; 265 266/* 267 * ISP Initialization Control Block. 268 * Little endian except where noted. 269 */ 270#define ICB_VERSION 1 271struct init_cb_24xx { 272 uint16_t version; 273 uint16_t reserved_1; 274 275 uint16_t frame_payload_size; 276 uint16_t execution_throttle; 277 uint16_t exchange_count; 278 279 uint16_t hard_address; 280 281 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 282 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 283 284 uint16_t response_q_inpointer; 285 uint16_t request_q_outpointer; 286 287 uint16_t login_retry_count; 288 289 uint16_t prio_request_q_outpointer; 290 291 uint16_t response_q_length; 292 uint16_t request_q_length; 293 294 uint16_t link_down_on_nos; /* Milliseconds. */ 295 296 uint16_t prio_request_q_length; 297 298 uint32_t request_q_address[2]; 299 uint32_t response_q_address[2]; 300 uint32_t prio_request_q_address[2]; 301 302 uint16_t msix; 303 uint8_t reserved_2[6]; 304 305 uint16_t atio_q_inpointer; 306 uint16_t atio_q_length; 307 uint32_t atio_q_address[2]; 308 309 uint16_t interrupt_delay_timer; /* 100us increments. */ 310 uint16_t login_timeout; 311 312 /* 313 * BIT 0 = Enable Hard Loop Id 314 * BIT 1 = Enable Fairness 315 * BIT 2 = Enable Full-Duplex 316 * BIT 3 = Reserved 317 * BIT 4 = Enable Target Mode 318 * BIT 5 = Disable Initiator Mode 319 * BIT 6 = Reserved 320 * BIT 7 = Reserved 321 * 322 * BIT 8 = Reserved 323 * BIT 9 = Non Participating LIP 324 * BIT 10 = Descending Loop ID Search 325 * BIT 11 = Acquire Loop ID in LIPA 326 * BIT 12 = Reserved 327 * BIT 13 = Full Login after LIP 328 * BIT 14 = Node Name Option 329 * BIT 15-31 = Reserved 330 */ 331 uint32_t firmware_options_1; 332 333 /* 334 * BIT 0 = Operation Mode bit 0 335 * BIT 1 = Operation Mode bit 1 336 * BIT 2 = Operation Mode bit 2 337 * BIT 3 = Operation Mode bit 3 338 * BIT 4 = Connection Options bit 0 339 * BIT 5 = Connection Options bit 1 340 * BIT 6 = Connection Options bit 2 341 * BIT 7 = Enable Non part on LIHA failure 342 * 343 * BIT 8 = Enable Class 2 344 * BIT 9 = Enable ACK0 345 * BIT 10 = Reserved 346 * BIT 11 = Enable FC-SP Security 347 * BIT 12 = FC Tape Enable 348 * BIT 13 = Reserved 349 * BIT 14 = Enable Target PRLI Control 350 * BIT 15-31 = Reserved 351 */ 352 uint32_t firmware_options_2; 353 354 /* 355 * BIT 0 = Reserved 356 * BIT 1 = Soft ID only 357 * BIT 2 = Reserved 358 * BIT 3 = Reserved 359 * BIT 4 = FCP RSP Payload bit 0 360 * BIT 5 = FCP RSP Payload bit 1 361 * BIT 6 = Enable Receive Out-of-Order data frame handling 362 * BIT 7 = Disable Automatic PLOGI on Local Loop 363 * 364 * BIT 8 = Reserved 365 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 366 * BIT 10 = Reserved 367 * BIT 11 = Reserved 368 * BIT 12 = Reserved 369 * BIT 13 = Data Rate bit 0 370 * BIT 14 = Data Rate bit 1 371 * BIT 15 = Data Rate bit 2 372 * BIT 16 = Enable 75 ohm Termination Select 373 * BIT 17-31 = Reserved 374 */ 375 uint32_t firmware_options_3; 376 uint16_t qos; 377 uint16_t rid; 378 uint8_t reserved_3[20]; 379}; 380 381/* 382 * ISP queue - command entry structure definition. 383 */ 384#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 385struct cmd_type_6 { 386 uint8_t entry_type; /* Entry type. */ 387 uint8_t entry_count; /* Entry count. */ 388 uint8_t sys_define; /* System defined. */ 389 uint8_t entry_status; /* Entry Status. */ 390 391 uint32_t handle; /* System handle. */ 392 393 uint16_t nport_handle; /* N_PORT handle. */ 394 uint16_t timeout; /* Command timeout. */ 395 396 uint16_t dseg_count; /* Data segment count. */ 397 398 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 399 400 struct scsi_lun lun; /* FCP LUN (BE). */ 401 402 uint16_t control_flags; /* Control flags. */ 403#define CF_DIF_SEG_DESCR_ENABLE BIT_3 404#define CF_DATA_SEG_DESCR_ENABLE BIT_2 405#define CF_READ_DATA BIT_1 406#define CF_WRITE_DATA BIT_0 407 408 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 409 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 410 411 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 412 413 uint32_t byte_count; /* Total byte count. */ 414 415 uint8_t port_id[3]; /* PortID of destination port. */ 416 uint8_t vp_index; 417 418 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 419 uint16_t fcp_data_dseg_len; /* Data segment length. */ 420 uint16_t reserved_1; /* MUST be set to 0. */ 421}; 422 423#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 424struct cmd_type_7 { 425 uint8_t entry_type; /* Entry type. */ 426 uint8_t entry_count; /* Entry count. */ 427 uint8_t sys_define; /* System defined. */ 428 uint8_t entry_status; /* Entry Status. */ 429 430 uint32_t handle; /* System handle. */ 431 432 uint16_t nport_handle; /* N_PORT handle. */ 433 uint16_t timeout; /* Command timeout. */ 434#define FW_MAX_TIMEOUT 0x1999 435 436 uint16_t dseg_count; /* Data segment count. */ 437 uint16_t reserved_1; 438 439 struct scsi_lun lun; /* FCP LUN (BE). */ 440 441 uint16_t task_mgmt_flags; /* Task management flags. */ 442#define TMF_CLEAR_ACA BIT_14 443#define TMF_TARGET_RESET BIT_13 444#define TMF_LUN_RESET BIT_12 445#define TMF_CLEAR_TASK_SET BIT_10 446#define TMF_ABORT_TASK_SET BIT_9 447#define TMF_DSD_LIST_ENABLE BIT_2 448#define TMF_READ_DATA BIT_1 449#define TMF_WRITE_DATA BIT_0 450 451 uint8_t task; 452#define TSK_SIMPLE 0 453#define TSK_HEAD_OF_QUEUE 1 454#define TSK_ORDERED 2 455#define TSK_ACA 4 456#define TSK_UNTAGGED 5 457 458 uint8_t crn; 459 460 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 461 uint32_t byte_count; /* Total byte count. */ 462 463 uint8_t port_id[3]; /* PortID of destination port. */ 464 uint8_t vp_index; 465 466 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 467 uint32_t dseg_0_len; /* Data segment 0 length. */ 468}; 469 470#define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6) 471 * (T10-DIF) */ 472struct cmd_type_crc_2 { 473 uint8_t entry_type; /* Entry type. */ 474 uint8_t entry_count; /* Entry count. */ 475 uint8_t sys_define; /* System defined. */ 476 uint8_t entry_status; /* Entry Status. */ 477 478 uint32_t handle; /* System handle. */ 479 480 uint16_t nport_handle; /* N_PORT handle. */ 481 uint16_t timeout; /* Command timeout. */ 482 483 uint16_t dseg_count; /* Data segment count. */ 484 485 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */ 486 487 struct scsi_lun lun; /* FCP LUN (BE). */ 488 489 uint16_t control_flags; /* Control flags. */ 490 491 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 492 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 493 494 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 495 496 uint32_t byte_count; /* Total byte count. */ 497 498 uint8_t port_id[3]; /* PortID of destination port. */ 499 uint8_t vp_index; 500 501 uint32_t crc_context_address[2]; /* Data segment address. */ 502 uint16_t crc_context_len; /* Data segment length. */ 503 uint16_t reserved_1; /* MUST be set to 0. */ 504}; 505 506 507/* 508 * ISP queue - status entry structure definition. 509 */ 510#define STATUS_TYPE 0x03 /* Status entry. */ 511struct sts_entry_24xx { 512 uint8_t entry_type; /* Entry type. */ 513 uint8_t entry_count; /* Entry count. */ 514 uint8_t sys_define; /* System defined. */ 515 uint8_t entry_status; /* Entry Status. */ 516 517 uint32_t handle; /* System handle. */ 518 519 uint16_t comp_status; /* Completion status. */ 520 uint16_t ox_id; /* OX_ID used by the firmware. */ 521 522 uint32_t residual_len; /* FW calc residual transfer length. */ 523 524 uint16_t reserved_1; 525 uint16_t state_flags; /* State flags. */ 526#define SF_TRANSFERRED_DATA BIT_11 527#define SF_FCP_RSP_DMA BIT_0 528 529 uint16_t reserved_2; 530 uint16_t scsi_status; /* SCSI status. */ 531#define SS_CONFIRMATION_REQ BIT_12 532 533 uint32_t rsp_residual_count; /* FCP RSP residual count. */ 534 535 uint32_t sense_len; /* FCP SENSE length. */ 536 uint32_t rsp_data_len; /* FCP response data length. */ 537 uint8_t data[28]; /* FCP response/sense information. */ 538 /* 539 * If DIF Error is set in comp_status, these additional fields are 540 * defined: 541 * &data[10] : uint8_t report_runt_bg[2]; - computed guard 542 * &data[12] : uint8_t actual_dif[8]; - DIF Data recieved 543 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed 544 */ 545}; 546 547 548/* 549 * Status entry completion status 550 */ 551#define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 552#define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 553#define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 554#define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 555#define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 556 557/* 558 * ISP queue - marker entry structure definition. 559 */ 560#define MARKER_TYPE 0x04 /* Marker entry. */ 561struct mrk_entry_24xx { 562 uint8_t entry_type; /* Entry type. */ 563 uint8_t entry_count; /* Entry count. */ 564 uint8_t handle_count; /* Handle count. */ 565 uint8_t entry_status; /* Entry Status. */ 566 567 uint32_t handle; /* System handle. */ 568 569 uint16_t nport_handle; /* N_PORT handle. */ 570 571 uint8_t modifier; /* Modifier (7-0). */ 572#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 573#define MK_SYNC_ID 1 /* Synchronize ID */ 574#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 575 uint8_t reserved_1; 576 577 uint8_t reserved_2; 578 uint8_t vp_index; 579 580 uint16_t reserved_3; 581 582 uint8_t lun[8]; /* FCP LUN (BE). */ 583 uint8_t reserved_4[40]; 584}; 585 586/* 587 * ISP queue - CT Pass-Through entry structure definition. 588 */ 589#define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 590struct ct_entry_24xx { 591 uint8_t entry_type; /* Entry type. */ 592 uint8_t entry_count; /* Entry count. */ 593 uint8_t sys_define; /* System Defined. */ 594 uint8_t entry_status; /* Entry Status. */ 595 596 uint32_t handle; /* System handle. */ 597 598 uint16_t comp_status; /* Completion status. */ 599 600 uint16_t nport_handle; /* N_PORT handle. */ 601 602 uint16_t cmd_dsd_count; 603 604 uint8_t vp_index; 605 uint8_t reserved_1; 606 607 uint16_t timeout; /* Command timeout. */ 608 uint16_t reserved_2; 609 610 uint16_t rsp_dsd_count; 611 612 uint8_t reserved_3[10]; 613 614 uint32_t rsp_byte_count; 615 uint32_t cmd_byte_count; 616 617 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 618 uint32_t dseg_0_len; /* Data segment 0 length. */ 619 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 620 uint32_t dseg_1_len; /* Data segment 1 length. */ 621}; 622 623/* 624 * ISP queue - ELS Pass-Through entry structure definition. 625 */ 626#define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 627struct els_entry_24xx { 628 uint8_t entry_type; /* Entry type. */ 629 uint8_t entry_count; /* Entry count. */ 630 uint8_t sys_define; /* System Defined. */ 631 uint8_t entry_status; /* Entry Status. */ 632 633 uint32_t handle; /* System handle. */ 634 635 uint16_t reserved_1; 636 637 uint16_t nport_handle; /* N_PORT handle. */ 638 639 uint16_t tx_dsd_count; 640 641 uint8_t vp_index; 642 uint8_t sof_type; 643#define EST_SOFI3 (1 << 4) 644#define EST_SOFI2 (3 << 4) 645 646 uint32_t rx_xchg_address; /* Receive exchange address. */ 647 uint16_t rx_dsd_count; 648 649 uint8_t opcode; 650 uint8_t reserved_2; 651 652 uint8_t port_id[3]; 653 uint8_t reserved_3; 654 655 uint16_t reserved_4; 656 657 uint16_t control_flags; /* Control flags. */ 658#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 659#define EPD_ELS_COMMAND (0 << 13) 660#define EPD_ELS_ACC (1 << 13) 661#define EPD_ELS_RJT (2 << 13) 662#define EPD_RX_XCHG (3 << 13) 663#define ECF_CLR_PASSTHRU_PEND BIT_12 664#define ECF_INCL_FRAME_HDR BIT_11 665 666 uint32_t rx_byte_count; 667 uint32_t tx_byte_count; 668 669 uint32_t tx_address[2]; /* Data segment 0 address. */ 670 uint32_t tx_len; /* Data segment 0 length. */ 671 uint32_t rx_address[2]; /* Data segment 1 address. */ 672 uint32_t rx_len; /* Data segment 1 length. */ 673}; 674 675struct els_sts_entry_24xx { 676 uint8_t entry_type; /* Entry type. */ 677 uint8_t entry_count; /* Entry count. */ 678 uint8_t sys_define; /* System Defined. */ 679 uint8_t entry_status; /* Entry Status. */ 680 681 uint32_t handle; /* System handle. */ 682 683 uint16_t comp_status; 684 685 uint16_t nport_handle; /* N_PORT handle. */ 686 687 uint16_t reserved_1; 688 689 uint8_t vp_index; 690 uint8_t sof_type; 691 692 uint32_t rx_xchg_address; /* Receive exchange address. */ 693 uint16_t reserved_2; 694 695 uint8_t opcode; 696 uint8_t reserved_3; 697 698 uint8_t port_id[3]; 699 uint8_t reserved_4; 700 701 uint16_t reserved_5; 702 703 uint16_t control_flags; /* Control flags. */ 704 uint32_t total_byte_count; 705 uint32_t error_subcode_1; 706 uint32_t error_subcode_2; 707}; 708/* 709 * ISP queue - Mailbox Command entry structure definition. 710 */ 711#define MBX_IOCB_TYPE 0x39 712struct mbx_entry_24xx { 713 uint8_t entry_type; /* Entry type. */ 714 uint8_t entry_count; /* Entry count. */ 715 uint8_t handle_count; /* Handle count. */ 716 uint8_t entry_status; /* Entry Status. */ 717 718 uint32_t handle; /* System handle. */ 719 720 uint16_t mbx[28]; 721}; 722 723 724#define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 725struct logio_entry_24xx { 726 uint8_t entry_type; /* Entry type. */ 727 uint8_t entry_count; /* Entry count. */ 728 uint8_t sys_define; /* System defined. */ 729 uint8_t entry_status; /* Entry Status. */ 730 731 uint32_t handle; /* System handle. */ 732 733 uint16_t comp_status; /* Completion status. */ 734#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 735 736 uint16_t nport_handle; /* N_PORT handle. */ 737 738 uint16_t control_flags; /* Control flags. */ 739 /* Modifiers. */ 740#define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 741#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 742#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 743#define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 744#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 745#define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 746#define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 747#define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 748#define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 749#define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 750 /* Commands. */ 751#define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 752#define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 753#define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 754#define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 755#define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 756#define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 757#define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 758 759 uint8_t vp_index; 760 uint8_t reserved_1; 761 762 uint8_t port_id[3]; /* PortID of destination port. */ 763 764 uint8_t rsp_size; /* Response size in 32bit words. */ 765 766 uint32_t io_parameter[11]; /* General I/O parameters. */ 767#define LSC_SCODE_NOLINK 0x01 768#define LSC_SCODE_NOIOCB 0x02 769#define LSC_SCODE_NOXCB 0x03 770#define LSC_SCODE_CMD_FAILED 0x04 771#define LSC_SCODE_NOFABRIC 0x05 772#define LSC_SCODE_FW_NOT_READY 0x07 773#define LSC_SCODE_NOT_LOGGED_IN 0x09 774#define LSC_SCODE_NOPCB 0x0A 775 776#define LSC_SCODE_ELS_REJECT 0x18 777#define LSC_SCODE_CMD_PARAM_ERR 0x19 778#define LSC_SCODE_PORTID_USED 0x1A 779#define LSC_SCODE_NPORT_USED 0x1B 780#define LSC_SCODE_NONPORT 0x1C 781#define LSC_SCODE_LOGGED_IN 0x1D 782#define LSC_SCODE_NOFLOGI_ACC 0x1F 783}; 784 785#define TSK_MGMT_IOCB_TYPE 0x14 786struct tsk_mgmt_entry { 787 uint8_t entry_type; /* Entry type. */ 788 uint8_t entry_count; /* Entry count. */ 789 uint8_t handle_count; /* Handle count. */ 790 uint8_t entry_status; /* Entry Status. */ 791 792 uint32_t handle; /* System handle. */ 793 794 uint16_t nport_handle; /* N_PORT handle. */ 795 796 uint16_t reserved_1; 797 798 uint16_t delay; /* Activity delay in seconds. */ 799 800 uint16_t timeout; /* Command timeout. */ 801 802 struct scsi_lun lun; /* FCP LUN (BE). */ 803 804 uint32_t control_flags; /* Control Flags. */ 805#define TCF_NOTMCMD_TO_TARGET BIT_31 806#define TCF_LUN_RESET BIT_4 807#define TCF_ABORT_TASK_SET BIT_3 808#define TCF_CLEAR_TASK_SET BIT_2 809#define TCF_TARGET_RESET BIT_1 810#define TCF_CLEAR_ACA BIT_0 811 812 uint8_t reserved_2[20]; 813 814 uint8_t port_id[3]; /* PortID of destination port. */ 815 uint8_t vp_index; 816 817 uint8_t reserved_3[12]; 818}; 819 820#define ABORT_IOCB_TYPE 0x33 821struct abort_entry_24xx { 822 uint8_t entry_type; /* Entry type. */ 823 uint8_t entry_count; /* Entry count. */ 824 uint8_t handle_count; /* Handle count. */ 825 uint8_t entry_status; /* Entry Status. */ 826 827 uint32_t handle; /* System handle. */ 828 829 uint16_t nport_handle; /* N_PORT handle. */ 830 /* or Completion status. */ 831 832 uint16_t options; /* Options. */ 833#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 834 835 uint32_t handle_to_abort; /* System handle to abort. */ 836 837 uint16_t req_que_no; 838 uint8_t reserved_1[30]; 839 840 uint8_t port_id[3]; /* PortID of destination port. */ 841 uint8_t vp_index; 842 843 uint8_t reserved_2[12]; 844}; 845 846/* 847 * ISP I/O Register Set structure definitions. 848 */ 849struct device_reg_24xx { 850 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 851#define FARX_DATA_FLAG BIT_31 852#define FARX_ACCESS_FLASH_CONF 0x7FFD0000 853#define FARX_ACCESS_FLASH_DATA 0x7FF00000 854#define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 855#define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 856 857#define FA_NVRAM_FUNC0_ADDR 0x80 858#define FA_NVRAM_FUNC1_ADDR 0x180 859 860#define FA_NVRAM_VPD_SIZE 0x200 861#define FA_NVRAM_VPD0_ADDR 0x00 862#define FA_NVRAM_VPD1_ADDR 0x100 863 864#define FA_BOOT_CODE_ADDR 0x00000 865 /* 866 * RISC code begins at offset 512KB 867 * within flash. Consisting of two 868 * contiguous RISC code segments. 869 */ 870#define FA_RISC_CODE_ADDR 0x20000 871#define FA_RISC_CODE_SEGMENTS 2 872 873#define FA_FLASH_DESCR_ADDR_24 0x11000 874#define FA_FLASH_LAYOUT_ADDR_24 0x11400 875#define FA_NPIV_CONF0_ADDR_24 0x16000 876#define FA_NPIV_CONF1_ADDR_24 0x17000 877 878#define FA_FW_AREA_ADDR 0x40000 879#define FA_VPD_NVRAM_ADDR 0x48000 880#define FA_FEATURE_ADDR 0x4C000 881#define FA_FLASH_DESCR_ADDR 0x50000 882#define FA_FLASH_LAYOUT_ADDR 0x50400 883#define FA_HW_EVENT0_ADDR 0x54000 884#define FA_HW_EVENT1_ADDR 0x54400 885#define FA_HW_EVENT_SIZE 0x200 886#define FA_HW_EVENT_ENTRY_SIZE 4 887#define FA_NPIV_CONF0_ADDR 0x5C000 888#define FA_NPIV_CONF1_ADDR 0x5D000 889#define FA_FCP_PRIO0_ADDR 0x10000 890#define FA_FCP_PRIO1_ADDR 0x12000 891 892/* 893 * Flash Error Log Event Codes. 894 */ 895#define HW_EVENT_RESET_ERR 0xF00B 896#define HW_EVENT_ISP_ERR 0xF020 897#define HW_EVENT_PARITY_ERR 0xF022 898#define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 899#define HW_EVENT_FLASH_FW_ERR 0xF024 900 901 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 902 903 uint32_t ctrl_status; /* Control/Status. */ 904#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 905#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 906#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 907#define CSRX_FUNCTION BIT_15 /* Function number. */ 908 /* PCI-X Bus Mode. */ 909#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 910#define PBM_PCI_33MHZ (0 << 8) 911#define PBM_PCIX_M1_66MHZ (1 << 8) 912#define PBM_PCIX_M1_100MHZ (2 << 8) 913#define PBM_PCIX_M1_133MHZ (3 << 8) 914#define PBM_PCIX_M2_66MHZ (5 << 8) 915#define PBM_PCIX_M2_100MHZ (6 << 8) 916#define PBM_PCIX_M2_133MHZ (7 << 8) 917#define PBM_PCI_66MHZ (8 << 8) 918 /* Max Write Burst byte count. */ 919#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 920#define MWB_512_BYTES (0 << 4) 921#define MWB_1024_BYTES (1 << 4) 922#define MWB_2048_BYTES (2 << 4) 923#define MWB_4096_BYTES (3 << 4) 924 925#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 926#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 927#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 928 929 uint32_t ictrl; /* Interrupt control. */ 930#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 931 932 uint32_t istatus; /* Interrupt status. */ 933#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 934 935 uint32_t unused_1[2]; /* Gap. */ 936 937 /* Request Queue. */ 938 uint32_t req_q_in; /* In-Pointer. */ 939 uint32_t req_q_out; /* Out-Pointer. */ 940 /* Response Queue. */ 941 uint32_t rsp_q_in; /* In-Pointer. */ 942 uint32_t rsp_q_out; /* Out-Pointer. */ 943 /* Priority Request Queue. */ 944 uint32_t preq_q_in; /* In-Pointer. */ 945 uint32_t preq_q_out; /* Out-Pointer. */ 946 947 uint32_t unused_2[2]; /* Gap. */ 948 949 /* ATIO Queue. */ 950 uint32_t atio_q_in; /* In-Pointer. */ 951 uint32_t atio_q_out; /* Out-Pointer. */ 952 953 uint32_t host_status; 954#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 955#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 956 957 uint32_t hccr; /* Host command & control register. */ 958 /* HCCR statuses. */ 959#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 960#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 961 /* HCCR commands. */ 962 /* NOOP. */ 963#define HCCRX_NOOP 0x00000000 964 /* Set RISC Reset. */ 965#define HCCRX_SET_RISC_RESET 0x10000000 966 /* Clear RISC Reset. */ 967#define HCCRX_CLR_RISC_RESET 0x20000000 968 /* Set RISC Pause. */ 969#define HCCRX_SET_RISC_PAUSE 0x30000000 970 /* Releases RISC Pause. */ 971#define HCCRX_REL_RISC_PAUSE 0x40000000 972 /* Set HOST to RISC interrupt. */ 973#define HCCRX_SET_HOST_INT 0x50000000 974 /* Clear HOST to RISC interrupt. */ 975#define HCCRX_CLR_HOST_INT 0x60000000 976 /* Clear RISC to PCI interrupt. */ 977#define HCCRX_CLR_RISC_INT 0xA0000000 978 979 uint32_t gpiod; /* GPIO Data register. */ 980 981 /* LED update mask. */ 982#define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 983 /* Data update mask. */ 984#define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 985 /* Data update mask. */ 986#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 987 /* LED control mask. */ 988#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 989 /* LED bit values. Color names as 990 * referenced in fw spec. 991 */ 992#define GPDX_LED_YELLOW_ON BIT_2 993#define GPDX_LED_GREEN_ON BIT_3 994#define GPDX_LED_AMBER_ON BIT_4 995 /* Data in/out. */ 996#define GPDX_DATA_INOUT (BIT_1|BIT_0) 997 998 uint32_t gpioe; /* GPIO Enable register. */ 999 /* Enable update mask. */ 1000#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 1001 /* Enable update mask. */ 1002#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1003 /* Enable. */ 1004#define GPEX_ENABLE (BIT_1|BIT_0) 1005 1006 uint32_t iobase_addr; /* I/O Bus Base Address register. */ 1007 1008 uint32_t unused_3[10]; /* Gap. */ 1009 1010 uint16_t mailbox0; 1011 uint16_t mailbox1; 1012 uint16_t mailbox2; 1013 uint16_t mailbox3; 1014 uint16_t mailbox4; 1015 uint16_t mailbox5; 1016 uint16_t mailbox6; 1017 uint16_t mailbox7; 1018 uint16_t mailbox8; 1019 uint16_t mailbox9; 1020 uint16_t mailbox10; 1021 uint16_t mailbox11; 1022 uint16_t mailbox12; 1023 uint16_t mailbox13; 1024 uint16_t mailbox14; 1025 uint16_t mailbox15; 1026 uint16_t mailbox16; 1027 uint16_t mailbox17; 1028 uint16_t mailbox18; 1029 uint16_t mailbox19; 1030 uint16_t mailbox20; 1031 uint16_t mailbox21; 1032 uint16_t mailbox22; 1033 uint16_t mailbox23; 1034 uint16_t mailbox24; 1035 uint16_t mailbox25; 1036 uint16_t mailbox26; 1037 uint16_t mailbox27; 1038 uint16_t mailbox28; 1039 uint16_t mailbox29; 1040 uint16_t mailbox30; 1041 uint16_t mailbox31; 1042 1043 uint32_t iobase_window; 1044 uint32_t iobase_c4; 1045 uint32_t iobase_c8; 1046 uint32_t unused_4_1[6]; /* Gap. */ 1047 uint32_t iobase_q; 1048 uint32_t unused_5[2]; /* Gap. */ 1049 uint32_t iobase_select; 1050 uint32_t unused_6[2]; /* Gap. */ 1051 uint32_t iobase_sdata; 1052}; 1053 1054/* Trace Control *************************************************************/ 1055 1056#define TC_AEN_DISABLE 0 1057 1058#define TC_EFT_ENABLE 4 1059#define TC_EFT_DISABLE 5 1060 1061#define TC_FCE_ENABLE 8 1062#define TC_FCE_OPTIONS 0 1063#define TC_FCE_DEFAULT_RX_SIZE 2112 1064#define TC_FCE_DEFAULT_TX_SIZE 2112 1065#define TC_FCE_DISABLE 9 1066#define TC_FCE_DISABLE_TRACE BIT_0 1067 1068/* MID Support ***************************************************************/ 1069 1070#define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ 1071#define MAX_MULTI_ID_FABRIC 256 /* ... */ 1072 1073#define for_each_mapped_vp_idx(_ha, _idx) \ 1074 for (_idx = find_next_bit((_ha)->vp_idx_map, \ 1075 (_ha)->max_npiv_vports + 1, 1); \ 1076 _idx <= (_ha)->max_npiv_vports; \ 1077 _idx = find_next_bit((_ha)->vp_idx_map, \ 1078 (_ha)->max_npiv_vports + 1, _idx + 1)) \ 1079 1080struct mid_conf_entry_24xx { 1081 uint16_t reserved_1; 1082 1083 /* 1084 * BIT 0 = Enable Hard Loop Id 1085 * BIT 1 = Acquire Loop ID in LIPA 1086 * BIT 2 = ID not Acquired 1087 * BIT 3 = Enable VP 1088 * BIT 4 = Enable Initiator Mode 1089 * BIT 5 = Disable Target Mode 1090 * BIT 6-7 = Reserved 1091 */ 1092 uint8_t options; 1093 1094 uint8_t hard_address; 1095 1096 uint8_t port_name[WWN_SIZE]; 1097 uint8_t node_name[WWN_SIZE]; 1098}; 1099 1100struct mid_init_cb_24xx { 1101 struct init_cb_24xx init_cb; 1102 1103 uint16_t count; 1104 uint16_t options; 1105 1106 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1107}; 1108 1109 1110struct mid_db_entry_24xx { 1111 uint16_t status; 1112#define MDBS_NON_PARTIC BIT_3 1113#define MDBS_ID_ACQUIRED BIT_1 1114#define MDBS_ENABLED BIT_0 1115 1116 uint8_t options; 1117 uint8_t hard_address; 1118 1119 uint8_t port_name[WWN_SIZE]; 1120 uint8_t node_name[WWN_SIZE]; 1121 1122 uint8_t port_id[3]; 1123 uint8_t reserved_1; 1124}; 1125 1126/* 1127 * Virtual Port Control IOCB 1128 */ 1129#define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */ 1130struct vp_ctrl_entry_24xx { 1131 uint8_t entry_type; /* Entry type. */ 1132 uint8_t entry_count; /* Entry count. */ 1133 uint8_t sys_define; /* System defined. */ 1134 uint8_t entry_status; /* Entry Status. */ 1135 1136 uint32_t handle; /* System handle. */ 1137 1138 uint16_t vp_idx_failed; 1139 1140 uint16_t comp_status; /* Completion status. */ 1141#define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ 1142#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 1143#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1144 1145 uint16_t command; 1146#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 1147#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 1148#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 1149#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 1150#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ 1151 1152 uint16_t vp_count; 1153 1154 uint8_t vp_idx_map[16]; 1155 uint16_t flags; 1156 uint16_t id; 1157 uint16_t reserved_4; 1158 uint16_t hopct; 1159 uint8_t reserved_5[24]; 1160}; 1161 1162/* 1163 * Modify Virtual Port Configuration IOCB 1164 */ 1165#define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */ 1166struct vp_config_entry_24xx { 1167 uint8_t entry_type; /* Entry type. */ 1168 uint8_t entry_count; /* Entry count. */ 1169 uint8_t handle_count; 1170 uint8_t entry_status; /* Entry Status. */ 1171 1172 uint32_t handle; /* System handle. */ 1173 1174 uint16_t flags; 1175#define CS_VF_BIND_VPORTS_TO_VF BIT_0 1176#define CS_VF_SET_QOS_OF_VPORTS BIT_1 1177#define CS_VF_SET_HOPS_OF_VPORTS BIT_2 1178 1179 uint16_t comp_status; /* Completion status. */ 1180#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 1181#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 1182#define CS_VCT_ERROR 0x03 /* Unknown error. */ 1183#define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 1184#define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1185 1186 uint8_t command; 1187#define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ 1188#define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ 1189 1190 uint8_t vp_count; 1191 1192 uint8_t vp_index1; 1193 uint8_t vp_index2; 1194 1195 uint8_t options_idx1; 1196 uint8_t hard_address_idx1; 1197 uint16_t reserved_vp1; 1198 uint8_t port_name_idx1[WWN_SIZE]; 1199 uint8_t node_name_idx1[WWN_SIZE]; 1200 1201 uint8_t options_idx2; 1202 uint8_t hard_address_idx2; 1203 uint16_t reserved_vp2; 1204 uint8_t port_name_idx2[WWN_SIZE]; 1205 uint8_t node_name_idx2[WWN_SIZE]; 1206 uint16_t id; 1207 uint16_t reserved_4; 1208 uint16_t hopct; 1209 uint8_t reserved_5[2]; 1210}; 1211 1212#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 1213struct vp_rpt_id_entry_24xx { 1214 uint8_t entry_type; /* Entry type. */ 1215 uint8_t entry_count; /* Entry count. */ 1216 uint8_t sys_define; /* System defined. */ 1217 uint8_t entry_status; /* Entry Status. */ 1218 1219 uint32_t handle; /* System handle. */ 1220 1221 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 1222 /* Format 1 -- | VP count |. */ 1223 uint16_t vp_idx; /* Format 0 -- Reserved. */ 1224 /* Format 1 -- VP status and index. */ 1225 1226 uint8_t port_id[3]; 1227 uint8_t format; 1228 1229 uint8_t vp_idx_map[16]; 1230 1231 uint8_t reserved_4[32]; 1232}; 1233 1234#define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ 1235struct vf_evfp_entry_24xx { 1236 uint8_t entry_type; /* Entry type. */ 1237 uint8_t entry_count; /* Entry count. */ 1238 uint8_t sys_define; /* System defined. */ 1239 uint8_t entry_status; /* Entry Status. */ 1240 1241 uint32_t handle; /* System handle. */ 1242 uint16_t comp_status; /* Completion status. */ 1243 uint16_t timeout; /* timeout */ 1244 uint16_t adim_tagging_mode; 1245 1246 uint16_t vfport_id; 1247 uint32_t exch_addr; 1248 1249 uint16_t nport_handle; /* N_PORT handle. */ 1250 uint16_t control_flags; 1251 uint32_t io_parameter_0; 1252 uint32_t io_parameter_1; 1253 uint32_t tx_address[2]; /* Data segment 0 address. */ 1254 uint32_t tx_len; /* Data segment 0 length. */ 1255 uint32_t rx_address[2]; /* Data segment 1 address. */ 1256 uint32_t rx_len; /* Data segment 1 length. */ 1257}; 1258 1259/* END MID Support ***********************************************************/ 1260 1261/* Flash Description Table ***************************************************/ 1262 1263struct qla_fdt_layout { 1264 uint8_t sig[4]; 1265 uint16_t version; 1266 uint16_t len; 1267 uint16_t checksum; 1268 uint8_t unused1[2]; 1269 uint8_t model[16]; 1270 uint16_t man_id; 1271 uint16_t id; 1272 uint8_t flags; 1273 uint8_t erase_cmd; 1274 uint8_t alt_erase_cmd; 1275 uint8_t wrt_enable_cmd; 1276 uint8_t wrt_enable_bits; 1277 uint8_t wrt_sts_reg_cmd; 1278 uint8_t unprotect_sec_cmd; 1279 uint8_t read_man_id_cmd; 1280 uint32_t block_size; 1281 uint32_t alt_block_size; 1282 uint32_t flash_size; 1283 uint32_t wrt_enable_data; 1284 uint8_t read_id_addr_len; 1285 uint8_t wrt_disable_bits; 1286 uint8_t read_dev_id_len; 1287 uint8_t chip_erase_cmd; 1288 uint16_t read_timeout; 1289 uint8_t protect_sec_cmd; 1290 uint8_t unused2[65]; 1291}; 1292 1293/* Flash Layout Table ********************************************************/ 1294 1295struct qla_flt_location { 1296 uint8_t sig[4]; 1297 uint16_t start_lo; 1298 uint16_t start_hi; 1299 uint8_t version; 1300 uint8_t unused[5]; 1301 uint16_t checksum; 1302}; 1303 1304struct qla_flt_header { 1305 uint16_t version; 1306 uint16_t length; 1307 uint16_t checksum; 1308 uint16_t unused; 1309}; 1310 1311#define FLT_REG_FW 0x01 1312#define FLT_REG_BOOT_CODE 0x07 1313#define FLT_REG_VPD_0 0x14 1314#define FLT_REG_NVRAM_0 0x15 1315#define FLT_REG_VPD_1 0x16 1316#define FLT_REG_NVRAM_1 0x17 1317#define FLT_REG_FDT 0x1a 1318#define FLT_REG_FLT 0x1c 1319#define FLT_REG_HW_EVENT_0 0x1d 1320#define FLT_REG_HW_EVENT_1 0x1f 1321#define FLT_REG_NPIV_CONF_0 0x29 1322#define FLT_REG_NPIV_CONF_1 0x2a 1323#define FLT_REG_GOLD_FW 0x2f 1324#define FLT_REG_FCP_PRIO_0 0x87 1325#define FLT_REG_FCP_PRIO_1 0x88 1326 1327struct qla_flt_region { 1328 uint32_t code; 1329 uint32_t size; 1330 uint32_t start; 1331 uint32_t end; 1332}; 1333 1334/* Flash NPIV Configuration Table ********************************************/ 1335 1336struct qla_npiv_header { 1337 uint8_t sig[2]; 1338 uint16_t version; 1339 uint16_t entries; 1340 uint16_t unused[4]; 1341 uint16_t checksum; 1342}; 1343 1344struct qla_npiv_entry { 1345 uint16_t flags; 1346 uint16_t vf_id; 1347 uint8_t q_qos; 1348 uint8_t f_qos; 1349 uint16_t unused1; 1350 uint8_t port_name[WWN_SIZE]; 1351 uint8_t node_name[WWN_SIZE]; 1352}; 1353 1354/* 84XX Support **************************************************************/ 1355 1356#define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ 1357#define A84_PANIC_RECOVERY 0x1 1358#define A84_OP_LOGIN_COMPLETE 0x2 1359#define A84_DIAG_LOGIN_COMPLETE 0x3 1360#define A84_GOLD_LOGIN_COMPLETE 0x4 1361 1362#define MBC_ISP84XX_RESET 0x3a /* Reset. */ 1363 1364#define FSTATE_REMOTE_FC_DOWN BIT_0 1365#define FSTATE_NSL_LINK_DOWN BIT_1 1366#define FSTATE_IS_DIAG_FW BIT_2 1367#define FSTATE_LOGGED_IN BIT_3 1368#define FSTATE_WAITING_FOR_VERIFY BIT_4 1369 1370#define VERIFY_CHIP_IOCB_TYPE 0x1B 1371struct verify_chip_entry_84xx { 1372 uint8_t entry_type; 1373 uint8_t entry_count; 1374 uint8_t sys_defined; 1375 uint8_t entry_status; 1376 1377 uint32_t handle; 1378 1379 uint16_t options; 1380#define VCO_DONT_UPDATE_FW BIT_0 1381#define VCO_FORCE_UPDATE BIT_1 1382#define VCO_DONT_RESET_UPDATE BIT_2 1383#define VCO_DIAG_FW BIT_3 1384#define VCO_END_OF_DATA BIT_14 1385#define VCO_ENABLE_DSD BIT_15 1386 1387 uint16_t reserved_1; 1388 1389 uint16_t data_seg_cnt; 1390 uint16_t reserved_2[3]; 1391 1392 uint32_t fw_ver; 1393 uint32_t exchange_address; 1394 1395 uint32_t reserved_3[3]; 1396 uint32_t fw_size; 1397 uint32_t fw_seq_size; 1398 uint32_t relative_offset; 1399 1400 uint32_t dseg_address[2]; 1401 uint32_t dseg_length; 1402}; 1403 1404struct verify_chip_rsp_84xx { 1405 uint8_t entry_type; 1406 uint8_t entry_count; 1407 uint8_t sys_defined; 1408 uint8_t entry_status; 1409 1410 uint32_t handle; 1411 1412 uint16_t comp_status; 1413#define CS_VCS_CHIP_FAILURE 0x3 1414#define CS_VCS_BAD_EXCHANGE 0x8 1415#define CS_VCS_SEQ_COMPLETEi 0x40 1416 1417 uint16_t failure_code; 1418#define VFC_CHECKSUM_ERROR 0x1 1419#define VFC_INVALID_LEN 0x2 1420#define VFC_ALREADY_IN_PROGRESS 0x8 1421 1422 uint16_t reserved_1[4]; 1423 1424 uint32_t fw_ver; 1425 uint32_t exchange_address; 1426 1427 uint32_t reserved_2[6]; 1428}; 1429 1430#define ACCESS_CHIP_IOCB_TYPE 0x2B 1431struct access_chip_84xx { 1432 uint8_t entry_type; 1433 uint8_t entry_count; 1434 uint8_t sys_defined; 1435 uint8_t entry_status; 1436 1437 uint32_t handle; 1438 1439 uint16_t options; 1440#define ACO_DUMP_MEMORY 0x0 1441#define ACO_LOAD_MEMORY 0x1 1442#define ACO_CHANGE_CONFIG_PARAM 0x2 1443#define ACO_REQUEST_INFO 0x3 1444 1445 uint16_t reserved1; 1446 1447 uint16_t dseg_count; 1448 uint16_t reserved2[3]; 1449 1450 uint32_t parameter1; 1451 uint32_t parameter2; 1452 uint32_t parameter3; 1453 1454 uint32_t reserved3[3]; 1455 uint32_t total_byte_cnt; 1456 uint32_t reserved4; 1457 1458 uint32_t dseg_address[2]; 1459 uint32_t dseg_length; 1460}; 1461 1462struct access_chip_rsp_84xx { 1463 uint8_t entry_type; 1464 uint8_t entry_count; 1465 uint8_t sys_defined; 1466 uint8_t entry_status; 1467 1468 uint32_t handle; 1469 1470 uint16_t comp_status; 1471 uint16_t failure_code; 1472 uint32_t residual_count; 1473 1474 uint32_t reserved[12]; 1475}; 1476 1477/* 81XX Support **************************************************************/ 1478 1479#define MBA_DCBX_START 0x8016 1480#define MBA_DCBX_COMPLETE 0x8030 1481#define MBA_FCF_CONF_ERR 0x8031 1482#define MBA_DCBX_PARAM_UPDATE 0x8032 1483#define MBA_IDC_COMPLETE 0x8100 1484#define MBA_IDC_NOTIFY 0x8101 1485#define MBA_IDC_TIME_EXT 0x8102 1486 1487#define MBC_IDC_ACK 0x101 1488#define MBC_RESTART_MPI_FW 0x3d 1489#define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */ 1490#define MBC_GET_XGMAC_STATS 0x7a 1491#define MBC_GET_DCBX_PARAMS 0x51 1492 1493/* Flash access control option field bit definitions */ 1494#define FAC_OPT_FORCE_SEMAPHORE BIT_15 1495#define FAC_OPT_REQUESTOR_ID BIT_14 1496#define FAC_OPT_CMD_SUBCODE 0xff 1497 1498/* Flash access control command subcodes */ 1499#define FAC_OPT_CMD_WRITE_PROTECT 0x00 1500#define FAC_OPT_CMD_WRITE_ENABLE 0x01 1501#define FAC_OPT_CMD_ERASE_SECTOR 0x02 1502#define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03 1503#define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04 1504#define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05 1505 1506struct nvram_81xx { 1507 /* NVRAM header. */ 1508 uint8_t id[4]; 1509 uint16_t nvram_version; 1510 uint16_t reserved_0; 1511 1512 /* Firmware Initialization Control Block. */ 1513 uint16_t version; 1514 uint16_t reserved_1; 1515 uint16_t frame_payload_size; 1516 uint16_t execution_throttle; 1517 uint16_t exchange_count; 1518 uint16_t reserved_2; 1519 1520 uint8_t port_name[WWN_SIZE]; 1521 uint8_t node_name[WWN_SIZE]; 1522 1523 uint16_t login_retry_count; 1524 uint16_t reserved_3; 1525 uint16_t interrupt_delay_timer; 1526 uint16_t login_timeout; 1527 1528 uint32_t firmware_options_1; 1529 uint32_t firmware_options_2; 1530 uint32_t firmware_options_3; 1531 1532 uint16_t reserved_4[4]; 1533 1534 /* Offset 64. */ 1535 uint8_t enode_mac[6]; 1536 uint16_t reserved_5[5]; 1537 1538 /* Offset 80. */ 1539 uint16_t reserved_6[24]; 1540 1541 /* Offset 128. */ 1542 uint16_t ex_version; 1543 uint8_t prio_fcf_matching_flags; 1544 uint8_t reserved_6_1[3]; 1545 uint16_t pri_fcf_vlan_id; 1546 uint8_t pri_fcf_fabric_name[8]; 1547 uint16_t reserved_6_2[7]; 1548 uint8_t spma_mac_addr[6]; 1549 uint16_t reserved_6_3[14]; 1550 1551 /* Offset 192. */ 1552 uint16_t reserved_7[32]; 1553 1554 /* 1555 * BIT 0 = Enable spinup delay 1556 * BIT 1 = Disable BIOS 1557 * BIT 2 = Enable Memory Map BIOS 1558 * BIT 3 = Enable Selectable Boot 1559 * BIT 4 = Disable RISC code load 1560 * BIT 5 = Disable Serdes 1561 * BIT 6 = Opt boot mode 1562 * BIT 7 = Interrupt enable 1563 * 1564 * BIT 8 = EV Control enable 1565 * BIT 9 = Enable lip reset 1566 * BIT 10 = Enable lip full login 1567 * BIT 11 = Enable target reset 1568 * BIT 12 = Stop firmware 1569 * BIT 13 = Enable nodename option 1570 * BIT 14 = Default WWPN valid 1571 * BIT 15 = Enable alternate WWN 1572 * 1573 * BIT 16 = CLP LUN string 1574 * BIT 17 = CLP Target string 1575 * BIT 18 = CLP BIOS enable string 1576 * BIT 19 = CLP Serdes string 1577 * BIT 20 = CLP WWPN string 1578 * BIT 21 = CLP WWNN string 1579 * BIT 22 = 1580 * BIT 23 = 1581 * BIT 24 = Keep WWPN 1582 * BIT 25 = Temp WWPN 1583 * BIT 26-31 = 1584 */ 1585 uint32_t host_p; 1586 1587 uint8_t alternate_port_name[WWN_SIZE]; 1588 uint8_t alternate_node_name[WWN_SIZE]; 1589 1590 uint8_t boot_port_name[WWN_SIZE]; 1591 uint16_t boot_lun_number; 1592 uint16_t reserved_8; 1593 1594 uint8_t alt1_boot_port_name[WWN_SIZE]; 1595 uint16_t alt1_boot_lun_number; 1596 uint16_t reserved_9; 1597 1598 uint8_t alt2_boot_port_name[WWN_SIZE]; 1599 uint16_t alt2_boot_lun_number; 1600 uint16_t reserved_10; 1601 1602 uint8_t alt3_boot_port_name[WWN_SIZE]; 1603 uint16_t alt3_boot_lun_number; 1604 uint16_t reserved_11; 1605 1606 /* 1607 * BIT 0 = Selective Login 1608 * BIT 1 = Alt-Boot Enable 1609 * BIT 2 = Reserved 1610 * BIT 3 = Boot Order List 1611 * BIT 4 = Reserved 1612 * BIT 5 = Selective LUN 1613 * BIT 6 = Reserved 1614 * BIT 7-31 = 1615 */ 1616 uint32_t efi_parameters; 1617 1618 uint8_t reset_delay; 1619 uint8_t reserved_12; 1620 uint16_t reserved_13; 1621 1622 uint16_t boot_id_number; 1623 uint16_t reserved_14; 1624 1625 uint16_t max_luns_per_target; 1626 uint16_t reserved_15; 1627 1628 uint16_t port_down_retry_count; 1629 uint16_t link_down_timeout; 1630 1631 /* FCode parameters. */ 1632 uint16_t fcode_parameter; 1633 1634 uint16_t reserved_16[3]; 1635 1636 /* Offset 352. */ 1637 uint8_t reserved_17[4]; 1638 uint16_t reserved_18[5]; 1639 uint8_t reserved_19[2]; 1640 uint16_t reserved_20[8]; 1641 1642 /* Offset 384. */ 1643 uint8_t reserved_21[16]; 1644 uint16_t reserved_22[3]; 1645 1646 /* 1647 * BIT 0 = Extended BB credits for LR 1648 * BIT 1 = Virtual Fabric Enable 1649 * BIT 2 = Enhanced Features Unused 1650 * BIT 3-7 = Enhanced Features Reserved 1651 */ 1652 /* Enhanced Features */ 1653 uint8_t enhanced_features; 1654 1655 uint8_t reserved_23; 1656 uint16_t reserved_24[4]; 1657 1658 /* Offset 416. */ 1659 uint16_t reserved_25[32]; 1660 1661 /* Offset 480. */ 1662 uint8_t model_name[16]; 1663 1664 /* Offset 496. */ 1665 uint16_t feature_mask_l; 1666 uint16_t feature_mask_h; 1667 uint16_t reserved_26[2]; 1668 1669 uint16_t subsystem_vendor_id; 1670 uint16_t subsystem_device_id; 1671 1672 uint32_t checksum; 1673}; 1674 1675/* 1676 * ISP Initialization Control Block. 1677 * Little endian except where noted. 1678 */ 1679#define ICB_VERSION 1 1680struct init_cb_81xx { 1681 uint16_t version; 1682 uint16_t reserved_1; 1683 1684 uint16_t frame_payload_size; 1685 uint16_t execution_throttle; 1686 uint16_t exchange_count; 1687 1688 uint16_t reserved_2; 1689 1690 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1691 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1692 1693 uint16_t response_q_inpointer; 1694 uint16_t request_q_outpointer; 1695 1696 uint16_t login_retry_count; 1697 1698 uint16_t prio_request_q_outpointer; 1699 1700 uint16_t response_q_length; 1701 uint16_t request_q_length; 1702 1703 uint16_t reserved_3; 1704 1705 uint16_t prio_request_q_length; 1706 1707 uint32_t request_q_address[2]; 1708 uint32_t response_q_address[2]; 1709 uint32_t prio_request_q_address[2]; 1710 1711 uint8_t reserved_4[8]; 1712 1713 uint16_t atio_q_inpointer; 1714 uint16_t atio_q_length; 1715 uint32_t atio_q_address[2]; 1716 1717 uint16_t interrupt_delay_timer; /* 100us increments. */ 1718 uint16_t login_timeout; 1719 1720 /* 1721 * BIT 0-3 = Reserved 1722 * BIT 4 = Enable Target Mode 1723 * BIT 5 = Disable Initiator Mode 1724 * BIT 6 = Reserved 1725 * BIT 7 = Reserved 1726 * 1727 * BIT 8-13 = Reserved 1728 * BIT 14 = Node Name Option 1729 * BIT 15-31 = Reserved 1730 */ 1731 uint32_t firmware_options_1; 1732 1733 /* 1734 * BIT 0 = Operation Mode bit 0 1735 * BIT 1 = Operation Mode bit 1 1736 * BIT 2 = Operation Mode bit 2 1737 * BIT 3 = Operation Mode bit 3 1738 * BIT 4-7 = Reserved 1739 * 1740 * BIT 8 = Enable Class 2 1741 * BIT 9 = Enable ACK0 1742 * BIT 10 = Reserved 1743 * BIT 11 = Enable FC-SP Security 1744 * BIT 12 = FC Tape Enable 1745 * BIT 13 = Reserved 1746 * BIT 14 = Enable Target PRLI Control 1747 * BIT 15-31 = Reserved 1748 */ 1749 uint32_t firmware_options_2; 1750 1751 /* 1752 * BIT 0-3 = Reserved 1753 * BIT 4 = FCP RSP Payload bit 0 1754 * BIT 5 = FCP RSP Payload bit 1 1755 * BIT 6 = Enable Receive Out-of-Order data frame handling 1756 * BIT 7 = Reserved 1757 * 1758 * BIT 8 = Reserved 1759 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 1760 * BIT 10-16 = Reserved 1761 * BIT 17 = Enable multiple FCFs 1762 * BIT 18-20 = MAC addressing mode 1763 * BIT 21-25 = Ethernet data rate 1764 * BIT 26 = Enable ethernet header rx IOCB for ATIO q 1765 * BIT 27 = Enable ethernet header rx IOCB for response q 1766 * BIT 28 = SPMA selection bit 0 1767 * BIT 28 = SPMA selection bit 1 1768 * BIT 30-31 = Reserved 1769 */ 1770 uint32_t firmware_options_3; 1771 1772 uint8_t reserved_5[8]; 1773 1774 uint8_t enode_mac[6]; 1775 1776 uint8_t reserved_6[10]; 1777}; 1778 1779struct mid_init_cb_81xx { 1780 struct init_cb_81xx init_cb; 1781 1782 uint16_t count; 1783 uint16_t options; 1784 1785 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1786}; 1787 1788struct ex_init_cb_81xx { 1789 uint16_t ex_version; 1790 uint8_t prio_fcf_matching_flags; 1791 uint8_t reserved_1[3]; 1792 uint16_t pri_fcf_vlan_id; 1793 uint8_t pri_fcf_fabric_name[8]; 1794 uint16_t reserved_2[7]; 1795 uint8_t spma_mac_addr[6]; 1796 uint16_t reserved_3[14]; 1797}; 1798 1799#define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000 1800#define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000 1801 1802/* FCP priority config defines *************************************/ 1803/* operations */ 1804#define QLFC_FCP_PRIO_DISABLE 0x0 1805#define QLFC_FCP_PRIO_ENABLE 0x1 1806#define QLFC_FCP_PRIO_GET_CONFIG 0x2 1807#define QLFC_FCP_PRIO_SET_CONFIG 0x3 1808 1809struct qla_fcp_prio_entry { 1810 uint16_t flags; /* Describes parameter(s) in FCP */ 1811 /* priority entry that are valid */ 1812#define FCP_PRIO_ENTRY_VALID 0x1 1813#define FCP_PRIO_ENTRY_TAG_VALID 0x2 1814#define FCP_PRIO_ENTRY_SPID_VALID 0x4 1815#define FCP_PRIO_ENTRY_DPID_VALID 0x8 1816#define FCP_PRIO_ENTRY_LUNB_VALID 0x10 1817#define FCP_PRIO_ENTRY_LUNE_VALID 0x20 1818#define FCP_PRIO_ENTRY_SWWN_VALID 0x40 1819#define FCP_PRIO_ENTRY_DWWN_VALID 0x80 1820 uint8_t tag; /* Priority value */ 1821 uint8_t reserved; /* Reserved for future use */ 1822 uint32_t src_pid; /* Src port id. high order byte */ 1823 /* unused; -1 (wild card) */ 1824 uint32_t dst_pid; /* Src port id. high order byte */ 1825 /* unused; -1 (wild card) */ 1826 uint16_t lun_beg; /* 1st lun num of lun range. */ 1827 /* -1 (wild card) */ 1828 uint16_t lun_end; /* 2nd lun num of lun range. */ 1829 /* -1 (wild card) */ 1830 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */ 1831 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */ 1832}; 1833 1834struct qla_fcp_prio_cfg { 1835 uint8_t signature[4]; /* "HQOS" signature of config data */ 1836 uint16_t version; /* 1: Initial version */ 1837 uint16_t length; /* config data size in num bytes */ 1838 uint16_t checksum; /* config data bytes checksum */ 1839 uint16_t num_entries; /* Number of entries */ 1840 uint16_t size_of_entry; /* Size of each entry in num bytes */ 1841 uint8_t attributes; /* enable/disable, persistence */ 1842#define FCP_PRIO_ATTR_DISABLE 0x0 1843#define FCP_PRIO_ATTR_ENABLE 0x1 1844#define FCP_PRIO_ATTR_PERSIST 0x2 1845 uint8_t reserved; /* Reserved for future use */ 1846#define FCP_PRIO_CFG_HDR_SIZE 0x10 1847 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */ 1848#define FCP_PRIO_CFG_ENTRY_SIZE 0x20 1849}; 1850 1851#define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/ 1852 1853/* 25XX Support ****************************************************/ 1854#define FA_FCP_PRIO0_ADDR_25 0x3C000 1855#define FA_FCP_PRIO1_ADDR_25 0x3E000 1856 1857/* 81XX Flash locations -- occupies second 2MB region. */ 1858#define FA_BOOT_CODE_ADDR_81 0x80000 1859#define FA_RISC_CODE_ADDR_81 0xA0000 1860#define FA_FW_AREA_ADDR_81 0xC0000 1861#define FA_VPD_NVRAM_ADDR_81 0xD0000 1862#define FA_VPD0_ADDR_81 0xD0000 1863#define FA_VPD1_ADDR_81 0xD0400 1864#define FA_NVRAM0_ADDR_81 0xD0080 1865#define FA_NVRAM1_ADDR_81 0xD0180 1866#define FA_FEATURE_ADDR_81 0xD4000 1867#define FA_FLASH_DESCR_ADDR_81 0xD8000 1868#define FA_FLASH_LAYOUT_ADDR_81 0xD8400 1869#define FA_HW_EVENT0_ADDR_81 0xDC000 1870#define FA_HW_EVENT1_ADDR_81 0xDC400 1871#define FA_NPIV_CONF0_ADDR_81 0xD1000 1872#define FA_NPIV_CONF1_ADDR_81 0xD2000 1873 1874#endif 1875