1/* 2 * Marvell 88SE64xx hardware specific 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * 7 * This file is licensed under GPLv2. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 22 * USA 23*/ 24 25#include "mv_sas.h" 26#include "mv_64xx.h" 27#include "mv_chips.h" 28 29static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i) 30{ 31 void __iomem *regs = mvi->regs; 32 u32 reg; 33 struct mvs_phy *phy = &mvi->phy[i]; 34 35 /* TODO check & save device type */ 36 reg = mr32(MVS_GBL_PORT_TYPE); 37 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 38 if (reg & MODE_SAS_SATA & (1 << i)) 39 phy->phy_type |= PORT_TYPE_SAS; 40 else 41 phy->phy_type |= PORT_TYPE_SATA; 42} 43 44static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id) 45{ 46 void __iomem *regs = mvi->regs; 47 u32 tmp; 48 49 tmp = mr32(MVS_PCS); 50 if (mvi->chip->n_phy <= 4) 51 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); 52 else 53 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); 54 mw32(MVS_PCS, tmp); 55} 56 57static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi) 58{ 59 void __iomem *regs = mvi->regs; 60 61 mvs_phy_hacks(mvi); 62 63 if (!(mvi->flags & MVF_FLAG_SOC)) { 64 /* TEST - for phy decoding error, adjust voltage levels */ 65 mw32(MVS_P0_VSR_ADDR + 0, 0x8); 66 mw32(MVS_P0_VSR_DATA + 0, 0x2F0); 67 68 mw32(MVS_P0_VSR_ADDR + 8, 0x8); 69 mw32(MVS_P0_VSR_DATA + 8, 0x2F0); 70 71 mw32(MVS_P0_VSR_ADDR + 16, 0x8); 72 mw32(MVS_P0_VSR_DATA + 16, 0x2F0); 73 74 mw32(MVS_P0_VSR_ADDR + 24, 0x8); 75 mw32(MVS_P0_VSR_DATA + 24, 0x2F0); 76 } else { 77 int i; 78 /* disable auto port detection */ 79 mw32(MVS_GBL_PORT_TYPE, 0); 80 for (i = 0; i < mvi->chip->n_phy; i++) { 81 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7); 82 mvs_write_port_vsr_data(mvi, i, 0x90000000); 83 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9); 84 mvs_write_port_vsr_data(mvi, i, 0x50f2); 85 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11); 86 mvs_write_port_vsr_data(mvi, i, 0x0e); 87 } 88 } 89} 90 91static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id) 92{ 93 void __iomem *regs = mvi->regs; 94 u32 reg, tmp; 95 96 if (!(mvi->flags & MVF_FLAG_SOC)) { 97 if (phy_id < 4) 98 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®); 99 else 100 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®); 101 102 } else 103 reg = mr32(MVS_PHY_CTL); 104 105 tmp = reg; 106 if (phy_id < 4) 107 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; 108 else 109 tmp |= (1U << (phy_id - 4)) << PCTL_LINK_OFFS; 110 111 if (!(mvi->flags & MVF_FLAG_SOC)) { 112 if (phy_id < 4) { 113 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); 114 mdelay(10); 115 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg); 116 } else { 117 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); 118 mdelay(10); 119 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg); 120 } 121 } else { 122 mw32(MVS_PHY_CTL, tmp); 123 mdelay(10); 124 mw32(MVS_PHY_CTL, reg); 125 } 126} 127 128static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) 129{ 130 u32 tmp; 131 tmp = mvs_read_port_irq_stat(mvi, phy_id); 132 tmp &= ~PHYEV_RDY_CH; 133 mvs_write_port_irq_stat(mvi, phy_id, tmp); 134 tmp = mvs_read_phy_ctl(mvi, phy_id); 135 if (hard == 1) 136 tmp |= PHY_RST_HARD; 137 else if (hard == 0) 138 tmp |= PHY_RST; 139 mvs_write_phy_ctl(mvi, phy_id, tmp); 140 if (hard) { 141 do { 142 tmp = mvs_read_phy_ctl(mvi, phy_id); 143 } while (tmp & PHY_RST_HARD); 144 } 145} 146 147void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) 148{ 149 void __iomem *regs = mvi->regs; 150 u32 tmp; 151 if (clear_all) { 152 tmp = mr32(MVS_INT_STAT_SRS_0); 153 if (tmp) { 154 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp); 155 mw32(MVS_INT_STAT_SRS_0, tmp); 156 } 157 } else { 158 tmp = mr32(MVS_INT_STAT_SRS_0); 159 if (tmp & (1 << (reg_set % 32))) { 160 printk(KERN_DEBUG "register set 0x%x was stopped.\n", 161 reg_set); 162 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); 163 } 164 } 165} 166 167static int __devinit mvs_64xx_chip_reset(struct mvs_info *mvi) 168{ 169 void __iomem *regs = mvi->regs; 170 u32 tmp; 171 int i; 172 173 /* make sure interrupts are masked immediately (paranoia) */ 174 mw32(MVS_GBL_CTL, 0); 175 tmp = mr32(MVS_GBL_CTL); 176 177 /* Reset Controller */ 178 if (!(tmp & HBA_RST)) { 179 if (mvi->flags & MVF_PHY_PWR_FIX) { 180 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); 181 tmp &= ~PCTL_PWR_OFF; 182 tmp |= PCTL_PHY_DSBL; 183 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); 184 185 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); 186 tmp &= ~PCTL_PWR_OFF; 187 tmp |= PCTL_PHY_DSBL; 188 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); 189 } 190 } 191 192 /* make sure interrupts are masked immediately (paranoia) */ 193 mw32(MVS_GBL_CTL, 0); 194 tmp = mr32(MVS_GBL_CTL); 195 196 /* Reset Controller */ 197 if (!(tmp & HBA_RST)) { 198 /* global reset, incl. COMRESET/H_RESET_N (self-clearing) */ 199 mw32_f(MVS_GBL_CTL, HBA_RST); 200 } 201 202 /* wait for reset to finish; timeout is just a guess */ 203 i = 1000; 204 while (i-- > 0) { 205 msleep(10); 206 207 if (!(mr32(MVS_GBL_CTL) & HBA_RST)) 208 break; 209 } 210 if (mr32(MVS_GBL_CTL) & HBA_RST) { 211 dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n"); 212 return -EBUSY; 213 } 214 return 0; 215} 216 217static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id) 218{ 219 void __iomem *regs = mvi->regs; 220 u32 tmp; 221 if (!(mvi->flags & MVF_FLAG_SOC)) { 222 u32 offs; 223 if (phy_id < 4) 224 offs = PCR_PHY_CTL; 225 else { 226 offs = PCR_PHY_CTL2; 227 phy_id -= 4; 228 } 229 pci_read_config_dword(mvi->pdev, offs, &tmp); 230 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); 231 pci_write_config_dword(mvi->pdev, offs, tmp); 232 } else { 233 tmp = mr32(MVS_PHY_CTL); 234 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); 235 mw32(MVS_PHY_CTL, tmp); 236 } 237} 238 239static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id) 240{ 241 void __iomem *regs = mvi->regs; 242 u32 tmp; 243 if (!(mvi->flags & MVF_FLAG_SOC)) { 244 u32 offs; 245 if (phy_id < 4) 246 offs = PCR_PHY_CTL; 247 else { 248 offs = PCR_PHY_CTL2; 249 phy_id -= 4; 250 } 251 pci_read_config_dword(mvi->pdev, offs, &tmp); 252 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); 253 pci_write_config_dword(mvi->pdev, offs, tmp); 254 } else { 255 tmp = mr32(MVS_PHY_CTL); 256 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); 257 mw32(MVS_PHY_CTL, tmp); 258 } 259} 260 261static int __devinit mvs_64xx_init(struct mvs_info *mvi) 262{ 263 void __iomem *regs = mvi->regs; 264 int i; 265 u32 tmp, cctl; 266 267 if (mvi->pdev && mvi->pdev->revision == 0) 268 mvi->flags |= MVF_PHY_PWR_FIX; 269 if (!(mvi->flags & MVF_FLAG_SOC)) { 270 mvs_show_pcie_usage(mvi); 271 tmp = mvs_64xx_chip_reset(mvi); 272 if (tmp) 273 return tmp; 274 } else { 275 tmp = mr32(MVS_PHY_CTL); 276 tmp &= ~PCTL_PWR_OFF; 277 tmp |= PCTL_PHY_DSBL; 278 mw32(MVS_PHY_CTL, tmp); 279 } 280 281 /* Init Chip */ 282 /* make sure RST is set; HBA_RST /should/ have done that for us */ 283 cctl = mr32(MVS_CTL) & 0xFFFF; 284 if (cctl & CCTL_RST) 285 cctl &= ~CCTL_RST; 286 else 287 mw32_f(MVS_CTL, cctl | CCTL_RST); 288 289 if (!(mvi->flags & MVF_FLAG_SOC)) { 290 /* write to device control _AND_ device status register */ 291 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp); 292 tmp &= ~PRD_REQ_MASK; 293 tmp |= PRD_REQ_SIZE; 294 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp); 295 296 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); 297 tmp &= ~PCTL_PWR_OFF; 298 tmp &= ~PCTL_PHY_DSBL; 299 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); 300 301 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); 302 tmp &= PCTL_PWR_OFF; 303 tmp &= ~PCTL_PHY_DSBL; 304 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); 305 } else { 306 tmp = mr32(MVS_PHY_CTL); 307 tmp &= ~PCTL_PWR_OFF; 308 tmp |= PCTL_COM_ON; 309 tmp &= ~PCTL_PHY_DSBL; 310 tmp |= PCTL_LINK_RST; 311 mw32(MVS_PHY_CTL, tmp); 312 msleep(100); 313 tmp &= ~PCTL_LINK_RST; 314 mw32(MVS_PHY_CTL, tmp); 315 msleep(100); 316 } 317 318 /* reset control */ 319 mw32(MVS_PCS, 0); /* MVS_PCS */ 320 /* init phys */ 321 mvs_64xx_phy_hacks(mvi); 322 323 /* enable auto port detection */ 324 mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN); 325 326 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); 327 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); 328 329 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); 330 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); 331 332 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ); 333 mw32(MVS_TX_LO, mvi->tx_dma); 334 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); 335 336 mw32(MVS_RX_CFG, MVS_RX_RING_SZ); 337 mw32(MVS_RX_LO, mvi->rx_dma); 338 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); 339 340 for (i = 0; i < mvi->chip->n_phy; i++) { 341 /* set phy local SAS address */ 342 /* should set little endian SAS address to 64xx chip */ 343 mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI, 344 cpu_to_be64(mvi->phy[i].dev_sas_addr)); 345 346 mvs_64xx_enable_xmt(mvi, i); 347 348 mvs_64xx_phy_reset(mvi, i, 1); 349 msleep(500); 350 mvs_64xx_detect_porttype(mvi, i); 351 } 352 if (mvi->flags & MVF_FLAG_SOC) { 353 /* set select registers */ 354 writel(0x0E008000, regs + 0x000); 355 writel(0x59000008, regs + 0x004); 356 writel(0x20, regs + 0x008); 357 writel(0x20, regs + 0x00c); 358 writel(0x20, regs + 0x010); 359 writel(0x20, regs + 0x014); 360 writel(0x20, regs + 0x018); 361 writel(0x20, regs + 0x01c); 362 } 363 for (i = 0; i < mvi->chip->n_phy; i++) { 364 /* clear phy int status */ 365 tmp = mvs_read_port_irq_stat(mvi, i); 366 tmp &= ~PHYEV_SIG_FIS; 367 mvs_write_port_irq_stat(mvi, i, tmp); 368 369 /* set phy int mask */ 370 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS | 371 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR | 372 PHYEV_DEC_ERR; 373 mvs_write_port_irq_mask(mvi, i, tmp); 374 375 msleep(100); 376 mvs_update_phyinfo(mvi, i, 1); 377 } 378 379 380 /* little endian for open address and command table, etc. */ 381 /* 382 * it seems that ( from the spec ) turning on big-endian won't 383 * do us any good on big-endian machines, need further confirmation 384 */ 385 cctl = mr32(MVS_CTL); 386 cctl |= CCTL_ENDIAN_CMD; 387 cctl |= CCTL_ENDIAN_DATA; 388 cctl &= ~CCTL_ENDIAN_OPEN; 389 cctl |= CCTL_ENDIAN_RSP; 390 mw32_f(MVS_CTL, cctl); 391 392 /* reset CMD queue */ 393 tmp = mr32(MVS_PCS); 394 tmp |= PCS_CMD_RST; 395 mw32(MVS_PCS, tmp); 396 /* interrupt coalescing may cause missing HW interrput in some case, 397 * and the max count is 0x1ff, while our max slot is 0x200, 398 * it will make count 0. 399 */ 400 tmp = 0; 401 mw32(MVS_INT_COAL, tmp); 402 403 tmp = 0x100; 404 mw32(MVS_INT_COAL_TMOUT, tmp); 405 406 /* ladies and gentlemen, start your engines */ 407 mw32(MVS_TX_CFG, 0); 408 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN); 409 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN); 410 /* enable CMD/CMPL_Q/RESP mode */ 411 mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN | 412 PCS_CMD_EN | PCS_CMD_STOP_ERR); 413 414 /* enable completion queue interrupt */ 415 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | 416 CINT_DMA_PCIE); 417 418 mw32(MVS_INT_MASK, tmp); 419 420 /* Enable SRS interrupt */ 421 mw32(MVS_INT_MASK_SRS_0, 0xFFFF); 422 423 return 0; 424} 425 426static int mvs_64xx_ioremap(struct mvs_info *mvi) 427{ 428 if (!mvs_ioremap(mvi, 4, 2)) 429 return 0; 430 return -1; 431} 432 433static void mvs_64xx_iounmap(struct mvs_info *mvi) 434{ 435 mvs_iounmap(mvi->regs); 436 mvs_iounmap(mvi->regs_ex); 437} 438 439static void mvs_64xx_interrupt_enable(struct mvs_info *mvi) 440{ 441 void __iomem *regs = mvi->regs; 442 u32 tmp; 443 444 tmp = mr32(MVS_GBL_CTL); 445 mw32(MVS_GBL_CTL, tmp | INT_EN); 446} 447 448static void mvs_64xx_interrupt_disable(struct mvs_info *mvi) 449{ 450 void __iomem *regs = mvi->regs; 451 u32 tmp; 452 453 tmp = mr32(MVS_GBL_CTL); 454 mw32(MVS_GBL_CTL, tmp & ~INT_EN); 455} 456 457static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq) 458{ 459 void __iomem *regs = mvi->regs; 460 u32 stat; 461 462 if (!(mvi->flags & MVF_FLAG_SOC)) { 463 stat = mr32(MVS_GBL_INT_STAT); 464 465 if (stat == 0 || stat == 0xffffffff) 466 return 0; 467 } else 468 stat = 1; 469 return stat; 470} 471 472static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat) 473{ 474 void __iomem *regs = mvi->regs; 475 476 /* clear CMD_CMPLT ASAP */ 477 mw32_f(MVS_INT_STAT, CINT_DONE); 478#ifndef MVS_USE_TASKLET 479 spin_lock(&mvi->lock); 480#endif 481 mvs_int_full(mvi); 482#ifndef MVS_USE_TASKLET 483 spin_unlock(&mvi->lock); 484#endif 485 return IRQ_HANDLED; 486} 487 488static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx) 489{ 490 u32 tmp; 491 mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32)); 492 mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32)); 493 do { 494 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3)); 495 } while (tmp & 1 << (slot_idx % 32)); 496 do { 497 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3)); 498 } while (tmp & 1 << (slot_idx % 32)); 499} 500 501static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, 502 u32 tfs) 503{ 504 void __iomem *regs = mvi->regs; 505 u32 tmp; 506 507 if (type == PORT_TYPE_SATA) { 508 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs); 509 mw32(MVS_INT_STAT_SRS_0, tmp); 510 } 511 mw32(MVS_INT_STAT, CINT_CI_STOP); 512 tmp = mr32(MVS_PCS) | 0xFF00; 513 mw32(MVS_PCS, tmp); 514} 515 516static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) 517{ 518 void __iomem *regs = mvi->regs; 519 u32 tmp, offs; 520 521 if (*tfs == MVS_ID_NOT_MAPPED) 522 return; 523 524 offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT); 525 if (*tfs < 16) { 526 tmp = mr32(MVS_PCS); 527 mw32(MVS_PCS, tmp & ~offs); 528 } else { 529 tmp = mr32(MVS_CTL); 530 mw32(MVS_CTL, tmp & ~offs); 531 } 532 533 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs); 534 if (tmp) 535 mw32(MVS_INT_STAT_SRS_0, tmp); 536 537 *tfs = MVS_ID_NOT_MAPPED; 538 return; 539} 540 541static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) 542{ 543 int i; 544 u32 tmp, offs; 545 void __iomem *regs = mvi->regs; 546 547 if (*tfs != MVS_ID_NOT_MAPPED) 548 return 0; 549 550 tmp = mr32(MVS_PCS); 551 552 for (i = 0; i < mvi->chip->srs_sz; i++) { 553 if (i == 16) 554 tmp = mr32(MVS_CTL); 555 offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT); 556 if (!(tmp & offs)) { 557 *tfs = i; 558 559 if (i < 16) 560 mw32(MVS_PCS, tmp | offs); 561 else 562 mw32(MVS_CTL, tmp | offs); 563 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i); 564 if (tmp) 565 mw32(MVS_INT_STAT_SRS_0, tmp); 566 return 0; 567 } 568 } 569 return MVS_ID_NOT_MAPPED; 570} 571 572void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd) 573{ 574 int i; 575 struct scatterlist *sg; 576 struct mvs_prd *buf_prd = prd; 577 for_each_sg(scatter, sg, nr, i) { 578 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 579 buf_prd->len = cpu_to_le32(sg_dma_len(sg)); 580 buf_prd++; 581 } 582} 583 584static int mvs_64xx_oob_done(struct mvs_info *mvi, int i) 585{ 586 u32 phy_st; 587 mvs_write_port_cfg_addr(mvi, i, 588 PHYR_PHY_STAT); 589 phy_st = mvs_read_port_cfg_data(mvi, i); 590 if (phy_st & PHY_OOB_DTCTD) 591 return 1; 592 return 0; 593} 594 595static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i, 596 struct sas_identify_frame *id) 597 598{ 599 struct mvs_phy *phy = &mvi->phy[i]; 600 struct asd_sas_phy *sas_phy = &phy->sas_phy; 601 602 sas_phy->linkrate = 603 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> 604 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET; 605 606 phy->minimum_linkrate = 607 (phy->phy_status & 608 PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8; 609 phy->maximum_linkrate = 610 (phy->phy_status & 611 PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12; 612 613 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY); 614 phy->dev_info = mvs_read_port_cfg_data(mvi, i); 615 616 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO); 617 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i); 618 619 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI); 620 phy->att_dev_sas_addr = 621 (u64) mvs_read_port_cfg_data(mvi, i) << 32; 622 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO); 623 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i); 624 phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr); 625} 626 627static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i) 628{ 629 u32 tmp; 630 struct mvs_phy *phy = &mvi->phy[i]; 631 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6); 632 tmp = mvs_read_port_vsr_data(mvi, i); 633 if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> 634 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) == 635 SAS_LINK_RATE_1_5_GBPS) 636 tmp &= ~PHY_MODE6_LATECLK; 637 else 638 tmp |= PHY_MODE6_LATECLK; 639 mvs_write_port_vsr_data(mvi, i, tmp); 640} 641 642void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, 643 struct sas_phy_linkrates *rates) 644{ 645 u32 lrmin = 0, lrmax = 0; 646 u32 tmp; 647 648 tmp = mvs_read_phy_ctl(mvi, phy_id); 649 lrmin = (rates->minimum_linkrate << 8); 650 lrmax = (rates->maximum_linkrate << 12); 651 652 if (lrmin) { 653 tmp &= ~(0xf << 8); 654 tmp |= lrmin; 655 } 656 if (lrmax) { 657 tmp &= ~(0xf << 12); 658 tmp |= lrmax; 659 } 660 mvs_write_phy_ctl(mvi, phy_id, tmp); 661 mvs_64xx_phy_reset(mvi, phy_id, 1); 662} 663 664static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi) 665{ 666 u32 tmp; 667 void __iomem *regs = mvi->regs; 668 tmp = mr32(MVS_PCS); 669 mw32(MVS_PCS, tmp & 0xFFFF); 670 mw32(MVS_PCS, tmp); 671 tmp = mr32(MVS_CTL); 672 mw32(MVS_CTL, tmp & 0xFFFF); 673 mw32(MVS_CTL, tmp); 674} 675 676 677u32 mvs_64xx_spi_read_data(struct mvs_info *mvi) 678{ 679 void __iomem *regs = mvi->regs_ex; 680 return ior32(SPI_DATA_REG_64XX); 681} 682 683void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data) 684{ 685 void __iomem *regs = mvi->regs_ex; 686 iow32(SPI_DATA_REG_64XX, data); 687} 688 689 690int mvs_64xx_spi_buildcmd(struct mvs_info *mvi, 691 u32 *dwCmd, 692 u8 cmd, 693 u8 read, 694 u8 length, 695 u32 addr 696 ) 697{ 698 u32 dwTmp; 699 700 dwTmp = ((u32)cmd << 24) | ((u32)length << 19); 701 if (read) 702 dwTmp |= 1U<<23; 703 704 if (addr != MV_MAX_U32) { 705 dwTmp |= 1U<<22; 706 dwTmp |= (addr & 0x0003FFFF); 707 } 708 709 *dwCmd = dwTmp; 710 return 0; 711} 712 713 714int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) 715{ 716 void __iomem *regs = mvi->regs_ex; 717 int retry; 718 719 for (retry = 0; retry < 1; retry++) { 720 iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE); 721 iow32(SPI_CMD_REG_64XX, cmd); 722 iow32(SPI_CTRL_REG_64XX, 723 SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART); 724 } 725 726 return 0; 727} 728 729int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) 730{ 731 void __iomem *regs = mvi->regs_ex; 732 u32 i, dwTmp; 733 734 for (i = 0; i < timeout; i++) { 735 dwTmp = ior32(SPI_CTRL_REG_64XX); 736 if (!(dwTmp & SPI_CTRL_SPISTART)) 737 return 0; 738 msleep(10); 739 } 740 741 return -1; 742} 743 744#ifndef DISABLE_HOTPLUG_DMA_FIX 745void mvs_64xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd) 746{ 747 int i; 748 struct mvs_prd *buf_prd = prd; 749 buf_prd += from; 750 for (i = 0; i < MAX_SG_ENTRY - from; i++) { 751 buf_prd->addr = cpu_to_le64(buf_dma); 752 buf_prd->len = cpu_to_le32(buf_len); 753 ++buf_prd; 754 } 755} 756#endif 757 758const struct mvs_dispatch mvs_64xx_dispatch = { 759 "mv64xx", 760 mvs_64xx_init, 761 NULL, 762 mvs_64xx_ioremap, 763 mvs_64xx_iounmap, 764 mvs_64xx_isr, 765 mvs_64xx_isr_status, 766 mvs_64xx_interrupt_enable, 767 mvs_64xx_interrupt_disable, 768 mvs_read_phy_ctl, 769 mvs_write_phy_ctl, 770 mvs_read_port_cfg_data, 771 mvs_write_port_cfg_data, 772 mvs_write_port_cfg_addr, 773 mvs_read_port_vsr_data, 774 mvs_write_port_vsr_data, 775 mvs_write_port_vsr_addr, 776 mvs_read_port_irq_stat, 777 mvs_write_port_irq_stat, 778 mvs_read_port_irq_mask, 779 mvs_write_port_irq_mask, 780 mvs_get_sas_addr, 781 mvs_64xx_command_active, 782 mvs_64xx_clear_srs_irq, 783 mvs_64xx_issue_stop, 784 mvs_start_delivery, 785 mvs_rx_update, 786 mvs_int_full, 787 mvs_64xx_assign_reg_set, 788 mvs_64xx_free_reg_set, 789 mvs_get_prd_size, 790 mvs_get_prd_count, 791 mvs_64xx_make_prd, 792 mvs_64xx_detect_porttype, 793 mvs_64xx_oob_done, 794 mvs_64xx_fix_phy_info, 795 mvs_64xx_phy_work_around, 796 mvs_64xx_phy_set_link_rate, 797 mvs_hw_max_link_rate, 798 mvs_64xx_phy_disable, 799 mvs_64xx_phy_enable, 800 mvs_64xx_phy_reset, 801 mvs_64xx_stp_reset, 802 mvs_64xx_clear_active_cmds, 803 mvs_64xx_spi_read_data, 804 mvs_64xx_spi_write_data, 805 mvs_64xx_spi_buildcmd, 806 mvs_64xx_spi_issuecmd, 807 mvs_64xx_spi_waitdataready, 808#ifndef DISABLE_HOTPLUG_DMA_FIX 809 mvs_64xx_fix_dma, 810#endif 811}; 812