1/* 2 * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18#include <bfa_priv.h> 19#include <bfi/bfi_ctreg.h> 20#include <bfa_ioc.h> 21 22BFA_TRC_FILE(HAL, IOCFC_CT); 23 24static u32 __ct_msix_err_vec_reg[] = { 25 HOST_MSIX_ERR_INDEX_FN0, 26 HOST_MSIX_ERR_INDEX_FN1, 27 HOST_MSIX_ERR_INDEX_FN2, 28 HOST_MSIX_ERR_INDEX_FN3, 29}; 30 31static void 32bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec) 33{ 34 int fn = bfa_ioc_pcifn(&bfa->ioc); 35 bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc); 36 37 if (msix) 38 bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], vec); 39 else 40 bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], 0); 41} 42 43/** 44 * Dummy interrupt handler for handling spurious interrupt during chip-reinit. 45 */ 46static void 47bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec) 48{ 49} 50 51void 52bfa_hwct_reginit(struct bfa_s *bfa) 53{ 54 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 55 bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc); 56 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); 57 58 if (fn == 0) { 59 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); 60 bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK); 61 } else { 62 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); 63 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); 64 } 65 66 for (i = 0; i < BFI_IOC_MAX_CQS; i++) { 67 /* 68 * CPE registers 69 */ 70 q = CPE_Q_NUM(fn, i); 71 bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5)); 72 bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5)); 73 bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5)); 74 bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5)); 75 76 /* 77 * RME registers 78 */ 79 q = CPE_Q_NUM(fn, i); 80 bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5)); 81 bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5)); 82 bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5)); 83 bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5)); 84 } 85} 86 87void 88bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq) 89{ 90 u32 r32; 91 92 r32 = bfa_reg_read(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]); 93 bfa_reg_write(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq], r32); 94} 95 96void 97bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq) 98{ 99 u32 r32; 100 101 r32 = bfa_reg_read(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); 102 bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq], r32); 103} 104 105void 106bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, 107 u32 *num_vecs, u32 *max_vec_bit) 108{ 109 *msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1; 110 *max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1)); 111 *num_vecs = BFA_MSIX_CT_MAX; 112} 113 114/** 115 * Setup MSI-X vector for catapult 116 */ 117void 118bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs) 119{ 120 bfa_assert((nvecs == 1) || (nvecs == BFA_MSIX_CT_MAX)); 121 bfa_trc(bfa, nvecs); 122 123 bfa->msix.nvecs = nvecs; 124 bfa_hwct_msix_uninstall(bfa); 125} 126 127void 128bfa_hwct_msix_install(struct bfa_s *bfa) 129{ 130 int i; 131 132 if (bfa->msix.nvecs == 0) 133 return; 134 135 if (bfa->msix.nvecs == 1) { 136 for (i = 0; i < BFA_MSIX_CT_MAX; i++) 137 bfa->msix.handler[i] = bfa_msix_all; 138 return; 139 } 140 141 for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++) 142 bfa->msix.handler[i] = bfa_msix_reqq; 143 144 for (; i <= BFA_MSIX_RME_Q3; i++) 145 bfa->msix.handler[i] = bfa_msix_rspq; 146 147 bfa_assert(i == BFA_MSIX_LPU_ERR); 148 bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err; 149} 150 151void 152bfa_hwct_msix_uninstall(struct bfa_s *bfa) 153{ 154 int i; 155 156 for (i = 0; i < BFA_MSIX_CT_MAX; i++) 157 bfa->msix.handler[i] = bfa_hwct_msix_dummy; 158} 159 160/** 161 * Enable MSI-X vectors 162 */ 163void 164bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) 165{ 166 bfa_trc(bfa, 0); 167 bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR); 168 bfa_ioc_isr_mode_set(&bfa->ioc, msix); 169} 170 171void 172bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) 173{ 174 *start = BFA_MSIX_RME_Q0; 175 *end = BFA_MSIX_RME_Q3; 176} 177