1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $ 43 */ 44 45#ifdef __linux__ 46#include "aic7xxx_osm.h" 47#include "aic7xxx_inline.h" 48#include "aic7xxx_93cx6.h" 49#else 50#include <dev/aic7xxx/aic7xxx_osm.h> 51#include <dev/aic7xxx/aic7xxx_inline.h> 52#include <dev/aic7xxx/aic7xxx_93cx6.h> 53#endif 54 55#include "aic7xxx_pci.h" 56 57static inline uint64_t 58ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 59{ 60 uint64_t id; 61 62 id = subvendor 63 | (subdevice << 16) 64 | ((uint64_t)vendor << 32) 65 | ((uint64_t)device << 48); 66 67 return (id); 68} 69 70#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 71#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 72 73#define DEVID_9005_TYPE(id) ((id) & 0xF) 74#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 75#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 76#define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 77#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 78 79#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 80#define DEVID_9005_MAXRATE_U160 0x0 81#define DEVID_9005_MAXRATE_ULTRA2 0x1 82#define DEVID_9005_MAXRATE_ULTRA 0x2 83#define DEVID_9005_MAXRATE_FAST 0x3 84 85#define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 86 87#define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 88#define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 89 90#define SUBID_9005_TYPE(id) ((id) & 0xF) 91#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 92#define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 93#define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 94#define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 95 96#define SUBID_9005_TYPE_KNOWN(id) \ 97 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 98 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 99 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 100 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 101 102#define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 103#define SUBID_9005_MAXRATE_ULTRA2 0x0 104#define SUBID_9005_MAXRATE_ULTRA 0x1 105#define SUBID_9005_MAXRATE_U160 0x2 106#define SUBID_9005_MAXRATE_RESERVED 0x3 107 108#define SUBID_9005_SEEPTYPE(id) \ 109 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 110 ? ((id) & 0xC0) >> 6 \ 111 : ((id) & 0x300) >> 8) 112#define SUBID_9005_SEEPTYPE_NONE 0x0 113#define SUBID_9005_SEEPTYPE_1K 0x1 114#define SUBID_9005_SEEPTYPE_2K_4K 0x2 115#define SUBID_9005_SEEPTYPE_RESERVED 0x3 116#define SUBID_9005_AUTOTERM(id) \ 117 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 118 ? (((id) & 0x400) >> 10) == 0 \ 119 : (((id) & 0x40) >> 6) == 0) 120 121#define SUBID_9005_NUMCHAN(id) \ 122 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 123 ? ((id) & 0x300) >> 8 \ 124 : ((id) & 0xC00) >> 10) 125 126#define SUBID_9005_LEGACYCONN(id) \ 127 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 128 ? 0 \ 129 : ((id) & 0x80) >> 7) 130 131#define SUBID_9005_MFUNCENB(id) \ 132 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 133 ? ((id) & 0x800) >> 11 \ 134 : ((id) & 0x1000) >> 12) 135/* 136 * Informational only. Should use chip register to be 137 * certain, but may be use in identification strings. 138 */ 139#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 140#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 141#define SUBID_9005_CARD_SEDIFF_MASK 0x8000 142 143static ahc_device_setup_t ahc_aic785X_setup; 144static ahc_device_setup_t ahc_aic7860_setup; 145static ahc_device_setup_t ahc_apa1480_setup; 146static ahc_device_setup_t ahc_aic7870_setup; 147static ahc_device_setup_t ahc_aic7870h_setup; 148static ahc_device_setup_t ahc_aha394X_setup; 149static ahc_device_setup_t ahc_aha394Xh_setup; 150static ahc_device_setup_t ahc_aha494X_setup; 151static ahc_device_setup_t ahc_aha494Xh_setup; 152static ahc_device_setup_t ahc_aha398X_setup; 153static ahc_device_setup_t ahc_aic7880_setup; 154static ahc_device_setup_t ahc_aic7880h_setup; 155static ahc_device_setup_t ahc_aha2940Pro_setup; 156static ahc_device_setup_t ahc_aha394XU_setup; 157static ahc_device_setup_t ahc_aha394XUh_setup; 158static ahc_device_setup_t ahc_aha398XU_setup; 159static ahc_device_setup_t ahc_aic7890_setup; 160static ahc_device_setup_t ahc_aic7892_setup; 161static ahc_device_setup_t ahc_aic7895_setup; 162static ahc_device_setup_t ahc_aic7895h_setup; 163static ahc_device_setup_t ahc_aic7896_setup; 164static ahc_device_setup_t ahc_aic7899_setup; 165static ahc_device_setup_t ahc_aha29160C_setup; 166static ahc_device_setup_t ahc_raid_setup; 167static ahc_device_setup_t ahc_aha394XX_setup; 168static ahc_device_setup_t ahc_aha494XX_setup; 169static ahc_device_setup_t ahc_aha398XX_setup; 170 171static const struct ahc_pci_identity ahc_pci_ident_table[] = { 172 /* aic7850 based controllers */ 173 { 174 ID_AHA_2902_04_10_15_20C_30C, 175 ID_ALL_MASK, 176 "Adaptec 2902/04/10/15/20C/30C SCSI adapter", 177 ahc_aic785X_setup 178 }, 179 /* aic7860 based controllers */ 180 { 181 ID_AHA_2930CU, 182 ID_ALL_MASK, 183 "Adaptec 2930CU SCSI adapter", 184 ahc_aic7860_setup 185 }, 186 { 187 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 188 ID_DEV_VENDOR_MASK, 189 "Adaptec 1480A Ultra SCSI adapter", 190 ahc_apa1480_setup 191 }, 192 { 193 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 194 ID_DEV_VENDOR_MASK, 195 "Adaptec 2940A Ultra SCSI adapter", 196 ahc_aic7860_setup 197 }, 198 { 199 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 200 ID_DEV_VENDOR_MASK, 201 "Adaptec 2940A/CN Ultra SCSI adapter", 202 ahc_aic7860_setup 203 }, 204 { 205 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 206 ID_DEV_VENDOR_MASK, 207 "Adaptec 2930C Ultra SCSI adapter (VAR)", 208 ahc_aic7860_setup 209 }, 210 /* aic7870 based controllers */ 211 { 212 ID_AHA_2940, 213 ID_ALL_MASK, 214 "Adaptec 2940 SCSI adapter", 215 ahc_aic7870_setup 216 }, 217 { 218 ID_AHA_3940, 219 ID_ALL_MASK, 220 "Adaptec 3940 SCSI adapter", 221 ahc_aha394X_setup 222 }, 223 { 224 ID_AHA_398X, 225 ID_ALL_MASK, 226 "Adaptec 398X SCSI RAID adapter", 227 ahc_aha398X_setup 228 }, 229 { 230 ID_AHA_2944, 231 ID_ALL_MASK, 232 "Adaptec 2944 SCSI adapter", 233 ahc_aic7870h_setup 234 }, 235 { 236 ID_AHA_3944, 237 ID_ALL_MASK, 238 "Adaptec 3944 SCSI adapter", 239 ahc_aha394Xh_setup 240 }, 241 { 242 ID_AHA_4944, 243 ID_ALL_MASK, 244 "Adaptec 4944 SCSI adapter", 245 ahc_aha494Xh_setup 246 }, 247 /* aic7880 based controllers */ 248 { 249 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 250 ID_DEV_VENDOR_MASK, 251 "Adaptec 2940 Ultra SCSI adapter", 252 ahc_aic7880_setup 253 }, 254 { 255 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 256 ID_DEV_VENDOR_MASK, 257 "Adaptec 3940 Ultra SCSI adapter", 258 ahc_aha394XU_setup 259 }, 260 { 261 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 2944 Ultra SCSI adapter", 264 ahc_aic7880h_setup 265 }, 266 { 267 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 3944 Ultra SCSI adapter", 270 ahc_aha394XUh_setup 271 }, 272 { 273 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 398X Ultra SCSI RAID adapter", 276 ahc_aha398XU_setup 277 }, 278 { 279 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 4944 Ultra SCSI adapter", 282 ahc_aic7880h_setup 283 }, 284 { 285 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 286 ID_DEV_VENDOR_MASK, 287 "Adaptec 2930 Ultra SCSI adapter", 288 ahc_aic7880_setup 289 }, 290 { 291 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 292 ID_DEV_VENDOR_MASK, 293 "Adaptec 2940 Pro Ultra SCSI adapter", 294 ahc_aha2940Pro_setup 295 }, 296 { 297 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 298 ID_DEV_VENDOR_MASK, 299 "Adaptec 2940/CN Ultra SCSI adapter", 300 ahc_aic7880_setup 301 }, 302 /* Ignore all SISL (AAC on MB) based controllers. */ 303 { 304 ID_9005_SISL_ID, 305 ID_9005_SISL_MASK, 306 NULL, 307 NULL 308 }, 309 /* aic7890 based controllers */ 310 { 311 ID_AHA_2930U2, 312 ID_ALL_MASK, 313 "Adaptec 2930 Ultra2 SCSI adapter", 314 ahc_aic7890_setup 315 }, 316 { 317 ID_AHA_2940U2B, 318 ID_ALL_MASK, 319 "Adaptec 2940B Ultra2 SCSI adapter", 320 ahc_aic7890_setup 321 }, 322 { 323 ID_AHA_2940U2_OEM, 324 ID_ALL_MASK, 325 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 326 ahc_aic7890_setup 327 }, 328 { 329 ID_AHA_2940U2, 330 ID_ALL_MASK, 331 "Adaptec 2940 Ultra2 SCSI adapter", 332 ahc_aic7890_setup 333 }, 334 { 335 ID_AHA_2950U2B, 336 ID_ALL_MASK, 337 "Adaptec 2950 Ultra2 SCSI adapter", 338 ahc_aic7890_setup 339 }, 340 { 341 ID_AIC7890_ARO, 342 ID_ALL_MASK, 343 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 344 ahc_aic7890_setup 345 }, 346 { 347 ID_AAA_131U2, 348 ID_ALL_MASK, 349 "Adaptec AAA-131 Ultra2 RAID adapter", 350 ahc_aic7890_setup 351 }, 352 /* aic7892 based controllers */ 353 { 354 ID_AHA_29160, 355 ID_ALL_MASK, 356 "Adaptec 29160 Ultra160 SCSI adapter", 357 ahc_aic7892_setup 358 }, 359 { 360 ID_AHA_29160_CPQ, 361 ID_ALL_MASK, 362 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 363 ahc_aic7892_setup 364 }, 365 { 366 ID_AHA_29160N, 367 ID_ALL_MASK, 368 "Adaptec 29160N Ultra160 SCSI adapter", 369 ahc_aic7892_setup 370 }, 371 { 372 ID_AHA_29160C, 373 ID_ALL_MASK, 374 "Adaptec 29160C Ultra160 SCSI adapter", 375 ahc_aha29160C_setup 376 }, 377 { 378 ID_AHA_29160B, 379 ID_ALL_MASK, 380 "Adaptec 29160B Ultra160 SCSI adapter", 381 ahc_aic7892_setup 382 }, 383 { 384 ID_AHA_19160B, 385 ID_ALL_MASK, 386 "Adaptec 19160B Ultra160 SCSI adapter", 387 ahc_aic7892_setup 388 }, 389 { 390 ID_AIC7892_ARO, 391 ID_ALL_MASK, 392 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 393 ahc_aic7892_setup 394 }, 395 { 396 ID_AHA_2915_30LP, 397 ID_ALL_MASK, 398 "Adaptec 2915/30LP Ultra160 SCSI adapter", 399 ahc_aic7892_setup 400 }, 401 /* aic7895 based controllers */ 402 { 403 ID_AHA_2940U_DUAL, 404 ID_ALL_MASK, 405 "Adaptec 2940/DUAL Ultra SCSI adapter", 406 ahc_aic7895_setup 407 }, 408 { 409 ID_AHA_3940AU, 410 ID_ALL_MASK, 411 "Adaptec 3940A Ultra SCSI adapter", 412 ahc_aic7895_setup 413 }, 414 { 415 ID_AHA_3944AU, 416 ID_ALL_MASK, 417 "Adaptec 3944A Ultra SCSI adapter", 418 ahc_aic7895h_setup 419 }, 420 { 421 ID_AIC7895_ARO, 422 ID_AIC7895_ARO_MASK, 423 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 424 ahc_aic7895_setup 425 }, 426 /* aic7896/97 based controllers */ 427 { 428 ID_AHA_3950U2B_0, 429 ID_ALL_MASK, 430 "Adaptec 3950B Ultra2 SCSI adapter", 431 ahc_aic7896_setup 432 }, 433 { 434 ID_AHA_3950U2B_1, 435 ID_ALL_MASK, 436 "Adaptec 3950B Ultra2 SCSI adapter", 437 ahc_aic7896_setup 438 }, 439 { 440 ID_AHA_3950U2D_0, 441 ID_ALL_MASK, 442 "Adaptec 3950D Ultra2 SCSI adapter", 443 ahc_aic7896_setup 444 }, 445 { 446 ID_AHA_3950U2D_1, 447 ID_ALL_MASK, 448 "Adaptec 3950D Ultra2 SCSI adapter", 449 ahc_aic7896_setup 450 }, 451 { 452 ID_AIC7896_ARO, 453 ID_ALL_MASK, 454 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 455 ahc_aic7896_setup 456 }, 457 /* aic7899 based controllers */ 458 { 459 ID_AHA_3960D, 460 ID_ALL_MASK, 461 "Adaptec 3960D Ultra160 SCSI adapter", 462 ahc_aic7899_setup 463 }, 464 { 465 ID_AHA_3960D_CPQ, 466 ID_ALL_MASK, 467 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 468 ahc_aic7899_setup 469 }, 470 { 471 ID_AIC7899_ARO, 472 ID_ALL_MASK, 473 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 474 ahc_aic7899_setup 475 }, 476 /* Generic chip probes for devices we don't know 'exactly' */ 477 { 478 ID_AIC7850 & ID_DEV_VENDOR_MASK, 479 ID_DEV_VENDOR_MASK, 480 "Adaptec aic7850 SCSI adapter", 481 ahc_aic785X_setup 482 }, 483 { 484 ID_AIC7855 & ID_DEV_VENDOR_MASK, 485 ID_DEV_VENDOR_MASK, 486 "Adaptec aic7855 SCSI adapter", 487 ahc_aic785X_setup 488 }, 489 { 490 ID_AIC7859 & ID_DEV_VENDOR_MASK, 491 ID_DEV_VENDOR_MASK, 492 "Adaptec aic7859 SCSI adapter", 493 ahc_aic7860_setup 494 }, 495 { 496 ID_AIC7860 & ID_DEV_VENDOR_MASK, 497 ID_DEV_VENDOR_MASK, 498 "Adaptec aic7860 Ultra SCSI adapter", 499 ahc_aic7860_setup 500 }, 501 { 502 ID_AIC7870 & ID_DEV_VENDOR_MASK, 503 ID_DEV_VENDOR_MASK, 504 "Adaptec aic7870 SCSI adapter", 505 ahc_aic7870_setup 506 }, 507 { 508 ID_AIC7880 & ID_DEV_VENDOR_MASK, 509 ID_DEV_VENDOR_MASK, 510 "Adaptec aic7880 Ultra SCSI adapter", 511 ahc_aic7880_setup 512 }, 513 { 514 ID_AIC7890 & ID_9005_GENERIC_MASK, 515 ID_9005_GENERIC_MASK, 516 "Adaptec aic7890/91 Ultra2 SCSI adapter", 517 ahc_aic7890_setup 518 }, 519 { 520 ID_AIC7892 & ID_9005_GENERIC_MASK, 521 ID_9005_GENERIC_MASK, 522 "Adaptec aic7892 Ultra160 SCSI adapter", 523 ahc_aic7892_setup 524 }, 525 { 526 ID_AIC7895 & ID_DEV_VENDOR_MASK, 527 ID_DEV_VENDOR_MASK, 528 "Adaptec aic7895 Ultra SCSI adapter", 529 ahc_aic7895_setup 530 }, 531 { 532 ID_AIC7896 & ID_9005_GENERIC_MASK, 533 ID_9005_GENERIC_MASK, 534 "Adaptec aic7896/97 Ultra2 SCSI adapter", 535 ahc_aic7896_setup 536 }, 537 { 538 ID_AIC7899 & ID_9005_GENERIC_MASK, 539 ID_9005_GENERIC_MASK, 540 "Adaptec aic7899 Ultra160 SCSI adapter", 541 ahc_aic7899_setup 542 }, 543 { 544 ID_AIC7810 & ID_DEV_VENDOR_MASK, 545 ID_DEV_VENDOR_MASK, 546 "Adaptec aic7810 RAID memory controller", 547 ahc_raid_setup 548 }, 549 { 550 ID_AIC7815 & ID_DEV_VENDOR_MASK, 551 ID_DEV_VENDOR_MASK, 552 "Adaptec aic7815 RAID memory controller", 553 ahc_raid_setup 554 } 555}; 556 557static const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table); 558 559#define AHC_394X_SLOT_CHANNEL_A 4 560#define AHC_394X_SLOT_CHANNEL_B 5 561 562#define AHC_398X_SLOT_CHANNEL_A 4 563#define AHC_398X_SLOT_CHANNEL_B 8 564#define AHC_398X_SLOT_CHANNEL_C 12 565 566#define AHC_494X_SLOT_CHANNEL_A 4 567#define AHC_494X_SLOT_CHANNEL_B 5 568#define AHC_494X_SLOT_CHANNEL_C 6 569#define AHC_494X_SLOT_CHANNEL_D 7 570 571#define DEVCONFIG 0x40 572#define PCIERRGENDIS 0x80000000ul 573#define SCBSIZE32 0x00010000ul /* aic789X only */ 574#define REXTVALID 0x00001000ul /* ultra cards only */ 575#define MPORTMODE 0x00000400ul /* aic7870+ only */ 576#define RAMPSM 0x00000200ul /* aic7870+ only */ 577#define VOLSENSE 0x00000100ul 578#define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 579#define SCBRAMSEL 0x00000080ul 580#define MRDCEN 0x00000040ul 581#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 582#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 583#define BERREN 0x00000008ul 584#define DACEN 0x00000004ul 585#define STPWLEVEL 0x00000002ul 586#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 587 588#define CSIZE_LATTIME 0x0c 589#define CACHESIZE 0x0000003ful /* only 5 bits */ 590#define LATTIME 0x0000ff00ul 591 592/* PCI STATUS definitions */ 593#define DPE 0x80 594#define SSE 0x40 595#define RMA 0x20 596#define RTA 0x10 597#define STA 0x08 598#define DPR 0x01 599 600static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 601 uint16_t subvendor, uint16_t subdevice); 602static int ahc_ext_scbram_present(struct ahc_softc *ahc); 603static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 604 int pcheck, int fast, int large); 605static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 606static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 607static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 608 struct seeprom_config *sc); 609static void configure_termination(struct ahc_softc *ahc, 610 struct seeprom_descriptor *sd, 611 u_int adapter_control, 612 u_int *sxfrctl1); 613 614static void ahc_new_term_detect(struct ahc_softc *ahc, 615 int *enableSEC_low, 616 int *enableSEC_high, 617 int *enablePRI_low, 618 int *enablePRI_high, 619 int *eeprom_present); 620static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 621 int *internal68_present, 622 int *externalcable_present, 623 int *eeprom_present); 624static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 625 int *externalcable_present, 626 int *eeprom_present); 627static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 628static uint8_t read_brdctl(struct ahc_softc *ahc); 629static void ahc_pci_intr(struct ahc_softc *ahc); 630static int ahc_pci_chip_init(struct ahc_softc *ahc); 631 632static int 633ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 634 uint16_t subdevice, uint16_t subvendor) 635{ 636 int result; 637 638 /* Default to invalid. */ 639 result = 0; 640 if (vendor == 0x9005 641 && subvendor == 0x9005 642 && subdevice != device 643 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 644 645 switch (SUBID_9005_TYPE(subdevice)) { 646 case SUBID_9005_TYPE_MB: 647 break; 648 case SUBID_9005_TYPE_CARD: 649 case SUBID_9005_TYPE_LCCARD: 650 /* 651 * Currently only trust Adaptec cards to 652 * get the sub device info correct. 653 */ 654 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 655 result = 1; 656 break; 657 case SUBID_9005_TYPE_RAID: 658 break; 659 default: 660 break; 661 } 662 } 663 return (result); 664} 665 666const struct ahc_pci_identity * 667ahc_find_pci_device(ahc_dev_softc_t pci) 668{ 669 uint64_t full_id; 670 uint16_t device; 671 uint16_t vendor; 672 uint16_t subdevice; 673 uint16_t subvendor; 674 const struct ahc_pci_identity *entry; 675 u_int i; 676 677 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 678 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 679 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 680 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 681 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 682 683 /* 684 * If the second function is not hooked up, ignore it. 685 * Unfortunately, not all MB vendors implement the 686 * subdevice ID as per the Adaptec spec, so do our best 687 * to sanity check it prior to accepting the subdevice 688 * ID as valid. 689 */ 690 if (ahc_get_pci_function(pci) > 0 691 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 692 && SUBID_9005_MFUNCENB(subdevice) == 0) 693 return (NULL); 694 695 for (i = 0; i < ahc_num_pci_devs; i++) { 696 entry = &ahc_pci_ident_table[i]; 697 if (entry->full_id == (full_id & entry->id_mask)) { 698 /* Honor exclusion entries. */ 699 if (entry->name == NULL) 700 return (NULL); 701 return (entry); 702 } 703 } 704 return (NULL); 705} 706 707int 708ahc_pci_config(struct ahc_softc *ahc, const struct ahc_pci_identity *entry) 709{ 710 u_int command; 711 u_int our_id; 712 u_int sxfrctl1; 713 u_int scsiseq; 714 u_int dscommand0; 715 uint32_t devconfig; 716 int error; 717 uint8_t sblkctl; 718 719 our_id = 0; 720 error = entry->setup(ahc); 721 if (error != 0) 722 return (error); 723 ahc->chip |= AHC_PCI; 724 ahc->description = entry->name; 725 726 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 727 728 error = ahc_pci_map_registers(ahc); 729 if (error != 0) 730 return (error); 731 732 /* 733 * Before we continue probing the card, ensure that 734 * its interrupts are *disabled*. We don't want 735 * a misstep to hang the machine in an interrupt 736 * storm. 737 */ 738 ahc_intr_enable(ahc, FALSE); 739 740 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 741 742 /* 743 * If we need to support high memory, enable dual 744 * address cycles. This bit must be set to enable 745 * high address bit generation even if we are on a 746 * 64bit bus (PCI64BIT set in devconfig). 747 */ 748 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 749 750 if (bootverbose) 751 printk("%s: Enabling 39Bit Addressing\n", 752 ahc_name(ahc)); 753 devconfig |= DACEN; 754 } 755 756 /* Ensure that pci error generation, a test feature, is disabled. */ 757 devconfig |= PCIERRGENDIS; 758 759 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 760 761 /* Ensure busmastering is enabled */ 762 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 763 command |= PCIM_CMD_BUSMASTEREN; 764 765 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 766 767 /* On all PCI adapters, we allow SCB paging */ 768 ahc->flags |= AHC_PAGESCBS; 769 770 error = ahc_softc_init(ahc); 771 if (error != 0) 772 return (error); 773 774 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 775 ahc->seqctl |= FAILDIS; 776 777 ahc->bus_intr = ahc_pci_intr; 778 ahc->bus_chip_init = ahc_pci_chip_init; 779 780 /* Remeber how the card was setup in case there is no SEEPROM */ 781 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 782 ahc_pause(ahc); 783 if ((ahc->features & AHC_ULTRA2) != 0) 784 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 785 else 786 our_id = ahc_inb(ahc, SCSIID) & OID; 787 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 788 scsiseq = ahc_inb(ahc, SCSISEQ); 789 } else { 790 sxfrctl1 = STPWEN; 791 our_id = 7; 792 scsiseq = 0; 793 } 794 795 error = ahc_reset(ahc, /*reinit*/FALSE); 796 if (error != 0) 797 return (ENXIO); 798 799 if ((ahc->features & AHC_DT) != 0) { 800 u_int sfunct; 801 802 /* Perform ALT-Mode Setup */ 803 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 804 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 805 ahc_outb(ahc, OPTIONMODE, 806 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 807 ahc_outb(ahc, SFUNCT, sfunct); 808 809 /* Normal mode setup */ 810 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 811 |TARGCRCENDEN); 812 } 813 814 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 815 dscommand0 |= MPARCKEN|CACHETHEN; 816 if ((ahc->features & AHC_ULTRA2) != 0) { 817 818 /* 819 * DPARCKEN doesn't work correctly on 820 * some MBs so don't use it. 821 */ 822 dscommand0 &= ~DPARCKEN; 823 } 824 825 /* 826 * Handle chips that must have cache line 827 * streaming (dis/en)abled. 828 */ 829 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 830 dscommand0 |= CACHETHEN; 831 832 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 833 dscommand0 &= ~CACHETHEN; 834 835 ahc_outb(ahc, DSCOMMAND0, dscommand0); 836 837 ahc->pci_cachesize = 838 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 839 /*bytes*/1) & CACHESIZE; 840 ahc->pci_cachesize *= 4; 841 842 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 843 && ahc->pci_cachesize == 4) { 844 845 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 846 0, /*bytes*/1); 847 ahc->pci_cachesize = 0; 848 } 849 850 /* 851 * We cannot perform ULTRA speeds without the presense 852 * of the external precision resistor. 853 */ 854 if ((ahc->features & AHC_ULTRA) != 0) { 855 uint32_t devconfig; 856 857 devconfig = ahc_pci_read_config(ahc->dev_softc, 858 DEVCONFIG, /*bytes*/4); 859 if ((devconfig & REXTVALID) == 0) 860 ahc->features &= ~AHC_ULTRA; 861 } 862 863 /* See if we have a SEEPROM and perform auto-term */ 864 check_extport(ahc, &sxfrctl1); 865 866 /* 867 * Take the LED out of diagnostic mode 868 */ 869 sblkctl = ahc_inb(ahc, SBLKCTL); 870 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 871 872 if ((ahc->features & AHC_ULTRA2) != 0) { 873 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 874 } else { 875 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 876 } 877 878 if (ahc->flags & AHC_USEDEFAULTS) { 879 /* 880 * PCI Adapter default setup 881 * Should only be used if the adapter does not have 882 * a SEEPROM. 883 */ 884 /* See if someone else set us up already */ 885 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 886 && scsiseq != 0) { 887 printk("%s: Using left over BIOS settings\n", 888 ahc_name(ahc)); 889 ahc->flags &= ~AHC_USEDEFAULTS; 890 ahc->flags |= AHC_BIOS_ENABLED; 891 } else { 892 /* 893 * Assume only one connector and always turn 894 * on termination. 895 */ 896 our_id = 0x07; 897 sxfrctl1 = STPWEN; 898 } 899 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 900 901 ahc->our_id = our_id; 902 } 903 904 /* 905 * Take a look to see if we have external SRAM. 906 * We currently do not attempt to use SRAM that is 907 * shared among multiple controllers. 908 */ 909 ahc_probe_ext_scbram(ahc); 910 911 /* 912 * Record our termination setting for the 913 * generic initialization routine. 914 */ 915 if ((sxfrctl1 & STPWEN) != 0) 916 ahc->flags |= AHC_TERM_ENB_A; 917 918 /* 919 * Save chip register configuration data for chip resets 920 * that occur during runtime and resume events. 921 */ 922 ahc->bus_softc.pci_softc.devconfig = 923 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 924 ahc->bus_softc.pci_softc.command = 925 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 926 ahc->bus_softc.pci_softc.csize_lattime = 927 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 928 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 929 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 930 if ((ahc->features & AHC_DT) != 0) { 931 u_int sfunct; 932 933 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 934 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 935 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 936 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 937 ahc_outb(ahc, SFUNCT, sfunct); 938 ahc->bus_softc.pci_softc.crccontrol1 = 939 ahc_inb(ahc, CRCCONTROL1); 940 } 941 if ((ahc->features & AHC_MULTI_FUNC) != 0) 942 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 943 944 if ((ahc->features & AHC_ULTRA2) != 0) 945 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 946 947 /* Core initialization */ 948 error = ahc_init(ahc); 949 if (error != 0) 950 return (error); 951 ahc->init_level++; 952 953 /* 954 * Allow interrupts now that we are completely setup. 955 */ 956 return ahc_pci_map_int(ahc); 957} 958 959/* 960 * Test for the presense of external sram in an 961 * "unshared" configuration. 962 */ 963static int 964ahc_ext_scbram_present(struct ahc_softc *ahc) 965{ 966 u_int chip; 967 int ramps; 968 int single_user; 969 uint32_t devconfig; 970 971 chip = ahc->chip & AHC_CHIPID_MASK; 972 devconfig = ahc_pci_read_config(ahc->dev_softc, 973 DEVCONFIG, /*bytes*/4); 974 single_user = (devconfig & MPORTMODE) != 0; 975 976 if ((ahc->features & AHC_ULTRA2) != 0) 977 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 978 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 979 /* 980 * External SCBRAM arbitration is flakey 981 * on these chips. Unfortunately this means 982 * we don't use the extra SCB ram space on the 983 * 3940AUW. 984 */ 985 ramps = 0; 986 else if (chip >= AHC_AIC7870) 987 ramps = (devconfig & RAMPSM) != 0; 988 else 989 ramps = 0; 990 991 if (ramps && single_user) 992 return (1); 993 return (0); 994} 995 996/* 997 * Enable external scbram. 998 */ 999static void 1000ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1001 int fast, int large) 1002{ 1003 uint32_t devconfig; 1004 1005 if (ahc->features & AHC_MULTI_FUNC) { 1006 /* 1007 * Set the SCB Base addr (highest address bit) 1008 * depending on which channel we are. 1009 */ 1010 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1011 } 1012 1013 ahc->flags &= ~AHC_LSCBS_ENABLED; 1014 if (large) 1015 ahc->flags |= AHC_LSCBS_ENABLED; 1016 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1017 if ((ahc->features & AHC_ULTRA2) != 0) { 1018 u_int dscommand0; 1019 1020 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1021 if (enable) 1022 dscommand0 &= ~INTSCBRAMSEL; 1023 else 1024 dscommand0 |= INTSCBRAMSEL; 1025 if (large) 1026 dscommand0 &= ~USCBSIZE32; 1027 else 1028 dscommand0 |= USCBSIZE32; 1029 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1030 } else { 1031 if (fast) 1032 devconfig &= ~EXTSCBTIME; 1033 else 1034 devconfig |= EXTSCBTIME; 1035 if (enable) 1036 devconfig &= ~SCBRAMSEL; 1037 else 1038 devconfig |= SCBRAMSEL; 1039 if (large) 1040 devconfig &= ~SCBSIZE32; 1041 else 1042 devconfig |= SCBSIZE32; 1043 } 1044 if (pcheck) 1045 devconfig |= EXTSCBPEN; 1046 else 1047 devconfig &= ~EXTSCBPEN; 1048 1049 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1050} 1051 1052/* 1053 * Take a look to see if we have external SRAM. 1054 * We currently do not attempt to use SRAM that is 1055 * shared among multiple controllers. 1056 */ 1057static void 1058ahc_probe_ext_scbram(struct ahc_softc *ahc) 1059{ 1060 int num_scbs; 1061 int test_num_scbs; 1062 int enable; 1063 int pcheck; 1064 int fast; 1065 int large; 1066 1067 enable = FALSE; 1068 pcheck = FALSE; 1069 fast = FALSE; 1070 large = FALSE; 1071 num_scbs = 0; 1072 1073 if (ahc_ext_scbram_present(ahc) == 0) 1074 goto done; 1075 1076 /* 1077 * Probe for the best parameters to use. 1078 */ 1079 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1080 num_scbs = ahc_probe_scbs(ahc); 1081 if (num_scbs == 0) { 1082 /* The SRAM wasn't really present. */ 1083 goto done; 1084 } 1085 enable = TRUE; 1086 1087 /* 1088 * Clear any outstanding parity error 1089 * and ensure that parity error reporting 1090 * is enabled. 1091 */ 1092 ahc_outb(ahc, SEQCTL, 0); 1093 ahc_outb(ahc, CLRINT, CLRPARERR); 1094 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1095 1096 /* Now see if we can do parity */ 1097 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1098 num_scbs = ahc_probe_scbs(ahc); 1099 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1100 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1101 pcheck = TRUE; 1102 1103 /* Clear any resulting parity error */ 1104 ahc_outb(ahc, CLRINT, CLRPARERR); 1105 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1106 1107 /* Now see if we can do fast timing */ 1108 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1109 test_num_scbs = ahc_probe_scbs(ahc); 1110 if (test_num_scbs == num_scbs 1111 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1112 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1113 fast = TRUE; 1114 1115 /* 1116 * See if we can use large SCBs and still maintain 1117 * the same overall count of SCBs. 1118 */ 1119 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1120 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1121 test_num_scbs = ahc_probe_scbs(ahc); 1122 if (test_num_scbs >= num_scbs) { 1123 large = TRUE; 1124 num_scbs = test_num_scbs; 1125 if (num_scbs >= 64) { 1126 /* 1127 * We have enough space to move the 1128 * "busy targets table" into SCB space 1129 * and make it qualify all the way to the 1130 * lun level. 1131 */ 1132 ahc->flags |= AHC_SCB_BTT; 1133 } 1134 } 1135 } 1136done: 1137 /* 1138 * Disable parity error reporting until we 1139 * can load instruction ram. 1140 */ 1141 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1142 /* Clear any latched parity error */ 1143 ahc_outb(ahc, CLRINT, CLRPARERR); 1144 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1145 if (bootverbose && enable) { 1146 printk("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1147 ahc_name(ahc), fast ? "fast" : "slow", 1148 pcheck ? ", parity checking enabled" : "", 1149 large ? 64 : 32); 1150 } 1151 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1152} 1153 1154/* 1155 * Perform some simple tests that should catch situations where 1156 * our registers are invalidly mapped. 1157 */ 1158int 1159ahc_pci_test_register_access(struct ahc_softc *ahc) 1160{ 1161 int error; 1162 u_int status1; 1163 uint32_t cmd; 1164 uint8_t hcntrl; 1165 1166 error = EIO; 1167 1168 /* 1169 * Enable PCI error interrupt status, but suppress NMIs 1170 * generated by SERR raised due to target aborts. 1171 */ 1172 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1173 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1174 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1175 1176 /* 1177 * First a simple test to see if any 1178 * registers can be read. Reading 1179 * HCNTRL has no side effects and has 1180 * at least one bit that is guaranteed to 1181 * be zero so it is a good register to 1182 * use for this test. 1183 */ 1184 hcntrl = ahc_inb(ahc, HCNTRL); 1185 1186 if (hcntrl == 0xFF) 1187 goto fail; 1188 1189 if ((hcntrl & CHIPRST) != 0) { 1190 /* 1191 * The chip has not been initialized since 1192 * PCI/EISA/VLB bus reset. Don't trust 1193 * "left over BIOS data". 1194 */ 1195 ahc->flags |= AHC_NO_BIOS_INIT; 1196 } 1197 1198 /* 1199 * Next create a situation where write combining 1200 * or read prefetching could be initiated by the 1201 * CPU or host bridge. Our device does not support 1202 * either, so look for data corruption and/or flagged 1203 * PCI errors. First pause without causing another 1204 * chip reset. 1205 */ 1206 hcntrl &= ~CHIPRST; 1207 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1208 while (ahc_is_paused(ahc) == 0) 1209 ; 1210 1211 /* Clear any PCI errors that occurred before our driver attached. */ 1212 status1 = ahc_pci_read_config(ahc->dev_softc, 1213 PCIR_STATUS + 1, /*bytes*/1); 1214 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1215 status1, /*bytes*/1); 1216 ahc_outb(ahc, CLRINT, CLRPARERR); 1217 1218 ahc_outb(ahc, SEQCTL, PERRORDIS); 1219 ahc_outb(ahc, SCBPTR, 0); 1220 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1221 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1222 goto fail; 1223 1224 status1 = ahc_pci_read_config(ahc->dev_softc, 1225 PCIR_STATUS + 1, /*bytes*/1); 1226 if ((status1 & STA) != 0) 1227 goto fail; 1228 1229 error = 0; 1230 1231fail: 1232 /* Silently clear any latched errors. */ 1233 status1 = ahc_pci_read_config(ahc->dev_softc, 1234 PCIR_STATUS + 1, /*bytes*/1); 1235 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1236 status1, /*bytes*/1); 1237 ahc_outb(ahc, CLRINT, CLRPARERR); 1238 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1239 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1240 return (error); 1241} 1242 1243/* 1244 * Check the external port logic for a serial eeprom 1245 * and termination/cable detection contrls. 1246 */ 1247static void 1248check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1249{ 1250 struct seeprom_descriptor sd; 1251 struct seeprom_config *sc; 1252 int have_seeprom; 1253 int have_autoterm; 1254 1255 sd.sd_ahc = ahc; 1256 sd.sd_control_offset = SEECTL; 1257 sd.sd_status_offset = SEECTL; 1258 sd.sd_dataout_offset = SEECTL; 1259 sc = ahc->seep_config; 1260 1261 /* 1262 * For some multi-channel devices, the c46 is simply too 1263 * small to work. For the other controller types, we can 1264 * get our information from either SEEPROM type. Set the 1265 * type to start our probe with accordingly. 1266 */ 1267 if (ahc->flags & AHC_LARGE_SEEPROM) 1268 sd.sd_chip = C56_66; 1269 else 1270 sd.sd_chip = C46; 1271 1272 sd.sd_MS = SEEMS; 1273 sd.sd_RDY = SEERDY; 1274 sd.sd_CS = SEECS; 1275 sd.sd_CK = SEECK; 1276 sd.sd_DO = SEEDO; 1277 sd.sd_DI = SEEDI; 1278 1279 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1280 if (have_seeprom) { 1281 1282 if (bootverbose) 1283 printk("%s: Reading SEEPROM...", ahc_name(ahc)); 1284 1285 for (;;) { 1286 u_int start_addr; 1287 1288 start_addr = 32 * (ahc->channel - 'A'); 1289 1290 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1291 start_addr, 1292 sizeof(*sc)/2); 1293 1294 if (have_seeprom) 1295 have_seeprom = ahc_verify_cksum(sc); 1296 1297 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1298 if (bootverbose) { 1299 if (have_seeprom == 0) 1300 printk ("checksum error\n"); 1301 else 1302 printk ("done.\n"); 1303 } 1304 break; 1305 } 1306 sd.sd_chip = C56_66; 1307 } 1308 ahc_release_seeprom(&sd); 1309 1310 /* Remember the SEEPROM type for later */ 1311 if (sd.sd_chip == C56_66) 1312 ahc->flags |= AHC_LARGE_SEEPROM; 1313 } 1314 1315 if (!have_seeprom) { 1316 /* 1317 * Pull scratch ram settings and treat them as 1318 * if they are the contents of an seeprom if 1319 * the 'ADPT' signature is found in SCB2. 1320 * We manually compose the data as 16bit values 1321 * to avoid endian issues. 1322 */ 1323 ahc_outb(ahc, SCBPTR, 2); 1324 if (ahc_inb(ahc, SCB_BASE) == 'A' 1325 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1326 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1327 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1328 uint16_t *sc_data; 1329 int i; 1330 1331 sc_data = (uint16_t *)sc; 1332 for (i = 0; i < 32; i++, sc_data++) { 1333 int j; 1334 1335 j = i * 2; 1336 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1337 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1338 } 1339 have_seeprom = ahc_verify_cksum(sc); 1340 if (have_seeprom) 1341 ahc->flags |= AHC_SCB_CONFIG_USED; 1342 } 1343 /* 1344 * Clear any SCB parity errors in case this data and 1345 * its associated parity was not initialized by the BIOS 1346 */ 1347 ahc_outb(ahc, CLRINT, CLRPARERR); 1348 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1349 } 1350 1351 if (!have_seeprom) { 1352 if (bootverbose) 1353 printk("%s: No SEEPROM available.\n", ahc_name(ahc)); 1354 ahc->flags |= AHC_USEDEFAULTS; 1355 kfree(ahc->seep_config); 1356 ahc->seep_config = NULL; 1357 sc = NULL; 1358 } else { 1359 ahc_parse_pci_eeprom(ahc, sc); 1360 } 1361 1362 /* 1363 * Cards that have the external logic necessary to talk to 1364 * a SEEPROM, are almost certain to have the remaining logic 1365 * necessary for auto-termination control. This assumption 1366 * hasn't failed yet... 1367 */ 1368 have_autoterm = have_seeprom; 1369 1370 /* 1371 * Some low-cost chips have SEEPROM and auto-term control built 1372 * in, instead of using a GAL. They can tell us directly 1373 * if the termination logic is enabled. 1374 */ 1375 if ((ahc->features & AHC_SPIOCAP) != 0) { 1376 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1377 have_autoterm = FALSE; 1378 } 1379 1380 if (have_autoterm) { 1381 ahc->flags |= AHC_HAS_TERM_LOGIC; 1382 ahc_acquire_seeprom(ahc, &sd); 1383 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1384 ahc_release_seeprom(&sd); 1385 } else if (have_seeprom) { 1386 *sxfrctl1 &= ~STPWEN; 1387 if ((sc->adapter_control & CFSTERM) != 0) 1388 *sxfrctl1 |= STPWEN; 1389 if (bootverbose) 1390 printk("%s: Low byte termination %sabled\n", 1391 ahc_name(ahc), 1392 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1393 } 1394} 1395 1396static void 1397ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1398{ 1399 /* 1400 * Put the data we've collected down into SRAM 1401 * where ahc_init will find it. 1402 */ 1403 int i; 1404 int max_targ = sc->max_targets & CFMAXTARG; 1405 u_int scsi_conf; 1406 uint16_t discenable; 1407 uint16_t ultraenb; 1408 1409 discenable = 0; 1410 ultraenb = 0; 1411 if ((sc->adapter_control & CFULTRAEN) != 0) { 1412 /* 1413 * Determine if this adapter has a "newstyle" 1414 * SEEPROM format. 1415 */ 1416 for (i = 0; i < max_targ; i++) { 1417 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1418 ahc->flags |= AHC_NEWEEPROM_FMT; 1419 break; 1420 } 1421 } 1422 } 1423 1424 for (i = 0; i < max_targ; i++) { 1425 u_int scsirate; 1426 uint16_t target_mask; 1427 1428 target_mask = 0x01 << i; 1429 if (sc->device_flags[i] & CFDISC) 1430 discenable |= target_mask; 1431 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1432 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1433 ultraenb |= target_mask; 1434 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1435 ultraenb |= target_mask; 1436 } 1437 if ((sc->device_flags[i] & CFXFER) == 0x04 1438 && (ultraenb & target_mask) != 0) { 1439 /* Treat 10MHz as a non-ultra speed */ 1440 sc->device_flags[i] &= ~CFXFER; 1441 ultraenb &= ~target_mask; 1442 } 1443 if ((ahc->features & AHC_ULTRA2) != 0) { 1444 u_int offset; 1445 1446 if (sc->device_flags[i] & CFSYNCH) 1447 offset = MAX_OFFSET_ULTRA2; 1448 else 1449 offset = 0; 1450 ahc_outb(ahc, TARG_OFFSET + i, offset); 1451 1452 /* 1453 * The ultra enable bits contain the 1454 * high bit of the ultra2 sync rate 1455 * field. 1456 */ 1457 scsirate = (sc->device_flags[i] & CFXFER) 1458 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1459 if (sc->device_flags[i] & CFWIDEB) 1460 scsirate |= WIDEXFER; 1461 } else { 1462 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1463 if (sc->device_flags[i] & CFSYNCH) 1464 scsirate |= SOFS; 1465 if (sc->device_flags[i] & CFWIDEB) 1466 scsirate |= WIDEXFER; 1467 } 1468 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1469 } 1470 ahc->our_id = sc->brtime_id & CFSCSIID; 1471 1472 scsi_conf = (ahc->our_id & 0x7); 1473 if (sc->adapter_control & CFSPARITY) 1474 scsi_conf |= ENSPCHK; 1475 if (sc->adapter_control & CFRESETB) 1476 scsi_conf |= RESET_SCSI; 1477 1478 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1479 1480 if (sc->bios_control & CFEXTEND) 1481 ahc->flags |= AHC_EXTENDED_TRANS_A; 1482 1483 if (sc->bios_control & CFBIOSEN) 1484 ahc->flags |= AHC_BIOS_ENABLED; 1485 if (ahc->features & AHC_ULTRA 1486 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1487 /* Should we enable Ultra mode? */ 1488 if (!(sc->adapter_control & CFULTRAEN)) 1489 /* Treat us as a non-ultra card */ 1490 ultraenb = 0; 1491 } 1492 1493 if (sc->signature == CFSIGNATURE 1494 || sc->signature == CFSIGNATURE2) { 1495 uint32_t devconfig; 1496 1497 /* Honor the STPWLEVEL settings */ 1498 devconfig = ahc_pci_read_config(ahc->dev_softc, 1499 DEVCONFIG, /*bytes*/4); 1500 devconfig &= ~STPWLEVEL; 1501 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1502 devconfig |= STPWLEVEL; 1503 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1504 devconfig, /*bytes*/4); 1505 } 1506 /* Set SCSICONF info */ 1507 ahc_outb(ahc, SCSICONF, scsi_conf); 1508 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1509 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1510 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1511 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1512} 1513 1514static void 1515configure_termination(struct ahc_softc *ahc, 1516 struct seeprom_descriptor *sd, 1517 u_int adapter_control, 1518 u_int *sxfrctl1) 1519{ 1520 uint8_t brddat; 1521 1522 brddat = 0; 1523 1524 /* 1525 * Update the settings in sxfrctl1 to match the 1526 * termination settings 1527 */ 1528 *sxfrctl1 = 0; 1529 1530 /* 1531 * SEECS must be on for the GALS to latch 1532 * the data properly. Be sure to leave MS 1533 * on or we will release the seeprom. 1534 */ 1535 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1536 if ((adapter_control & CFAUTOTERM) != 0 1537 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1538 int internal50_present; 1539 int internal68_present; 1540 int externalcable_present; 1541 int eeprom_present; 1542 int enableSEC_low; 1543 int enableSEC_high; 1544 int enablePRI_low; 1545 int enablePRI_high; 1546 int sum; 1547 1548 enableSEC_low = 0; 1549 enableSEC_high = 0; 1550 enablePRI_low = 0; 1551 enablePRI_high = 0; 1552 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1553 ahc_new_term_detect(ahc, &enableSEC_low, 1554 &enableSEC_high, 1555 &enablePRI_low, 1556 &enablePRI_high, 1557 &eeprom_present); 1558 if ((adapter_control & CFSEAUTOTERM) == 0) { 1559 if (bootverbose) 1560 printk("%s: Manual SE Termination\n", 1561 ahc_name(ahc)); 1562 enableSEC_low = (adapter_control & CFSELOWTERM); 1563 enableSEC_high = 1564 (adapter_control & CFSEHIGHTERM); 1565 } 1566 if ((adapter_control & CFAUTOTERM) == 0) { 1567 if (bootverbose) 1568 printk("%s: Manual LVD Termination\n", 1569 ahc_name(ahc)); 1570 enablePRI_low = (adapter_control & CFSTERM); 1571 enablePRI_high = (adapter_control & CFWSTERM); 1572 } 1573 /* Make the table calculations below happy */ 1574 internal50_present = 0; 1575 internal68_present = 1; 1576 externalcable_present = 1; 1577 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1578 aic785X_cable_detect(ahc, &internal50_present, 1579 &externalcable_present, 1580 &eeprom_present); 1581 /* Can never support a wide connector. */ 1582 internal68_present = 0; 1583 } else { 1584 aic787X_cable_detect(ahc, &internal50_present, 1585 &internal68_present, 1586 &externalcable_present, 1587 &eeprom_present); 1588 } 1589 1590 if ((ahc->features & AHC_WIDE) == 0) 1591 internal68_present = 0; 1592 1593 if (bootverbose 1594 && (ahc->features & AHC_ULTRA2) == 0) { 1595 printk("%s: internal 50 cable %s present", 1596 ahc_name(ahc), 1597 internal50_present ? "is":"not"); 1598 1599 if ((ahc->features & AHC_WIDE) != 0) 1600 printk(", internal 68 cable %s present", 1601 internal68_present ? "is":"not"); 1602 printk("\n%s: external cable %s present\n", 1603 ahc_name(ahc), 1604 externalcable_present ? "is":"not"); 1605 } 1606 if (bootverbose) 1607 printk("%s: BIOS eeprom %s present\n", 1608 ahc_name(ahc), eeprom_present ? "is" : "not"); 1609 1610 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1611 /* 1612 * The 50 pin connector is a separate bus, 1613 * so force it to always be terminated. 1614 * In the future, perform current sensing 1615 * to determine if we are in the middle of 1616 * a properly terminated bus. 1617 */ 1618 internal50_present = 0; 1619 } 1620 1621 /* 1622 * Now set the termination based on what 1623 * we found. 1624 * Flash Enable = BRDDAT7 1625 * Secondary High Term Enable = BRDDAT6 1626 * Secondary Low Term Enable = BRDDAT5 (7890) 1627 * Primary High Term Enable = BRDDAT4 (7890) 1628 */ 1629 if ((ahc->features & AHC_ULTRA2) == 0 1630 && (internal50_present != 0) 1631 && (internal68_present != 0) 1632 && (externalcable_present != 0)) { 1633 printk("%s: Illegal cable configuration!!. " 1634 "Only two connectors on the " 1635 "adapter may be used at a " 1636 "time!\n", ahc_name(ahc)); 1637 1638 /* 1639 * Pretend there are no cables in the hope 1640 * that having all of the termination on 1641 * gives us a more stable bus. 1642 */ 1643 internal50_present = 0; 1644 internal68_present = 0; 1645 externalcable_present = 0; 1646 } 1647 1648 if ((ahc->features & AHC_WIDE) != 0 1649 && ((externalcable_present == 0) 1650 || (internal68_present == 0) 1651 || (enableSEC_high != 0))) { 1652 brddat |= BRDDAT6; 1653 if (bootverbose) { 1654 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1655 printk("%s: 68 pin termination " 1656 "Enabled\n", ahc_name(ahc)); 1657 else 1658 printk("%s: %sHigh byte termination " 1659 "Enabled\n", ahc_name(ahc), 1660 enableSEC_high ? "Secondary " 1661 : ""); 1662 } 1663 } 1664 1665 sum = internal50_present + internal68_present 1666 + externalcable_present; 1667 if (sum < 2 || (enableSEC_low != 0)) { 1668 if ((ahc->features & AHC_ULTRA2) != 0) 1669 brddat |= BRDDAT5; 1670 else 1671 *sxfrctl1 |= STPWEN; 1672 if (bootverbose) { 1673 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1674 printk("%s: 50 pin termination " 1675 "Enabled\n", ahc_name(ahc)); 1676 else 1677 printk("%s: %sLow byte termination " 1678 "Enabled\n", ahc_name(ahc), 1679 enableSEC_low ? "Secondary " 1680 : ""); 1681 } 1682 } 1683 1684 if (enablePRI_low != 0) { 1685 *sxfrctl1 |= STPWEN; 1686 if (bootverbose) 1687 printk("%s: Primary Low Byte termination " 1688 "Enabled\n", ahc_name(ahc)); 1689 } 1690 1691 /* 1692 * Setup STPWEN before setting up the rest of 1693 * the termination per the tech note on the U160 cards. 1694 */ 1695 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1696 1697 if (enablePRI_high != 0) { 1698 brddat |= BRDDAT4; 1699 if (bootverbose) 1700 printk("%s: Primary High Byte " 1701 "termination Enabled\n", 1702 ahc_name(ahc)); 1703 } 1704 1705 write_brdctl(ahc, brddat); 1706 1707 } else { 1708 if ((adapter_control & CFSTERM) != 0) { 1709 *sxfrctl1 |= STPWEN; 1710 1711 if (bootverbose) 1712 printk("%s: %sLow byte termination Enabled\n", 1713 ahc_name(ahc), 1714 (ahc->features & AHC_ULTRA2) ? "Primary " 1715 : ""); 1716 } 1717 1718 if ((adapter_control & CFWSTERM) != 0 1719 && (ahc->features & AHC_WIDE) != 0) { 1720 brddat |= BRDDAT6; 1721 if (bootverbose) 1722 printk("%s: %sHigh byte termination Enabled\n", 1723 ahc_name(ahc), 1724 (ahc->features & AHC_ULTRA2) 1725 ? "Secondary " : ""); 1726 } 1727 1728 /* 1729 * Setup STPWEN before setting up the rest of 1730 * the termination per the tech note on the U160 cards. 1731 */ 1732 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1733 1734 if ((ahc->features & AHC_WIDE) != 0) 1735 write_brdctl(ahc, brddat); 1736 } 1737 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1738} 1739 1740static void 1741ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1742 int *enableSEC_high, int *enablePRI_low, 1743 int *enablePRI_high, int *eeprom_present) 1744{ 1745 uint8_t brdctl; 1746 1747 /* 1748 * BRDDAT7 = Eeprom 1749 * BRDDAT6 = Enable Secondary High Byte termination 1750 * BRDDAT5 = Enable Secondary Low Byte termination 1751 * BRDDAT4 = Enable Primary high byte termination 1752 * BRDDAT3 = Enable Primary low byte termination 1753 */ 1754 brdctl = read_brdctl(ahc); 1755 *eeprom_present = brdctl & BRDDAT7; 1756 *enableSEC_high = (brdctl & BRDDAT6); 1757 *enableSEC_low = (brdctl & BRDDAT5); 1758 *enablePRI_high = (brdctl & BRDDAT4); 1759 *enablePRI_low = (brdctl & BRDDAT3); 1760} 1761 1762static void 1763aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1764 int *internal68_present, int *externalcable_present, 1765 int *eeprom_present) 1766{ 1767 uint8_t brdctl; 1768 1769 /* 1770 * First read the status of our cables. 1771 * Set the rom bank to 0 since the 1772 * bank setting serves as a multiplexor 1773 * for the cable detection logic. 1774 * BRDDAT5 controls the bank switch. 1775 */ 1776 write_brdctl(ahc, 0); 1777 1778 /* 1779 * Now read the state of the internal 1780 * connectors. BRDDAT6 is INT50 and 1781 * BRDDAT7 is INT68. 1782 */ 1783 brdctl = read_brdctl(ahc); 1784 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1785 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1786 1787 /* 1788 * Set the rom bank to 1 and determine 1789 * the other signals. 1790 */ 1791 write_brdctl(ahc, BRDDAT5); 1792 1793 /* 1794 * Now read the state of the external 1795 * connectors. BRDDAT6 is EXT68 and 1796 * BRDDAT7 is EPROMPS. 1797 */ 1798 brdctl = read_brdctl(ahc); 1799 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1800 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1801} 1802 1803static void 1804aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1805 int *externalcable_present, int *eeprom_present) 1806{ 1807 uint8_t brdctl; 1808 uint8_t spiocap; 1809 1810 spiocap = ahc_inb(ahc, SPIOCAP); 1811 spiocap &= ~SOFTCMDEN; 1812 spiocap |= EXT_BRDCTL; 1813 ahc_outb(ahc, SPIOCAP, spiocap); 1814 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1815 ahc_flush_device_writes(ahc); 1816 ahc_delay(500); 1817 ahc_outb(ahc, BRDCTL, 0); 1818 ahc_flush_device_writes(ahc); 1819 ahc_delay(500); 1820 brdctl = ahc_inb(ahc, BRDCTL); 1821 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1822 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1823 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1824} 1825 1826int 1827ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1828{ 1829 int wait; 1830 1831 if ((ahc->features & AHC_SPIOCAP) != 0 1832 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1833 return (0); 1834 1835 /* 1836 * Request access of the memory port. When access is 1837 * granted, SEERDY will go high. We use a 1 second 1838 * timeout which should be near 1 second more than 1839 * is needed. Reason: after the chip reset, there 1840 * should be no contention. 1841 */ 1842 SEEPROM_OUTB(sd, sd->sd_MS); 1843 wait = 1000; /* 1 second timeout in msec */ 1844 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1845 ahc_delay(1000); /* delay 1 msec */ 1846 } 1847 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1848 SEEPROM_OUTB(sd, 0); 1849 return (0); 1850 } 1851 return(1); 1852} 1853 1854void 1855ahc_release_seeprom(struct seeprom_descriptor *sd) 1856{ 1857 /* Release access to the memory port and the serial EEPROM. */ 1858 SEEPROM_OUTB(sd, 0); 1859} 1860 1861static void 1862write_brdctl(struct ahc_softc *ahc, uint8_t value) 1863{ 1864 uint8_t brdctl; 1865 1866 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1867 brdctl = BRDSTB; 1868 if (ahc->channel == 'B') 1869 brdctl |= BRDCS; 1870 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1871 brdctl = 0; 1872 } else { 1873 brdctl = BRDSTB|BRDCS; 1874 } 1875 ahc_outb(ahc, BRDCTL, brdctl); 1876 ahc_flush_device_writes(ahc); 1877 brdctl |= value; 1878 ahc_outb(ahc, BRDCTL, brdctl); 1879 ahc_flush_device_writes(ahc); 1880 if ((ahc->features & AHC_ULTRA2) != 0) 1881 brdctl |= BRDSTB_ULTRA2; 1882 else 1883 brdctl &= ~BRDSTB; 1884 ahc_outb(ahc, BRDCTL, brdctl); 1885 ahc_flush_device_writes(ahc); 1886 if ((ahc->features & AHC_ULTRA2) != 0) 1887 brdctl = 0; 1888 else 1889 brdctl &= ~BRDCS; 1890 ahc_outb(ahc, BRDCTL, brdctl); 1891} 1892 1893static uint8_t 1894read_brdctl(struct ahc_softc *ahc) 1895{ 1896 uint8_t brdctl; 1897 uint8_t value; 1898 1899 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1900 brdctl = BRDRW; 1901 if (ahc->channel == 'B') 1902 brdctl |= BRDCS; 1903 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1904 brdctl = BRDRW_ULTRA2; 1905 } else { 1906 brdctl = BRDRW|BRDCS; 1907 } 1908 ahc_outb(ahc, BRDCTL, brdctl); 1909 ahc_flush_device_writes(ahc); 1910 value = ahc_inb(ahc, BRDCTL); 1911 ahc_outb(ahc, BRDCTL, 0); 1912 return (value); 1913} 1914 1915static void 1916ahc_pci_intr(struct ahc_softc *ahc) 1917{ 1918 u_int error; 1919 u_int status1; 1920 1921 error = ahc_inb(ahc, ERROR); 1922 if ((error & PCIERRSTAT) == 0) 1923 return; 1924 1925 status1 = ahc_pci_read_config(ahc->dev_softc, 1926 PCIR_STATUS + 1, /*bytes*/1); 1927 1928 printk("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1929 ahc_name(ahc), 1930 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1931 1932 if (status1 & DPE) { 1933 ahc->pci_target_perr_count++; 1934 printk("%s: Data Parity Error Detected during address " 1935 "or write data phase\n", ahc_name(ahc)); 1936 } 1937 if (status1 & SSE) { 1938 printk("%s: Signal System Error Detected\n", ahc_name(ahc)); 1939 } 1940 if (status1 & RMA) { 1941 printk("%s: Received a Master Abort\n", ahc_name(ahc)); 1942 } 1943 if (status1 & RTA) { 1944 printk("%s: Received a Target Abort\n", ahc_name(ahc)); 1945 } 1946 if (status1 & STA) { 1947 printk("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1948 } 1949 if (status1 & DPR) { 1950 printk("%s: Data Parity Error has been reported via PERR#\n", 1951 ahc_name(ahc)); 1952 } 1953 1954 /* Clear latched errors. */ 1955 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1956 status1, /*bytes*/1); 1957 1958 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1959 printk("%s: Latched PCIERR interrupt with " 1960 "no status bits set\n", ahc_name(ahc)); 1961 } else { 1962 ahc_outb(ahc, CLRINT, CLRPARERR); 1963 } 1964 1965 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { 1966 printk( 1967"%s: WARNING WARNING WARNING WARNING\n" 1968"%s: Too many PCI parity errors observed as a target.\n" 1969"%s: Some device on this bus is generating bad parity.\n" 1970"%s: This is an error *observed by*, not *generated by*, this controller.\n" 1971"%s: PCI parity error checking has been disabled.\n" 1972"%s: WARNING WARNING WARNING WARNING\n", 1973 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 1974 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); 1975 ahc->seqctl |= FAILDIS; 1976 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1977 } 1978 ahc_unpause(ahc); 1979} 1980 1981static int 1982ahc_pci_chip_init(struct ahc_softc *ahc) 1983{ 1984 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 1985 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 1986 if ((ahc->features & AHC_DT) != 0) { 1987 u_int sfunct; 1988 1989 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1990 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1991 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 1992 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 1993 ahc_outb(ahc, SFUNCT, sfunct); 1994 ahc_outb(ahc, CRCCONTROL1, 1995 ahc->bus_softc.pci_softc.crccontrol1); 1996 } 1997 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1998 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 1999 2000 if ((ahc->features & AHC_ULTRA2) != 0) 2001 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 2002 2003 return (ahc_chip_init(ahc)); 2004} 2005 2006#ifdef CONFIG_PM 2007void 2008ahc_pci_resume(struct ahc_softc *ahc) 2009{ 2010 /* 2011 * We assume that the OS has restored our register 2012 * mappings, etc. Just update the config space registers 2013 * that the OS doesn't know about and rely on our chip 2014 * reset handler to handle the rest. 2015 */ 2016 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 2017 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4); 2018 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 2019 ahc->bus_softc.pci_softc.command, /*bytes*/1); 2020 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 2021 ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1); 2022 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2023 struct seeprom_descriptor sd; 2024 u_int sxfrctl1; 2025 2026 sd.sd_ahc = ahc; 2027 sd.sd_control_offset = SEECTL; 2028 sd.sd_status_offset = SEECTL; 2029 sd.sd_dataout_offset = SEECTL; 2030 2031 ahc_acquire_seeprom(ahc, &sd); 2032 configure_termination(ahc, &sd, 2033 ahc->seep_config->adapter_control, 2034 &sxfrctl1); 2035 ahc_release_seeprom(&sd); 2036 } 2037} 2038#endif 2039 2040static int 2041ahc_aic785X_setup(struct ahc_softc *ahc) 2042{ 2043 ahc_dev_softc_t pci; 2044 uint8_t rev; 2045 2046 pci = ahc->dev_softc; 2047 ahc->channel = 'A'; 2048 ahc->chip = AHC_AIC7850; 2049 ahc->features = AHC_AIC7850_FE; 2050 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2051 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2052 if (rev >= 1) 2053 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2054 ahc->instruction_ram_size = 512; 2055 return (0); 2056} 2057 2058static int 2059ahc_aic7860_setup(struct ahc_softc *ahc) 2060{ 2061 ahc_dev_softc_t pci; 2062 uint8_t rev; 2063 2064 pci = ahc->dev_softc; 2065 ahc->channel = 'A'; 2066 ahc->chip = AHC_AIC7860; 2067 ahc->features = AHC_AIC7860_FE; 2068 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2069 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2070 if (rev >= 1) 2071 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2072 ahc->instruction_ram_size = 512; 2073 return (0); 2074} 2075 2076static int 2077ahc_apa1480_setup(struct ahc_softc *ahc) 2078{ 2079 int error; 2080 2081 error = ahc_aic7860_setup(ahc); 2082 if (error != 0) 2083 return (error); 2084 ahc->features |= AHC_REMOVABLE; 2085 return (0); 2086} 2087 2088static int 2089ahc_aic7870_setup(struct ahc_softc *ahc) 2090{ 2091 2092 ahc->channel = 'A'; 2093 ahc->chip = AHC_AIC7870; 2094 ahc->features = AHC_AIC7870_FE; 2095 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2096 ahc->instruction_ram_size = 512; 2097 return (0); 2098} 2099 2100static int 2101ahc_aic7870h_setup(struct ahc_softc *ahc) 2102{ 2103 int error = ahc_aic7870_setup(ahc); 2104 2105 ahc->features |= AHC_HVD; 2106 2107 return error; 2108} 2109 2110static int 2111ahc_aha394X_setup(struct ahc_softc *ahc) 2112{ 2113 int error; 2114 2115 error = ahc_aic7870_setup(ahc); 2116 if (error == 0) 2117 error = ahc_aha394XX_setup(ahc); 2118 return (error); 2119} 2120 2121static int 2122ahc_aha394Xh_setup(struct ahc_softc *ahc) 2123{ 2124 int error = ahc_aha394X_setup(ahc); 2125 2126 ahc->features |= AHC_HVD; 2127 2128 return error; 2129} 2130 2131static int 2132ahc_aha398X_setup(struct ahc_softc *ahc) 2133{ 2134 int error; 2135 2136 error = ahc_aic7870_setup(ahc); 2137 if (error == 0) 2138 error = ahc_aha398XX_setup(ahc); 2139 return (error); 2140} 2141 2142static int 2143ahc_aha494X_setup(struct ahc_softc *ahc) 2144{ 2145 int error; 2146 2147 error = ahc_aic7870_setup(ahc); 2148 if (error == 0) 2149 error = ahc_aha494XX_setup(ahc); 2150 return (error); 2151} 2152 2153static int 2154ahc_aha494Xh_setup(struct ahc_softc *ahc) 2155{ 2156 int error = ahc_aha494X_setup(ahc); 2157 2158 ahc->features |= AHC_HVD; 2159 2160 return error; 2161} 2162 2163static int 2164ahc_aic7880_setup(struct ahc_softc *ahc) 2165{ 2166 ahc_dev_softc_t pci; 2167 uint8_t rev; 2168 2169 pci = ahc->dev_softc; 2170 ahc->channel = 'A'; 2171 ahc->chip = AHC_AIC7880; 2172 ahc->features = AHC_AIC7880_FE; 2173 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2174 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2175 if (rev >= 1) { 2176 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2177 } else { 2178 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2179 } 2180 ahc->instruction_ram_size = 512; 2181 return (0); 2182} 2183 2184static int 2185ahc_aic7880h_setup(struct ahc_softc *ahc) 2186{ 2187 int error = ahc_aic7880_setup(ahc); 2188 2189 ahc->features |= AHC_HVD; 2190 2191 return error; 2192} 2193 2194 2195static int 2196ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2197{ 2198 2199 ahc->flags |= AHC_INT50_SPEEDFLEX; 2200 return (ahc_aic7880_setup(ahc)); 2201} 2202 2203static int 2204ahc_aha394XU_setup(struct ahc_softc *ahc) 2205{ 2206 int error; 2207 2208 error = ahc_aic7880_setup(ahc); 2209 if (error == 0) 2210 error = ahc_aha394XX_setup(ahc); 2211 return (error); 2212} 2213 2214static int 2215ahc_aha394XUh_setup(struct ahc_softc *ahc) 2216{ 2217 int error = ahc_aha394XU_setup(ahc); 2218 2219 ahc->features |= AHC_HVD; 2220 2221 return error; 2222} 2223 2224static int 2225ahc_aha398XU_setup(struct ahc_softc *ahc) 2226{ 2227 int error; 2228 2229 error = ahc_aic7880_setup(ahc); 2230 if (error == 0) 2231 error = ahc_aha398XX_setup(ahc); 2232 return (error); 2233} 2234 2235static int 2236ahc_aic7890_setup(struct ahc_softc *ahc) 2237{ 2238 ahc_dev_softc_t pci; 2239 uint8_t rev; 2240 2241 pci = ahc->dev_softc; 2242 ahc->channel = 'A'; 2243 ahc->chip = AHC_AIC7890; 2244 ahc->features = AHC_AIC7890_FE; 2245 ahc->flags |= AHC_NEWEEPROM_FMT; 2246 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2247 if (rev == 0) 2248 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2249 ahc->instruction_ram_size = 768; 2250 return (0); 2251} 2252 2253static int 2254ahc_aic7892_setup(struct ahc_softc *ahc) 2255{ 2256 2257 ahc->channel = 'A'; 2258 ahc->chip = AHC_AIC7892; 2259 ahc->features = AHC_AIC7892_FE; 2260 ahc->flags |= AHC_NEWEEPROM_FMT; 2261 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2262 ahc->instruction_ram_size = 1024; 2263 return (0); 2264} 2265 2266static int 2267ahc_aic7895_setup(struct ahc_softc *ahc) 2268{ 2269 ahc_dev_softc_t pci; 2270 uint8_t rev; 2271 2272 pci = ahc->dev_softc; 2273 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2274 /* 2275 * The 'C' revision of the aic7895 has a few additional features. 2276 */ 2277 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2278 if (rev >= 4) { 2279 ahc->chip = AHC_AIC7895C; 2280 ahc->features = AHC_AIC7895C_FE; 2281 } else { 2282 u_int command; 2283 2284 ahc->chip = AHC_AIC7895; 2285 ahc->features = AHC_AIC7895_FE; 2286 2287 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2288 command |= PCIM_CMD_MWRICEN; 2289 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2290 ahc->bugs |= AHC_PCI_MWI_BUG; 2291 } 2292 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2293 | AHC_CACHETHEN_BUG; 2294 2295 ahc->flags |= AHC_NEWEEPROM_FMT; 2296 ahc->instruction_ram_size = 512; 2297 return (0); 2298} 2299 2300static int 2301ahc_aic7895h_setup(struct ahc_softc *ahc) 2302{ 2303 int error = ahc_aic7895_setup(ahc); 2304 2305 ahc->features |= AHC_HVD; 2306 2307 return error; 2308} 2309 2310static int 2311ahc_aic7896_setup(struct ahc_softc *ahc) 2312{ 2313 ahc_dev_softc_t pci; 2314 2315 pci = ahc->dev_softc; 2316 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2317 ahc->chip = AHC_AIC7896; 2318 ahc->features = AHC_AIC7896_FE; 2319 ahc->flags |= AHC_NEWEEPROM_FMT; 2320 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2321 ahc->instruction_ram_size = 768; 2322 return (0); 2323} 2324 2325static int 2326ahc_aic7899_setup(struct ahc_softc *ahc) 2327{ 2328 ahc_dev_softc_t pci; 2329 2330 pci = ahc->dev_softc; 2331 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2332 ahc->chip = AHC_AIC7899; 2333 ahc->features = AHC_AIC7899_FE; 2334 ahc->flags |= AHC_NEWEEPROM_FMT; 2335 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2336 ahc->instruction_ram_size = 1024; 2337 return (0); 2338} 2339 2340static int 2341ahc_aha29160C_setup(struct ahc_softc *ahc) 2342{ 2343 int error; 2344 2345 error = ahc_aic7899_setup(ahc); 2346 if (error != 0) 2347 return (error); 2348 ahc->features |= AHC_REMOVABLE; 2349 return (0); 2350} 2351 2352static int 2353ahc_raid_setup(struct ahc_softc *ahc) 2354{ 2355 printk("RAID functionality unsupported\n"); 2356 return (ENXIO); 2357} 2358 2359static int 2360ahc_aha394XX_setup(struct ahc_softc *ahc) 2361{ 2362 ahc_dev_softc_t pci; 2363 2364 pci = ahc->dev_softc; 2365 switch (ahc_get_pci_slot(pci)) { 2366 case AHC_394X_SLOT_CHANNEL_A: 2367 ahc->channel = 'A'; 2368 break; 2369 case AHC_394X_SLOT_CHANNEL_B: 2370 ahc->channel = 'B'; 2371 break; 2372 default: 2373 printk("adapter at unexpected slot %d\n" 2374 "unable to map to a channel\n", 2375 ahc_get_pci_slot(pci)); 2376 ahc->channel = 'A'; 2377 } 2378 return (0); 2379} 2380 2381static int 2382ahc_aha398XX_setup(struct ahc_softc *ahc) 2383{ 2384 ahc_dev_softc_t pci; 2385 2386 pci = ahc->dev_softc; 2387 switch (ahc_get_pci_slot(pci)) { 2388 case AHC_398X_SLOT_CHANNEL_A: 2389 ahc->channel = 'A'; 2390 break; 2391 case AHC_398X_SLOT_CHANNEL_B: 2392 ahc->channel = 'B'; 2393 break; 2394 case AHC_398X_SLOT_CHANNEL_C: 2395 ahc->channel = 'C'; 2396 break; 2397 default: 2398 printk("adapter at unexpected slot %d\n" 2399 "unable to map to a channel\n", 2400 ahc_get_pci_slot(pci)); 2401 ahc->channel = 'A'; 2402 break; 2403 } 2404 ahc->flags |= AHC_LARGE_SEEPROM; 2405 return (0); 2406} 2407 2408static int 2409ahc_aha494XX_setup(struct ahc_softc *ahc) 2410{ 2411 ahc_dev_softc_t pci; 2412 2413 pci = ahc->dev_softc; 2414 switch (ahc_get_pci_slot(pci)) { 2415 case AHC_494X_SLOT_CHANNEL_A: 2416 ahc->channel = 'A'; 2417 break; 2418 case AHC_494X_SLOT_CHANNEL_B: 2419 ahc->channel = 'B'; 2420 break; 2421 case AHC_494X_SLOT_CHANNEL_C: 2422 ahc->channel = 'C'; 2423 break; 2424 case AHC_494X_SLOT_CHANNEL_D: 2425 ahc->channel = 'D'; 2426 break; 2427 default: 2428 printk("adapter at unexpected slot %d\n" 2429 "unable to map to a channel\n", 2430 ahc_get_pci_slot(pci)); 2431 ahc->channel = 'A'; 2432 } 2433 ahc->flags |= AHC_LARGE_SEEPROM; 2434 return (0); 2435} 2436