1/* 2 * Driver for NEC VR4100 series Real Time Clock unit. 3 * 4 * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20#include <linux/err.h> 21#include <linux/fs.h> 22#include <linux/init.h> 23#include <linux/ioport.h> 24#include <linux/interrupt.h> 25#include <linux/module.h> 26#include <linux/platform_device.h> 27#include <linux/rtc.h> 28#include <linux/spinlock.h> 29#include <linux/types.h> 30#include <linux/log2.h> 31 32#include <asm/div64.h> 33#include <asm/io.h> 34#include <asm/uaccess.h> 35 36MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>"); 37MODULE_DESCRIPTION("NEC VR4100 series RTC driver"); 38MODULE_LICENSE("GPL v2"); 39 40/* RTC 1 registers */ 41#define ETIMELREG 0x00 42#define ETIMEMREG 0x02 43#define ETIMEHREG 0x04 44/* RFU */ 45#define ECMPLREG 0x08 46#define ECMPMREG 0x0a 47#define ECMPHREG 0x0c 48/* RFU */ 49#define RTCL1LREG 0x10 50#define RTCL1HREG 0x12 51#define RTCL1CNTLREG 0x14 52#define RTCL1CNTHREG 0x16 53#define RTCL2LREG 0x18 54#define RTCL2HREG 0x1a 55#define RTCL2CNTLREG 0x1c 56#define RTCL2CNTHREG 0x1e 57 58/* RTC 2 registers */ 59#define TCLKLREG 0x00 60#define TCLKHREG 0x02 61#define TCLKCNTLREG 0x04 62#define TCLKCNTHREG 0x06 63/* RFU */ 64#define RTCINTREG 0x1e 65 #define TCLOCK_INT 0x08 66 #define RTCLONG2_INT 0x04 67 #define RTCLONG1_INT 0x02 68 #define ELAPSEDTIME_INT 0x01 69 70#define RTC_FREQUENCY 32768 71#define MAX_PERIODIC_RATE 6553 72 73static void __iomem *rtc1_base; 74static void __iomem *rtc2_base; 75 76#define rtc1_read(offset) readw(rtc1_base + (offset)) 77#define rtc1_write(offset, value) writew((value), rtc1_base + (offset)) 78 79#define rtc2_read(offset) readw(rtc2_base + (offset)) 80#define rtc2_write(offset, value) writew((value), rtc2_base + (offset)) 81 82static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */ 83 84static DEFINE_SPINLOCK(rtc_lock); 85static char rtc_name[] = "RTC"; 86static unsigned long periodic_count; 87static unsigned int alarm_enabled; 88static int aie_irq; 89static int pie_irq; 90 91static inline unsigned long read_elapsed_second(void) 92{ 93 94 unsigned long first_low, first_mid, first_high; 95 96 unsigned long second_low, second_mid, second_high; 97 98 do { 99 first_low = rtc1_read(ETIMELREG); 100 first_mid = rtc1_read(ETIMEMREG); 101 first_high = rtc1_read(ETIMEHREG); 102 second_low = rtc1_read(ETIMELREG); 103 second_mid = rtc1_read(ETIMEMREG); 104 second_high = rtc1_read(ETIMEHREG); 105 } while (first_low != second_low || first_mid != second_mid || 106 first_high != second_high); 107 108 return (first_high << 17) | (first_mid << 1) | (first_low >> 15); 109} 110 111static inline void write_elapsed_second(unsigned long sec) 112{ 113 spin_lock_irq(&rtc_lock); 114 115 rtc1_write(ETIMELREG, (uint16_t)(sec << 15)); 116 rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1)); 117 rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17)); 118 119 spin_unlock_irq(&rtc_lock); 120} 121 122static void vr41xx_rtc_release(struct device *dev) 123{ 124 125 spin_lock_irq(&rtc_lock); 126 127 rtc1_write(ECMPLREG, 0); 128 rtc1_write(ECMPMREG, 0); 129 rtc1_write(ECMPHREG, 0); 130 rtc1_write(RTCL1LREG, 0); 131 rtc1_write(RTCL1HREG, 0); 132 133 spin_unlock_irq(&rtc_lock); 134 135 disable_irq(aie_irq); 136 disable_irq(pie_irq); 137} 138 139static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time) 140{ 141 unsigned long epoch_sec, elapsed_sec; 142 143 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0); 144 elapsed_sec = read_elapsed_second(); 145 146 rtc_time_to_tm(epoch_sec + elapsed_sec, time); 147 148 return 0; 149} 150 151static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time) 152{ 153 unsigned long epoch_sec, current_sec; 154 155 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0); 156 current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday, 157 time->tm_hour, time->tm_min, time->tm_sec); 158 159 write_elapsed_second(current_sec - epoch_sec); 160 161 return 0; 162} 163 164static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 165{ 166 unsigned long low, mid, high; 167 struct rtc_time *time = &wkalrm->time; 168 169 spin_lock_irq(&rtc_lock); 170 171 low = rtc1_read(ECMPLREG); 172 mid = rtc1_read(ECMPMREG); 173 high = rtc1_read(ECMPHREG); 174 wkalrm->enabled = alarm_enabled; 175 176 spin_unlock_irq(&rtc_lock); 177 178 rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time); 179 180 return 0; 181} 182 183static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 184{ 185 unsigned long alarm_sec; 186 struct rtc_time *time = &wkalrm->time; 187 188 alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday, 189 time->tm_hour, time->tm_min, time->tm_sec); 190 191 spin_lock_irq(&rtc_lock); 192 193 if (alarm_enabled) 194 disable_irq(aie_irq); 195 196 rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15)); 197 rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1)); 198 rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17)); 199 200 if (wkalrm->enabled) 201 enable_irq(aie_irq); 202 203 alarm_enabled = wkalrm->enabled; 204 205 spin_unlock_irq(&rtc_lock); 206 207 return 0; 208} 209 210static int vr41xx_rtc_irq_set_freq(struct device *dev, int freq) 211{ 212 u64 count; 213 214 if (!is_power_of_2(freq)) 215 return -EINVAL; 216 count = RTC_FREQUENCY; 217 do_div(count, freq); 218 219 spin_lock_irq(&rtc_lock); 220 221 periodic_count = count; 222 rtc1_write(RTCL1LREG, periodic_count); 223 rtc1_write(RTCL1HREG, periodic_count >> 16); 224 225 spin_unlock_irq(&rtc_lock); 226 227 return 0; 228} 229 230static int vr41xx_rtc_irq_set_state(struct device *dev, int enabled) 231{ 232 if (enabled) 233 enable_irq(pie_irq); 234 else 235 disable_irq(pie_irq); 236 237 return 0; 238} 239 240static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) 241{ 242 switch (cmd) { 243 case RTC_AIE_ON: 244 spin_lock_irq(&rtc_lock); 245 246 if (!alarm_enabled) { 247 enable_irq(aie_irq); 248 alarm_enabled = 1; 249 } 250 251 spin_unlock_irq(&rtc_lock); 252 break; 253 case RTC_AIE_OFF: 254 spin_lock_irq(&rtc_lock); 255 256 if (alarm_enabled) { 257 disable_irq(aie_irq); 258 alarm_enabled = 0; 259 } 260 261 spin_unlock_irq(&rtc_lock); 262 break; 263 case RTC_EPOCH_READ: 264 return put_user(epoch, (unsigned long __user *)arg); 265 case RTC_EPOCH_SET: 266 /* Doesn't support before 1900 */ 267 if (arg < 1900) 268 return -EINVAL; 269 epoch = arg; 270 break; 271 default: 272 return -ENOIOCTLCMD; 273 } 274 275 return 0; 276} 277 278static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id) 279{ 280 struct platform_device *pdev = (struct platform_device *)dev_id; 281 struct rtc_device *rtc = platform_get_drvdata(pdev); 282 283 rtc2_write(RTCINTREG, ELAPSEDTIME_INT); 284 285 rtc_update_irq(rtc, 1, RTC_AF); 286 287 return IRQ_HANDLED; 288} 289 290static irqreturn_t rtclong1_interrupt(int irq, void *dev_id) 291{ 292 struct platform_device *pdev = (struct platform_device *)dev_id; 293 struct rtc_device *rtc = platform_get_drvdata(pdev); 294 unsigned long count = periodic_count; 295 296 rtc2_write(RTCINTREG, RTCLONG1_INT); 297 298 rtc1_write(RTCL1LREG, count); 299 rtc1_write(RTCL1HREG, count >> 16); 300 301 rtc_update_irq(rtc, 1, RTC_PF); 302 303 return IRQ_HANDLED; 304} 305 306static const struct rtc_class_ops vr41xx_rtc_ops = { 307 .release = vr41xx_rtc_release, 308 .ioctl = vr41xx_rtc_ioctl, 309 .read_time = vr41xx_rtc_read_time, 310 .set_time = vr41xx_rtc_set_time, 311 .read_alarm = vr41xx_rtc_read_alarm, 312 .set_alarm = vr41xx_rtc_set_alarm, 313 .irq_set_freq = vr41xx_rtc_irq_set_freq, 314 .irq_set_state = vr41xx_rtc_irq_set_state, 315}; 316 317static int __devinit rtc_probe(struct platform_device *pdev) 318{ 319 struct resource *res; 320 struct rtc_device *rtc; 321 int retval; 322 323 if (pdev->num_resources != 4) 324 return -EBUSY; 325 326 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 327 if (!res) 328 return -EBUSY; 329 330 rtc1_base = ioremap(res->start, resource_size(res)); 331 if (!rtc1_base) 332 return -EBUSY; 333 334 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 335 if (!res) { 336 retval = -EBUSY; 337 goto err_rtc1_iounmap; 338 } 339 340 rtc2_base = ioremap(res->start, resource_size(res)); 341 if (!rtc2_base) { 342 retval = -EBUSY; 343 goto err_rtc1_iounmap; 344 } 345 346 rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE); 347 if (IS_ERR(rtc)) { 348 retval = PTR_ERR(rtc); 349 goto err_iounmap_all; 350 } 351 352 rtc->max_user_freq = MAX_PERIODIC_RATE; 353 354 spin_lock_irq(&rtc_lock); 355 356 rtc1_write(ECMPLREG, 0); 357 rtc1_write(ECMPMREG, 0); 358 rtc1_write(ECMPHREG, 0); 359 rtc1_write(RTCL1LREG, 0); 360 rtc1_write(RTCL1HREG, 0); 361 362 spin_unlock_irq(&rtc_lock); 363 364 aie_irq = platform_get_irq(pdev, 0); 365 if (aie_irq <= 0) { 366 retval = -EBUSY; 367 goto err_device_unregister; 368 } 369 370 retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED, 371 "elapsed_time", pdev); 372 if (retval < 0) 373 goto err_device_unregister; 374 375 pie_irq = platform_get_irq(pdev, 1); 376 if (pie_irq <= 0) 377 goto err_free_irq; 378 379 retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED, 380 "rtclong1", pdev); 381 if (retval < 0) 382 goto err_free_irq; 383 384 platform_set_drvdata(pdev, rtc); 385 386 disable_irq(aie_irq); 387 disable_irq(pie_irq); 388 389 printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n"); 390 391 return 0; 392 393err_free_irq: 394 free_irq(aie_irq, pdev); 395 396err_device_unregister: 397 rtc_device_unregister(rtc); 398 399err_iounmap_all: 400 iounmap(rtc2_base); 401 rtc2_base = NULL; 402 403err_rtc1_iounmap: 404 iounmap(rtc1_base); 405 rtc1_base = NULL; 406 407 return retval; 408} 409 410static int __devexit rtc_remove(struct platform_device *pdev) 411{ 412 struct rtc_device *rtc; 413 414 rtc = platform_get_drvdata(pdev); 415 if (rtc) 416 rtc_device_unregister(rtc); 417 418 platform_set_drvdata(pdev, NULL); 419 420 free_irq(aie_irq, pdev); 421 free_irq(pie_irq, pdev); 422 if (rtc1_base) 423 iounmap(rtc1_base); 424 if (rtc2_base) 425 iounmap(rtc2_base); 426 427 return 0; 428} 429 430/* work with hotplug and coldplug */ 431MODULE_ALIAS("platform:RTC"); 432 433static struct platform_driver rtc_platform_driver = { 434 .probe = rtc_probe, 435 .remove = __devexit_p(rtc_remove), 436 .driver = { 437 .name = rtc_name, 438 .owner = THIS_MODULE, 439 }, 440}; 441 442static int __init vr41xx_rtc_init(void) 443{ 444 return platform_driver_register(&rtc_platform_driver); 445} 446 447static void __exit vr41xx_rtc_exit(void) 448{ 449 platform_driver_unregister(&rtc_platform_driver); 450} 451 452module_init(vr41xx_rtc_init); 453module_exit(vr41xx_rtc_exit); 454