1/* 2 * drivers/pcmcia/m32r_cfc.c 3 * 4 * Device driver for the CFC functionality of M32R. 5 * 6 * Copyright (c) 2001, 2002, 2003, 2004 7 * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara 8 */ 9 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/init.h> 13#include <linux/types.h> 14#include <linux/fcntl.h> 15#include <linux/string.h> 16#include <linux/kernel.h> 17#include <linux/errno.h> 18#include <linux/timer.h> 19#include <linux/ioport.h> 20#include <linux/delay.h> 21#include <linux/workqueue.h> 22#include <linux/interrupt.h> 23#include <linux/platform_device.h> 24#include <linux/bitops.h> 25#include <asm/irq.h> 26#include <asm/io.h> 27#include <asm/system.h> 28 29#include <pcmcia/ss.h> 30#include <pcmcia/cs.h> 31 32#undef MAX_IO_WIN 33#define MAX_IO_WIN 1 34#undef MAX_WIN 35#define MAX_WIN 1 36 37#include "m32r_cfc.h" 38 39/* Poll status interval -- 0 means default to interrupt */ 40static int poll_interval = 0; 41 42typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t; 43 44typedef struct pcc_socket { 45 u_short type, flags; 46 struct pcmcia_socket socket; 47 unsigned int number; 48 unsigned int ioaddr; 49 u_long mapaddr; 50 u_long base; /* PCC register base */ 51 u_char cs_irq1, cs_irq2, intr; 52 pccard_io_map io_map[MAX_IO_WIN]; 53 pccard_mem_map mem_map[MAX_WIN]; 54 u_char io_win; 55 u_char mem_win; 56 pcc_as_t current_space; 57 u_char last_iodbex; 58#ifdef CONFIG_PROC_FS 59 struct proc_dir_entry *proc; 60#endif 61} pcc_socket_t; 62 63static int pcc_sockets = 0; 64static pcc_socket_t socket[M32R_MAX_PCC] = { 65 { 0, }, /* ... */ 66}; 67 68/*====================================================================*/ 69 70static unsigned int pcc_get(u_short, unsigned int); 71static void pcc_set(u_short, unsigned int , unsigned int ); 72 73static DEFINE_SPINLOCK(pcc_lock); 74 75#if !defined(CONFIG_PLAT_USRV) 76static inline u_long pcc_port2addr(unsigned long port, int size) { 77 u_long addr = 0; 78 u_long odd; 79 80 if (size == 1) { /* byte access */ 81 odd = (port&1) << 11; 82 port -= port & 1; 83 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port; 84 } else if (size == 2) 85 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port; 86 87 return addr; 88} 89#else /* CONFIG_PLAT_USRV */ 90static inline u_long pcc_port2addr(unsigned long port, int size) { 91 u_long odd; 92 u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8; 93 94 if (size == 1) { /* byte access */ 95 odd = port & 1; 96 port -= odd; 97 odd <<= 11; 98 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff); 99 } else if (size == 2) /* word access */ 100 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff); 101 102 return addr; 103} 104#endif /* CONFIG_PLAT_USRV */ 105 106void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size, 107 size_t nmemb, int flag) 108{ 109 u_long addr; 110 unsigned char *bp = (unsigned char *)buf; 111 unsigned long flags; 112 113 pr_debug("m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, " 114 "size=%u, nmemb=%d, flag=%d\n", 115 sock, port, buf, size, nmemb, flag); 116 117 addr = pcc_port2addr(port, 1); 118 if (!addr) { 119 printk("m32r_cfc:ioread_byte null port :%#lx\n",port); 120 return; 121 } 122 pr_debug("m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr); 123 124 spin_lock_irqsave(&pcc_lock, flags); 125 /* read Byte */ 126 while (nmemb--) 127 *bp++ = readb(addr); 128 spin_unlock_irqrestore(&pcc_lock, flags); 129} 130 131void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size, 132 size_t nmemb, int flag) 133{ 134 u_long addr; 135 unsigned short *bp = (unsigned short *)buf; 136 unsigned long flags; 137 138 pr_debug("m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, " 139 "buf=%p, size=%u, nmemb=%d, flag=%d\n", 140 sock, port, buf, size, nmemb, flag); 141 142 if (size != 2) 143 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size, 144 port); 145 if (size == 9) 146 printk("m32r_cfc: ioread_word :insw \n"); 147 148 addr = pcc_port2addr(port, 2); 149 if (!addr) { 150 printk("m32r_cfc:ioread_word null port :%#lx\n",port); 151 return; 152 } 153 pr_debug("m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr); 154 155 spin_lock_irqsave(&pcc_lock, flags); 156 /* read Word */ 157 while (nmemb--) 158 *bp++ = readw(addr); 159 spin_unlock_irqrestore(&pcc_lock, flags); 160} 161 162void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size, 163 size_t nmemb, int flag) 164{ 165 u_long addr; 166 unsigned char *bp = (unsigned char *)buf; 167 unsigned long flags; 168 169 pr_debug("m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, " 170 "buf=%p, size=%u, nmemb=%d, flag=%d\n", 171 sock, port, buf, size, nmemb, flag); 172 173 /* write Byte */ 174 addr = pcc_port2addr(port, 1); 175 if (!addr) { 176 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port); 177 return; 178 } 179 pr_debug("m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr); 180 181 spin_lock_irqsave(&pcc_lock, flags); 182 while (nmemb--) 183 writeb(*bp++, addr); 184 spin_unlock_irqrestore(&pcc_lock, flags); 185} 186 187void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size, 188 size_t nmemb, int flag) 189{ 190 u_long addr; 191 unsigned short *bp = (unsigned short *)buf; 192 unsigned long flags; 193 194 pr_debug("m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, " 195 "buf=%p, size=%u, nmemb=%d, flag=%d\n", 196 sock, port, buf, size, nmemb, flag); 197 198 if(size != 2) 199 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n", 200 size, port); 201 if(size == 9) 202 printk("m32r_cfc: iowrite_word :outsw \n"); 203 204 addr = pcc_port2addr(port, 2); 205 if (!addr) { 206 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port); 207 return; 208 } 209 if (addr & 1) { 210 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port, 211 addr); 212 return; 213 } 214 pr_debug("m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr); 215 216 spin_lock_irqsave(&pcc_lock, flags); 217 while (nmemb--) 218 writew(*bp++, addr); 219 spin_unlock_irqrestore(&pcc_lock, flags); 220} 221 222/*====================================================================*/ 223 224#define IS_REGISTERED 0x2000 225#define IS_ALIVE 0x8000 226 227typedef struct pcc_t { 228 char *name; 229 u_short flags; 230} pcc_t; 231 232static pcc_t pcc[] = { 233#if !defined(CONFIG_PLAT_USRV) 234 { "m32r_cfc", 0 }, { "", 0 }, 235#else /* CONFIG_PLAT_USRV */ 236 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, 237 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 }, 238#endif /* CONFIG_PLAT_USRV */ 239}; 240 241static irqreturn_t pcc_interrupt(int, void *); 242 243/*====================================================================*/ 244 245static struct timer_list poll_timer; 246 247static unsigned int pcc_get(u_short sock, unsigned int reg) 248{ 249 unsigned int val = inw(reg); 250 pr_debug("m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val); 251 return val; 252} 253 254 255static void pcc_set(u_short sock, unsigned int reg, unsigned int data) 256{ 257 outw(data, reg); 258 pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data); 259} 260 261/*====================================================================== 262 263 See if a card is present, powered up, in IO mode, and already 264 bound to a (non PC Card) Linux driver. We leave these alone. 265 266 We make an exception for cards that seem to be serial devices. 267 268======================================================================*/ 269 270static int __init is_alive(u_short sock) 271{ 272 unsigned int stat; 273 274 pr_debug("m32r_cfc: is_alive:\n"); 275 276 printk("CF: "); 277 stat = pcc_get(sock, (unsigned int)PLD_CFSTS); 278 if (!stat) 279 printk("No "); 280 printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat); 281 pr_debug("m32r_cfc: is_alive: sock stat is 0x%04x\n", stat); 282 283 return 0; 284} 285 286static void add_pcc_socket(ulong base, int irq, ulong mapaddr, 287 unsigned int ioaddr) 288{ 289 pcc_socket_t *t = &socket[pcc_sockets]; 290 291 pr_debug("m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, " 292 "mapaddr=%#lx, ioaddr=%08x\n", 293 base, irq, mapaddr, ioaddr); 294 295 /* add sockets */ 296 t->ioaddr = ioaddr; 297 t->mapaddr = mapaddr; 298#if !defined(CONFIG_PLAT_USRV) 299 t->base = 0; 300 t->flags = 0; 301 t->cs_irq1 = irq; // insert irq 302 t->cs_irq2 = irq + 1; // eject irq 303#else /* CONFIG_PLAT_USRV */ 304 t->base = base; 305 t->flags = 0; 306 t->cs_irq1 = 0; // insert irq 307 t->cs_irq2 = 0; // eject irq 308#endif /* CONFIG_PLAT_USRV */ 309 310 if (is_alive(pcc_sockets)) 311 t->flags |= IS_ALIVE; 312 313 /* add pcc */ 314#if !defined(CONFIG_PLAT_USRV) 315 request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc"); 316#else /* CONFIG_PLAT_USRV */ 317 { 318 unsigned int reg_base; 319 320 reg_base = (unsigned int)PLD_CFRSTCR; 321 reg_base |= pcc_sockets << 8; 322 request_region(reg_base, 0x20, "m32r_cfc"); 323 } 324#endif /* CONFIG_PLAT_USRV */ 325 printk(KERN_INFO " %s ", pcc[pcc_sockets].name); 326 printk("pcc at 0x%08lx\n", t->base); 327 328 /* Update socket interrupt information, capabilities */ 329 t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP); 330 t->socket.map_size = M32R_PCC_MAPSIZE; 331 t->socket.io_offset = ioaddr; /* use for io access offset */ 332 t->socket.irq_mask = 0; 333#if !defined(CONFIG_PLAT_USRV) 334 t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */ 335#else /* CONFIG_PLAT_USRV */ 336 t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets; 337#endif /* CONFIG_PLAT_USRV */ 338 339#ifndef CONFIG_PLAT_USRV 340 /* insert interrupt */ 341 request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt); 342#ifndef CONFIG_PLAT_MAPPI3 343 /* eject interrupt */ 344 request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt); 345#endif 346 pr_debug("m32r_cfc: enable CFMSK, RDYSEL\n"); 347 pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01); 348#endif /* CONFIG_PLAT_USRV */ 349#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || \ 350 defined(CONFIG_PLAT_OPSPUT) 351 pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200); 352#endif 353 pcc_sockets++; 354 355 return; 356} 357 358 359/*====================================================================*/ 360 361static irqreturn_t pcc_interrupt(int irq, void *dev) 362{ 363 int i; 364 u_int events = 0; 365 int handled = 0; 366 367 pr_debug("m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev); 368 for (i = 0; i < pcc_sockets; i++) { 369 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq) 370 continue; 371 372 handled = 1; 373 pr_debug("m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ", 374 i, irq); 375 events |= SS_DETECT; /* insert or eject */ 376 if (events) 377 pcmcia_parse_events(&socket[i].socket, events); 378 } 379 pr_debug("m32r_cfc: pcc_interrupt: done\n"); 380 381 return IRQ_RETVAL(handled); 382} /* pcc_interrupt */ 383 384static void pcc_interrupt_wrapper(u_long data) 385{ 386 pr_debug("m32r_cfc: pcc_interrupt_wrapper:\n"); 387 pcc_interrupt(0, NULL); 388 init_timer(&poll_timer); 389 poll_timer.expires = jiffies + poll_interval; 390 add_timer(&poll_timer); 391} 392 393/*====================================================================*/ 394 395static int _pcc_get_status(u_short sock, u_int *value) 396{ 397 u_int status; 398 399 pr_debug("m32r_cfc: _pcc_get_status:\n"); 400 status = pcc_get(sock, (unsigned int)PLD_CFSTS); 401 *value = (status) ? SS_DETECT : 0; 402 pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status); 403 404#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || \ 405 defined(CONFIG_PLAT_OPSPUT) 406 if ( status ) { 407 /* enable CF power */ 408 status = inw((unsigned int)PLD_CPCR); 409 if (!(status & PLD_CPCR_CF)) { 410 pr_debug("m32r_cfc: _pcc_get_status: " 411 "power on (CPCR=0x%08x)\n", status); 412 status |= PLD_CPCR_CF; 413 outw(status, (unsigned int)PLD_CPCR); 414 udelay(100); 415 } 416 *value |= SS_POWERON; 417 418 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */ 419 udelay(100); 420 421 *value |= SS_READY; /* always ready */ 422 *value |= SS_3VCARD; 423 } else { 424 /* disable CF power */ 425 status = inw((unsigned int)PLD_CPCR); 426 status &= ~PLD_CPCR_CF; 427 outw(status, (unsigned int)PLD_CPCR); 428 udelay(100); 429 pr_debug("m32r_cfc: _pcc_get_status: " 430 "power off (CPCR=0x%08x)\n", status); 431 } 432#elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) 433 if ( status ) { 434 status = pcc_get(sock, (unsigned int)PLD_CPCR); 435 if (status == 0) { /* power off */ 436 pcc_set(sock, (unsigned int)PLD_CPCR, 1); 437 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */ 438 udelay(50); 439 } 440 *value |= SS_POWERON; 441 442 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); 443 udelay(50); 444 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101); 445 udelay(25); /* for IDE reset */ 446 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100); 447 mdelay(2); /* for IDE reset */ 448 449 *value |= SS_READY; 450 *value |= SS_3VCARD; 451 } else { 452 /* disable CF power */ 453 pcc_set(sock, (unsigned int)PLD_CPCR, 0); 454 udelay(100); 455 pr_debug("m32r_cfc: _pcc_get_status: " 456 "power off (CPCR=0x%08x)\n", status); 457 } 458#else 459#error no platform configuration 460#endif 461 pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n", 462 sock, *value); 463 return 0; 464} /* _get_status */ 465 466/*====================================================================*/ 467 468static int _pcc_set_socket(u_short sock, socket_state_t *state) 469{ 470 pr_debug("m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " 471 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags, 472 state->Vcc, state->Vpp, state->io_irq, state->csc_mask); 473 474#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || \ 475 defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || \ 476 defined(CONFIG_PLAT_MAPPI3) 477 if (state->Vcc) { 478 if ((state->Vcc != 50) && (state->Vcc != 33)) 479 return -EINVAL; 480 /* accept 5V and 3.3V */ 481 } 482#endif 483 if (state->flags & SS_RESET) { 484 pr_debug(":RESET\n"); 485 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101); 486 }else{ 487 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100); 488 } 489 if (state->flags & SS_OUTPUT_ENA){ 490 pr_debug(":OUTPUT_ENA\n"); 491 /* bit clear */ 492 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0); 493 } else { 494 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1); 495 } 496 497 if(state->flags & SS_IOCARD){ 498 pr_debug(":IOCARD"); 499 } 500 if (state->flags & SS_PWR_AUTO) { 501 pr_debug(":PWR_AUTO"); 502 } 503 if (state->csc_mask & SS_DETECT) 504 pr_debug(":csc-SS_DETECT"); 505 if (state->flags & SS_IOCARD) { 506 if (state->csc_mask & SS_STSCHG) 507 pr_debug(":STSCHG"); 508 } else { 509 if (state->csc_mask & SS_BATDEAD) 510 pr_debug(":BATDEAD"); 511 if (state->csc_mask & SS_BATWARN) 512 pr_debug(":BATWARN"); 513 if (state->csc_mask & SS_READY) 514 pr_debug(":READY"); 515 } 516 pr_debug("\n"); 517 return 0; 518} /* _set_socket */ 519 520/*====================================================================*/ 521 522static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io) 523{ 524 u_char map; 525 526 pr_debug("m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, " 527 "%#llx-%#llx)\n", sock, io->map, io->flags, 528 io->speed, (unsigned long long)io->start, 529 (unsigned long long)io->stop); 530 map = io->map; 531 532 return 0; 533} /* _set_io_map */ 534 535/*====================================================================*/ 536 537static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem) 538{ 539 540 u_char map = mem->map; 541 u_long addr; 542 pcc_socket_t *t = &socket[sock]; 543 544 pr_debug("m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, " 545 "%#llx, %#x)\n", sock, map, mem->flags, 546 mem->speed, (unsigned long long)mem->static_start, 547 mem->card_start); 548 549 /* 550 * sanity check 551 */ 552 if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){ 553 return -EINVAL; 554 } 555 556 /* 557 * de-activate 558 */ 559 if ((mem->flags & MAP_ACTIVE) == 0) { 560 t->current_space = as_none; 561 return 0; 562 } 563 564 /* 565 * Set mode 566 */ 567 if (mem->flags & MAP_ATTRIB) { 568 t->current_space = as_attr; 569 } else { 570 t->current_space = as_comm; 571 } 572 573 /* 574 * Set address 575 */ 576 addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK); 577 mem->static_start = addr + mem->card_start; 578 579 return 0; 580 581} /* _set_mem_map */ 582 583 584/*====================================================================*/ 585 586/* this is horribly ugly... proper locking needs to be done here at 587 * some time... */ 588#define LOCKED(x) do { \ 589 int retval; \ 590 unsigned long flags; \ 591 spin_lock_irqsave(&pcc_lock, flags); \ 592 retval = x; \ 593 spin_unlock_irqrestore(&pcc_lock, flags); \ 594 return retval; \ 595} while (0) 596 597 598static int pcc_get_status(struct pcmcia_socket *s, u_int *value) 599{ 600 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 601 602 if (socket[sock].flags & IS_ALIVE) { 603 dev_dbg(&s->dev, "pcc_get_status: sock(%d) -EINVAL\n", sock); 604 *value = 0; 605 return -EINVAL; 606 } 607 dev_dbg(&s->dev, "pcc_get_status: sock(%d)\n", sock); 608 LOCKED(_pcc_get_status(sock, value)); 609} 610 611static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state) 612{ 613 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 614 615 if (socket[sock].flags & IS_ALIVE) { 616 dev_dbg(&s->dev, "pcc_set_socket: sock(%d) -EINVAL\n", sock); 617 return -EINVAL; 618 } 619 dev_dbg(&s->dev, "pcc_set_socket: sock(%d)\n", sock); 620 LOCKED(_pcc_set_socket(sock, state)); 621} 622 623static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) 624{ 625 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 626 627 if (socket[sock].flags & IS_ALIVE) { 628 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d) -EINVAL\n", sock); 629 return -EINVAL; 630 } 631 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d)\n", sock); 632 LOCKED(_pcc_set_io_map(sock, io)); 633} 634 635static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem) 636{ 637 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 638 639 if (socket[sock].flags & IS_ALIVE) { 640 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d) -EINVAL\n", sock); 641 return -EINVAL; 642 } 643 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d)\n", sock); 644 LOCKED(_pcc_set_mem_map(sock, mem)); 645} 646 647static int pcc_init(struct pcmcia_socket *s) 648{ 649 dev_dbg(&s->dev, "pcc_init()\n"); 650 return 0; 651} 652 653static struct pccard_operations pcc_operations = { 654 .init = pcc_init, 655 .get_status = pcc_get_status, 656 .set_socket = pcc_set_socket, 657 .set_io_map = pcc_set_io_map, 658 .set_mem_map = pcc_set_mem_map, 659}; 660 661 662/*====================================================================*/ 663 664static struct platform_driver pcc_driver = { 665 .driver = { 666 .name = "cfc", 667 .owner = THIS_MODULE, 668 }, 669}; 670 671static struct platform_device pcc_device = { 672 .name = "cfc", 673 .id = 0, 674}; 675 676/*====================================================================*/ 677 678static int __init init_m32r_pcc(void) 679{ 680 int i, ret; 681 682 ret = platform_driver_register(&pcc_driver); 683 if (ret) 684 return ret; 685 686 ret = platform_device_register(&pcc_device); 687 if (ret){ 688 platform_driver_unregister(&pcc_driver); 689 return ret; 690 } 691 692#if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) 693 pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f); 694 pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200); 695#endif 696 697 pcc_sockets = 0; 698 699#if !defined(CONFIG_PLAT_USRV) 700 add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE, 701 CFC_IOPORT_BASE); 702#else /* CONFIG_PLAT_USRV */ 703 { 704 ulong base, mapaddr; 705 unsigned int ioaddr; 706 707 for (i = 0 ; i < M32R_MAX_PCC ; i++) { 708 base = (ulong)PLD_CFRSTCR; 709 base = base | (i << 8); 710 ioaddr = (i + 1) << 12; 711 mapaddr = CFC_ATTR_MAPBASE | (i << 20); 712 add_pcc_socket(base, 0, mapaddr, ioaddr); 713 } 714 } 715#endif /* CONFIG_PLAT_USRV */ 716 717 if (pcc_sockets == 0) { 718 printk("socket is not found.\n"); 719 platform_device_unregister(&pcc_device); 720 platform_driver_unregister(&pcc_driver); 721 return -ENODEV; 722 } 723 724 /* Set up interrupt handler(s) */ 725 726 for (i = 0 ; i < pcc_sockets ; i++) { 727 socket[i].socket.dev.parent = &pcc_device.dev; 728 socket[i].socket.ops = &pcc_operations; 729 socket[i].socket.resource_ops = &pccard_static_ops; 730 socket[i].socket.owner = THIS_MODULE; 731 socket[i].number = i; 732 ret = pcmcia_register_socket(&socket[i].socket); 733 if (!ret) 734 socket[i].flags |= IS_REGISTERED; 735 736 } 737 738 /* Finally, schedule a polling interrupt */ 739 if (poll_interval != 0) { 740 poll_timer.function = pcc_interrupt_wrapper; 741 poll_timer.data = 0; 742 init_timer(&poll_timer); 743 poll_timer.expires = jiffies + poll_interval; 744 add_timer(&poll_timer); 745 } 746 747 return 0; 748} /* init_m32r_pcc */ 749 750static void __exit exit_m32r_pcc(void) 751{ 752 int i; 753 754 for (i = 0; i < pcc_sockets; i++) 755 if (socket[i].flags & IS_REGISTERED) 756 pcmcia_unregister_socket(&socket[i].socket); 757 758 platform_device_unregister(&pcc_device); 759 if (poll_interval != 0) 760 del_timer_sync(&poll_timer); 761 762 platform_driver_unregister(&pcc_driver); 763} /* exit_m32r_pcc */ 764 765module_init(init_m32r_pcc); 766module_exit(exit_m32r_pcc); 767MODULE_LICENSE("Dual MPL/GPL"); 768/*====================================================================*/ 769