1/* 2 * This file is part of wl1271 3 * 4 * Copyright (C) 2008-2010 Nokia Corporation 5 * 6 * Contact: Luciano Coelho <luciano.coelho@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 */ 23 24#include <linux/gpio.h> 25#include <linux/slab.h> 26 27#include "wl1271_acx.h" 28#include "wl1271_reg.h" 29#include "wl1271_boot.h" 30#include "wl1271_io.h" 31#include "wl1271_event.h" 32 33static struct wl1271_partition_set part_table[PART_TABLE_LEN] = { 34 [PART_DOWN] = { 35 .mem = { 36 .start = 0x00000000, 37 .size = 0x000177c0 38 }, 39 .reg = { 40 .start = REGISTERS_BASE, 41 .size = 0x00008800 42 }, 43 .mem2 = { 44 .start = 0x00000000, 45 .size = 0x00000000 46 }, 47 .mem3 = { 48 .start = 0x00000000, 49 .size = 0x00000000 50 }, 51 }, 52 53 [PART_WORK] = { 54 .mem = { 55 .start = 0x00040000, 56 .size = 0x00014fc0 57 }, 58 .reg = { 59 .start = REGISTERS_BASE, 60 .size = 0x0000a000 61 }, 62 .mem2 = { 63 .start = 0x003004f8, 64 .size = 0x00000004 65 }, 66 .mem3 = { 67 .start = 0x00040404, 68 .size = 0x00000000 69 }, 70 }, 71 72 [PART_DRPW] = { 73 .mem = { 74 .start = 0x00040000, 75 .size = 0x00014fc0 76 }, 77 .reg = { 78 .start = DRPW_BASE, 79 .size = 0x00006000 80 }, 81 .mem2 = { 82 .start = 0x00000000, 83 .size = 0x00000000 84 }, 85 .mem3 = { 86 .start = 0x00000000, 87 .size = 0x00000000 88 } 89 } 90}; 91 92static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag) 93{ 94 u32 cpu_ctrl; 95 96 /* 10.5.0 run the firmware (I) */ 97 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL); 98 99 /* 10.5.1 run the firmware (II) */ 100 cpu_ctrl |= flag; 101 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); 102} 103 104static void wl1271_boot_fw_version(struct wl1271 *wl) 105{ 106 struct wl1271_static_data static_data; 107 108 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data), 109 false); 110 111 strncpy(wl->chip.fw_ver, static_data.fw_version, 112 sizeof(wl->chip.fw_ver)); 113 114 /* make sure the string is NULL-terminated */ 115 wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0'; 116} 117 118static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf, 119 size_t fw_data_len, u32 dest) 120{ 121 struct wl1271_partition_set partition; 122 int addr, chunk_num, partition_limit; 123 u8 *p, *chunk; 124 125 /* whal_FwCtrl_LoadFwImageSm() */ 126 127 wl1271_debug(DEBUG_BOOT, "starting firmware upload"); 128 129 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d", 130 fw_data_len, CHUNK_SIZE); 131 132 if ((fw_data_len % 4) != 0) { 133 wl1271_error("firmware length not multiple of four"); 134 return -EIO; 135 } 136 137 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL); 138 if (!chunk) { 139 wl1271_error("allocation for firmware upload chunk failed"); 140 return -ENOMEM; 141 } 142 143 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition)); 144 partition.mem.start = dest; 145 wl1271_set_partition(wl, &partition); 146 147 /* 10.1 set partition limit and chunk num */ 148 chunk_num = 0; 149 partition_limit = part_table[PART_DOWN].mem.size; 150 151 while (chunk_num < fw_data_len / CHUNK_SIZE) { 152 /* 10.2 update partition, if needed */ 153 addr = dest + (chunk_num + 2) * CHUNK_SIZE; 154 if (addr > partition_limit) { 155 addr = dest + chunk_num * CHUNK_SIZE; 156 partition_limit = chunk_num * CHUNK_SIZE + 157 part_table[PART_DOWN].mem.size; 158 partition.mem.start = addr; 159 wl1271_set_partition(wl, &partition); 160 } 161 162 /* 10.3 upload the chunk */ 163 addr = dest + chunk_num * CHUNK_SIZE; 164 p = buf + chunk_num * CHUNK_SIZE; 165 memcpy(chunk, p, CHUNK_SIZE); 166 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", 167 p, addr); 168 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false); 169 170 chunk_num++; 171 } 172 173 /* 10.4 upload the last chunk */ 174 addr = dest + chunk_num * CHUNK_SIZE; 175 p = buf + chunk_num * CHUNK_SIZE; 176 memcpy(chunk, p, fw_data_len % CHUNK_SIZE); 177 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x", 178 fw_data_len % CHUNK_SIZE, p, addr); 179 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false); 180 181 kfree(chunk); 182 return 0; 183} 184 185static int wl1271_boot_upload_firmware(struct wl1271 *wl) 186{ 187 u32 chunks, addr, len; 188 int ret = 0; 189 u8 *fw; 190 191 fw = wl->fw; 192 chunks = be32_to_cpup((__be32 *) fw); 193 fw += sizeof(u32); 194 195 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks); 196 197 while (chunks--) { 198 addr = be32_to_cpup((__be32 *) fw); 199 fw += sizeof(u32); 200 len = be32_to_cpup((__be32 *) fw); 201 fw += sizeof(u32); 202 203 if (len > 300000) { 204 wl1271_info("firmware chunk too long: %u", len); 205 return -EINVAL; 206 } 207 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u", 208 chunks, addr, len); 209 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr); 210 if (ret != 0) 211 break; 212 fw += len; 213 } 214 215 return ret; 216} 217 218static int wl1271_boot_upload_nvs(struct wl1271 *wl) 219{ 220 size_t nvs_len, burst_len; 221 int i; 222 u32 dest_addr, val; 223 u8 *nvs_ptr, *nvs_aligned; 224 225 if (wl->nvs == NULL) 226 return -ENODEV; 227 228 /* only the first part of the NVS needs to be uploaded */ 229 nvs_len = sizeof(wl->nvs->nvs); 230 nvs_ptr = (u8 *)wl->nvs->nvs; 231 232 /* update current MAC address to NVS */ 233 nvs_ptr[11] = wl->mac_addr[0]; 234 nvs_ptr[10] = wl->mac_addr[1]; 235 nvs_ptr[6] = wl->mac_addr[2]; 236 nvs_ptr[5] = wl->mac_addr[3]; 237 nvs_ptr[4] = wl->mac_addr[4]; 238 nvs_ptr[3] = wl->mac_addr[5]; 239 240 /* 241 * Layout before the actual NVS tables: 242 * 1 byte : burst length. 243 * 2 bytes: destination address. 244 * n bytes: data to burst copy. 245 * 246 * This is ended by a 0 length, then the NVS tables. 247 */ 248 249 while (nvs_ptr[0]) { 250 burst_len = nvs_ptr[0]; 251 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8)); 252 253 dest_addr += REGISTERS_BASE; 254 255 /* We move our pointer to the data */ 256 nvs_ptr += 3; 257 258 for (i = 0; i < burst_len; i++) { 259 val = (nvs_ptr[0] | (nvs_ptr[1] << 8) 260 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); 261 262 wl1271_debug(DEBUG_BOOT, 263 "nvs burst write 0x%x: 0x%x", 264 dest_addr, val); 265 wl1271_write32(wl, dest_addr, val); 266 267 nvs_ptr += 4; 268 dest_addr += 4; 269 } 270 } 271 272 /* 273 * We've reached the first zero length, the first NVS table 274 * is 7 bytes further. 275 */ 276 nvs_ptr += 7; 277 nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs; 278 nvs_len = ALIGN(nvs_len, 4); 279 280 /* Now we must set the partition correctly */ 281 wl1271_set_partition(wl, &part_table[PART_WORK]); 282 283 /* Copy the NVS tables to a new block to ensure alignment */ 284 nvs_ptr += 3; 285 286 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); if 287 (!nvs_aligned) return -ENOMEM; 288 289 /* And finally we upload the NVS tables */ 290 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false); 291 292 kfree(nvs_aligned); 293 return 0; 294} 295 296static void wl1271_boot_enable_interrupts(struct wl1271 *wl) 297{ 298 wl1271_enable_interrupts(wl); 299 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, 300 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); 301 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL); 302} 303 304static int wl1271_boot_soft_reset(struct wl1271 *wl) 305{ 306 unsigned long timeout; 307 u32 boot_data; 308 309 /* perform soft reset */ 310 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); 311 312 /* SOFT_RESET is self clearing */ 313 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); 314 while (1) { 315 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET); 316 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); 317 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) 318 break; 319 320 if (time_after(jiffies, timeout)) { 321 /* 1.2 check pWhalBus->uSelfClearTime if the 322 * timeout was reached */ 323 wl1271_error("soft reset timeout"); 324 return -1; 325 } 326 327 udelay(SOFT_RESET_STALL_TIME); 328 } 329 330 /* disable Rx/Tx */ 331 wl1271_write32(wl, ENABLE, 0x0); 332 333 /* disable auto calibration on start*/ 334 wl1271_write32(wl, SPARE_A2, 0xffff); 335 336 return 0; 337} 338 339static int wl1271_boot_run_firmware(struct wl1271 *wl) 340{ 341 int loop, ret; 342 u32 chip_id, intr; 343 344 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); 345 346 chip_id = wl1271_read32(wl, CHIP_ID_B); 347 348 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); 349 350 if (chip_id != wl->chip.id) { 351 wl1271_error("chip id doesn't match after firmware boot"); 352 return -EIO; 353 } 354 355 /* wait for init to complete */ 356 loop = 0; 357 while (loop++ < INIT_LOOP) { 358 udelay(INIT_LOOP_DELAY); 359 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); 360 361 if (intr == 0xffffffff) { 362 wl1271_error("error reading hardware complete " 363 "init indication"); 364 return -EIO; 365 } 366 /* check that ACX_INTR_INIT_COMPLETE is enabled */ 367 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) { 368 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK, 369 WL1271_ACX_INTR_INIT_COMPLETE); 370 break; 371 } 372 } 373 374 if (loop > INIT_LOOP) { 375 wl1271_error("timeout waiting for the hardware to " 376 "complete initialization"); 377 return -EIO; 378 } 379 380 /* get hardware config command mail box */ 381 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR); 382 383 /* get hardware config event mail box */ 384 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR); 385 386 /* set the working partition to its "running" mode offset */ 387 wl1271_set_partition(wl, &part_table[PART_WORK]); 388 389 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x", 390 wl->cmd_box_addr, wl->event_box_addr); 391 392 wl1271_boot_fw_version(wl); 393 394 /* 395 * in case of full asynchronous mode the firmware event must be 396 * ready to receive event from the command mailbox 397 */ 398 399 /* unmask required mbox events */ 400 wl->event_mask = BSS_LOSE_EVENT_ID | 401 SCAN_COMPLETE_EVENT_ID | 402 PS_REPORT_EVENT_ID | 403 JOIN_EVENT_COMPLETE_ID | 404 DISCONNECT_EVENT_COMPLETE_ID | 405 RSSI_SNR_TRIGGER_0_EVENT_ID | 406 PSPOLL_DELIVERY_FAILURE_EVENT_ID | 407 SOFT_GEMINI_SENSE_EVENT_ID; 408 409 ret = wl1271_event_unmask(wl); 410 if (ret < 0) { 411 wl1271_error("EVENT mask setting failed"); 412 return ret; 413 } 414 415 wl1271_event_mbox_config(wl); 416 417 /* firmware startup completed */ 418 return 0; 419} 420 421static int wl1271_boot_write_irq_polarity(struct wl1271 *wl) 422{ 423 u32 polarity; 424 425 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY); 426 427 /* We use HIGH polarity, so unset the LOW bit */ 428 polarity &= ~POLARITY_LOW; 429 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity); 430 431 return 0; 432} 433 434static void wl1271_boot_hw_version(struct wl1271 *wl) 435{ 436 u32 fuse; 437 438 fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1); 439 fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET; 440 441 wl->hw_pg_ver = (s8)fuse; 442} 443 444int wl1271_boot(struct wl1271 *wl) 445{ 446 int ret = 0; 447 u32 tmp, clk, pause; 448 449 wl1271_boot_hw_version(wl); 450 451 if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4) 452 /* ref clk: 19.2/38.4/38.4-XTAL */ 453 clk = 0x3; 454 else if (REF_CLOCK == 1 || REF_CLOCK == 3) 455 /* ref clk: 26/52 */ 456 clk = 0x5; 457 458 if (REF_CLOCK != 0) { 459 u16 val; 460 /* Set clock type (open drain) */ 461 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE); 462 val &= FREF_CLK_TYPE_BITS; 463 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val); 464 465 /* Set clock pull mode (no pull) */ 466 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL); 467 val |= NO_PULL; 468 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val); 469 } else { 470 u16 val; 471 /* Set clock polarity */ 472 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY); 473 val &= FREF_CLK_POLARITY_BITS; 474 val |= CLK_REQ_OUTN_SEL; 475 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); 476 } 477 478 wl1271_write32(wl, PLL_PARAMETERS, clk); 479 480 pause = wl1271_read32(wl, PLL_PARAMETERS); 481 482 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause); 483 484 pause &= ~(WU_COUNTER_PAUSE_VAL); 485 pause |= WU_COUNTER_PAUSE_VAL; 486 wl1271_write32(wl, WU_COUNTER_PAUSE, pause); 487 488 /* Continue the ELP wake up sequence */ 489 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 490 udelay(500); 491 492 wl1271_set_partition(wl, &part_table[PART_DRPW]); 493 494 /* Read-modify-write DRPW_SCRATCH_START register (see next state) 495 to be used by DRPw FW. The RTRIM value will be added by the FW 496 before taking DRPw out of reset */ 497 498 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START); 499 clk = wl1271_read32(wl, DRPW_SCRATCH_START); 500 501 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); 502 503 /* 2 */ 504 clk |= (REF_CLOCK << 1) << 4; 505 wl1271_write32(wl, DRPW_SCRATCH_START, clk); 506 507 wl1271_set_partition(wl, &part_table[PART_WORK]); 508 509 /* Disable interrupts */ 510 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 511 512 ret = wl1271_boot_soft_reset(wl); 513 if (ret < 0) 514 goto out; 515 516 /* 2. start processing NVS file */ 517 ret = wl1271_boot_upload_nvs(wl); 518 if (ret < 0) 519 goto out; 520 521 /* write firmware's last address (ie. it's length) to 522 * ACX_EEPROMLESS_IND_REG */ 523 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG"); 524 525 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG); 526 527 tmp = wl1271_read32(wl, CHIP_ID_B); 528 529 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 530 531 /* 6. read the EEPROM parameters */ 532 tmp = wl1271_read32(wl, SCR_PAD2); 533 534 ret = wl1271_boot_write_irq_polarity(wl); 535 if (ret < 0) 536 goto out; 537 538 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, 539 WL1271_ACX_ALL_EVENTS_VECTOR); 540 541 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly 542 * to upload_fw) */ 543 544 ret = wl1271_boot_upload_firmware(wl); 545 if (ret < 0) 546 goto out; 547 548 /* 10.5 start firmware */ 549 ret = wl1271_boot_run_firmware(wl); 550 if (ret < 0) 551 goto out; 552 553 /* Enable firmware interrupts now */ 554 wl1271_boot_enable_interrupts(wl); 555 556 /* set the wl1271 default filters */ 557 wl->rx_config = WL1271_DEFAULT_RX_CONFIG; 558 wl->rx_filter = WL1271_DEFAULT_RX_FILTER; 559 560 wl1271_event_mbox_config(wl); 561 562out: 563 return ret; 564} 565