1/* 2 * This file is part of wl12xx 3 * 4 * Copyright (c) 1998-2007 Texas Instruments Incorporated 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * Contact: Kalle Valo <kalle.valo@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25#ifndef __REG_H__ 26#define __REG_H__ 27 28#include <linux/bitops.h> 29 30#define REGISTERS_BASE 0x00300000 31#define DRPW_BASE 0x00310000 32 33#define REGISTERS_DOWN_SIZE 0x00008800 34#define REGISTERS_WORK_SIZE 0x0000b000 35 36#define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC 37 38/* ELP register commands */ 39#define ELPCTRL_WAKE_UP 0x1 40#define ELPCTRL_WAKE_UP_WLAN_READY 0x5 41#define ELPCTRL_SLEEP 0x0 42/* ELP WLAN_READY bit */ 43#define ELPCTRL_WLAN_READY 0x2 44 45/* Device Configuration registers*/ 46#define SOR_CFG (REGISTERS_BASE + 0x0800) 47#define ECPU_CTRL (REGISTERS_BASE + 0x0804) 48#define HI_CFG (REGISTERS_BASE + 0x0808) 49 50/* EEPROM registers */ 51#define EE_START (REGISTERS_BASE + 0x080C) 52#define EE_CTL (REGISTERS_BASE + 0x2000) 53#define EE_DATA (REGISTERS_BASE + 0x2004) 54#define EE_ADDR (REGISTERS_BASE + 0x2008) 55 56#define EE_CTL_READ 2 57 58#define CHIP_ID_B (REGISTERS_BASE + 0x5674) 59 60#define CHIP_ID_1251_PG10 (0x7010101) 61#define CHIP_ID_1251_PG11 (0x7020101) 62#define CHIP_ID_1251_PG12 (0x7030101) 63 64#define ENABLE (REGISTERS_BASE + 0x5450) 65 66/* Power Management registers */ 67#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804) 68#define ELP_CMD (REGISTERS_BASE + 0x5808) 69#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810) 70#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814) 71#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818) 72 73#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820) 74 75/* Scratch Pad registers*/ 76#define SCR_PAD0 (REGISTERS_BASE + 0x5608) 77#define SCR_PAD1 (REGISTERS_BASE + 0x560C) 78#define SCR_PAD2 (REGISTERS_BASE + 0x5610) 79#define SCR_PAD3 (REGISTERS_BASE + 0x5614) 80#define SCR_PAD4 (REGISTERS_BASE + 0x5618) 81#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C) 82#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620) 83#define SCR_PAD5 (REGISTERS_BASE + 0x5624) 84#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628) 85#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C) 86#define SCR_PAD6 (REGISTERS_BASE + 0x5630) 87#define SCR_PAD7 (REGISTERS_BASE + 0x5634) 88#define SCR_PAD8 (REGISTERS_BASE + 0x5638) 89#define SCR_PAD9 (REGISTERS_BASE + 0x563C) 90 91/* Spare registers*/ 92#define SPARE_A1 (REGISTERS_BASE + 0x0994) 93#define SPARE_A2 (REGISTERS_BASE + 0x0998) 94#define SPARE_A3 (REGISTERS_BASE + 0x099C) 95#define SPARE_A4 (REGISTERS_BASE + 0x09A0) 96#define SPARE_A5 (REGISTERS_BASE + 0x09A4) 97#define SPARE_A6 (REGISTERS_BASE + 0x09A8) 98#define SPARE_A7 (REGISTERS_BASE + 0x09AC) 99#define SPARE_A8 (REGISTERS_BASE + 0x09B0) 100#define SPARE_B1 (REGISTERS_BASE + 0x5420) 101#define SPARE_B2 (REGISTERS_BASE + 0x5424) 102#define SPARE_B3 (REGISTERS_BASE + 0x5428) 103#define SPARE_B4 (REGISTERS_BASE + 0x542C) 104#define SPARE_B5 (REGISTERS_BASE + 0x5430) 105#define SPARE_B6 (REGISTERS_BASE + 0x5434) 106#define SPARE_B7 (REGISTERS_BASE + 0x5438) 107#define SPARE_B8 (REGISTERS_BASE + 0x543C) 108 109enum wl12xx_acx_int_reg { 110 ACX_REG_INTERRUPT_TRIG, 111 ACX_REG_INTERRUPT_TRIG_H, 112 113/*============================================= 114 Host Interrupt Mask Register - 32bit (RW) 115 ------------------------------------------ 116 Setting a bit in this register masks the 117 corresponding interrupt to the host. 118 0 - RX0 - Rx first dubble buffer Data Interrupt 119 1 - TXD - Tx Data Interrupt 120 2 - TXXFR - Tx Transfer Interrupt 121 3 - RX1 - Rx second dubble buffer Data Interrupt 122 4 - RXXFR - Rx Transfer Interrupt 123 5 - EVENT_A - Event Mailbox interrupt 124 6 - EVENT_B - Event Mailbox interrupt 125 7 - WNONHST - Wake On Host Interrupt 126 8 - TRACE_A - Debug Trace interrupt 127 9 - TRACE_B - Debug Trace interrupt 128 10 - CDCMP - Command Complete Interrupt 129 11 - 130 12 - 131 13 - 132 14 - ICOMP - Initialization Complete Interrupt 133 16 - SG SE - Soft Gemini - Sense enable interrupt 134 17 - SG SD - Soft Gemini - Sense disable interrupt 135 18 - - 136 19 - - 137 20 - - 138 21- - 139 Default: 0x0001 140*==============================================*/ 141 ACX_REG_INTERRUPT_MASK, 142 143/*============================================= 144 Host Interrupt Mask Set 16bit, (Write only) 145 ------------------------------------------ 146 Setting a bit in this register sets 147 the corresponding bin in ACX_HINT_MASK register 148 without effecting the mask 149 state of other bits (0 = no effect). 150==============================================*/ 151 ACX_REG_HINT_MASK_SET, 152 153/*============================================= 154 Host Interrupt Mask Clear 16bit,(Write only) 155 ------------------------------------------ 156 Setting a bit in this register clears 157 the corresponding bin in ACX_HINT_MASK register 158 without effecting the mask 159 state of other bits (0 = no effect). 160=============================================*/ 161 ACX_REG_HINT_MASK_CLR, 162 163/*============================================= 164 Host Interrupt Status Nondestructive Read 165 16bit,(Read only) 166 ------------------------------------------ 167 The host can read this register to determine 168 which interrupts are active. 169 Reading this register doesn't 170 effect its content. 171=============================================*/ 172 ACX_REG_INTERRUPT_NO_CLEAR, 173 174/*============================================= 175 Host Interrupt Status Clear on Read Register 176 16bit,(Read only) 177 ------------------------------------------ 178 The host can read this register to determine 179 which interrupts are active. 180 Reading this register clears it, 181 thus making all interrupts inactive. 182==============================================*/ 183 ACX_REG_INTERRUPT_CLEAR, 184 185/*============================================= 186 Host Interrupt Acknowledge Register 187 16bit,(Write only) 188 ------------------------------------------ 189 The host can set individual bits in this 190 register to clear (acknowledge) the corresp. 191 interrupt status bits in the HINT_STS_CLR and 192 HINT_STS_ND registers, thus making the 193 assotiated interrupt inactive. (0-no effect) 194==============================================*/ 195 ACX_REG_INTERRUPT_ACK, 196 197/*=============================================== 198 Host Software Reset - 32bit RW 199 ------------------------------------------ 200 [31:1] Reserved 201 0 SOFT_RESET Soft Reset - When this bit is set, 202 it holds the Wlan hardware in a soft reset state. 203 This reset disables all MAC and baseband processor 204 clocks except the CardBus/PCI interface clock. 205 It also initializes all MAC state machines except 206 the host interface. It does not reload the 207 contents of the EEPROM. When this bit is cleared 208 (not self-clearing), the Wlan hardware 209 exits the software reset state. 210===============================================*/ 211 ACX_REG_SLV_SOFT_RESET, 212 213/*=============================================== 214 EEPROM Burst Read Start - 32bit RW 215 ------------------------------------------ 216 [31:1] Reserved 217 0 ACX_EE_START - EEPROM Burst Read Start 0 218 Setting this bit starts a burst read from 219 the external EEPROM. 220 If this bit is set (after reset) before an EEPROM read/write, 221 the burst read starts at EEPROM address 0. 222 Otherwise, it starts at the address 223 following the address of the previous access. 224 TheWlan hardware hardware clears this bit automatically. 225 226 Default: 0x00000000 227*================================================*/ 228 ACX_REG_EE_START, 229 230/* Embedded ARM CPU Control */ 231 232/*=============================================== 233 Halt eCPU - 32bit RW 234 ------------------------------------------ 235 0 HALT_ECPU Halt Embedded CPU - This bit is the 236 compliment of bit 1 (MDATA2) in the SOR_CFG register. 237 During a hardware reset, this bit holds 238 the inverse of MDATA2. 239 When downloading firmware from the host, 240 set this bit (pull down MDATA2). 241 The host clears this bit after downloading the firmware into 242 zero-wait-state SSRAM. 243 When loading firmware from Flash, clear this bit (pull up MDATA2) 244 so that the eCPU can run the bootloader code in Flash 245 HALT_ECPU eCPU State 246 -------------------- 247 1 halt eCPU 248 0 enable eCPU 249 ===============================================*/ 250 ACX_REG_ECPU_CONTROL, 251 252 ACX_REG_TABLE_LEN 253}; 254 255#define ACX_SLV_SOFT_RESET_BIT BIT(0) 256#define ACX_REG_EEPROM_START_BIT BIT(0) 257 258/* Command/Information Mailbox Pointers */ 259 260/*=============================================== 261 Command Mailbox Pointer - 32bit RW 262 ------------------------------------------ 263 This register holds the start address of 264 the command mailbox located in the Wlan hardware memory. 265 The host must read this pointer after a reset to 266 find the location of the command mailbox. 267 The Wlan hardware initializes the command mailbox 268 pointer with the default address of the command mailbox. 269 The command mailbox pointer is not valid until after 270 the host receives the Init Complete interrupt from 271 the Wlan hardware. 272 ===============================================*/ 273#define REG_COMMAND_MAILBOX_PTR (SCR_PAD0) 274 275/*=============================================== 276 Information Mailbox Pointer - 32bit RW 277 ------------------------------------------ 278 This register holds the start address of 279 the information mailbox located in the Wlan hardware memory. 280 The host must read this pointer after a reset to find 281 the location of the information mailbox. 282 The Wlan hardware initializes the information mailbox pointer 283 with the default address of the information mailbox. 284 The information mailbox pointer is not valid 285 until after the host receives the Init Complete interrupt from 286 the Wlan hardware. 287 ===============================================*/ 288#define REG_EVENT_MAILBOX_PTR (SCR_PAD1) 289 290 291/* Misc */ 292 293#define REG_ENABLE_TX_RX (ENABLE) 294/* 295 * Rx configuration (filter) information element 296 * --------------------------------------------- 297 */ 298#define REG_RX_CONFIG (RX_CFG) 299#define REG_RX_FILTER (RX_FILTER_CFG) 300 301 302#define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002 303 304/* promiscuous - receives all valid frames */ 305#define RX_CFG_PROMISCUOUS 0x0008 306 307/* receives frames from any BSSID */ 308#define RX_CFG_BSSID 0x0020 309 310/* receives frames destined to any MAC address */ 311#define RX_CFG_MAC 0x0010 312 313#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010 314#define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000 315#define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020 316#define RX_CFG_ENABLE_ANY_BSSID 0x0000 317 318/* discards all broadcast frames */ 319#define RX_CFG_DISABLE_BCAST 0x0200 320 321#define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400 322#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800 323#define RX_CFG_COPY_RX_STATUS 0x2000 324#define RX_CFG_TSF 0x10000 325 326#define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \ 327 RX_CFG_ENABLE_ONLY_MY_BSSID) 328 329#define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\ 330 | RX_CFG_ENABLE_ANY_BSSID) 331 332#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \ 333 RX_CFG_ENABLE_ANY_BSSID) 334 335#define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\ 336 | RX_CFG_ENABLE_ONLY_MY_BSSID) 337 338#define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \ 339 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \ 340 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF) 341 342#define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC) 343 344#define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \ 345 RX_CFG_ENABLE_ONLY_MY_DEST_MAC) 346 347#define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \ 348 RX_CFG_ENABLE_ONLY_MY_DEST_MAC) 349 350#define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\ 351 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\ 352 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN) 353 354#define RX_FILTER_OPTION_FILTER_ALL 0 355 356#define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\ 357 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN) 358 359#define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\ 360 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\ 361 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\ 362 | CFG_RX_PRSP_EN) 363 364 365/*=============================================== 366 EEPROM Read/Write Request 32bit RW 367 ------------------------------------------ 368 1 EE_READ - EEPROM Read Request 1 - Setting this bit 369 loads a single byte of data into the EE_DATA 370 register from the EEPROM location specified in 371 the EE_ADDR register. 372 The Wlan hardware hardware clears this bit automatically. 373 EE_DATA is valid when this bit is cleared. 374 375 0 EE_WRITE - EEPROM Write Request - Setting this bit 376 writes a single byte of data from the EE_DATA register into the 377 EEPROM location specified in the EE_ADDR register. 378 The Wlan hardware hardware clears this bit automatically. 379*===============================================*/ 380#define EE_CTL (REGISTERS_BASE + 0x2000) 381#define ACX_EE_CTL_REG EE_CTL 382#define EE_WRITE 0x00000001ul 383#define EE_READ 0x00000002ul 384 385/*=============================================== 386 EEPROM Address - 32bit RW 387 ------------------------------------------ 388 This register specifies the address 389 within the EEPROM from/to which to read/write data. 390 ===============================================*/ 391#define EE_ADDR (REGISTERS_BASE + 0x2008) 392#define ACX_EE_ADDR_REG EE_ADDR 393 394/*=============================================== 395 EEPROM Data - 32bit RW 396 ------------------------------------------ 397 This register either holds the read 8 bits of 398 data from the EEPROM or the write data 399 to be written to the EEPROM. 400 ===============================================*/ 401#define EE_DATA (REGISTERS_BASE + 0x2004) 402#define ACX_EE_DATA_REG EE_DATA 403 404#define EEPROM_ACCESS_TO 10000 /* timeout counter */ 405#define START_EEPROM_MGR 0x00000001 406 407/*=============================================== 408 EEPROM Base Address - 32bit RW 409 ------------------------------------------ 410 This register holds the upper nine bits 411 [23:15] of the 24-bit Wlan hardware memory 412 address for burst reads from EEPROM accesses. 413 The EEPROM provides the lower 15 bits of this address. 414 The MSB of the address from the EEPROM is ignored. 415 ===============================================*/ 416#define ACX_EE_CFG EE_CFG 417 418/*=============================================== 419 GPIO Output Values -32bit, RW 420 ------------------------------------------ 421 [31:16] Reserved 422 [15: 0] Specify the output values (at the output driver inputs) for 423 GPIO[15:0], respectively. 424 ===============================================*/ 425#define ACX_GPIO_OUT_REG GPIO_OUT 426#define ACX_MAX_GPIO_LINES 15 427 428/*=============================================== 429 Contention window -32bit, RW 430 ------------------------------------------ 431 [31:26] Reserved 432 [25:16] Max (0x3ff) 433 [15:07] Reserved 434 [06:00] Current contention window value - default is 0x1F 435 ===============================================*/ 436#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG 437#define ACX_CONT_WIND_MIN_MASK 0x0000007f 438#define ACX_CONT_WIND_MAX 0x03ff0000 439 440/*=============================================== 441 HI_CFG Interface Configuration Register Values 442 ------------------------------------------ 443 ===============================================*/ 444#define HI_CFG_UART_ENABLE 0x00000004 445#define HI_CFG_RST232_ENABLE 0x00000008 446#define HI_CFG_CLOCK_REQ_SELECT 0x00000010 447#define HI_CFG_HOST_INT_ENABLE 0x00000020 448#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 449#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 450#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 451#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 452#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 453 454/* 455 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile 456 * for platforms using active high interrupt level 457 */ 458#ifdef USE_ACTIVE_HIGH 459#define HI_CFG_DEF_VAL \ 460 (HI_CFG_UART_ENABLE | \ 461 HI_CFG_RST232_ENABLE | \ 462 HI_CFG_CLOCK_REQ_SELECT | \ 463 HI_CFG_HOST_INT_ENABLE) 464#else 465#define HI_CFG_DEF_VAL \ 466 (HI_CFG_UART_ENABLE | \ 467 HI_CFG_RST232_ENABLE | \ 468 HI_CFG_CLOCK_REQ_SELECT | \ 469 HI_CFG_HOST_INT_ENABLE) 470 471#endif 472 473#define REF_FREQ_19_2 0 474#define REF_FREQ_26_0 1 475#define REF_FREQ_38_4 2 476#define REF_FREQ_40_0 3 477#define REF_FREQ_33_6 4 478#define REF_FREQ_NUM 5 479 480#define LUT_PARAM_INTEGER_DIVIDER 0 481#define LUT_PARAM_FRACTIONAL_DIVIDER 1 482#define LUT_PARAM_ATTN_BB 2 483#define LUT_PARAM_ALPHA_BB 3 484#define LUT_PARAM_STOP_TIME_BB 4 485#define LUT_PARAM_BB_PLL_LOOP_FILTER 5 486#define LUT_PARAM_NUM 6 487 488#define ACX_EEPROMLESS_IND_REG (SCR_PAD4) 489#define USE_EEPROM 0 490#define SOFT_RESET_MAX_TIME 1000000 491#define SOFT_RESET_STALL_TIME 1000 492#define NVS_DATA_BUNDARY_ALIGNMENT 4 493 494 495/* Firmware image load chunk size */ 496#define CHUNK_SIZE 512 497 498/* Firmware image header size */ 499#define FW_HDR_SIZE 8 500 501#define ECPU_CONTROL_HALT 0x00000101 502 503 504/****************************************************************************** 505 506 CHANNELS, BAND & REG DOMAINS definitions 507 508******************************************************************************/ 509 510 511enum { 512 RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */ 513 RADIO_BAND_5GHZ = 1, /* 5 Ghz band */ 514 RADIO_BAND_JAPAN_4_9_GHZ = 2, 515 DEFAULT_BAND = RADIO_BAND_2_4GHZ, 516 INVALID_BAND = 0xFE, 517 MAX_RADIO_BANDS = 0xFF 518}; 519 520enum { 521 NO_RATE = 0, 522 RATE_1MBPS = 0x0A, 523 RATE_2MBPS = 0x14, 524 RATE_5_5MBPS = 0x37, 525 RATE_6MBPS = 0x0B, 526 RATE_9MBPS = 0x0F, 527 RATE_11MBPS = 0x6E, 528 RATE_12MBPS = 0x0A, 529 RATE_18MBPS = 0x0E, 530 RATE_22MBPS = 0xDC, 531 RATE_24MBPS = 0x09, 532 RATE_36MBPS = 0x0D, 533 RATE_48MBPS = 0x08, 534 RATE_54MBPS = 0x0C 535}; 536 537enum { 538 RATE_INDEX_1MBPS = 0, 539 RATE_INDEX_2MBPS = 1, 540 RATE_INDEX_5_5MBPS = 2, 541 RATE_INDEX_6MBPS = 3, 542 RATE_INDEX_9MBPS = 4, 543 RATE_INDEX_11MBPS = 5, 544 RATE_INDEX_12MBPS = 6, 545 RATE_INDEX_18MBPS = 7, 546 RATE_INDEX_22MBPS = 8, 547 RATE_INDEX_24MBPS = 9, 548 RATE_INDEX_36MBPS = 10, 549 RATE_INDEX_48MBPS = 11, 550 RATE_INDEX_54MBPS = 12, 551 RATE_INDEX_MAX = RATE_INDEX_54MBPS, 552 MAX_RATE_INDEX, 553 INVALID_RATE_INDEX = MAX_RATE_INDEX, 554 RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF 555}; 556 557enum { 558 RATE_MASK_1MBPS = 0x1, 559 RATE_MASK_2MBPS = 0x2, 560 RATE_MASK_5_5MBPS = 0x4, 561 RATE_MASK_11MBPS = 0x20, 562}; 563 564#define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */ 565#define OFDM_RATE_BIT BIT(6) 566#define PBCC_RATE_BIT BIT(7) 567 568enum { 569 CCK_LONG = 0, 570 CCK_SHORT = SHORT_PREAMBLE_BIT, 571 PBCC_LONG = PBCC_RATE_BIT, 572 PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT, 573 OFDM = OFDM_RATE_BIT 574}; 575 576/****************************************************************************** 577 578Transmit-Descriptor RATE-SET field definitions... 579 580Define a new "Rate-Set" for TX path that incorporates the 581Rate & Modulation info into a single 16-bit field. 582 583TxdRateSet_t: 584b15 - Indicates Preamble type (1=SHORT, 0=LONG). 585 Notes: 586 Must be LONG (0) for 1Mbps rate. 587 Does not apply (set to 0) for RevG-OFDM rates. 588b14 - Indicates PBCC encoding (1=PBCC, 0=not). 589 Notes: 590 Does not apply (set to 0) for rates 1 and 2 Mbps. 591 Does not apply (set to 0) for RevG-OFDM rates. 592b13 - Unused (set to 0). 593b12-b0 - Supported Rate indicator bits as defined below. 594 595******************************************************************************/ 596 597 598/************************************************************************* 599 600 Interrupt Trigger Register (Host -> WiLink) 601 602**************************************************************************/ 603 604/* Hardware to Embedded CPU Interrupts - first 32-bit register set */ 605 606/* 607 * Host Command Interrupt. Setting this bit masks 608 * the interrupt that the host issues to inform 609 * the FW that it has sent a command 610 * to the Wlan hardware Command Mailbox. 611 */ 612#define INTR_TRIG_CMD BIT(0) 613 614/* 615 * Host Event Acknowlegde Interrupt. The host 616 * sets this bit to acknowledge that it received 617 * the unsolicited information from the event 618 * mailbox. 619 */ 620#define INTR_TRIG_EVENT_ACK BIT(1) 621 622/* 623 * The host sets this bit to inform the Wlan 624 * FW that a TX packet is in the XFER 625 * Buffer #0. 626 */ 627#define INTR_TRIG_TX_PROC0 BIT(2) 628 629/* 630 * The host sets this bit to inform the FW 631 * that it read a packet from RX XFER 632 * Buffer #0. 633 */ 634#define INTR_TRIG_RX_PROC0 BIT(3) 635 636#define INTR_TRIG_DEBUG_ACK BIT(4) 637 638#define INTR_TRIG_STATE_CHANGED BIT(5) 639 640 641/* Hardware to Embedded CPU Interrupts - second 32-bit register set */ 642 643/* 644 * The host sets this bit to inform the FW 645 * that it read a packet from RX XFER 646 * Buffer #1. 647 */ 648#define INTR_TRIG_RX_PROC1 BIT(17) 649 650/* 651 * The host sets this bit to inform the Wlan 652 * hardware that a TX packet is in the XFER 653 * Buffer #1. 654 */ 655#define INTR_TRIG_TX_PROC1 BIT(18) 656 657#endif 658